UPSTREAM: PCI: rockchip: Add quirk to disable RC's ASPM L0s

[firefly-linux-kernel-4.4.55.git] / drivers / pci / host / pcie-rockchip.c

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 1fcd42a1589d4607b0a7b0f788add9df01d44c5c..86f08f3ecabcf287cd626a973ebbcde4c85ef50d 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -140,6 +140,8 @@
 #define   PCIE_RC_CONFIG_DCR_CSPL_SHIFT                18
 #define   PCIE_RC_CONFIG_DCR_CSPL_LIMIT                0xff
 #define   PCIE_RC_CONFIG_DCR_CPLS_SHIFT                26
+#define PCIE_RC_CONFIG_LINK_CAP                (PCIE_RC_CONFIG_BASE + 0xcc)
+#define   PCIE_RC_CONFIG_LINK_CAP_L0S          BIT(10)
 #define PCIE_RC_CONFIG_LCS             (PCIE_RC_CONFIG_BASE + 0xd0)
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
 #define PCIE_RC_CONFIG_THP_CAP         (PCIE_RC_CONFIG_BASE + 0x274)
@@ -648,6 +650,13 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
        status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
        rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
 
+       /* Clear L0s from RC's link cap */
+       if (of_property_read_bool(dev->of_node, "quirk,apsm-no-l0s")) {
+               status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
+               status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S;
+               rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
+       }
+
        rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
 
        rockchip_pcie_write(rockchip,