clk: rockchip: rk3368: add aclk_cci_pre ID
[firefly-linux-kernel-4.4.55.git] / drivers / clk / rockchip / clk-rk3368.c
index e4554a3ca525d82d22b8dac079d4ba9515d870d6..89a9d0a78d6fe268c3be3213a1582916f5e04e70 100644 (file)
@@ -329,8 +329,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
                        RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
                        RK3368_CLKGATE_CON(0), 13, GFLAGS),
 
-       COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
-                       RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS,
+       COMPOSITE(ACLK_CCI_PRE, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
+                       RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3368_CLKGATE_CON(0), 12, GFLAGS),
        GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
 
@@ -338,6 +338,9 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
                        RK3368_CLKGATE_CON(1), 8, GFLAGS),
        GATE(0, "gpll_ddr", "gpll", 0,
                        RK3368_CLKGATE_CON(1), 9, GFLAGS),
+       COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
+                       RK3368_CLKSEL_CON(13), 4, 1, 0, 0, ROCKCHIP_DDRCLK_SCPI),
+
        COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
                        RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),