clk: rockchip: rk3368: add aclk_cci_pre ID
authorElaine Zhang <zhangqing@rock-chips.com>
Fri, 7 Apr 2017 09:35:28 +0000 (17:35 +0800)
committerHuang, Tao <huangtao@rock-chips.com>
Fri, 7 Apr 2017 10:51:15 +0000 (18:51 +0800)
Change-Id: I855e79023a9e244c2db37af88a075a4ef4c36aec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
drivers/clk/rockchip/clk-rk3368.c
include/dt-bindings/clock/rk3368-cru.h

index a5e5050..89a9d0a 100644 (file)
@@ -329,8 +329,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
                        RK3368_CLKSEL_CON(4), 8, 5, DFLAGS,
                        RK3368_CLKGATE_CON(0), 13, GFLAGS),
 
-       COMPOSITE(0, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
-                       RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 7, DFLAGS,
+       COMPOSITE(ACLK_CCI_PRE, "aclk_cci_pre", mux_pll_src_cpll_gpll_usb_npll_p, CLK_IGNORE_UNUSED,
+                       RK3368_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3368_CLKGATE_CON(0), 12, GFLAGS),
        GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
 
index 24ba64e..690800d 100644 (file)
 #define ACLK_VIDEO             208
 #define ACLK_BUS               209
 #define ACLK_PERI              210
+#define ACLK_CCI_PRE           211
 
 /* pclk gates */
 #define PCLK_GPIO0             320