clk: rockchip: rk3328: add pclk for acodec

[firefly-linux-kernel-4.4.55.git] / drivers / clk / rockchip / clk-rk3328.c

diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index 31b7a79ca3768563bf6055bb2b6977c9b3699bf1..5b170871d684ab8d512629499a2de90b2d368cbf 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -20,6 +20,7 @@
 #include <dt-bindings/clock/rk3328-cru.h>
 #include "clk.h"
 
+#define RK3328_GRF_SOC_CON4            0x410
 #define RK3328_GRF_SOC_STATUS0         0x480
 #define RK3328_GRF_MAC_CON1            0x904
 #define RK3328_GRF_MAC_CON2            0x908
@@ -214,6 +215,8 @@ PNAME(mux_mac2io_src_p)             = { "clk_mac2io_src",
                                    "gmac_clkin" };
 PNAME(mux_mac2phy_src_p)       = { "clk_mac2phy_src",
                                    "phy_50m_out" };
+PNAME(mux_mac2io_ext_p)                = { "clk_mac2io",
+                                   "gmac_clkin" };
 
 static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
        [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
@@ -586,7 +589,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
        COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_4plls_p, 0,
                        RK3328_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
                        RK3328_CLKGATE_CON(5), 5, GFLAGS),
-       GATE(0, "clk_hdmi_sfc", "xin24m", 0,
+       GATE(SCLK_HDMI_SFC, "clk_hdmi_sfc", "xin24m", 0,
                        RK3328_CLKGATE_CON(5), 4, GFLAGS),
 
        COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
@@ -683,6 +686,8 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
                        RK3328_CLKGATE_CON(3), 5, GFLAGS),
        MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,
                        RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
+       MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,
+                       RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
 
        COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
                        RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
@@ -729,7 +734,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 
        /* PD_PERI */
        GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
-       GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
+       GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
 
        GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
        GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
@@ -790,6 +795,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
        GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS),
        GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS),
        GATE(0, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 4, GFLAGS),
+       GATE(PCLK_ACODEC, "pclk_acodec", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),
        GATE(0, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 6, GFLAGS),
        GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS),
        GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),