clk: rockchip: rk3328: add pclk for acodec

[firefly-linux-kernel-4.4.55.git] / drivers / clk / clk-qoriq.c

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 1ab0fb81c6a0ef7746d77427c488bdb84235011a..a5070f9cb0d4aa2797d614150a320046dbf1b42d 100644 (file)
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -700,6 +700,7 @@ static struct clk * __init create_mux_common(struct clockgen *cg,
                                             struct mux_hwclock *hwc,
                                             const struct clk_ops *ops,
                                             unsigned long min_rate,
+                                            unsigned long max_rate,
                                             unsigned long pct80_rate,
                                             const char *fmt, int idx)
 {
@@ -728,6 +729,8 @@ static struct clk * __init create_mux_common(struct clockgen *cg,
                        continue;
                if (rate < min_rate)
                        continue;
+               if (rate > max_rate)
+                       continue;
 
                parent_names[j] = div->name;
                hwc->parent_to_clksel[j] = i;
@@ -759,14 +762,18 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
        struct mux_hwclock *hwc;
        const struct clockgen_pll_div *div;
        unsigned long plat_rate, min_rate;
-       u64 pct80_rate;
+       u64 max_rate, pct80_rate;
        u32 clksel;
 
        hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
        if (!hwc)
                return NULL;
 
-       hwc->reg = cg->regs + 0x20 * idx;
+       if (cg->info.flags & CG_VER3)
+               hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
+       else
+               hwc->reg = cg->regs + 0x20 * idx;
+
        hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
 
        /*
@@ -778,11 +785,13 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
         */
        clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
        div = get_pll_div(cg, hwc, clksel);
-       if (!div)
+       if (!div) {
+               kfree(hwc);
                return NULL;
+       }
 
-       pct80_rate = clk_get_rate(div->clk);
-       pct80_rate *= 8;
+       max_rate = clk_get_rate(div->clk);
+       pct80_rate = max_rate * 8;
        do_div(pct80_rate, 10);
 
        plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
@@ -792,7 +801,7 @@ static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
        else
                min_rate = plat_rate / 2;
 
-       return create_mux_common(cg, hwc, &cmux_ops, min_rate,
+       return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
                                 pct80_rate, "cg-cmux%d", idx);
 }
 
@@ -807,7 +816,7 @@ static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
        hwc->reg = cg->regs + 0x20 * idx + 0x10;
        hwc->info = cg->info.hwaccel[idx];
 
-       return create_mux_common(cg, hwc, &hwaccel_ops, 0, 0,
+       return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
                                 "cg-hwaccel%d", idx);
 }