+ iep: iep@ff900000 {
+ compatible = "rockchip,iep";
+ iommu_enabled = <1>;
+ iommus = <&iep_mmu>;
+ reg = <0x0 0xff900000 0x0 0x800>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+ clock-names = "aclk_iep", "hclk_iep";
+ power-domains = <&power RK3368_PD_VIO>;
+ allocator = <1>;
+ version = <2>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu@ff900800 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff900800 0x0 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "iep_mmu";
+ power-domains = <&power RK3368_PD_VIO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ isp: isp@ff910000 {
+ compatible = "rockchip,rk3368-isp", "rockchip,isp";
+ reg = <0x0 0xff910000 0x0 0x4000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&power RK3368_PD_VIO>;
+ clocks =
+ <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
+ <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
+ <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
+ <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
+ clock-names =
+ "aclk_isp", "hclk_isp", "clk_isp",
+ "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
+ "clk_cif_pll", "hclk_mipiphy1",
+ "pclk_dphyrx", "clk_vio0_noc";
+
+ pinctrl-names =
+ "default", "isp_dvp8bit2", "isp_dvp10bit",
+ "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
+ "isp_mipi_fl", "isp_mipi_fl_prefl",
+ "isp_flash_as_gpio", "isp_flash_as_trigger_out";
+ pinctrl-0 = <&cif_clkout>;
+ pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
+ pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
+ pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
+ pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
+ pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
+ pinctrl-6 = <&cif_clkout>;
+ pinctrl-7 = <&cif_clkout &isp_prelight>;
+ pinctrl-8 = <&isp_flash_trigger_as_gpio>;
+ pinctrl-9 = <&isp_flash_trigger>;
+ rockchip,isp,mipiphy = <2>;
+ rockchip,isp,cifphy = <1>;
+ rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
+ rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
+ rockchip,grf = <&grf>;
+ rockchip,cru = <&cru>;
+ rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+ rockchip,isp,iommu-enable = <1>;
+ iommus = <&isp_mmu>;
+ status = "disabled";
+ };
+