#clock-cells = <0>;
};
- gmac_clkin: rmii_clkin {
+ gmac_clkin: gmac_clkin {
compatible = "rockchip,rk-fixed-clock";
clock-output-names = "gmac_clkin";
- clock-frequency = <0>;
+ clock-frequency = <125000000>;
#clock-cells = <0>;
};
clocks = <&clk_gpll>;
clock-output-names = "clk_gpll_div2";
clock-div = <2>;
- clock-mult = <20>;
+ clock-mult = <1>;
#clock-cells = <0>;
};
clocks = <&clk_gpll>;
clock-output-names = "clk_gpll_div3";
clock-div = <3>;
- clock-mult = <20>;
+ clock-mult = <1>;
#clock-cells = <0>;
};
- clk_pvtm_func: clk_pvtm_func {
+ g_clk_pvtm_func: g_clk_pvtm_func {
compatible = "rockchip,rk-fixed-factor-clock";
clocks = <&xin24m>;
- clock-output-names = "clk_pvtm_func";
+ clock-output-names = "g_clk_pvtm_func";
clock-div = <1>;
- clock-mult = <20>;
+ clock-mult = <1>;
#clock-cells = <0>;
};
#clock-cells = <0>;
};
+ pclkin_cif_inv: pclkin_cif_inv {
+ compatible = "rockchip,rk-fixed-factor-clock";
+ clocks = <&clk_gates3 3>;
+ clock-output-names = "pclkin_cif_inv";
+ clock-div = <1>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ hclk_vio_niu: hclk_vio_niu {
+ compatible = "rockchip,rk-fixed-factor-clock";
+ clocks = <&hclk_vio_pre>;
+ clock-output-names = "hclk_vio_niu";
+ clock-div = <1>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_vio0_niu: aclk_vio0_niu {
+ compatible = "rockchip,rk-fixed-factor-clock";
+ clocks = <&aclk_vio0_pre>;
+ clock-output-names = "aclk_vio0_niu";
+ clock-div = <1>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_vio1_niu: aclk_vio1_niu {
+ compatible = "rockchip,rk-fixed-factor-clock";
+ clocks = <&aclk_vio1_pre>;
+ clock-output-names = "aclk_vio1_niu";
+ clock-div = <1>;
+ clock-mult = <1>;
+ #clock-cells = <0>;
+ };
+
};
+ pd_cons {
+ compatible = "rockchip,rk-pd-cons";
+
+ pd_gpu: pd_gpu {
+ compatible = "rockchip,rk-pd-clock";
+ clock-output-names = "pd_gpu";
+ rockchip,pd-id = <CLK_PD_GPU>;
+ #clock-cells = <0>;
+ };
+
+ pd_video: pd_video {
+ compatible = "rockchip,rk-pd-clock";
+ clock-output-names = "pd_video";
+ rockchip,pd-id = <CLK_PD_VIDEO>;
+ #clock-cells = <0>;
+ };
+
+ pd_vio: pd_vio {
+ compatible = "rockchip,rk-pd-clock";
+ clock-output-names = "pd_vio";
+ rockchip,pd-id = <CLK_PD_VIO>;
+ #clock-cells = <0>;
+ };
+
+ pd_vop: pd_vop {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_vop";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_vip: pd_vip {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_vip";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_iep: pd_iep {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_iep";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_rga: pd_rga {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_rga";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_ebc: pd_ebc {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_ebc";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_mipidsi: pd_mipidsi {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_mipidsi";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ pd_hdmi: pd_hdmi {
+ compatible = "rockchip,rk-pd-clock";
+ clocks = <&pd_vio>;
+ clock-output-names = "pd_hdmi";
+ rockchip,pd-id = <CLK_PD_VIRT>;
+ #clock-cells = <0>;
+ };
+
+ };
+
+
clock_regs {
compatible = "rockchip,rk-clock-regs";
#address-cells = <1>;
clock-output-names = "clk_cpll";
rockchip,pll-type = <CLK_PLL_312XPLUS>;
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
clk_gpll: pll-clk@0030 {
#clock-init-cells = <1>;
};
- aclk_cpu_pre_div: aclk_cpu_pre_div {
+ aclk_cpu_div: aclk_cpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 5>;
- clocks = <&aclk_cpu_pre>;
- clock-output-names = "aclk_cpu_pre";
+ clocks = <&aclk_cpu>;
+ clock-output-names = "aclk_cpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
- aclk_cpu_pre: aclk_cpu_pre_mux {
+ aclk_cpu: aclk_cpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <13 2>;
clocks = <&clk_apll>, <&clk_gpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
- clock-output-names = "aclk_cpu_pre";
+ clock-output-names = "aclk_cpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
hclk_cpu_pre: hclk_cpu_pre_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 2>;
- clocks = <&aclk_cpu_pre>;
+ clocks = <&aclk_cpu>;
clock-output-names = "hclk_cpu_pre";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
pclk_cpu_pre: pclk_cpu_pre_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 3>;
- clocks = <&aclk_cpu_pre>;
+ clocks = <&aclk_cpu>;
clock-output-names = "pclk_cpu_pre";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
clk_pvtm_div: clk_pvtm_div {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <0 7>;
- clocks = <&clk_pvtm_func>;
+ clocks = <&g_clk_pvtm_func>;
clock-output-names = "clk_pvtm";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>;
clock-output-names = "clk_nandc";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
};
rockchip,bits = <8 5>;
clocks = <&xin24m>;
clock-output-names = "clk_24m";
+ rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
};
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ #clock-init-cells = <1>;
};
/* reg[5]: reserved */
#address-cells = <1>;
#size-cells = <1>;
- aclk_peri_pre_div: aclk_peri_pre_div {
+ aclk_peri_div: aclk_peri_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
- clocks = <&aclk_peri_pre>;
- clock-output-names = "aclk_peri_pre";
+ clocks = <&aclk_peri>;
+ clock-output-names = "aclk_peri";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
hclk_peri_pre: hclk_peri_pre_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <8 2>;
- clocks = <&aclk_peri_pre>;
+ clocks = <&aclk_peri>;
clock-output-names = "hclk_peri_pre";
rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
rockchip,div-relations =
pclk_peri_pre: pclk_peri_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <12 2>;
- clocks = <&aclk_peri_pre>;
+ clocks = <&aclk_peri>;
clock-output-names = "pclk_peri_pre";
rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
rockchip,div-relations =
#clock-init-cells = <1>;
};
- aclk_peri_pre: aclk_peri_pre_mux {
+ aclk_peri: aclk_peri_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <14 2>;
clocks = <&clk_gpll>,<&clk_cpll>,<&clk_gpll_div2>,<&clk_gpll_div3>;
- clock-output-names = "aclk_peri_pre";
+ clock-output-names = "aclk_peri";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
clock-output-names = "clk_sdio";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
clk_emmc_div: clk_emmc_div {
clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>, <&xin24m>;
clock-output-names = "clk_emmc";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
};
clocks = <&clk_cpll>,<&clk_gpll>, <&clk_gpll_div2>;
clock-output-names = "dclk_ebc";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
/* reg[7:2]: reserved */
clk_crypto_div: clk_crypto_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 2>;
- clocks = <&aclk_cpu_pre>;
+ clocks = <&aclk_cpu>;
clock-output-names = "clk_crypto";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
#clock-cells = <0>;
rockchip,flags = <(CLK_GET_RATE_NOCACHE |
CLK_SET_RATE_NO_REPARENT)>;
- rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
+ rockchip,clkops-idx = <CLKOPS_RATE_DDR_DIV2>;
};
/* reg[7:2]: reserved */
clk_ddr: ddr_clk_pll_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <8 1>;
- clocks = <&clk_dpll>, <&clk_gpll_div2>;
+ clocks = <&clk_dpll>, <&dummy>;
clock-output-names = "clk_ddr";
#clock-cells = <0>;
};
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
- rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
clk_cif_out: clk_cif_out_mux {
clk_cif0_in: clk_cif0_in_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <7 1>;
- clocks = <&pclkin_cif>, <&dummy>;
+ clocks = <&pclkin_cif>, <&pclkin_cif_inv>;
clock-output-names = "clk_cif0_in";
#clock-cells = <0>;
#clock-init-cells = <1>;
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
clk_vepu: clk_vepu_mux {
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
clk_vdpu: clk_vdpu_mux {
#address-cells = <1>;
#size-cells = <1>;
- clk_gpu_pre_div: clk_gpu_pre_div {
+ clk_gpu_div: clk_gpu_div {
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
- clocks = <&clk_gpu_pre>;
- clock-output-names = "clk_gpu_pre";
+ clocks = <&clk_gpu>;
+ clock-output-names = "clk_gpu";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx =
rockchip,flags = <CLK_SET_RATE_PARENT_IN_ORDER>;
};
- clk_gpu_pre: clk_gpu_pre_mux {
+ clk_gpu: clk_gpu_mux {
compatible = "rockchip,rk3188-mux-con";
rockchip,bits = <5 3>;
clocks = <&clk_cpll>, <&clk_gpll>, <&clk_gpll_div2>, <&clk_gpll_div3>, <&usb480m>;
- clock-output-names = "clk_gpu_pre";
+ clock-output-names = "clk_gpu";
#clock-cells = <0>;
#clock-init-cells = <1>;
};
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
clk_hevc_core: clk_hevc_core_mux {
reg = <0x00d0 0x4>;
clocks =
<&clk_core>, <&dummy>,
- <&dummy>, <&aclk_cpu_pre>,
+ <&dummy>, <&aclk_cpu>,
- <&aclk_cpu_pre>, <&aclk_cpu_pre>,
+ <&aclk_cpu>, <&aclk_cpu>,
<&dummy>, <&clk_core>,
<&dummy>, <&clk_i2s_2ch_pll>,
<&i2s_2ch_frac>, <&hclk_vio_pre>,
- <&aclk_cpu_pre>, <&clk_i2s_2ch_out>,
+ <&aclk_cpu>, <&clk_i2s_2ch_out>,
<&clk_i2s_2ch>, <&dummy>;
clock-output-names =
- "pclk_dbg", "aclk_cpu_pre", /*clk_cpu_cpll*/
- "clk_ddr", "aclk_cpu_pre",
+ "pclk_dbg", "aclk_cpu", /*clk_cpu_cpll*/
+ "reserved", "aclk_cpu_pre",
"hclk_cpu_pre", "pclk_cpu_pre",
"clk_core", "aclk_core_pre",
"clk_crypto", "clk_i2s_2ch_out",
"clk_i2s_2ch", "clk_testout";
- rockchip,suspend-clkgating-setting=<0x0 0x0>;
+ rockchip,suspend-clkgating-setting=<0x11ff 0x0>;
#clock-cells = <1>;
};
"clk_uart2_div", "uart2_frac",
"clk_tsp", "reserved";
- rockchip,suspend-clkgating-setting=<0x0 0x0>;
+ rockchip,suspend-clkgating-setting=<0x000f 0x0>;
#clock-cells = <1>;
};
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00d8 0x4>;
clocks =
- <&dummy>, <&aclk_peri_pre>,
- <&aclk_peri_pre>, <&aclk_peri_pre>,
+ <&aclk_peri>, <&aclk_peri>,
+ <&aclk_peri>, <&aclk_peri>,
<&clk_mac_ref>, <&clk_mac_ref>,
<&clk_mac_ref>, <&clk_mac_ref>,
<&spdif_frac>, <&clk_sdio>,
<&clk_emmc>, <&xin24m>;
clock-output-names =
- "aclk_peri_pre", "aclk_peri_pre",
+ "aclk_peri", "aclk_peri_pre",
"hclk_peri_pre", "pclk_peri_pre",
"clk_mac_ref", "clk_mac_refout",
"spdif_frac", "clk_sdio",
"clk_emmc", "clk_mipi_24m";
- rockchip,suspend-clkgating-setting=<0x0 0x0>;
+ rockchip,suspend-clkgating-setting=<0x000f 0x0>;
#clock-cells = <1>;
};
<&pclk_cpu_pre>, <&clk_vepu>,
<&clk_hevc_core>, <&clk_vdpu>,
- <&hclk_vdpu>, <&clk_gpu_pre>,
- <&aclk_peri_pre>, <&clk_sfc>;
+ <&hclk_vdpu>, <&clk_gpu>,
+ <&aclk_peri>, <&clk_sfc>;
clock-output-names =
"aclk_vio0_pre", "dclk_lcdc0",
"g_pclk_hdmi", "clk_vepu",
"clk_hevc_core", "clk_vdpu",
- "hclk_vdpu", "clk_gpu_pre",
+ "hclk_vdpu", "clk_gpu",
"g_hclk_gps", "clk_sfc";
- rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
+ rockchip,suspend-clkgating-setting=<0x0060 0x0000>;
#clock-cells = <1>;
};
reg = <0x00e0 0x4>;
clocks =
<&hclk_peri_pre>, <&pclk_peri_pre>,
- <&aclk_peri_pre>, <&aclk_peri_pre>,
+ <&aclk_peri>, <&aclk_peri>,
<&clk_i2s_8ch_pll>, <&i2s_8ch_frac>,
<&clk_i2s_8ch>, <&dummy>,
<&dummy>, <&dummy>,
- <&aclk_cpu_pre>, <&dummy>,
+ <&aclk_cpu>, <&dummy>,
- <&aclk_cpu_pre>, <&dummy>,
+ <&aclk_cpu>, <&dummy>,
<&dummy>, <&dummy>;
clock-output-names =
"g_aclk_intmem", "reserved",
"reserved", "reserved";
- rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
+ rockchip,suspend-clkgating-setting = <0xff8f 0x0000>;
#clock-cells = <1>;
};
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00e4 0x4>;
clocks =
- <&pclk_cpu_pre>, <&aclk_peri_pre>,
+ <&pclk_cpu_pre>, <&aclk_peri>,
<&pclk_peri_pre>, <&dummy>,
<&pclk_cpu_pre>, <&dummy>,
"reserved", "g_hclk_otg0",
"g_pclk_acodec", "reserved";
- rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
+ rockchip,suspend-clkgating-setting = <0x00f0 0x0000>;
#clock-cells = <1>;
};
compatible = "rockchip,rk3188-gate-clk";
reg = <0x00e8 0x4>;
clocks =
- <&aclk_vio0_pre>, <&hclk_vio_pre>,
+ <&aclk_vio0_niu>, <&hclk_vio_niu>,
<&dummy>, <&dummy>,
- <&hclk_vio_pre>, <&aclk_vio0_pre>,
+ <&hclk_vio_niu>, <&aclk_vio0_niu>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>,
- <&hclk_vio_pre>, <&aclk_vio0_pre>,
+ <&hclk_vio_niu>, <&aclk_vio0_niu>,
<&hclk_vio_pre>, <&aclk_vio0_pre>,
<&dummy>, <&dummy>;
"reserved", "reserved",
"g_hclk_rga", "g_aclk_rga",
- "g_hclk_vio_bus", "g_aclk_vio",
+ "hclk_vio_niu", "aclk_vio0_niu",
"reserved", "reserved";
rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
"g_pclk_spi0", "reserved",
"g_pclk_saradc", "g_pclk_wdt";
- rockchip,suspend-clkgating-setting = <0x0000 0x0000>;
+ rockchip,suspend-clkgating-setting = <0x8480 0x0000>;
#clock-cells = <1>;
};
"g_pclk_gpio3", "reserved",
"reserved", "reserved";
- rockchip,suspend-clkgating-setting=<0x0000 0x0000>;
+ rockchip,suspend-clkgating-setting=<0xff0f 0x0000>;
#clock-cells = <1>;
};
<&dummy>, <&dummy>,
<&pclk_pmu_pre>, <&pclk_pmu_pre>,
- <&dummy>, <&hclk_vio_pre>,
- <&hclk_vio_pre>, <&hclk_vio_pre>,
+ <&dummy>, <&hclk_vio_niu>,
+ <&hclk_vio_niu>, <&hclk_vio_niu>,
- <&aclk_vio1_pre>, <&hclk_vio_pre>,
+ <&aclk_vio1_niu>, <&hclk_vio_niu>,
<&aclk_vio1_pre>, <&dummy>,
<&pclk_peri_pre>, <&hclk_peri_pre>,
- <&hclk_peri_pre>, <&aclk_peri_pre>;
+ <&hclk_peri_pre>, <&aclk_peri>;
clock-output-names =
"reserved", "reserved",
"g_pclk_mipi", "g_hclk_iep",
"g_aclk_iep", "g_hclk_ebc",
- "g_aclk_vio1_niu", "reserved",
+ "aclk_vio1_niu", "reserved",
"g_pclk_sim_card", "g_hclk_usb_peri",
"g_hclk_pe_arbi", "g_aclk_peri_niu";
- rockchip,suspend-clkgating-setting=<0x0 0x0>;
+ rockchip,suspend-clkgating-setting=<0xf00f 0x0>;
#clock-cells = <1>;
};
<&xin24m>, <&xin24m>,
<&xin24m>, <&hclk_peri_pre>,
- <&aclk_peri_pre>, <&pclk_peri_pre>,
+ <&aclk_peri>, <&pclk_peri_pre>,
<&hclk_peri_pre>, <&clk_tsp_in>,
<&hclk_peri_pre>, <&clk_nandc>;
clock-output-names =
- "clk_pvtm_core", "clk_pvtm_gpu",
- "clk_pvtm_func", "clk_timer0",
+ "g_clk_pvtm_core", "g_clk_pvtm_gpu",
+ "g_clk_pvtm_func", "clk_timer0",
"clk_timer1", "clk_timer2",
"clk_timer3", "clk_timer4",
"g_hclk_tsp", "g_clkin0_tsp",
"g_hclk_usbhost", "clk_nandc";
- rockchip,suspend-clkgating-setting = <0x0 0x0>; /* pwm logic vol */
+ rockchip,suspend-clkgating-setting = <0x0000 0x0>; /* pwm logic vol */
#clock-cells = <1>;
};