#clock-cells = <0>;
rockchip,flags = <(CLK_GET_RATE_NOCACHE |
CLK_SET_RATE_NO_REPARENT)>;
- rockchip,clkops-idx = <CLKOPS_RATE_DDR>;
+ rockchip,clkops-idx = <CLKOPS_RATE_DDR_DIV2>;
};
/* reg[7:2]: reserved */
#clock-cells = <0>;
rockchip,clkops-idx =
<CLKOPS_RATE_MUX_DIV>;
- rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
clk_cif_out: clk_cif_out_mux {