arm: dts: rk3288-evb: 32.768K clk node for BT

[firefly-linux-kernel-4.4.55.git] / arch / arm / boot / dts / integratorcp.dts

diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 72693a69f8300421f687f404ffa9f95768ea33d3..d43f15b4f79a242d2437f6ea45626556380c010c 100644 (file)
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -13,25 +13,107 @@
                bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
        };
 
-       cpcon {
-               /* CP controller registers */
+       /*
+        * The Integrator/CP overall clocking architecture can be found in
+        * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which
+        * appear to illustrate the layout used in most configurations.
+        */
+
+       /* The codec chrystal operates at 24.576 MHz */
+       xtal_codec: xtal24.576@24.576M {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <24576000>;
+       };
+
+       /* The chrystal is divided by 2 by the codec for the AACI bit clock */
+       aaci_bitclk: aaci_bitclk@12.288M {
+               #clock-cells = <0>;
+               compatible = "fixed-factor-clock";
+               clock-div = <2>;
+               clock-mult = <1>;
+               clocks = <&xtal_codec>;
+       };
+
+       /* This is a 25MHz chrystal on the base board */
+       xtal25mhz: xtal25mhz@25M {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <25000000>;
+       };
+
+       /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
+       uartclk: uartclk@14.74M {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <14745600>;
+       };
+
+       /* Actually sysclk I think */
+       pclk: pclk@0 {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <0>;
+       };
+
+       core-module@10000000 {
+               /* 24 MHz chrystal on the core module */
+               xtal24mhz: xtal24mhz@24M {
+                       #clock-cells = <0>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <24000000>;
+               };
+
+               /*
+                * External oscillator on the core module, usually used
+                * to drive video circuitry. Driven from the 24MHz clock.
+                */
+               auxosc: cm_aux_osc@25M {
+                       #clock-cells = <0>;
+                       compatible = "arm,integrator-cm-auxosc";
+                       clocks = <&xtal24mhz>;
+               };
+
+               /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
+               kmiclk: kmiclk@1M {
+                       #clock-cells = <0>;
+                       compatible = "fixed-factor-clock";
+                       clock-div = <3>;
+                       clock-mult = <1>;
+                       clocks = <&xtal24mhz>;
+               };
+
+               /* The timer clock is the 24 MHz oscillator divided to 1MHz */
+               timclk: timclk@1M {
+                       #clock-cells = <0>;
+                       compatible = "fixed-factor-clock";
+                       clock-div = <24>;
+                       clock-mult = <1>;
+                       clocks = <&xtal24mhz>;
+               };
+       };
+
+       syscon {
+               compatible = "arm,integrator-cp-syscon";
                reg = <0xcb000000 0x100>;
        };
 
        timer0: timer@13000000 {
-               /* TIMER0 runs @ 25MHz */
+               /* TIMER0 runs directly on the 25MHz chrystal */
                compatible = "arm,integrator-cp-timer";
-               status = "disabled";
+               clocks = <&xtal25mhz>;
        };
 
        timer1: timer@13000100 {
                /* TIMER1 runs @ 1MHz */
                compatible = "arm,integrator-cp-timer";
+               clocks = <&timclk>;
        };
 
        timer2: timer@13000200 {
                /* TIMER2 runs @ 1MHz */
                compatible = "arm,integrator-cp-timer";
+               clocks = <&timclk>;
        };
 
        pic: pic@14000000 {
@@ -47,8 +129,11 @@
                valid-mask = <0x00000007>;
        };
 
+       /* The SIC is cascaded off IRQ 26 on the PIC */
        sic: sic@ca000000 {
                compatible = "arm,versatile-fpga-irq";
+               interrupt-parent = <&pic>;
+               interrupts = <26>;
                #interrupt-cells = <1>;
                interrupt-controller;
                reg = <0xca000000 0x100>;
@@ -71,22 +156,32 @@
                 */
                rtc@15000000 {
                        compatible = "arm,pl031", "arm,primecell";
+                       clocks = <&pclk>;
+                       clock-names = "apb_pclk";
                };
 
                uart@16000000 {
                        compatible = "arm,pl011", "arm,primecell";
+                       clocks = <&uartclk>, <&pclk>;
+                       clock-names = "uartclk", "apb_pclk";
                };
 
                uart@17000000 {
                        compatible = "arm,pl011", "arm,primecell";
+                       clocks = <&uartclk>, <&pclk>;
+                       clock-names = "uartclk", "apb_pclk";
                };
 
                kmi@18000000 {
                        compatible = "arm,pl050", "arm,primecell";
+                       clocks = <&kmiclk>, <&pclk>;
+                       clock-names = "KMIREFCLK", "apb_pclk";
                };
 
                kmi@19000000 {
                        compatible = "arm,pl050", "arm,primecell";
+                       clocks = <&kmiclk>, <&pclk>;
+                       clock-names = "KMIREFCLK", "apb_pclk";
                };
 
                /*
@@ -97,18 +192,24 @@
                        reg = <0x1c000000 0x1000>;
                        interrupts = <23 24>;
                        max-frequency = <515633>;
+                       clocks = <&uartclk>, <&pclk>;
+                       clock-names = "mclk", "apb_pclk";
                };
 
                aaci@1d000000 {
                        compatible = "arm,pl041", "arm,primecell";
                        reg = <0x1d000000 0x1000>;
                        interrupts = <25>;
+                       clocks = <&pclk>;
+                       clock-names = "apb_pclk";
                };
 
                clcd@c0000000 {
                        compatible = "arm,pl110", "arm,primecell";
                        reg = <0xC0000000 0x1000>;
                        interrupts = <22>;
+                       clocks = <&auxosc>, <&pclk>;
+                       clock-names = "clcd", "apb_pclk";
                };
        };
 };