drm/panel: add support for Sharp F402 2048x1536 panel
[firefly-linux-kernel-4.4.55.git] / Documentation / devicetree / bindings / display / rockchip / dw_mipi_dsi_rockchip.txt
index 1ed91f92251b0fd4a62215504563eaf923c750d0..e26bfd4d819e176efb07c918985477b1af381c61 100644 (file)
@@ -5,23 +5,33 @@ Required properties:
 - #address-cells: Should be <1>.
 - #size-cells: Should be <0>.
 - compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+  or "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
   or "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
 - reg: Represent the physical address range of the controller.
 - interrupts: Represent the controller's interrupt to the CPU(s).
-- clocks, clock-names: Phandles to the controller's pll reference
-  clock(ref) and APB clock(pclk) as described in [1].
+- clocks, clock-names: Phandles to the controller's APB clock(pclk) as
+  described in [1].
 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
 - ports: contain a port node with endpoint definitions as defined in [2].
   For vopb,set the reg = <0> and set the reg = <1> for vopl.
 
 Optional properties
 - clocks, clock-names: phandle to the mipi dsi phy config clock, name should be
-  "phy_cfg".
+  "phy_cfg".phandle to the mipi dsi phy reference clock, name should be 'ref'.
+- phys: phandle to third party MIPI PHY node
+- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
+  attribute, provides phandle to MIPI PHY node
+- resets : phandle to the reset of MIPI DSI APB Clock.
+- reset-names : should be "apb".
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
+[3] Documentation/devicetree/bindings/reset/reset.txt
 
 Example:
+
+For Rockchip RK3288:
+
        mipi_dsi: mipi@ff960000 {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -64,3 +74,37 @@ Example:
                        status = "okay";
                };
        };
+
+For Rockchip RK3368:
+
+mipi_dsi_host: mipi-dsi-host@ff960000 {
+       compatible = "rockchip,rk3368-mipi-dsi";
+       phys = <&mipi_dphy>;
+       phy-names = "mipi_dphy";
+       resets = <&cru SRST_MIPIDSI0>;
+       reset-names = "apb";
+       ...
+
+       ports@1 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <1>;
+
+               mipi_in: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       mipi_in_vop: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&vop_out_mipi>;
+                       };
+               };
+       };
+
+       dsi_panel: panel@0 {
+               compatible = "simple-panel-dsi";
+               reg = <0>;
+               dsi,lanes = <4>;
+               ...
+       };
+};