sound/soc/rockchip/rockchip_i2s.c

   1 /* sound/soc/rockchip/rockchip_i2s.c
   2  *
   3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
   4  *
   5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
   6  * Author: Jianqun <jay.xu@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/delay.h>
  15 #include <linux/of_gpio.h>
  16 #include <linux/clk.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/regmap.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/dmaengine_pcm.h>
  21
  22 #include "rockchip_i2s.h"
  23
  24 #define DRV_NAME "rockchip-i2s"
  25
  26 struct rk_i2s_dev {
  27         struct device *dev;
  28
  29         struct clk *hclk;
  30         struct clk *mclk;
  31
  32         struct snd_dmaengine_dai_dma_data capture_dma_data;
  33         struct snd_dmaengine_dai_dma_data playback_dma_data;
  34
  35         struct regmap *regmap;
  36
  37 /*
  38  * Used to indicate the tx/rx status.
  39  * I2S controller hopes to start the tx and rx together,
  40  * also to stop them when they are both try to stop.
  41 */
  42         bool tx_start;
  43         bool rx_start;
  44         bool is_master_mode;
  45 };
  46
  47 static int i2s_runtime_suspend(struct device *dev)
  48 {
  49         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  50
  51         clk_disable_unprepare(i2s->mclk);
  52
  53         return 0;
  54 }
  55
  56 static int i2s_runtime_resume(struct device *dev)
  57 {
  58         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  59         int ret;
  60
  61         ret = clk_prepare_enable(i2s->mclk);
  62         if (ret) {
  63                 dev_err(i2s->dev, "clock enable failed %d\n", ret);
  64                 return ret;
  65         }
  66
  67         return 0;
  68 }
  69
  70 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
  71 {
  72         return snd_soc_dai_get_drvdata(dai);
  73 }
  74
  75 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
  76 {
  77         unsigned int val = 0;
  78         int retry = 10;
  79
  80         if (on) {
  81                 regmap_update_bits(i2s->regmap, I2S_DMACR,
  82                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
  83
  84                 regmap_update_bits(i2s->regmap, I2S_XFER,
  85                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
  86                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
  87
  88                 i2s->tx_start = true;
  89         } else {
  90                 i2s->tx_start = false;
  91
  92                 regmap_update_bits(i2s->regmap, I2S_DMACR,
  93                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
  94
  95                 if (!i2s->rx_start) {
  96                         regmap_update_bits(i2s->regmap, I2S_XFER,
  97                                            I2S_XFER_TXS_START |
  98                                            I2S_XFER_RXS_START,
  99                                            I2S_XFER_TXS_STOP |
 100                                            I2S_XFER_RXS_STOP);
 101
 102                         regmap_update_bits(i2s->regmap, I2S_CLR,
 103                                            I2S_CLR_TXC | I2S_CLR_RXC,
 104                                            I2S_CLR_TXC | I2S_CLR_RXC);
 105
 106                         regmap_read(i2s->regmap, I2S_CLR, &val);
 107
 108                         /* Should wait for clear operation to finish */
 109                         while (val) {
 110                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 111                                 retry--;
 112                                 if (!retry) {
 113                                         dev_warn(i2s->dev, "fail to clear\n");
 114                                         break;
 115                                 }
 116                         }
 117                 }
 118         }
 119 }
 120
 121 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 122 {
 123         unsigned int val = 0;
 124         int retry = 10;
 125
 126         if (on) {
 127                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 128                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
 129
 130                 regmap_update_bits(i2s->regmap, I2S_XFER,
 131                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 132                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 133
 134                 i2s->rx_start = true;
 135         } else {
 136                 i2s->rx_start = false;
 137
 138                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 139                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
 140
 141                 if (!i2s->tx_start) {
 142                         regmap_update_bits(i2s->regmap, I2S_XFER,
 143                                            I2S_XFER_TXS_START |
 144                                            I2S_XFER_RXS_START,
 145                                            I2S_XFER_TXS_STOP |
 146                                            I2S_XFER_RXS_STOP);
 147
 148                         regmap_update_bits(i2s->regmap, I2S_CLR,
 149                                            I2S_CLR_TXC | I2S_CLR_RXC,
 150                                            I2S_CLR_TXC | I2S_CLR_RXC);
 151
 152                         regmap_read(i2s->regmap, I2S_CLR, &val);
 153
 154                         /* Should wait for clear operation to finish */
 155                         while (val) {
 156                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 157                                 retry--;
 158                                 if (!retry) {
 159                                         dev_warn(i2s->dev, "fail to clear\n");
 160                                         break;
 161                                 }
 162                         }
 163                 }
 164         }
 165 }
 166
 167 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 168                                 unsigned int fmt)
 169 {
 170         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 171         unsigned int mask = 0, val = 0;
 172
 173         mask = I2S_CKR_MSS_MASK;
 174         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 175         case SND_SOC_DAIFMT_CBS_CFS:
 176                 /* Set source clock in Master mode */
 177                 val = I2S_CKR_MSS_MASTER;
 178                 i2s->is_master_mode = true;
 179                 break;
 180         case SND_SOC_DAIFMT_CBM_CFM:
 181                 val = I2S_CKR_MSS_SLAVE;
 182                 i2s->is_master_mode = false;
 183                 break;
 184         default:
 185                 return -EINVAL;
 186         }
 187
 188         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 189
 190         mask = I2S_TXCR_IBM_MASK;
 191         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 192         case SND_SOC_DAIFMT_RIGHT_J:
 193                 val = I2S_TXCR_IBM_RSJM;
 194                 break;
 195         case SND_SOC_DAIFMT_LEFT_J:
 196                 val = I2S_TXCR_IBM_LSJM;
 197                 break;
 198         case SND_SOC_DAIFMT_I2S:
 199                 val = I2S_TXCR_IBM_NORMAL;
 200                 break;
 201         default:
 202                 return -EINVAL;
 203         }
 204
 205         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
 206
 207         mask = I2S_RXCR_IBM_MASK;
 208         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 209         case SND_SOC_DAIFMT_RIGHT_J:
 210                 val = I2S_RXCR_IBM_RSJM;
 211                 break;
 212         case SND_SOC_DAIFMT_LEFT_J:
 213                 val = I2S_RXCR_IBM_LSJM;
 214                 break;
 215         case SND_SOC_DAIFMT_I2S:
 216                 val = I2S_RXCR_IBM_NORMAL;
 217                 break;
 218         default:
 219                 return -EINVAL;
 220         }
 221
 222         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
 223
 224         return 0;
 225 }
 226
 227 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 228                                   struct snd_pcm_hw_params *params,
 229                                   struct snd_soc_dai *dai)
 230 {
 231         struct rk_i2s_dev *i2s = to_info(dai);
 232         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 233         unsigned int val = 0;
 234         unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
 235
 236         if (i2s->is_master_mode) {
 237                 mclk_rate = clk_get_rate(i2s->mclk);
 238                 bclk_rate = 2 * 32 * params_rate(params);
 239                 if (bclk_rate && mclk_rate % bclk_rate)
 240                         return -EINVAL;
 241
 242                 div_bclk = mclk_rate / bclk_rate;
 243                 div_lrck = bclk_rate / params_rate(params);
 244                 regmap_update_bits(i2s->regmap, I2S_CKR,
 245                                    I2S_CKR_MDIV_MASK,
 246                                    I2S_CKR_MDIV(div_bclk));
 247
 248                 regmap_update_bits(i2s->regmap, I2S_CKR,
 249                                    I2S_CKR_TSD_MASK |
 250                                    I2S_CKR_RSD_MASK,
 251                                    I2S_CKR_TSD(div_lrck) |
 252                                    I2S_CKR_RSD(div_lrck));
 253         }
 254
 255         switch (params_format(params)) {
 256         case SNDRV_PCM_FORMAT_S8:
 257                 val |= I2S_TXCR_VDW(8);
 258                 break;
 259         case SNDRV_PCM_FORMAT_S16_LE:
 260                 val |= I2S_TXCR_VDW(16);
 261                 break;
 262         case SNDRV_PCM_FORMAT_S20_3LE:
 263                 val |= I2S_TXCR_VDW(20);
 264                 break;
 265         case SNDRV_PCM_FORMAT_S24_LE:
 266                 val |= I2S_TXCR_VDW(24);
 267                 break;
 268         default:
 269                 return -EINVAL;
 270         }
 271
 272         switch (params_channels(params)) {
 273         case 8:
 274                 val |= I2S_CHN_8;
 275                 break;
 276         case 6:
 277                 val |= I2S_CHN_6;
 278                 break;
 279         case 4:
 280                 val |= I2S_CHN_4;
 281                 break;
 282         case 2:
 283                 val |= I2S_CHN_2;
 284                 break;
 285         default:
 286                 dev_err(i2s->dev, "invalid channel: %d\n",
 287                         params_channels(params));
 288                 return -EINVAL;
 289         }
 290
 291         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 292                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 293                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 294                                    val);
 295         else
 296                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 297                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 298                                    val);
 299
 300         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
 301                            I2S_DMACR_TDL(16));
 302         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
 303                            I2S_DMACR_RDL(16));
 304
 305         val = I2S_CKR_TRCM_TXRX;
 306         if (dai->driver->symmetric_rates || rtd->dai_link->symmetric_rates)
 307                 val = I2S_CKR_TRCM_TXSHARE;
 308
 309         regmap_update_bits(i2s->regmap, I2S_CKR,
 310                            I2S_CKR_TRCM_MASK,
 311                            val);
 312         return 0;
 313 }
 314
 315 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
 316                                 int cmd, struct snd_soc_dai *dai)
 317 {
 318         struct rk_i2s_dev *i2s = to_info(dai);
 319         int ret = 0;
 320
 321         switch (cmd) {
 322         case SNDRV_PCM_TRIGGER_START:
 323         case SNDRV_PCM_TRIGGER_RESUME:
 324         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 325                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 326                         rockchip_snd_rxctrl(i2s, 1);
 327                 else
 328                         rockchip_snd_txctrl(i2s, 1);
 329                 break;
 330         case SNDRV_PCM_TRIGGER_SUSPEND:
 331         case SNDRV_PCM_TRIGGER_STOP:
 332         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 333                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 334                         rockchip_snd_rxctrl(i2s, 0);
 335                 else
 336                         rockchip_snd_txctrl(i2s, 0);
 337                 break;
 338         default:
 339                 ret = -EINVAL;
 340                 break;
 341         }
 342
 343         return ret;
 344 }
 345
 346 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
 347                                    unsigned int freq, int dir)
 348 {
 349         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 350         int ret;
 351
 352         ret = clk_set_rate(i2s->mclk, freq);
 353         if (ret)
 354                 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
 355
 356         return ret;
 357 }
 358
 359 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 360 {
 361         struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
 362
 363         dai->capture_dma_data = &i2s->capture_dma_data;
 364         dai->playback_dma_data = &i2s->playback_dma_data;
 365
 366         return 0;
 367 }
 368
 369 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 370         .hw_params = rockchip_i2s_hw_params,
 371         .set_sysclk = rockchip_i2s_set_sysclk,
 372         .set_fmt = rockchip_i2s_set_fmt,
 373         .trigger = rockchip_i2s_trigger,
 374 };
 375
 376 static struct snd_soc_dai_driver rockchip_i2s_dai = {
 377         .probe = rockchip_i2s_dai_probe,
 378         .playback = {
 379                 .stream_name = "Playback",
 380                 .channels_min = 2,
 381                 .channels_max = 8,
 382                 .rates = SNDRV_PCM_RATE_8000_192000,
 383                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 384                             SNDRV_PCM_FMTBIT_S16_LE |
 385                             SNDRV_PCM_FMTBIT_S20_3LE |
 386                             SNDRV_PCM_FMTBIT_S24_LE),
 387         },
 388         .capture = {
 389                 .stream_name = "Capture",
 390                 .channels_min = 2,
 391                 .channels_max = 2,
 392                 .rates = SNDRV_PCM_RATE_8000_192000,
 393                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 394                             SNDRV_PCM_FMTBIT_S16_LE |
 395                             SNDRV_PCM_FMTBIT_S20_3LE |
 396                             SNDRV_PCM_FMTBIT_S24_LE),
 397         },
 398         .ops = &rockchip_i2s_dai_ops,
 399         .symmetric_rates = 1,
 400 };
 401
 402 static const struct snd_soc_component_driver rockchip_i2s_component = {
 403         .name = DRV_NAME,
 404 };
 405
 406 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
 407 {
 408         switch (reg) {
 409         case I2S_TXCR:
 410         case I2S_RXCR:
 411         case I2S_CKR:
 412         case I2S_DMACR:
 413         case I2S_INTCR:
 414         case I2S_XFER:
 415         case I2S_CLR:
 416         case I2S_TXDR:
 417                 return true;
 418         default:
 419                 return false;
 420         }
 421 }
 422
 423 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
 424 {
 425         switch (reg) {
 426         case I2S_TXCR:
 427         case I2S_RXCR:
 428         case I2S_CKR:
 429         case I2S_DMACR:
 430         case I2S_INTCR:
 431         case I2S_XFER:
 432         case I2S_CLR:
 433         case I2S_RXDR:
 434         case I2S_FIFOLR:
 435         case I2S_INTSR:
 436                 return true;
 437         default:
 438                 return false;
 439         }
 440 }
 441
 442 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
 443 {
 444         switch (reg) {
 445         case I2S_INTSR:
 446         case I2S_CLR:
 447                 return true;
 448         default:
 449                 return false;
 450         }
 451 }
 452
 453 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
 454 {
 455         switch (reg) {
 456         default:
 457                 return false;
 458         }
 459 }
 460
 461 static const struct reg_default rockchip_i2s_reg_defaults[] = {
 462         {0x00, 0x0000000f},
 463         {0x04, 0x0000000f},
 464         {0x08, 0x00071f1f},
 465         {0x10, 0x001f0000},
 466         {0x14, 0x01f00000},
 467 };
 468
 469 static const struct regmap_config rockchip_i2s_regmap_config = {
 470         .reg_bits = 32,
 471         .reg_stride = 4,
 472         .val_bits = 32,
 473         .max_register = I2S_RXDR,
 474         .reg_defaults = rockchip_i2s_reg_defaults,
 475         .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
 476         .writeable_reg = rockchip_i2s_wr_reg,
 477         .readable_reg = rockchip_i2s_rd_reg,
 478         .volatile_reg = rockchip_i2s_volatile_reg,
 479         .precious_reg = rockchip_i2s_precious_reg,
 480         .cache_type = REGCACHE_FLAT,
 481 };
 482
 483 static int rockchip_i2s_probe(struct platform_device *pdev)
 484 {
 485         struct device_node *node = pdev->dev.of_node;
 486         struct rk_i2s_dev *i2s;
 487         struct resource *res;
 488         void __iomem *regs;
 489         int ret;
 490         int val;
 491
 492         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 493         if (!i2s) {
 494                 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
 495                 return -ENOMEM;
 496         }
 497
 498         /* try to prepare related clocks */
 499         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
 500         if (IS_ERR(i2s->hclk)) {
 501                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
 502                 return PTR_ERR(i2s->hclk);
 503         }
 504         ret = clk_prepare_enable(i2s->hclk);
 505         if (ret) {
 506                 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
 507                 return ret;
 508         }
 509
 510         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
 511         if (IS_ERR(i2s->mclk)) {
 512                 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
 513                 return PTR_ERR(i2s->mclk);
 514         }
 515
 516         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 517         regs = devm_ioremap_resource(&pdev->dev, res);
 518         if (IS_ERR(regs))
 519                 return PTR_ERR(regs);
 520
 521         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 522                                             &rockchip_i2s_regmap_config);
 523         if (IS_ERR(i2s->regmap)) {
 524                 dev_err(&pdev->dev,
 525                         "Failed to initialise managed register map\n");
 526                 return PTR_ERR(i2s->regmap);
 527         }
 528
 529         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 530         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 531         i2s->playback_dma_data.maxburst = 4;
 532
 533         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 534         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 535         i2s->capture_dma_data.maxburst = 4;
 536
 537         i2s->dev = &pdev->dev;
 538         dev_set_drvdata(&pdev->dev, i2s);
 539
 540         pm_runtime_enable(&pdev->dev);
 541         if (!pm_runtime_enabled(&pdev->dev)) {
 542                 ret = i2s_runtime_resume(&pdev->dev);
 543                 if (ret)
 544                         goto err_pm_disable;
 545         }
 546
 547         /* refine capture channels */
 548         if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
 549                 if (val >= 2 && val <= 8)
 550                         rockchip_i2s_dai.capture.channels_max = val;
 551                 else
 552                         rockchip_i2s_dai.capture.channels_max = 2;
 553         }
 554
 555         ret = devm_snd_soc_register_component(&pdev->dev,
 556                                               &rockchip_i2s_component,
 557                                               &rockchip_i2s_dai, 1);
 558         if (ret) {
 559                 dev_err(&pdev->dev, "Could not register DAI\n");
 560                 goto err_suspend;
 561         }
 562
 563         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 564         if (ret) {
 565                 dev_err(&pdev->dev, "Could not register PCM\n");
 566                 return ret;
 567         }
 568
 569         return 0;
 570
 571 err_suspend:
 572         if (!pm_runtime_status_suspended(&pdev->dev))
 573                 i2s_runtime_suspend(&pdev->dev);
 574 err_pm_disable:
 575         pm_runtime_disable(&pdev->dev);
 576
 577         return ret;
 578 }
 579
 580 static int rockchip_i2s_remove(struct platform_device *pdev)
 581 {
 582         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
 583
 584         pm_runtime_disable(&pdev->dev);
 585         if (!pm_runtime_status_suspended(&pdev->dev))
 586                 i2s_runtime_suspend(&pdev->dev);
 587
 588         clk_disable_unprepare(i2s->mclk);
 589         clk_disable_unprepare(i2s->hclk);
 590
 591         return 0;
 592 }
 593
 594 static const struct of_device_id rockchip_i2s_match[] = {
 595         { .compatible = "rockchip,rk3066-i2s", },
 596         {},
 597 };
 598
 599 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
 600         SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
 601                            NULL)
 602 };
 603
 604 static struct platform_driver rockchip_i2s_driver = {
 605         .probe = rockchip_i2s_probe,
 606         .remove = rockchip_i2s_remove,
 607         .driver = {
 608                 .name = DRV_NAME,
 609                 .of_match_table = of_match_ptr(rockchip_i2s_match),
 610                 .pm = &rockchip_i2s_pm_ops,
 611         },
 612 };
 613 module_platform_driver(rockchip_i2s_driver);
 614
 615 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
 616 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
 617 MODULE_LICENSE("GPL v2");
 618 MODULE_ALIAS("platform:" DRV_NAME);
 619 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);