sound/soc/rockchip/rockchip_i2s.c

   1 /* sound/soc/rockchip/rockchip_i2s.c
   2  *
   3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
   4  *
   5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
   6  * Author: Jianqun <jay.xu@rock-chips.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/mfd/syscon.h>
  15 #include <linux/delay.h>
  16 #include <linux/of_gpio.h>
  17 #include <linux/of_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21 #include <sound/pcm_params.h>
  22 #include <sound/dmaengine_pcm.h>
  23
  24 #include "rockchip_i2s.h"
  25
  26 #define DRV_NAME "rockchip-i2s"
  27
  28 struct rk_i2s_pins {
  29         u32 reg_offset;
  30         u32 shift;
  31 };
  32
  33 struct rk_i2s_dev {
  34         struct device *dev;
  35
  36         struct clk *hclk;
  37         struct clk *mclk;
  38
  39         struct snd_dmaengine_dai_dma_data capture_dma_data;
  40         struct snd_dmaengine_dai_dma_data playback_dma_data;
  41
  42         struct regmap *regmap;
  43         struct regmap *grf;
  44
  45 /*
  46  * Used to indicate the tx/rx status.
  47  * I2S controller hopes to start the tx and rx together,
  48  * also to stop them when they are both try to stop.
  49 */
  50         bool tx_start;
  51         bool rx_start;
  52         bool is_master_mode;
  53         const struct rk_i2s_pins *pins;
  54         unsigned int bclk_fs;
  55 };
  56
  57 static int i2s_runtime_suspend(struct device *dev)
  58 {
  59         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  60
  61         regcache_cache_only(i2s->regmap, true);
  62         clk_disable_unprepare(i2s->mclk);
  63
  64         return 0;
  65 }
  66
  67 static int i2s_runtime_resume(struct device *dev)
  68 {
  69         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
  70         int ret;
  71
  72         ret = clk_prepare_enable(i2s->mclk);
  73         if (ret) {
  74                 dev_err(i2s->dev, "clock enable failed %d\n", ret);
  75                 return ret;
  76         }
  77
  78         regcache_cache_only(i2s->regmap, false);
  79         regcache_mark_dirty(i2s->regmap);
  80
  81         ret = regcache_sync(i2s->regmap);
  82         if (ret)
  83                 clk_disable_unprepare(i2s->mclk);
  84
  85         return ret;
  86 }
  87
  88 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
  89 {
  90         return snd_soc_dai_get_drvdata(dai);
  91 }
  92
  93 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
  94 {
  95         unsigned int val = 0;
  96         int retry = 10;
  97
  98         if (on) {
  99                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 100                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
 101
 102                 regmap_update_bits(i2s->regmap, I2S_XFER,
 103                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 104                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 105
 106                 i2s->tx_start = true;
 107         } else {
 108                 i2s->tx_start = false;
 109
 110                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 111                                    I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
 112
 113                 if (!i2s->rx_start) {
 114                         regmap_update_bits(i2s->regmap, I2S_XFER,
 115                                            I2S_XFER_TXS_START |
 116                                            I2S_XFER_RXS_START,
 117                                            I2S_XFER_TXS_STOP |
 118                                            I2S_XFER_RXS_STOP);
 119
 120                         udelay(150);
 121                         regmap_update_bits(i2s->regmap, I2S_CLR,
 122                                            I2S_CLR_TXC | I2S_CLR_RXC,
 123                                            I2S_CLR_TXC | I2S_CLR_RXC);
 124
 125                         regmap_read(i2s->regmap, I2S_CLR, &val);
 126
 127                         /* Should wait for clear operation to finish */
 128                         while (val) {
 129                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 130                                 retry--;
 131                                 if (!retry) {
 132                                         dev_warn(i2s->dev, "fail to clear\n");
 133                                         break;
 134                                 }
 135                         }
 136                 }
 137         }
 138 }
 139
 140 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 141 {
 142         unsigned int val = 0;
 143         int retry = 10;
 144
 145         if (on) {
 146                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 147                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
 148
 149                 regmap_update_bits(i2s->regmap, I2S_XFER,
 150                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START,
 151                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 152
 153                 i2s->rx_start = true;
 154         } else {
 155                 i2s->rx_start = false;
 156
 157                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 158                                    I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
 159
 160                 if (!i2s->tx_start) {
 161                         regmap_update_bits(i2s->regmap, I2S_XFER,
 162                                            I2S_XFER_TXS_START |
 163                                            I2S_XFER_RXS_START,
 164                                            I2S_XFER_TXS_STOP |
 165                                            I2S_XFER_RXS_STOP);
 166
 167                         udelay(150);
 168                         regmap_update_bits(i2s->regmap, I2S_CLR,
 169                                            I2S_CLR_TXC | I2S_CLR_RXC,
 170                                            I2S_CLR_TXC | I2S_CLR_RXC);
 171
 172                         regmap_read(i2s->regmap, I2S_CLR, &val);
 173
 174                         /* Should wait for clear operation to finish */
 175                         while (val) {
 176                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 177                                 retry--;
 178                                 if (!retry) {
 179                                         dev_warn(i2s->dev, "fail to clear\n");
 180                                         break;
 181                                 }
 182                         }
 183                 }
 184         }
 185 }
 186
 187 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 188                                 unsigned int fmt)
 189 {
 190         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 191         unsigned int mask = 0, val = 0;
 192
 193         mask = I2S_CKR_MSS_MASK;
 194         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 195         case SND_SOC_DAIFMT_CBS_CFS:
 196                 /* Set source clock in Master mode */
 197                 val = I2S_CKR_MSS_MASTER;
 198                 i2s->is_master_mode = true;
 199                 break;
 200         case SND_SOC_DAIFMT_CBM_CFM:
 201                 val = I2S_CKR_MSS_SLAVE;
 202                 i2s->is_master_mode = false;
 203                 break;
 204         default:
 205                 return -EINVAL;
 206         }
 207
 208         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 209
 210         mask = I2S_CKR_CKP_MASK;
 211         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 212         case SND_SOC_DAIFMT_NB_NF:
 213                 val = I2S_CKR_CKP_NEG;
 214                 break;
 215         case SND_SOC_DAIFMT_IB_NF:
 216                 val = I2S_CKR_CKP_POS;
 217                 break;
 218         default:
 219                 return -EINVAL;
 220         }
 221
 222         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 223
 224         mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK;
 225         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 226         case SND_SOC_DAIFMT_RIGHT_J:
 227                 val = I2S_TXCR_IBM_RSJM;
 228                 break;
 229         case SND_SOC_DAIFMT_LEFT_J:
 230                 val = I2S_TXCR_IBM_LSJM;
 231                 break;
 232         case SND_SOC_DAIFMT_I2S:
 233                 val = I2S_TXCR_IBM_NORMAL;
 234                 break;
 235         case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
 236                 val = I2S_TXCR_TFS_PCM;
 237                 break;
 238         case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
 239                 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1);
 240                 break;
 241         default:
 242                 return -EINVAL;
 243         }
 244
 245         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
 246
 247         mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK;
 248         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 249         case SND_SOC_DAIFMT_RIGHT_J:
 250                 val = I2S_RXCR_IBM_RSJM;
 251                 break;
 252         case SND_SOC_DAIFMT_LEFT_J:
 253                 val = I2S_RXCR_IBM_LSJM;
 254                 break;
 255         case SND_SOC_DAIFMT_I2S:
 256                 val = I2S_RXCR_IBM_NORMAL;
 257                 break;
 258         case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */
 259                 val = I2S_RXCR_TFS_PCM;
 260                 break;
 261         case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */
 262                 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1);
 263                 break;
 264         default:
 265                 return -EINVAL;
 266         }
 267
 268         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
 269
 270         return 0;
 271 }
 272
 273 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 274                                   struct snd_pcm_hw_params *params,
 275                                   struct snd_soc_dai *dai)
 276 {
 277         struct rk_i2s_dev *i2s = to_info(dai);
 278         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 279         unsigned int val = 0;
 280         unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
 281
 282         if (i2s->is_master_mode) {
 283                 mclk_rate = clk_get_rate(i2s->mclk);
 284                 bclk_rate = i2s->bclk_fs * params_rate(params);
 285                 if (bclk_rate && mclk_rate % bclk_rate)
 286                         return -EINVAL;
 287
 288                 div_bclk = mclk_rate / bclk_rate;
 289                 div_lrck = bclk_rate / params_rate(params);
 290                 regmap_update_bits(i2s->regmap, I2S_CKR,
 291                                    I2S_CKR_MDIV_MASK,
 292                                    I2S_CKR_MDIV(div_bclk));
 293
 294                 regmap_update_bits(i2s->regmap, I2S_CKR,
 295                                    I2S_CKR_TSD_MASK |
 296                                    I2S_CKR_RSD_MASK,
 297                                    I2S_CKR_TSD(div_lrck) |
 298                                    I2S_CKR_RSD(div_lrck));
 299         }
 300
 301         switch (params_format(params)) {
 302         case SNDRV_PCM_FORMAT_S8:
 303                 val |= I2S_TXCR_VDW(8);
 304                 break;
 305         case SNDRV_PCM_FORMAT_S16_LE:
 306                 val |= I2S_TXCR_VDW(16);
 307                 break;
 308         case SNDRV_PCM_FORMAT_S20_3LE:
 309                 val |= I2S_TXCR_VDW(20);
 310                 break;
 311         case SNDRV_PCM_FORMAT_S24_LE:
 312                 val |= I2S_TXCR_VDW(24);
 313                 break;
 314         case SNDRV_PCM_FORMAT_S32_LE:
 315                 val |= I2S_TXCR_VDW(32);
 316                 break;
 317         default:
 318                 return -EINVAL;
 319         }
 320
 321         switch (params_channels(params)) {
 322         case 8:
 323                 val |= I2S_CHN_8;
 324                 break;
 325         case 6:
 326                 val |= I2S_CHN_6;
 327                 break;
 328         case 4:
 329                 val |= I2S_CHN_4;
 330                 break;
 331         case 2:
 332                 val |= I2S_CHN_2;
 333                 break;
 334         default:
 335                 dev_err(i2s->dev, "invalid channel: %d\n",
 336                         params_channels(params));
 337                 return -EINVAL;
 338         }
 339
 340         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 341                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 342                                    I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
 343                                    val);
 344         else
 345                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 346                                    I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
 347                                    val);
 348
 349         if (!IS_ERR(i2s->grf) && i2s->pins) {
 350                 regmap_read(i2s->regmap, I2S_TXCR, &val);
 351                 val &= I2S_TXCR_CSR_MASK;
 352
 353                 switch (val) {
 354                 case I2S_CHN_4:
 355                         val = I2S_IO_4CH_OUT_6CH_IN;
 356                         break;
 357                 case I2S_CHN_6:
 358                         val = I2S_IO_6CH_OUT_4CH_IN;
 359                         break;
 360                 case I2S_CHN_8:
 361                         val = I2S_IO_8CH_OUT_2CH_IN;
 362                         break;
 363                 default:
 364                         val = I2S_IO_2CH_OUT_8CH_IN;
 365                         break;
 366                 }
 367
 368                 val <<= i2s->pins->shift;
 369                 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
 370                 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
 371         }
 372
 373         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
 374                            I2S_DMACR_TDL(16));
 375         regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
 376                            I2S_DMACR_RDL(16));
 377
 378         val = I2S_CKR_TRCM_TXRX;
 379         if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
 380                 val = I2S_CKR_TRCM_TXONLY;
 381
 382         regmap_update_bits(i2s->regmap, I2S_CKR,
 383                            I2S_CKR_TRCM_MASK,
 384                            val);
 385         return 0;
 386 }
 387
 388 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
 389                                 int cmd, struct snd_soc_dai *dai)
 390 {
 391         struct rk_i2s_dev *i2s = to_info(dai);
 392         int ret = 0;
 393
 394         switch (cmd) {
 395         case SNDRV_PCM_TRIGGER_START:
 396         case SNDRV_PCM_TRIGGER_RESUME:
 397         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 398                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 399                         rockchip_snd_rxctrl(i2s, 1);
 400                 else
 401                         rockchip_snd_txctrl(i2s, 1);
 402                 break;
 403         case SNDRV_PCM_TRIGGER_SUSPEND:
 404         case SNDRV_PCM_TRIGGER_STOP:
 405         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 406                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 407                         rockchip_snd_rxctrl(i2s, 0);
 408                 else
 409                         rockchip_snd_txctrl(i2s, 0);
 410                 break;
 411         default:
 412                 ret = -EINVAL;
 413                 break;
 414         }
 415
 416         return ret;
 417 }
 418
 419 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
 420                                    unsigned int freq, int dir)
 421 {
 422         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 423         int ret;
 424
 425         ret = clk_set_rate(i2s->mclk, freq);
 426         if (ret)
 427                 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
 428
 429         return ret;
 430 }
 431
 432 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 433 {
 434         struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
 435
 436         dai->capture_dma_data = &i2s->capture_dma_data;
 437         dai->playback_dma_data = &i2s->playback_dma_data;
 438
 439         return 0;
 440 }
 441
 442 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 443         .hw_params = rockchip_i2s_hw_params,
 444         .set_sysclk = rockchip_i2s_set_sysclk,
 445         .set_fmt = rockchip_i2s_set_fmt,
 446         .trigger = rockchip_i2s_trigger,
 447 };
 448
 449 static struct snd_soc_dai_driver rockchip_i2s_dai = {
 450         .probe = rockchip_i2s_dai_probe,
 451         .playback = {
 452                 .stream_name = "Playback",
 453                 .channels_min = 2,
 454                 .channels_max = 8,
 455                 .rates = SNDRV_PCM_RATE_8000_192000,
 456                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 457                             SNDRV_PCM_FMTBIT_S16_LE |
 458                             SNDRV_PCM_FMTBIT_S20_3LE |
 459                             SNDRV_PCM_FMTBIT_S24_LE |
 460                             SNDRV_PCM_FMTBIT_S32_LE),
 461         },
 462         .capture = {
 463                 .stream_name = "Capture",
 464                 .channels_min = 2,
 465                 .channels_max = 2,
 466                 .rates = SNDRV_PCM_RATE_8000_192000,
 467                 .formats = (SNDRV_PCM_FMTBIT_S8 |
 468                             SNDRV_PCM_FMTBIT_S16_LE |
 469                             SNDRV_PCM_FMTBIT_S20_3LE |
 470                             SNDRV_PCM_FMTBIT_S24_LE |
 471                             SNDRV_PCM_FMTBIT_S32_LE),
 472         },
 473         .ops = &rockchip_i2s_dai_ops,
 474         .symmetric_rates = 1,
 475 };
 476
 477 static const struct snd_soc_component_driver rockchip_i2s_component = {
 478         .name = DRV_NAME,
 479 };
 480
 481 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
 482 {
 483         switch (reg) {
 484         case I2S_TXCR:
 485         case I2S_RXCR:
 486         case I2S_CKR:
 487         case I2S_DMACR:
 488         case I2S_INTCR:
 489         case I2S_XFER:
 490         case I2S_CLR:
 491         case I2S_TXDR:
 492                 return true;
 493         default:
 494                 return false;
 495         }
 496 }
 497
 498 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
 499 {
 500         switch (reg) {
 501         case I2S_TXCR:
 502         case I2S_RXCR:
 503         case I2S_CKR:
 504         case I2S_DMACR:
 505         case I2S_INTCR:
 506         case I2S_XFER:
 507         case I2S_CLR:
 508         case I2S_RXDR:
 509         case I2S_FIFOLR:
 510         case I2S_INTSR:
 511                 return true;
 512         default:
 513                 return false;
 514         }
 515 }
 516
 517 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
 518 {
 519         switch (reg) {
 520         case I2S_INTSR:
 521         case I2S_CLR:
 522                 return true;
 523         default:
 524                 return false;
 525         }
 526 }
 527
 528 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
 529 {
 530         switch (reg) {
 531         default:
 532                 return false;
 533         }
 534 }
 535
 536 static const struct reg_default rockchip_i2s_reg_defaults[] = {
 537         {0x00, 0x0000000f},
 538         {0x04, 0x0000000f},
 539         {0x08, 0x00071f1f},
 540         {0x10, 0x001f0000},
 541         {0x14, 0x01f00000},
 542 };
 543
 544 static const struct regmap_config rockchip_i2s_regmap_config = {
 545         .reg_bits = 32,
 546         .reg_stride = 4,
 547         .val_bits = 32,
 548         .max_register = I2S_RXDR,
 549         .reg_defaults = rockchip_i2s_reg_defaults,
 550         .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
 551         .writeable_reg = rockchip_i2s_wr_reg,
 552         .readable_reg = rockchip_i2s_rd_reg,
 553         .volatile_reg = rockchip_i2s_volatile_reg,
 554         .precious_reg = rockchip_i2s_precious_reg,
 555         .cache_type = REGCACHE_FLAT,
 556 };
 557
 558 static const struct rk_i2s_pins rk3399_i2s_pins = {
 559         .reg_offset = 0xe220,
 560         .shift = 11,
 561 };
 562
 563 static const struct of_device_id rockchip_i2s_match[] = {
 564         { .compatible = "rockchip,rk3066-i2s", },
 565         { .compatible = "rockchip,rk3188-i2s", },
 566         { .compatible = "rockchip,rk3288-i2s", },
 567         { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
 568         {},
 569 };
 570
 571 static int rockchip_i2s_probe(struct platform_device *pdev)
 572 {
 573         struct device_node *node = pdev->dev.of_node;
 574         const struct of_device_id *of_id;
 575         struct rk_i2s_dev *i2s;
 576         struct snd_soc_dai_driver *soc_dai;
 577         struct resource *res;
 578         void __iomem *regs;
 579         int ret;
 580         int val;
 581
 582         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 583         if (!i2s) {
 584                 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
 585                 return -ENOMEM;
 586         }
 587
 588         i2s->dev = &pdev->dev;
 589
 590         i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
 591         if (!IS_ERR(i2s->grf)) {
 592                 of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
 593                 if (!of_id || !of_id->data)
 594                         return -EINVAL;
 595
 596                 i2s->pins = of_id->data;
 597         }
 598
 599         /* try to prepare related clocks */
 600         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
 601         if (IS_ERR(i2s->hclk)) {
 602                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
 603                 return PTR_ERR(i2s->hclk);
 604         }
 605         ret = clk_prepare_enable(i2s->hclk);
 606         if (ret) {
 607                 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
 608                 return ret;
 609         }
 610
 611         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
 612         if (IS_ERR(i2s->mclk)) {
 613                 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
 614                 return PTR_ERR(i2s->mclk);
 615         }
 616
 617         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 618         regs = devm_ioremap_resource(&pdev->dev, res);
 619         if (IS_ERR(regs))
 620                 return PTR_ERR(regs);
 621
 622         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 623                                             &rockchip_i2s_regmap_config);
 624         if (IS_ERR(i2s->regmap)) {
 625                 dev_err(&pdev->dev,
 626                         "Failed to initialise managed register map\n");
 627                 return PTR_ERR(i2s->regmap);
 628         }
 629
 630         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 631         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 632         i2s->playback_dma_data.maxburst = 16;
 633
 634         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 635         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 636         i2s->capture_dma_data.maxburst = 16;
 637
 638         dev_set_drvdata(&pdev->dev, i2s);
 639
 640         pm_runtime_enable(&pdev->dev);
 641         if (!pm_runtime_enabled(&pdev->dev)) {
 642                 ret = i2s_runtime_resume(&pdev->dev);
 643                 if (ret)
 644                         goto err_pm_disable;
 645         }
 646
 647         soc_dai = devm_kzalloc(&pdev->dev,
 648                                sizeof(*soc_dai), GFP_KERNEL);
 649         if (!soc_dai)
 650                 return -ENOMEM;
 651
 652         memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
 653         if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
 654                 if (val >= 2 && val <= 8)
 655                         soc_dai->playback.channels_max = val;
 656         }
 657
 658         if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
 659                 if (val >= 2 && val <= 8)
 660                         soc_dai->capture.channels_max = val;
 661         }
 662
 663         i2s->bclk_fs = 64;
 664         if (!of_property_read_u32(node, "rockchip,bclk-fs", &val)) {
 665                 if ((val >= 32) && (val % 2 == 0))
 666                         i2s->bclk_fs = val;
 667         }
 668
 669         ret = devm_snd_soc_register_component(&pdev->dev,
 670                                               &rockchip_i2s_component,
 671                                               soc_dai, 1);
 672
 673         if (ret) {
 674                 dev_err(&pdev->dev, "Could not register DAI\n");
 675                 goto err_suspend;
 676         }
 677
 678         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 679         if (ret) {
 680                 dev_err(&pdev->dev, "Could not register PCM\n");
 681                 return ret;
 682         }
 683
 684         return 0;
 685
 686 err_suspend:
 687         if (!pm_runtime_status_suspended(&pdev->dev))
 688                 i2s_runtime_suspend(&pdev->dev);
 689 err_pm_disable:
 690         pm_runtime_disable(&pdev->dev);
 691
 692         return ret;
 693 }
 694
 695 static int rockchip_i2s_remove(struct platform_device *pdev)
 696 {
 697         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
 698
 699         pm_runtime_disable(&pdev->dev);
 700         if (!pm_runtime_status_suspended(&pdev->dev))
 701                 i2s_runtime_suspend(&pdev->dev);
 702
 703         clk_disable_unprepare(i2s->mclk);
 704         clk_disable_unprepare(i2s->hclk);
 705
 706         return 0;
 707 }
 708
 709 #ifdef CONFIG_PM_SLEEP
 710 static int rockchip_i2s_suspend(struct device *dev)
 711 {
 712         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 713
 714         regcache_mark_dirty(i2s->regmap);
 715
 716         return 0;
 717 }
 718
 719 static int rockchip_i2s_resume(struct device *dev)
 720 {
 721         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 722         int ret;
 723
 724         ret = pm_runtime_get_sync(dev);
 725         if (ret < 0)
 726                 return ret;
 727         ret = regcache_sync(i2s->regmap);
 728         pm_runtime_put(dev);
 729
 730         return ret;
 731 }
 732 #endif
 733
 734 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
 735         SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
 736                            NULL)
 737         SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_suspend, rockchip_i2s_resume)
 738 };
 739
 740 static struct platform_driver rockchip_i2s_driver = {
 741         .probe = rockchip_i2s_probe,
 742         .remove = rockchip_i2s_remove,
 743         .driver = {
 744                 .name = DRV_NAME,
 745                 .of_match_table = of_match_ptr(rockchip_i2s_match),
 746                 .pm = &rockchip_i2s_pm_ops,
 747         },
 748 };
 749 module_platform_driver(rockchip_i2s_driver);
 750
 751 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
 752 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
 753 MODULE_LICENSE("GPL v2");
 754 MODULE_ALIAS("platform:" DRV_NAME);
 755 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);