sound/soc/rockchip/rk30_i2s.c

   1 /*
   2  * Rockchip I2S ALSA SoC Digital Audio Interface(DAI)  driver
   3  *
   4  * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/module.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/device.h>
  21 #include <linux/delay.h>
  22 #include <linux/clk.h>
  23 #include <linux/version.h>
  24 #include <linux/of.h>
  25 #include <linux/of_gpio.h>
  26 #include <linux/io.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/regmap.h>
  30 #include <linux/rockchip/cpu.h>
  31 #include <linux/rockchip/cru.h>
  32 #include <linux/rockchip/grf.h>
  33 #include <linux/slab.h>
  34 #include <asm/dma.h>
  35 #include <sound/core.h>
  36 #include <sound/pcm.h>
  37 #include <sound/pcm_params.h>
  38 #include <sound/initval.h>
  39 #include <sound/soc.h>
  40 #include <sound/dmaengine_pcm.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/workqueue.h>
  43
  44 #include "rk_pcm.h"
  45 #include "rk_i2s.h"
  46
  47 #define CLK_SET_LATER
  48 #define I2S_DEFAULT_FREQ        (11289600)
  49 #define I2S_DMA_BURST_SIZE      (16) /* size * width: 16*4 = 64 bytes */
  50 static DEFINE_SPINLOCK(lock);
  51
  52 #if defined(CONFIG_RK_HDMI) && defined(CONFIG_SND_RK_SOC_HDMI_I2S)
  53 extern int snd_config_hdmi_audio(struct snd_pcm_hw_params *params);
  54 #endif
  55
  56 struct rk_i2s_dev {
  57         struct device *dev;
  58         struct clk *clk; /* bclk */
  59         struct clk *mclk; /*mclk output only */
  60         struct clk *hclk; /*ahb clk */
  61         struct snd_dmaengine_dai_dma_data capture_dma_data;
  62         struct snd_dmaengine_dai_dma_data playback_dma_data;
  63         struct regmap *regmap;
  64         bool tx_start;
  65         bool rx_start;
  66 #ifdef CLK_SET_LATER
  67         struct delayed_work clk_delayed_work;
  68 #endif
  69 };
  70
  71 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
  72 {
  73         return snd_soc_dai_get_drvdata(dai);
  74 }
  75
  76 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
  77 {
  78         unsigned long flags;
  79         unsigned int val = 0;
  80         int retry = 10;
  81
  82         spin_lock_irqsave(&lock, flags);
  83
  84         dev_dbg(i2s->dev, "%s: %d: on: %d\n", __func__, __LINE__, on);
  85
  86         if (on) {
  87                 regmap_update_bits(i2s->regmap, I2S_DMACR,
  88                                    I2S_DMACR_TDE_MASK, I2S_DMACR_TDE_ENABLE);
  89
  90                 regmap_update_bits(i2s->regmap, I2S_XFER,
  91                                    I2S_XFER_TXS_MASK | I2S_XFER_RXS_MASK,
  92                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
  93
  94                 i2s->tx_start = true;
  95         } else {
  96                 i2s->tx_start = false;
  97
  98                 regmap_update_bits(i2s->regmap, I2S_DMACR,
  99                                    I2S_DMACR_TDE_MASK, I2S_DMACR_TDE_DISABLE);
 100
 101
 102                 if (!i2s->rx_start) {
 103                         regmap_update_bits(i2s->regmap, I2S_XFER,
 104                                            I2S_XFER_TXS_MASK |
 105                                            I2S_XFER_RXS_MASK,
 106                                            I2S_XFER_TXS_STOP |
 107                                            I2S_XFER_RXS_STOP);
 108
 109                         regmap_update_bits(i2s->regmap, I2S_CLR,
 110                                            I2S_CLR_TXC_MASK | I2S_CLR_RXC_MASK,
 111                                            I2S_CLR_TXC | I2S_CLR_RXC);
 112
 113                         regmap_read(i2s->regmap, I2S_CLR, &val);
 114
 115                         /* Should wait for clear operation to finish */
 116                         while (val) {
 117                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 118                                 retry--;
 119                                 if (!retry) {
 120                                         dev_warn(i2s->dev, "fail to clear\n");
 121                                         break;
 122                                 }
 123                         }
 124                         dev_dbg(i2s->dev, "%s: %d: stop xfer\n",
 125                                 __func__, __LINE__);
 126                 }
 127         }
 128
 129         spin_unlock_irqrestore(&lock, flags);
 130 }
 131
 132 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
 133 {
 134         unsigned long flags;
 135         unsigned int val = 0;
 136         int retry = 10;
 137
 138         spin_lock_irqsave(&lock, flags);
 139
 140         dev_dbg(i2s->dev, "%s: %d: on: %d\n", __func__, __LINE__, on);
 141
 142         if (on) {
 143                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 144                                    I2S_DMACR_RDE_MASK, I2S_DMACR_RDE_ENABLE);
 145
 146                 regmap_update_bits(i2s->regmap, I2S_XFER,
 147                                    I2S_XFER_TXS_MASK | I2S_XFER_RXS_MASK,
 148                                    I2S_XFER_TXS_START | I2S_XFER_RXS_START);
 149
 150                 i2s->rx_start = true;
 151         } else {
 152                 i2s->rx_start = false;
 153
 154                 regmap_update_bits(i2s->regmap, I2S_DMACR,
 155                                    I2S_DMACR_RDE_MASK, I2S_DMACR_RDE_DISABLE);
 156
 157                 if (!i2s->tx_start) {
 158                         regmap_update_bits(i2s->regmap, I2S_XFER,
 159                                            I2S_XFER_TXS_MASK |
 160                                            I2S_XFER_RXS_MASK,
 161                                            I2S_XFER_TXS_STOP |
 162                                            I2S_XFER_RXS_STOP);
 163
 164                         regmap_update_bits(i2s->regmap, I2S_CLR,
 165                                            I2S_CLR_TXC_MASK | I2S_CLR_RXC_MASK,
 166                                            I2S_CLR_TXC | I2S_CLR_RXC);
 167
 168                         regmap_read(i2s->regmap, I2S_CLR, &val);
 169
 170                         /* Should wait for clear operation to finish */
 171                         while (val) {
 172                                 regmap_read(i2s->regmap, I2S_CLR, &val);
 173                                 retry--;
 174                                 if (!retry) {
 175                                         dev_warn(i2s->dev, "fail to clear\n");
 176                                         break;
 177                                 }
 178                         }
 179                         dev_dbg(i2s->dev, "%s: %d: stop xfer\n",
 180                                 __func__, __LINE__);
 181                 }
 182         }
 183
 184         spin_unlock_irqrestore(&lock, flags);
 185 }
 186
 187 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 188                                 unsigned int fmt)
 189 {
 190         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 191         unsigned int mask = 0, val = 0;
 192         int ret = 0;
 193         unsigned long flags;
 194
 195         spin_lock_irqsave(&lock, flags);
 196
 197         mask = I2S_CKR_MSS_MASK;
 198         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 199         case SND_SOC_DAIFMT_CBS_CFS:
 200                 /* Codec is slave, so set cpu master */
 201                 val = I2S_CKR_MSS_MASTER;
 202                 break;
 203         case SND_SOC_DAIFMT_CBM_CFM:
 204                 /* Codec is master, so set cpu slave */
 205                 val = I2S_CKR_MSS_SLAVE;
 206                 break;
 207         default:
 208                 ret = -EINVAL;
 209                 goto err_fmt;
 210         }
 211
 212         regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
 213
 214         mask = I2S_TXCR_IBM_MASK;
 215         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 216         case SND_SOC_DAIFMT_RIGHT_J:
 217                 val = I2S_TXCR_IBM_RSJM;
 218                 break;
 219         case SND_SOC_DAIFMT_LEFT_J:
 220                 val = I2S_TXCR_IBM_LSJM;
 221                 break;
 222         case SND_SOC_DAIFMT_I2S:
 223                 val = I2S_TXCR_IBM_NORMAL;
 224                 break;
 225         default:
 226                 ret = -EINVAL;
 227                 goto err_fmt;
 228         }
 229
 230         regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
 231
 232         mask = I2S_RXCR_IBM_MASK;
 233         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 234         case SND_SOC_DAIFMT_RIGHT_J:
 235                 val = I2S_RXCR_IBM_RSJM;
 236                 break;
 237         case SND_SOC_DAIFMT_LEFT_J:
 238                 val = I2S_RXCR_IBM_LSJM;
 239                 break;
 240         case SND_SOC_DAIFMT_I2S:
 241                 val = I2S_RXCR_IBM_NORMAL;
 242                 break;
 243         default:
 244                 ret = -EINVAL;
 245                 goto err_fmt;
 246         }
 247
 248         regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
 249
 250 err_fmt:
 251
 252         spin_unlock_irqrestore(&lock, flags);
 253         return ret;
 254 }
 255
 256 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 257                                   struct snd_pcm_hw_params *params,
 258                                   struct snd_soc_dai *dai)
 259 {
 260         struct rk_i2s_dev *i2s = to_info(dai);
 261         unsigned int val = 0;
 262         unsigned long flags;
 263
 264         spin_lock_irqsave(&lock, flags);
 265
 266         dev_dbg(i2s->dev, "%s: %d\n", __func__, __LINE__);
 267
 268         switch (params_format(params)) {
 269         case SNDRV_PCM_FORMAT_S8:
 270                 val |= I2S_TXCR_VDW(8);
 271                 break;
 272         case SNDRV_PCM_FORMAT_S16_LE:
 273                 val |= I2S_TXCR_VDW(16);
 274                 break;
 275         case SNDRV_PCM_FORMAT_S20_3LE:
 276                 val |= I2S_TXCR_VDW(20);
 277                 break;
 278         case SNDRV_PCM_FORMAT_S24_LE:
 279         case SNDRV_PCM_FORMAT_S24_3LE:
 280                 val |= I2S_TXCR_VDW(24);
 281                 break;
 282         case SNDRV_PCM_FORMAT_S32_LE:
 283                 val |= I2S_TXCR_VDW(32);
 284                 break;
 285         default:
 286                 dev_err(i2s->dev, "invalid fmt: %d\n", params_format(params));
 287                 spin_unlock_irqrestore(&lock, flags);
 288                 return -EINVAL;
 289         }
 290
 291         switch (params_channels(params)) {
 292         case I2S_CHANNEL_8:
 293                 val |= I2S_TXCR_CHN_8;
 294                 break;
 295         case I2S_CHANNEL_6:
 296                 val |= I2S_TXCR_CHN_6;
 297                 break;
 298         case I2S_CHANNEL_4:
 299                 val |= I2S_TXCR_CHN_4;
 300                 break;
 301         case I2S_CHANNEL_2:
 302                 val |= I2S_TXCR_CHN_2;
 303                 break;
 304         default:
 305                 dev_err(i2s->dev, "invalid channel: %d\n",
 306                         params_channels(params));
 307                 spin_unlock_irqrestore(&lock, flags);
 308                 return -EINVAL;
 309         }
 310
 311         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 312                 regmap_update_bits(i2s->regmap, I2S_TXCR,
 313                                    I2S_TXCR_VDW_MASK |
 314                                    I2S_TXCR_CSR_MASK,
 315                                    val);
 316         } else {
 317                 regmap_update_bits(i2s->regmap, I2S_RXCR,
 318                                    I2S_RXCR_VDW_MASK, val);
 319         }
 320
 321         regmap_update_bits(i2s->regmap, I2S_DMACR,
 322                            I2S_DMACR_TDL_MASK | I2S_DMACR_RDL_MASK,
 323                            I2S_DMACR_TDL(16) | I2S_DMACR_RDL(16));
 324
 325 #if defined(CONFIG_RK_HDMI) && defined(CONFIG_SND_RK_SOC_HDMI_I2S)
 326         snd_config_hdmi_audio(params);
 327 #endif
 328         spin_unlock_irqrestore(&lock, flags);
 329
 330         return 0;
 331 }
 332
 333 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 334                                 struct snd_soc_dai *dai)
 335 {
 336         struct rk_i2s_dev *i2s = to_info(dai);
 337         int ret = 0;
 338
 339         switch (cmd) {
 340         case SNDRV_PCM_TRIGGER_START:
 341         case SNDRV_PCM_TRIGGER_RESUME:
 342         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 343                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 344                         rockchip_snd_rxctrl(i2s, 1);
 345                 else
 346                         rockchip_snd_txctrl(i2s, 1);
 347                 break;
 348         case SNDRV_PCM_TRIGGER_SUSPEND:
 349         case SNDRV_PCM_TRIGGER_STOP:
 350         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 351                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 352                         rockchip_snd_rxctrl(i2s, 0);
 353                 else
 354                         rockchip_snd_txctrl(i2s, 0);
 355                 break;
 356         default:
 357                 ret = -EINVAL;
 358                 break;
 359         }
 360
 361         return ret;
 362 }
 363
 364 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
 365                                    int clk_id, unsigned int freq, int dir)
 366 {
 367         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 368         int ret;
 369
 370         ret = clk_set_rate(i2s->clk, freq);
 371         if (ret)
 372                 dev_err(i2s->dev, "fail set clk: freq: %d\n", freq);
 373
 374         return ret;
 375 }
 376
 377 static int rockchip_i2s_set_clkdiv(struct snd_soc_dai *cpu_dai,
 378                                    int div_id, int div)
 379 {
 380         struct rk_i2s_dev *i2s = to_info(cpu_dai);
 381         unsigned int val = 0;
 382         unsigned long flags;
 383
 384         spin_lock_irqsave(&lock, flags);
 385
 386         dev_dbg(i2s->dev, "%s: div_id=%d, div=%d\n", __func__, div_id, div);
 387
 388         switch (div_id) {
 389         case ROCKCHIP_DIV_BCLK:
 390                 val |= I2S_CKR_TSD(div);
 391                 val |= I2S_CKR_RSD(div);
 392                 regmap_update_bits(i2s->regmap, I2S_CKR,
 393                                    I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK,
 394                                    val);
 395                 break;
 396         case ROCKCHIP_DIV_MCLK:
 397                 val |= I2S_CKR_MDIV(div);
 398                 regmap_update_bits(i2s->regmap, I2S_CKR,
 399                                    I2S_CKR_MDIV_MASK, val);
 400                 break;
 401         default:
 402                 spin_unlock_irqrestore(&lock, flags);
 403                 return -EINVAL;
 404         }
 405
 406         spin_unlock_irqrestore(&lock, flags);
 407
 408         return 0;
 409 }
 410
 411 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
 412 {
 413         struct rk_i2s_dev *i2s = to_info(dai);
 414
 415         dai->capture_dma_data = &i2s->capture_dma_data;
 416         dai->playback_dma_data = &i2s->playback_dma_data;
 417
 418         return 0;
 419 }
 420
 421 static struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
 422         .trigger = rockchip_i2s_trigger,
 423         .hw_params = rockchip_i2s_hw_params,
 424         .set_fmt = rockchip_i2s_set_fmt,
 425         .set_clkdiv = rockchip_i2s_set_clkdiv,
 426         .set_sysclk = rockchip_i2s_set_sysclk,
 427 };
 428
 429 #define ROCKCHIP_I2S_RATES SNDRV_PCM_RATE_8000_192000
 430 #define ROCKCHIP_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
 431                               SNDRV_PCM_FMTBIT_S20_3LE | \
 432                               SNDRV_PCM_FMTBIT_S24_LE | \
 433                               SNDRV_PCM_FORMAT_S32_LE)
 434
 435 struct snd_soc_dai_driver rockchip_i2s_dai[] = {
 436         {
 437                 .probe = rockchip_i2s_dai_probe,
 438                 .name = "rockchip-i2s.0",
 439                 .id = 0,
 440                 .playback = {
 441                         .channels_min = 2,
 442                         .channels_max = 8,
 443                         .rates = ROCKCHIP_I2S_RATES,
 444                         .formats = ROCKCHIP_I2S_FORMATS,
 445                 },
 446                 .capture = {
 447                         .channels_min = 2,
 448                         .channels_max = 2,
 449                         .rates = ROCKCHIP_I2S_RATES,
 450                         .formats = ROCKCHIP_I2S_FORMATS,
 451                 },
 452                 .ops = &rockchip_i2s_dai_ops,
 453                 .symmetric_rates = 1,
 454         },
 455         {
 456                 .probe = rockchip_i2s_dai_probe,
 457                 .name = "rockchip-i2s.1",
 458                 .id = 1,
 459                 .playback = {
 460                         .channels_min = 2,
 461                         .channels_max = 2,
 462                         .rates = ROCKCHIP_I2S_RATES,
 463                         .formats = ROCKCHIP_I2S_FORMATS,
 464                 },
 465                 .capture = {
 466                         .channels_min = 2,
 467                         .channels_max = 2,
 468                         .rates = ROCKCHIP_I2S_RATES,
 469                         .formats = ROCKCHIP_I2S_FORMATS,
 470                 },
 471                 .ops = &rockchip_i2s_dai_ops,
 472                 .symmetric_rates = 1,
 473         },
 474 };
 475
 476 static const struct snd_soc_component_driver rockchip_i2s_component = {
 477         .name = "rockchip-i2s",
 478 };
 479
 480 #ifdef CONFIG_PM
 481 static int i2s_runtime_suspend(struct device *dev)
 482 {
 483         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 484
 485         dev_dbg(i2s->dev, "%s\n", __func__);
 486         return pinctrl_pm_select_sleep_state(dev);
 487 }
 488
 489 static int i2s_runtime_resume(struct device *dev)
 490 {
 491         struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
 492
 493         dev_dbg(i2s->dev, "%s\n", __func__);
 494         return pinctrl_pm_select_default_state(dev);
 495 }
 496 #else
 497 #define i2s_runtime_suspend NULL
 498 #define i2s_runtime_resume NULL
 499 #endif
 500
 501 #ifdef CLK_SET_LATER
 502 static void set_clk_later_work(struct work_struct *work)
 503 {
 504         struct rk_i2s_dev *i2s = container_of(work, struct rk_i2s_dev,
 505                                                  clk_delayed_work.work);
 506
 507         clk_set_rate(i2s->clk, I2S_DEFAULT_FREQ);
 508         if (!IS_ERR(i2s->mclk))
 509                 clk_set_rate(i2s->mclk, I2S_DEFAULT_FREQ);
 510 }
 511 #endif
 512
 513 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
 514 {
 515         switch (reg) {
 516         case I2S_TXCR:
 517         case I2S_RXCR:
 518         case I2S_CKR:
 519         case I2S_DMACR:
 520         case I2S_INTCR:
 521         case I2S_XFER:
 522         case I2S_CLR:
 523         case I2S_TXDR:
 524                 return true;
 525         default:
 526                 return false;
 527         }
 528 }
 529
 530 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
 531 {
 532         switch (reg) {
 533         case I2S_TXCR:
 534         case I2S_RXCR:
 535         case I2S_CKR:
 536         case I2S_DMACR:
 537         case I2S_INTCR:
 538         case I2S_XFER:
 539         case I2S_CLR:
 540         case I2S_RXDR:
 541         case I2S_FIFOLR:
 542         case I2S_INTSR:
 543                 return true;
 544         default:
 545                 return false;
 546         }
 547 }
 548
 549 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
 550 {
 551         switch (reg) {
 552         case I2S_INTSR:
 553         case I2S_CLR:
 554                 return true;
 555         default:
 556                 return false;
 557         }
 558 }
 559
 560 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
 561 {
 562         switch (reg) {
 563         default:
 564                 return false;
 565         }
 566 }
 567
 568 static const struct regmap_config rockchip_i2s_regmap_config = {
 569         .reg_bits = 32,
 570         .reg_stride = 4,
 571         .val_bits = 32,
 572         .max_register = I2S_RXDR,
 573         .writeable_reg = rockchip_i2s_wr_reg,
 574         .readable_reg = rockchip_i2s_rd_reg,
 575         .volatile_reg = rockchip_i2s_volatile_reg,
 576         .precious_reg = rockchip_i2s_precious_reg,
 577         .cache_type = REGCACHE_FLAT,
 578 };
 579
 580 static int rockchip_i2s_probe(struct platform_device *pdev)
 581 {
 582         struct device_node *node = pdev->dev.of_node;
 583         struct rk_i2s_dev *i2s;
 584         struct resource *res;
 585         void __iomem *regs;
 586         int ret;
 587
 588         ret = of_property_read_u32(node, "i2s-id", &pdev->id);
 589         if (ret < 0) {
 590                 dev_err(&pdev->dev, "Property 'i2s-id' missing or invalid\n");
 591                 ret = -EINVAL;
 592                 goto err;
 593         }
 594
 595         if (soc_is_rk3126b()) {
 596                 int sdi_src = 0;
 597
 598                 /* rk3126b has no i2s1 controller(i2s_8ch) */
 599                 if (1 == pdev->id) {
 600                         pr_info("rk3126b has no i2s1 controller\n");
 601                         ret = -ENODEV;
 602                         goto err;
 603                 }
 604
 605                 ret = of_property_read_u32(node, "sdi_source",
 606                                            &sdi_src);
 607                 if (ret < 0)
 608                         sdi_src = 0;
 609
 610                 if (1 == sdi_src) {
 611                         int val;
 612
 613                         /*GRF_SOC_CON*/
 614                         val = readl_relaxed(RK_GRF_VIRT + 0x0140);
 615                         val = val | 0x04000400;
 616                         writel_relaxed(val, RK_GRF_VIRT + 0x0140);
 617                 }
 618         }
 619
 620         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 621         if (!i2s) {
 622                 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
 623                 ret = -ENOMEM;
 624                 goto err;
 625         }
 626
 627         i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
 628         if (IS_ERR(i2s->hclk)) {
 629                 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
 630                 ret = PTR_ERR(i2s->hclk);
 631                 goto err;
 632         } else {
 633                 clk_prepare_enable(i2s->hclk);
 634         }
 635
 636         i2s->clk = devm_clk_get(&pdev->dev, "i2s_clk");
 637         if (IS_ERR(i2s->clk)) {
 638                 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
 639                 ret = PTR_ERR(i2s->clk);
 640                 goto err;
 641         }
 642 #ifdef CLK_SET_LATER
 643         INIT_DELAYED_WORK(&i2s->clk_delayed_work, set_clk_later_work);
 644         schedule_delayed_work(&i2s->clk_delayed_work, msecs_to_jiffies(10));
 645 #else
 646         clk_set_rate(i2s->clk, I2S_DEFAULT_FREQ);
 647 #endif
 648         clk_prepare_enable(i2s->clk);
 649
 650         i2s->mclk = devm_clk_get(&pdev->dev, "i2s_mclk");
 651         if (IS_ERR(i2s->mclk)) {
 652                 dev_info(&pdev->dev, "i2s%d has no mclk\n", pdev->id);
 653         } else {
 654         #ifndef CLK_SET_LATER
 655                 clk_set_rate(i2s->mclk, I2S_DEFAULT_FREQ);
 656         #endif
 657                 clk_prepare_enable(i2s->mclk);
 658         }
 659
 660         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 661         regs = devm_ioremap_resource(&pdev->dev, res);
 662         if (IS_ERR(regs)) {
 663                 ret = PTR_ERR(regs);
 664                 goto err;
 665         }
 666
 667         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 668                                             &rockchip_i2s_regmap_config);
 669         if (IS_ERR(i2s->regmap)) {
 670                 dev_err(&pdev->dev,
 671                         "Failed to initialise managed register map\n");
 672                 ret = PTR_ERR(i2s->regmap);
 673                 goto err;
 674         }
 675
 676         i2s->playback_dma_data.addr = res->start + I2S_TXDR;
 677         i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 678         i2s->playback_dma_data.maxburst = I2S_DMA_BURST_SIZE;
 679
 680         i2s->capture_dma_data.addr = res->start + I2S_RXDR;
 681         i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 682         i2s->capture_dma_data.maxburst = I2S_DMA_BURST_SIZE;
 683
 684         i2s->tx_start = false;
 685         i2s->rx_start = false;
 686
 687         i2s->dev = &pdev->dev;
 688         dev_set_drvdata(&pdev->dev, i2s);
 689
 690         pm_runtime_enable(&pdev->dev);
 691         if (!pm_runtime_enabled(&pdev->dev)) {
 692                 ret = i2s_runtime_resume(&pdev->dev);
 693                 if (ret)
 694                         goto err_pm_disable;
 695         }
 696
 697         ret = snd_soc_register_component(&pdev->dev, &rockchip_i2s_component,
 698                                          &rockchip_i2s_dai[pdev->id], 1);
 699
 700         if (ret) {
 701                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 702                 ret = -ENOMEM;
 703                 goto err_suspend;
 704         }
 705
 706         ret = rockchip_pcm_platform_register(&pdev->dev);
 707         if (ret) {
 708                 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
 709                 goto err_unregister_component;
 710         }
 711
 712         rockchip_snd_txctrl(i2s, 0);
 713         rockchip_snd_rxctrl(i2s, 0);
 714
 715         return 0;
 716
 717 err_unregister_component:
 718         snd_soc_unregister_component(&pdev->dev);
 719 err_suspend:
 720         if (!pm_runtime_status_suspended(&pdev->dev))
 721                 i2s_runtime_suspend(&pdev->dev);
 722 err_pm_disable:
 723         pm_runtime_disable(&pdev->dev);
 724 err:
 725         return ret;
 726 }
 727
 728 static int rockchip_i2s_remove(struct platform_device *pdev)
 729 {
 730         struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
 731
 732         pm_runtime_disable(&pdev->dev);
 733         if (!pm_runtime_status_suspended(&pdev->dev))
 734                 i2s_runtime_suspend(&pdev->dev);
 735
 736         if (!IS_ERR(i2s->mclk))
 737                 clk_disable_unprepare(i2s->mclk);
 738
 739         clk_disable_unprepare(i2s->clk);
 740         clk_disable_unprepare(i2s->hclk);
 741         rockchip_pcm_platform_unregister(&pdev->dev);
 742         snd_soc_unregister_component(&pdev->dev);
 743
 744         return 0;
 745 }
 746
 747 #ifdef CONFIG_OF
 748 static const struct of_device_id rockchip_i2s_match[] = {
 749         { .compatible = "rockchip-i2s", },
 750         {},
 751 };
 752 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
 753 #endif
 754
 755 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
 756         SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
 757                            NULL)
 758 };
 759
 760 static struct platform_driver rockchip_i2s_driver = {
 761         .probe  = rockchip_i2s_probe,
 762         .remove = rockchip_i2s_remove,
 763         .driver = {
 764                 .name   = "rockchip-i2s",
 765                 .owner  = THIS_MODULE,
 766                 .of_match_table = of_match_ptr(rockchip_i2s_match),
 767                 .pm     = &rockchip_i2s_pm_ops,
 768         },
 769 };
 770
 771 static int __init rockchip_i2s_init(void)
 772 {
 773         return platform_driver_register(&rockchip_i2s_driver);
 774 }
 775 subsys_initcall_sync(rockchip_i2s_init);
 776
 777 static void __exit rockchip_i2s_exit(void)
 778 {
 779         platform_driver_unregister(&rockchip_i2s_driver);
 780 }
 781 module_exit(rockchip_i2s_exit);
 782
 783 MODULE_AUTHOR("Sugar <sugar.zhang@rock-chips.com>");
 784 MODULE_DESCRIPTION("Rockchip I2S Controller Driver");
 785 MODULE_LICENSE("GPL v2");