sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #endif
  58 #include <sound/core.h>
  59 #include <sound/initval.h>
  60 #include <sound/hdaudio.h>
  61 #include <sound/hda_i915.h>
  62 #include <linux/vgaarb.h>
  63 #include <linux/vga_switcheroo.h>
  64 #include <linux/firmware.h>
  65 #include "hda_codec.h"
  66 #include "hda_controller.h"
  67 #include "hda_intel.h"
  68
  69 #define CREATE_TRACE_POINTS
  70 #include "hda_intel_trace.h"
  71
  72 /* position fix mode */
  73 enum {
  74         POS_FIX_AUTO,
  75         POS_FIX_LPIB,
  76         POS_FIX_POSBUF,
  77         POS_FIX_VIACOMBO,
  78         POS_FIX_COMBO,
  79 };
  80
  81 /* Defines for ATI HD Audio support in SB450 south bridge */
  82 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  83 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  84
  85 /* Defines for Nvidia HDA support */
  86 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  87 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  88 #define NVIDIA_HDA_ISTRM_COH          0x4d
  89 #define NVIDIA_HDA_OSTRM_COH          0x4c
  90 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  91
  92 /* Defines for Intel SCH HDA snoop control */
  93 #define INTEL_HDA_CGCTL  0x48
  94 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  95 #define INTEL_SCH_HDA_DEVC      0x78
  96 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  97
  98 /* Define IN stream 0 FIFO size offset in VIA controller */
  99 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 100 /* Define VIA HD Audio Device ID*/
 101 #define VIA_HDAC_DEVICE_ID              0x3288
 102
 103 /* max number of SDs */
 104 /* ICH, ATI and VIA have 4 playback and 4 capture */
 105 #define ICH6_NUM_CAPTURE        4
 106 #define ICH6_NUM_PLAYBACK       4
 107
 108 /* ULI has 6 playback and 5 capture */
 109 #define ULI_NUM_CAPTURE         5
 110 #define ULI_NUM_PLAYBACK        6
 111
 112 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 113 #define ATIHDMI_NUM_CAPTURE     0
 114 #define ATIHDMI_NUM_PLAYBACK    8
 115
 116 /* TERA has 4 playback and 3 capture */
 117 #define TERA_NUM_CAPTURE        3
 118 #define TERA_NUM_PLAYBACK       4
 119
 120
 121 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 122 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 123 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 124 static char *model[SNDRV_CARDS];
 125 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 126 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 127 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int probe_only[SNDRV_CARDS];
 129 static int jackpoll_ms[SNDRV_CARDS];
 130 static bool single_cmd;
 131 static int enable_msi = -1;
 132 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 133 static char *patch[SNDRV_CARDS];
 134 #endif
 135 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 136 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 137                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 138 #endif
 139
 140 module_param_array(index, int, NULL, 0444);
 141 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 142 module_param_array(id, charp, NULL, 0444);
 143 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 144 module_param_array(enable, bool, NULL, 0444);
 145 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 146 module_param_array(model, charp, NULL, 0444);
 147 MODULE_PARM_DESC(model, "Use the given board model.");
 148 module_param_array(position_fix, int, NULL, 0444);
 149 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 150                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
 151 module_param_array(bdl_pos_adj, int, NULL, 0644);
 152 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 153 module_param_array(probe_mask, int, NULL, 0444);
 154 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 155 module_param_array(probe_only, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 157 module_param_array(jackpoll_ms, int, NULL, 0444);
 158 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 159 module_param(single_cmd, bool, 0444);
 160 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 161                  "(for debugging only).");
 162 module_param(enable_msi, bint, 0444);
 163 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 164 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 165 module_param_array(patch, charp, NULL, 0444);
 166 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 167 #endif
 168 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 169 module_param_array(beep_mode, bool, NULL, 0444);
 170 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 171                             "(0=off, 1=on) (default=1).");
 172 #endif
 173
 174 #ifdef CONFIG_PM
 175 static int param_set_xint(const char *val, const struct kernel_param *kp);
 176 static const struct kernel_param_ops param_ops_xint = {
 177         .set = param_set_xint,
 178         .get = param_get_int,
 179 };
 180 #define param_check_xint param_check_int
 181
 182 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 183 module_param(power_save, xint, 0644);
 184 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 185                  "(in second, 0 = disable).");
 186
 187 /* reset the HD-audio controller in power save mode.
 188  * this may give more power-saving, but will take longer time to
 189  * wake up.
 190  */
 191 static bool power_save_controller = 1;
 192 module_param(power_save_controller, bool, 0644);
 193 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 194 #else
 195 #define power_save      0
 196 #endif /* CONFIG_PM */
 197
 198 static int align_buffer_size = -1;
 199 module_param(align_buffer_size, bint, 0644);
 200 MODULE_PARM_DESC(align_buffer_size,
 201                 "Force buffer and period sizes to be multiple of 128 bytes.");
 202
 203 #ifdef CONFIG_X86
 204 static int hda_snoop = -1;
 205 module_param_named(snoop, hda_snoop, bint, 0444);
 206 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 207 #else
 208 #define hda_snoop               true
 209 #endif
 210
 211
 212 MODULE_LICENSE("GPL");
 213 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 214                          "{Intel, ICH6M},"
 215                          "{Intel, ICH7},"
 216                          "{Intel, ESB2},"
 217                          "{Intel, ICH8},"
 218                          "{Intel, ICH9},"
 219                          "{Intel, ICH10},"
 220                          "{Intel, PCH},"
 221                          "{Intel, CPT},"
 222                          "{Intel, PPT},"
 223                          "{Intel, LPT},"
 224                          "{Intel, LPT_LP},"
 225                          "{Intel, WPT_LP},"
 226                          "{Intel, SPT},"
 227                          "{Intel, SPT_LP},"
 228                          "{Intel, HPT},"
 229                          "{Intel, PBG},"
 230                          "{Intel, SCH},"
 231                          "{ATI, SB450},"
 232                          "{ATI, SB600},"
 233                          "{ATI, RS600},"
 234                          "{ATI, RS690},"
 235                          "{ATI, RS780},"
 236                          "{ATI, R600},"
 237                          "{ATI, RV630},"
 238                          "{ATI, RV610},"
 239                          "{ATI, RV670},"
 240                          "{ATI, RV635},"
 241                          "{ATI, RV620},"
 242                          "{ATI, RV770},"
 243                          "{VIA, VT8251},"
 244                          "{VIA, VT8237A},"
 245                          "{SiS, SIS966},"
 246                          "{ULI, M5461}}");
 247 MODULE_DESCRIPTION("Intel HDA driver");
 248
 249 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 250 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 251 #define SUPPORT_VGA_SWITCHEROO
 252 #endif
 253 #endif
 254
 255
 256 /*
 257  */
 258
 259 /* driver types */
 260 enum {
 261         AZX_DRIVER_ICH,
 262         AZX_DRIVER_PCH,
 263         AZX_DRIVER_SCH,
 264         AZX_DRIVER_HDMI,
 265         AZX_DRIVER_ATI,
 266         AZX_DRIVER_ATIHDMI,
 267         AZX_DRIVER_ATIHDMI_NS,
 268         AZX_DRIVER_VIA,
 269         AZX_DRIVER_SIS,
 270         AZX_DRIVER_ULI,
 271         AZX_DRIVER_NVIDIA,
 272         AZX_DRIVER_TERA,
 273         AZX_DRIVER_CTX,
 274         AZX_DRIVER_CTHDA,
 275         AZX_DRIVER_CMEDIA,
 276         AZX_DRIVER_GENERIC,
 277         AZX_NUM_DRIVERS, /* keep this as last entry */
 278 };
 279
 280 #define azx_get_snoop_type(chip) \
 281         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 283
 284 /* quirks for old Intel chipsets */
 285 #define AZX_DCAPS_INTEL_ICH \
 286         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 287
 288 /* quirks for Intel PCH */
 289 #define AZX_DCAPS_INTEL_PCH_NOPM \
 290         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 291          AZX_DCAPS_REVERSE_ASSIGN | AZX_DCAPS_SNOOP_TYPE(SCH))
 292
 293 #define AZX_DCAPS_INTEL_PCH \
 294         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 295
 296 #define AZX_DCAPS_INTEL_HASWELL \
 297         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 298          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 299          AZX_DCAPS_SNOOP_TYPE(SCH))
 300
 301 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 302 #define AZX_DCAPS_INTEL_BROADWELL \
 303         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 304          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 305          AZX_DCAPS_SNOOP_TYPE(SCH))
 306
 307 #define AZX_DCAPS_INTEL_BAYTRAIL \
 308         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 309
 310 #define AZX_DCAPS_INTEL_BRASWELL \
 311         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 312
 313 #define AZX_DCAPS_INTEL_SKYLAKE \
 314         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 315          AZX_DCAPS_I915_POWERWELL)
 316
 317 #define AZX_DCAPS_INTEL_BROXTON \
 318         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 319          AZX_DCAPS_I915_POWERWELL)
 320
 321 /* quirks for ATI SB / AMD Hudson */
 322 #define AZX_DCAPS_PRESET_ATI_SB \
 323         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 324          AZX_DCAPS_SNOOP_TYPE(ATI))
 325
 326 /* quirks for ATI/AMD HDMI */
 327 #define AZX_DCAPS_PRESET_ATI_HDMI \
 328         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 329          AZX_DCAPS_NO_MSI64)
 330
 331 /* quirks for ATI HDMI with snoop off */
 332 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 333         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 334
 335 /* quirks for Nvidia */
 336 #define AZX_DCAPS_PRESET_NVIDIA \
 337         (AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI | /*AZX_DCAPS_ALIGN_BUFSIZE |*/ \
 338          AZX_DCAPS_NO_64BIT | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 339          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 340
 341 #define AZX_DCAPS_PRESET_CTHDA \
 342         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 343          AZX_DCAPS_NO_64BIT |\
 344          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 345
 346 /*
 347  * vga_switcheroo support
 348  */
 349 #ifdef SUPPORT_VGA_SWITCHEROO
 350 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 351 #else
 352 #define use_vga_switcheroo(chip)        0
 353 #endif
 354
 355 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 356                                         ((pci)->device == 0x0c0c) || \
 357                                         ((pci)->device == 0x0d0c) || \
 358                                         ((pci)->device == 0x160c))
 359
 360 #define IS_BROXTON(pci) ((pci)->device == 0x5a98)
 361
 362 static char *driver_short_names[] = {
 363         [AZX_DRIVER_ICH] = "HDA Intel",
 364         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 365         [AZX_DRIVER_SCH] = "HDA Intel MID",
 366         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 367         [AZX_DRIVER_ATI] = "HDA ATI SB",
 368         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 369         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 370         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 371         [AZX_DRIVER_SIS] = "HDA SIS966",
 372         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 373         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 374         [AZX_DRIVER_TERA] = "HDA Teradici",
 375         [AZX_DRIVER_CTX] = "HDA Creative",
 376         [AZX_DRIVER_CTHDA] = "HDA Creative",
 377         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 378         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 379 };
 380
 381 #ifdef CONFIG_X86
 382 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 383 {
 384         int pages;
 385
 386         if (azx_snoop(chip))
 387                 return;
 388         if (!dmab || !dmab->area || !dmab->bytes)
 389                 return;
 390
 391 #ifdef CONFIG_SND_DMA_SGBUF
 392         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 393                 struct snd_sg_buf *sgbuf = dmab->private_data;
 394                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 395                         return; /* deal with only CORB/RIRB buffers */
 396                 if (on)
 397                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 398                 else
 399                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 400                 return;
 401         }
 402 #endif
 403
 404         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 405         if (on)
 406                 set_memory_wc((unsigned long)dmab->area, pages);
 407         else
 408                 set_memory_wb((unsigned long)dmab->area, pages);
 409 }
 410
 411 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 412                                  bool on)
 413 {
 414         __mark_pages_wc(chip, buf, on);
 415 }
 416 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 417                                    struct snd_pcm_substream *substream, bool on)
 418 {
 419         if (azx_dev->wc_marked != on) {
 420                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 421                 azx_dev->wc_marked = on;
 422         }
 423 }
 424 #else
 425 /* NOP for other archs */
 426 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 427                                  bool on)
 428 {
 429 }
 430 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 431                                    struct snd_pcm_substream *substream, bool on)
 432 {
 433 }
 434 #endif
 435
 436 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 437
 438 /*
 439  * initialize the PCI registers
 440  */
 441 /* update bits in a PCI register byte */
 442 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 443                             unsigned char mask, unsigned char val)
 444 {
 445         unsigned char data;
 446
 447         pci_read_config_byte(pci, reg, &data);
 448         data &= ~mask;
 449         data |= (val & mask);
 450         pci_write_config_byte(pci, reg, data);
 451 }
 452
 453 static void azx_init_pci(struct azx *chip)
 454 {
 455         int snoop_type = azx_get_snoop_type(chip);
 456
 457         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 458          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 459          * Ensuring these bits are 0 clears playback static on some HD Audio
 460          * codecs.
 461          * The PCI register TCSEL is defined in the Intel manuals.
 462          */
 463         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 464                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 465                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 466         }
 467
 468         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 469          * we need to enable snoop.
 470          */
 471         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 472                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 473                         azx_snoop(chip));
 474                 update_pci_byte(chip->pci,
 475                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 476                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 477         }
 478
 479         /* For NVIDIA HDA, enable snoop */
 480         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 481                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 482                         azx_snoop(chip));
 483                 update_pci_byte(chip->pci,
 484                                 NVIDIA_HDA_TRANSREG_ADDR,
 485                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 486                 update_pci_byte(chip->pci,
 487                                 NVIDIA_HDA_ISTRM_COH,
 488                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 489                 update_pci_byte(chip->pci,
 490                                 NVIDIA_HDA_OSTRM_COH,
 491                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 492         }
 493
 494         /* Enable SCH/PCH snoop if needed */
 495         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 496                 unsigned short snoop;
 497                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 498                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 499                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 500                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 501                         if (!azx_snoop(chip))
 502                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 503                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 504                         pci_read_config_word(chip->pci,
 505                                 INTEL_SCH_HDA_DEVC, &snoop);
 506                 }
 507                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 508                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 509                         "Disabled" : "Enabled");
 510         }
 511 }
 512
 513 /*
 514  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 515  * and makes an audio stream sensitive to system latencies when
 516  * 24/32 bits are playing.
 517  * Adjusting threshold of DMA fifo to force the DMA request
 518  * sooner to improve latency tolerance at the expense of power.
 519  */
 520 static void bxt_reduce_dma_latency(struct azx *chip)
 521 {
 522         u32 val;
 523
 524         val = azx_readl(chip, SKL_EM4L);
 525         val &= (0x3 << 20);
 526         azx_writel(chip, SKL_EM4L, val);
 527 }
 528
 529 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 530 {
 531         struct hdac_bus *bus = azx_bus(chip);
 532         struct pci_dev *pci = chip->pci;
 533         u32 val;
 534
 535         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 536                 snd_hdac_set_codec_wakeup(bus, true);
 537         if (IS_BROXTON(pci)) {
 538                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 539                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 540                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 541         }
 542         azx_init_chip(chip, full_reset);
 543         if (IS_BROXTON(pci)) {
 544                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 545                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 546                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 547         }
 548         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 549                 snd_hdac_set_codec_wakeup(bus, false);
 550
 551         /* reduce dma latency to avoid noise */
 552         if (IS_BROXTON(pci))
 553                 bxt_reduce_dma_latency(chip);
 554 }
 555
 556 /* calculate runtime delay from LPIB */
 557 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 558                                    unsigned int pos)
 559 {
 560         struct snd_pcm_substream *substream = azx_dev->core.substream;
 561         int stream = substream->stream;
 562         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 563         int delay;
 564
 565         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 566                 delay = pos - lpib_pos;
 567         else
 568                 delay = lpib_pos - pos;
 569         if (delay < 0) {
 570                 if (delay >= azx_dev->core.delay_negative_threshold)
 571                         delay = 0;
 572                 else
 573                         delay += azx_dev->core.bufsize;
 574         }
 575
 576         if (delay >= azx_dev->core.period_bytes) {
 577                 dev_info(chip->card->dev,
 578                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 579                          delay, azx_dev->core.period_bytes);
 580                 delay = 0;
 581                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 582                 chip->get_delay[stream] = NULL;
 583         }
 584
 585         return bytes_to_frames(substream->runtime, delay);
 586 }
 587
 588 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 589
 590 /* called from IRQ */
 591 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 592 {
 593         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 594         int ok;
 595
 596         ok = azx_position_ok(chip, azx_dev);
 597         if (ok == 1) {
 598                 azx_dev->irq_pending = 0;
 599                 return ok;
 600         } else if (ok == 0) {
 601                 /* bogus IRQ, process it later */
 602                 azx_dev->irq_pending = 1;
 603                 schedule_work(&hda->irq_pending_work);
 604         }
 605         return 0;
 606 }
 607
 608 /* Enable/disable i915 display power for the link */
 609 static int azx_intel_link_power(struct azx *chip, bool enable)
 610 {
 611         struct hdac_bus *bus = azx_bus(chip);
 612
 613         return snd_hdac_display_power(bus, enable);
 614 }
 615
 616 /*
 617  * Check whether the current DMA position is acceptable for updating
 618  * periods.  Returns non-zero if it's OK.
 619  *
 620  * Many HD-audio controllers appear pretty inaccurate about
 621  * the update-IRQ timing.  The IRQ is issued before actually the
 622  * data is processed.  So, we need to process it afterwords in a
 623  * workqueue.
 624  */
 625 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 626 {
 627         struct snd_pcm_substream *substream = azx_dev->core.substream;
 628         int stream = substream->stream;
 629         u32 wallclk;
 630         unsigned int pos;
 631
 632         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 633         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 634                 return -1;      /* bogus (too early) interrupt */
 635
 636         if (chip->get_position[stream])
 637                 pos = chip->get_position[stream](chip, azx_dev);
 638         else { /* use the position buffer as default */
 639                 pos = azx_get_pos_posbuf(chip, azx_dev);
 640                 if (!pos || pos == (u32)-1) {
 641                         dev_info(chip->card->dev,
 642                                  "Invalid position buffer, using LPIB read method instead.\n");
 643                         chip->get_position[stream] = azx_get_pos_lpib;
 644                         if (chip->get_position[0] == azx_get_pos_lpib &&
 645                             chip->get_position[1] == azx_get_pos_lpib)
 646                                 azx_bus(chip)->use_posbuf = false;
 647                         pos = azx_get_pos_lpib(chip, azx_dev);
 648                         chip->get_delay[stream] = NULL;
 649                 } else {
 650                         chip->get_position[stream] = azx_get_pos_posbuf;
 651                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 652                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 653                 }
 654         }
 655
 656         if (pos >= azx_dev->core.bufsize)
 657                 pos = 0;
 658
 659         if (WARN_ONCE(!azx_dev->core.period_bytes,
 660                       "hda-intel: zero azx_dev->period_bytes"))
 661                 return -1; /* this shouldn't happen! */
 662         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 663             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 664                 /* NG - it's below the first next period boundary */
 665                 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
 666         azx_dev->core.start_wallclk += wallclk;
 667         return 1; /* OK, it's fine */
 668 }
 669
 670 /*
 671  * The work for pending PCM period updates.
 672  */
 673 static void azx_irq_pending_work(struct work_struct *work)
 674 {
 675         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 676         struct azx *chip = &hda->chip;
 677         struct hdac_bus *bus = azx_bus(chip);
 678         struct hdac_stream *s;
 679         int pending, ok;
 680
 681         if (!hda->irq_pending_warned) {
 682                 dev_info(chip->card->dev,
 683                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 684                          chip->card->number);
 685                 hda->irq_pending_warned = 1;
 686         }
 687
 688         for (;;) {
 689                 pending = 0;
 690                 spin_lock_irq(&bus->reg_lock);
 691                 list_for_each_entry(s, &bus->stream_list, list) {
 692                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 693                         if (!azx_dev->irq_pending ||
 694                             !s->substream ||
 695                             !s->running)
 696                                 continue;
 697                         ok = azx_position_ok(chip, azx_dev);
 698                         if (ok > 0) {
 699                                 azx_dev->irq_pending = 0;
 700                                 spin_unlock(&bus->reg_lock);
 701                                 snd_pcm_period_elapsed(s->substream);
 702                                 spin_lock(&bus->reg_lock);
 703                         } else if (ok < 0) {
 704                                 pending = 0;    /* too early */
 705                         } else
 706                                 pending++;
 707                 }
 708                 spin_unlock_irq(&bus->reg_lock);
 709                 if (!pending)
 710                         return;
 711                 msleep(1);
 712         }
 713 }
 714
 715 /* clear irq_pending flags and assure no on-going workq */
 716 static void azx_clear_irq_pending(struct azx *chip)
 717 {
 718         struct hdac_bus *bus = azx_bus(chip);
 719         struct hdac_stream *s;
 720
 721         spin_lock_irq(&bus->reg_lock);
 722         list_for_each_entry(s, &bus->stream_list, list) {
 723                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 724                 azx_dev->irq_pending = 0;
 725         }
 726         spin_unlock_irq(&bus->reg_lock);
 727 }
 728
 729 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 730 {
 731         struct hdac_bus *bus = azx_bus(chip);
 732
 733         if (request_irq(chip->pci->irq, azx_interrupt,
 734                         chip->msi ? 0 : IRQF_SHARED,
 735                         KBUILD_MODNAME, chip)) {
 736                 dev_err(chip->card->dev,
 737                         "unable to grab IRQ %d, disabling device\n",
 738                         chip->pci->irq);
 739                 if (do_disconnect)
 740                         snd_card_disconnect(chip->card);
 741                 return -1;
 742         }
 743         bus->irq = chip->pci->irq;
 744         pci_intx(chip->pci, !chip->msi);
 745         return 0;
 746 }
 747
 748 /* get the current DMA position with correction on VIA chips */
 749 static unsigned int azx_via_get_position(struct azx *chip,
 750                                          struct azx_dev *azx_dev)
 751 {
 752         unsigned int link_pos, mini_pos, bound_pos;
 753         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 754         unsigned int fifo_size;
 755
 756         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 757         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 758                 /* Playback, no problem using link position */
 759                 return link_pos;
 760         }
 761
 762         /* Capture */
 763         /* For new chipset,
 764          * use mod to get the DMA position just like old chipset
 765          */
 766         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 767         mod_dma_pos %= azx_dev->core.period_bytes;
 768
 769         /* azx_dev->fifo_size can't get FIFO size of in stream.
 770          * Get from base address + offset.
 771          */
 772         fifo_size = readw(azx_bus(chip)->remap_addr +
 773                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 774
 775         if (azx_dev->insufficient) {
 776                 /* Link position never gather than FIFO size */
 777                 if (link_pos <= fifo_size)
 778                         return 0;
 779
 780                 azx_dev->insufficient = 0;
 781         }
 782
 783         if (link_pos <= fifo_size)
 784                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 785         else
 786                 mini_pos = link_pos - fifo_size;
 787
 788         /* Find nearest previous boudary */
 789         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 790         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 791         if (mod_link_pos >= fifo_size)
 792                 bound_pos = link_pos - mod_link_pos;
 793         else if (mod_dma_pos >= mod_mini_pos)
 794                 bound_pos = mini_pos - mod_mini_pos;
 795         else {
 796                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 797                 if (bound_pos >= azx_dev->core.bufsize)
 798                         bound_pos = 0;
 799         }
 800
 801         /* Calculate real DMA position we want */
 802         return bound_pos + mod_dma_pos;
 803 }
 804
 805 #ifdef CONFIG_PM
 806 static DEFINE_MUTEX(card_list_lock);
 807 static LIST_HEAD(card_list);
 808
 809 static void azx_add_card_list(struct azx *chip)
 810 {
 811         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 812         mutex_lock(&card_list_lock);
 813         list_add(&hda->list, &card_list);
 814         mutex_unlock(&card_list_lock);
 815 }
 816
 817 static void azx_del_card_list(struct azx *chip)
 818 {
 819         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 820         mutex_lock(&card_list_lock);
 821         list_del_init(&hda->list);
 822         mutex_unlock(&card_list_lock);
 823 }
 824
 825 /* trigger power-save check at writing parameter */
 826 static int param_set_xint(const char *val, const struct kernel_param *kp)
 827 {
 828         struct hda_intel *hda;
 829         struct azx *chip;
 830         int prev = power_save;
 831         int ret = param_set_int(val, kp);
 832
 833         if (ret || prev == power_save)
 834                 return ret;
 835
 836         mutex_lock(&card_list_lock);
 837         list_for_each_entry(hda, &card_list, list) {
 838                 chip = &hda->chip;
 839                 if (!hda->probe_continued || chip->disabled)
 840                         continue;
 841                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 842         }
 843         mutex_unlock(&card_list_lock);
 844         return 0;
 845 }
 846 #else
 847 #define azx_add_card_list(chip) /* NOP */
 848 #define azx_del_card_list(chip) /* NOP */
 849 #endif /* CONFIG_PM */
 850
 851 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK
 852  * depends on GPU. Two Extended Mode registers EM4 (M value) and EM5 (N Value)
 853  * are used to convert CDClk (Core Display Clock) to 24MHz BCLK:
 854  * BCLK = CDCLK * M / N
 855  * The values will be lost when the display power well is disabled and need to
 856  * be restored to avoid abnormal playback speed.
 857  */
 858 static void haswell_set_bclk(struct hda_intel *hda)
 859 {
 860         struct azx *chip = &hda->chip;
 861         int cdclk_freq;
 862         unsigned int bclk_m, bclk_n;
 863
 864         if (!hda->need_i915_power)
 865                 return;
 866
 867         cdclk_freq = snd_hdac_get_display_clk(azx_bus(chip));
 868         switch (cdclk_freq) {
 869         case 337500:
 870                 bclk_m = 16;
 871                 bclk_n = 225;
 872                 break;
 873
 874         case 450000:
 875         default: /* default CDCLK 450MHz */
 876                 bclk_m = 4;
 877                 bclk_n = 75;
 878                 break;
 879
 880         case 540000:
 881                 bclk_m = 4;
 882                 bclk_n = 90;
 883                 break;
 884
 885         case 675000:
 886                 bclk_m = 8;
 887                 bclk_n = 225;
 888                 break;
 889         }
 890
 891         azx_writew(chip, HSW_EM4, bclk_m);
 892         azx_writew(chip, HSW_EM5, bclk_n);
 893 }
 894
 895 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 896 /*
 897  * power management
 898  */
 899 static int azx_suspend(struct device *dev)
 900 {
 901         struct snd_card *card = dev_get_drvdata(dev);
 902         struct azx *chip;
 903         struct hda_intel *hda;
 904         struct hdac_bus *bus;
 905
 906         if (!card)
 907                 return 0;
 908
 909         chip = card->private_data;
 910         hda = container_of(chip, struct hda_intel, chip);
 911         if (chip->disabled || hda->init_failed || !chip->running)
 912                 return 0;
 913
 914         bus = azx_bus(chip);
 915         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 916         azx_clear_irq_pending(chip);
 917         azx_stop_chip(chip);
 918         azx_enter_link_reset(chip);
 919         if (bus->irq >= 0) {
 920                 free_irq(bus->irq, chip);
 921                 bus->irq = -1;
 922         }
 923
 924         if (chip->msi)
 925                 pci_disable_msi(chip->pci);
 926         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 927                 && hda->need_i915_power)
 928                 snd_hdac_display_power(bus, false);
 929
 930         trace_azx_suspend(chip);
 931         return 0;
 932 }
 933
 934 static int azx_resume(struct device *dev)
 935 {
 936         struct pci_dev *pci = to_pci_dev(dev);
 937         struct snd_card *card = dev_get_drvdata(dev);
 938         struct azx *chip;
 939         struct hda_intel *hda;
 940
 941         if (!card)
 942                 return 0;
 943
 944         chip = card->private_data;
 945         hda = container_of(chip, struct hda_intel, chip);
 946         if (chip->disabled || hda->init_failed || !chip->running)
 947                 return 0;
 948
 949         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 950                 && hda->need_i915_power) {
 951                 snd_hdac_display_power(azx_bus(chip), true);
 952                 haswell_set_bclk(hda);
 953         }
 954         if (chip->msi)
 955                 if (pci_enable_msi(pci) < 0)
 956                         chip->msi = 0;
 957         if (azx_acquire_irq(chip, 1) < 0)
 958                 return -EIO;
 959         azx_init_pci(chip);
 960
 961         hda_intel_init_chip(chip, true);
 962
 963         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 964
 965         trace_azx_resume(chip);
 966         return 0;
 967 }
 968 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 969
 970 #ifdef CONFIG_PM_SLEEP
 971 /* put codec down to D3 at hibernation for Intel SKL+;
 972  * otherwise BIOS may still access the codec and screw up the driver
 973  */
 974 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
 975 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
 976 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 977 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci))
 978
 979 static int azx_freeze_noirq(struct device *dev)
 980 {
 981         struct pci_dev *pci = to_pci_dev(dev);
 982
 983         if (IS_SKL_PLUS(pci))
 984                 pci_set_power_state(pci, PCI_D3hot);
 985
 986         return 0;
 987 }
 988
 989 static int azx_thaw_noirq(struct device *dev)
 990 {
 991         struct pci_dev *pci = to_pci_dev(dev);
 992
 993         if (IS_SKL_PLUS(pci))
 994                 pci_set_power_state(pci, PCI_D0);
 995
 996         return 0;
 997 }
 998 #endif /* CONFIG_PM_SLEEP */
 999
1000 #ifdef CONFIG_PM
1001 static int azx_runtime_suspend(struct device *dev)
1002 {
1003         struct snd_card *card = dev_get_drvdata(dev);
1004         struct azx *chip;
1005         struct hda_intel *hda;
1006
1007         if (!card)
1008                 return 0;
1009
1010         chip = card->private_data;
1011         hda = container_of(chip, struct hda_intel, chip);
1012         if (chip->disabled || hda->init_failed)
1013                 return 0;
1014
1015         if (!azx_has_pm_runtime(chip))
1016                 return 0;
1017
1018         /* enable controller wake up event */
1019         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1020                   STATESTS_INT_MASK);
1021
1022         azx_stop_chip(chip);
1023         azx_enter_link_reset(chip);
1024         azx_clear_irq_pending(chip);
1025         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1026                 && hda->need_i915_power)
1027                 snd_hdac_display_power(azx_bus(chip), false);
1028
1029         trace_azx_runtime_suspend(chip);
1030         return 0;
1031 }
1032
1033 static int azx_runtime_resume(struct device *dev)
1034 {
1035         struct snd_card *card = dev_get_drvdata(dev);
1036         struct azx *chip;
1037         struct hda_intel *hda;
1038         struct hdac_bus *bus;
1039         struct hda_codec *codec;
1040         int status;
1041
1042         if (!card)
1043                 return 0;
1044
1045         chip = card->private_data;
1046         hda = container_of(chip, struct hda_intel, chip);
1047         if (chip->disabled || hda->init_failed)
1048                 return 0;
1049
1050         if (!azx_has_pm_runtime(chip))
1051                 return 0;
1052
1053         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1054                 bus = azx_bus(chip);
1055                 if (hda->need_i915_power) {
1056                         snd_hdac_display_power(bus, true);
1057                         haswell_set_bclk(hda);
1058                 } else {
1059                         /* toggle codec wakeup bit for STATESTS read */
1060                         snd_hdac_set_codec_wakeup(bus, true);
1061                         snd_hdac_set_codec_wakeup(bus, false);
1062                 }
1063         }
1064
1065         /* Read STATESTS before controller reset */
1066         status = azx_readw(chip, STATESTS);
1067
1068         azx_init_pci(chip);
1069         hda_intel_init_chip(chip, true);
1070
1071         if (status) {
1072                 list_for_each_codec(codec, &chip->bus)
1073                         if (status & (1 << codec->addr))
1074                                 schedule_delayed_work(&codec->jackpoll_work,
1075                                                       codec->jackpoll_interval);
1076         }
1077
1078         /* disable controller Wake Up event*/
1079         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1080                         ~STATESTS_INT_MASK);
1081
1082         trace_azx_runtime_resume(chip);
1083         return 0;
1084 }
1085
1086 static int azx_runtime_idle(struct device *dev)
1087 {
1088         struct snd_card *card = dev_get_drvdata(dev);
1089         struct azx *chip;
1090         struct hda_intel *hda;
1091
1092         if (!card)
1093                 return 0;
1094
1095         chip = card->private_data;
1096         hda = container_of(chip, struct hda_intel, chip);
1097         if (chip->disabled || hda->init_failed)
1098                 return 0;
1099
1100         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1101             azx_bus(chip)->codec_powered || !chip->running)
1102                 return -EBUSY;
1103
1104         return 0;
1105 }
1106
1107 static const struct dev_pm_ops azx_pm = {
1108         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1109 #ifdef CONFIG_PM_SLEEP
1110         .freeze_noirq = azx_freeze_noirq,
1111         .thaw_noirq = azx_thaw_noirq,
1112 #endif
1113         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1114 };
1115
1116 #define AZX_PM_OPS      &azx_pm
1117 #else
1118 #define AZX_PM_OPS      NULL
1119 #endif /* CONFIG_PM */
1120
1121
1122 static int azx_probe_continue(struct azx *chip);
1123
1124 #ifdef SUPPORT_VGA_SWITCHEROO
1125 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1126
1127 static void azx_vs_set_state(struct pci_dev *pci,
1128                              enum vga_switcheroo_state state)
1129 {
1130         struct snd_card *card = pci_get_drvdata(pci);
1131         struct azx *chip = card->private_data;
1132         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1133         bool disabled;
1134
1135         wait_for_completion(&hda->probe_wait);
1136         if (hda->init_failed)
1137                 return;
1138
1139         disabled = (state == VGA_SWITCHEROO_OFF);
1140         if (chip->disabled == disabled)
1141                 return;
1142
1143         if (!hda->probe_continued) {
1144                 chip->disabled = disabled;
1145                 if (!disabled) {
1146                         dev_info(chip->card->dev,
1147                                  "Start delayed initialization\n");
1148                         if (azx_probe_continue(chip) < 0) {
1149                                 dev_err(chip->card->dev, "initialization error\n");
1150                                 hda->init_failed = true;
1151                         }
1152                 }
1153         } else {
1154                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1155                          disabled ? "Disabling" : "Enabling");
1156                 if (disabled) {
1157                         pm_runtime_put_sync_suspend(card->dev);
1158                         azx_suspend(card->dev);
1159                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1160                          * however we have no ACPI handle, so pci/acpi can't put us there,
1161                          * put ourselves there */
1162                         pci->current_state = PCI_D3cold;
1163                         chip->disabled = true;
1164                         if (snd_hda_lock_devices(&chip->bus))
1165                                 dev_warn(chip->card->dev,
1166                                          "Cannot lock devices!\n");
1167                 } else {
1168                         snd_hda_unlock_devices(&chip->bus);
1169                         pm_runtime_get_noresume(card->dev);
1170                         chip->disabled = false;
1171                         azx_resume(card->dev);
1172                 }
1173         }
1174 }
1175
1176 static bool azx_vs_can_switch(struct pci_dev *pci)
1177 {
1178         struct snd_card *card = pci_get_drvdata(pci);
1179         struct azx *chip = card->private_data;
1180         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1181
1182         wait_for_completion(&hda->probe_wait);
1183         if (hda->init_failed)
1184                 return false;
1185         if (chip->disabled || !hda->probe_continued)
1186                 return true;
1187         if (snd_hda_lock_devices(&chip->bus))
1188                 return false;
1189         snd_hda_unlock_devices(&chip->bus);
1190         return true;
1191 }
1192
1193 static void init_vga_switcheroo(struct azx *chip)
1194 {
1195         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1196         struct pci_dev *p = get_bound_vga(chip->pci);
1197         if (p) {
1198                 dev_info(chip->card->dev,
1199                          "Handle vga_switcheroo audio client\n");
1200                 hda->use_vga_switcheroo = 1;
1201                 pci_dev_put(p);
1202         }
1203 }
1204
1205 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1206         .set_gpu_state = azx_vs_set_state,
1207         .can_switch = azx_vs_can_switch,
1208 };
1209
1210 static int register_vga_switcheroo(struct azx *chip)
1211 {
1212         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1213         int err;
1214
1215         if (!hda->use_vga_switcheroo)
1216                 return 0;
1217         /* FIXME: currently only handling DIS controller
1218          * is there any machine with two switchable HDMI audio controllers?
1219          */
1220         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1221                                                    VGA_SWITCHEROO_DIS);
1222         if (err < 0)
1223                 return err;
1224         hda->vga_switcheroo_registered = 1;
1225
1226         /* register as an optimus hdmi audio power domain */
1227         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1228                                                          &hda->hdmi_pm_domain);
1229         return 0;
1230 }
1231 #else
1232 #define init_vga_switcheroo(chip)               /* NOP */
1233 #define register_vga_switcheroo(chip)           0
1234 #define check_hdmi_disabled(pci)        false
1235 #endif /* SUPPORT_VGA_SWITCHER */
1236
1237 /*
1238  * destructor
1239  */
1240 static int azx_free(struct azx *chip)
1241 {
1242         struct pci_dev *pci = chip->pci;
1243         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1244         struct hdac_bus *bus = azx_bus(chip);
1245
1246         if (azx_has_pm_runtime(chip) && chip->running)
1247                 pm_runtime_get_noresume(&pci->dev);
1248
1249         azx_del_card_list(chip);
1250
1251         hda->init_failed = 1; /* to be sure */
1252         complete_all(&hda->probe_wait);
1253
1254         if (use_vga_switcheroo(hda)) {
1255                 if (chip->disabled && hda->probe_continued)
1256                         snd_hda_unlock_devices(&chip->bus);
1257                 if (hda->vga_switcheroo_registered)
1258                         vga_switcheroo_unregister_client(chip->pci);
1259         }
1260
1261         if (bus->chip_init) {
1262                 azx_clear_irq_pending(chip);
1263                 azx_stop_all_streams(chip);
1264                 azx_stop_chip(chip);
1265         }
1266
1267         if (bus->irq >= 0)
1268                 free_irq(bus->irq, (void*)chip);
1269         if (chip->msi)
1270                 pci_disable_msi(chip->pci);
1271         iounmap(bus->remap_addr);
1272
1273         azx_free_stream_pages(chip);
1274         azx_free_streams(chip);
1275         snd_hdac_bus_exit(bus);
1276
1277         if (chip->region_requested)
1278                 pci_release_regions(chip->pci);
1279
1280         pci_disable_device(chip->pci);
1281 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1282         release_firmware(chip->fw);
1283 #endif
1284
1285         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1286                 if (hda->need_i915_power)
1287                         snd_hdac_display_power(bus, false);
1288                 snd_hdac_i915_exit(bus);
1289         }
1290         kfree(hda);
1291
1292         return 0;
1293 }
1294
1295 static int azx_dev_disconnect(struct snd_device *device)
1296 {
1297         struct azx *chip = device->device_data;
1298
1299         chip->bus.shutdown = 1;
1300         return 0;
1301 }
1302
1303 static int azx_dev_free(struct snd_device *device)
1304 {
1305         return azx_free(device->device_data);
1306 }
1307
1308 #ifdef SUPPORT_VGA_SWITCHEROO
1309 /*
1310  * Check of disabled HDMI controller by vga_switcheroo
1311  */
1312 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1313 {
1314         struct pci_dev *p;
1315
1316         /* check only discrete GPU */
1317         switch (pci->vendor) {
1318         case PCI_VENDOR_ID_ATI:
1319         case PCI_VENDOR_ID_AMD:
1320         case PCI_VENDOR_ID_NVIDIA:
1321                 if (pci->devfn == 1) {
1322                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1323                                                         pci->bus->number, 0);
1324                         if (p) {
1325                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1326                                         return p;
1327                                 pci_dev_put(p);
1328                         }
1329                 }
1330                 break;
1331         }
1332         return NULL;
1333 }
1334
1335 static bool check_hdmi_disabled(struct pci_dev *pci)
1336 {
1337         bool vga_inactive = false;
1338         struct pci_dev *p = get_bound_vga(pci);
1339
1340         if (p) {
1341                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1342                         vga_inactive = true;
1343                 pci_dev_put(p);
1344         }
1345         return vga_inactive;
1346 }
1347 #endif /* SUPPORT_VGA_SWITCHEROO */
1348
1349 /*
1350  * white/black-listing for position_fix
1351  */
1352 static struct snd_pci_quirk position_fix_list[] = {
1353         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1354         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1355         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1356         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1357         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1358         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1359         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1360         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1361         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1362         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1363         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1364         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1365         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1366         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1367         {}
1368 };
1369
1370 static int check_position_fix(struct azx *chip, int fix)
1371 {
1372         const struct snd_pci_quirk *q;
1373
1374         switch (fix) {
1375         case POS_FIX_AUTO:
1376         case POS_FIX_LPIB:
1377         case POS_FIX_POSBUF:
1378         case POS_FIX_VIACOMBO:
1379         case POS_FIX_COMBO:
1380                 return fix;
1381         }
1382
1383         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1384         if (q) {
1385                 dev_info(chip->card->dev,
1386                          "position_fix set to %d for device %04x:%04x\n",
1387                          q->value, q->subvendor, q->subdevice);
1388                 return q->value;
1389         }
1390
1391         /* Check VIA/ATI HD Audio Controller exist */
1392         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1393                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1394                 return POS_FIX_VIACOMBO;
1395         }
1396         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1397                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1398                 return POS_FIX_LPIB;
1399         }
1400         return POS_FIX_AUTO;
1401 }
1402
1403 static void assign_position_fix(struct azx *chip, int fix)
1404 {
1405         static azx_get_pos_callback_t callbacks[] = {
1406                 [POS_FIX_AUTO] = NULL,
1407                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1408                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1409                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1410                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1411         };
1412
1413         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1414
1415         /* combo mode uses LPIB only for playback */
1416         if (fix == POS_FIX_COMBO)
1417                 chip->get_position[1] = NULL;
1418
1419         if (fix == POS_FIX_POSBUF &&
1420             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1421                 chip->get_delay[0] = chip->get_delay[1] =
1422                         azx_get_delay_from_lpib;
1423         }
1424
1425 }
1426
1427 /*
1428  * black-lists for probe_mask
1429  */
1430 static struct snd_pci_quirk probe_mask_list[] = {
1431         /* Thinkpad often breaks the controller communication when accessing
1432          * to the non-working (or non-existing) modem codec slot.
1433          */
1434         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1435         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1436         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1437         /* broken BIOS */
1438         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1439         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1440         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1441         /* forced codec slots */
1442         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1443         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1444         /* WinFast VP200 H (Teradici) user reported broken communication */
1445         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1446         {}
1447 };
1448
1449 #define AZX_FORCE_CODEC_MASK    0x100
1450
1451 static void check_probe_mask(struct azx *chip, int dev)
1452 {
1453         const struct snd_pci_quirk *q;
1454
1455         chip->codec_probe_mask = probe_mask[dev];
1456         if (chip->codec_probe_mask == -1) {
1457                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1458                 if (q) {
1459                         dev_info(chip->card->dev,
1460                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1461                                  q->value, q->subvendor, q->subdevice);
1462                         chip->codec_probe_mask = q->value;
1463                 }
1464         }
1465
1466         /* check forced option */
1467         if (chip->codec_probe_mask != -1 &&
1468             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1469                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1470                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1471                          (int)azx_bus(chip)->codec_mask);
1472         }
1473 }
1474
1475 /*
1476  * white/black-list for enable_msi
1477  */
1478 static struct snd_pci_quirk msi_black_list[] = {
1479         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1480         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1481         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1482         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1483         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1484         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1485         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1486         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1487         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1488         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1489         {}
1490 };
1491
1492 static void check_msi(struct azx *chip)
1493 {
1494         const struct snd_pci_quirk *q;
1495
1496         if (enable_msi >= 0) {
1497                 chip->msi = !!enable_msi;
1498                 return;
1499         }
1500         chip->msi = 1;  /* enable MSI as default */
1501         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1502         if (q) {
1503                 dev_info(chip->card->dev,
1504                          "msi for device %04x:%04x set to %d\n",
1505                          q->subvendor, q->subdevice, q->value);
1506                 chip->msi = q->value;
1507                 return;
1508         }
1509
1510         /* NVidia chipsets seem to cause troubles with MSI */
1511         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1512                 dev_info(chip->card->dev, "Disabling MSI\n");
1513                 chip->msi = 0;
1514         }
1515 }
1516
1517 /* check the snoop mode availability */
1518 static void azx_check_snoop_available(struct azx *chip)
1519 {
1520         int snoop = hda_snoop;
1521
1522         if (snoop >= 0) {
1523                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1524                          snoop ? "snoop" : "non-snoop");
1525                 chip->snoop = snoop;
1526                 return;
1527         }
1528
1529         snoop = true;
1530         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1531             chip->driver_type == AZX_DRIVER_VIA) {
1532                 /* force to non-snoop mode for a new VIA controller
1533                  * when BIOS is set
1534                  */
1535                 u8 val;
1536                 pci_read_config_byte(chip->pci, 0x42, &val);
1537                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1538                         snoop = false;
1539         }
1540
1541         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1542                 snoop = false;
1543
1544         chip->snoop = snoop;
1545         if (!snoop)
1546                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1547 }
1548
1549 static void azx_probe_work(struct work_struct *work)
1550 {
1551         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1552         azx_probe_continue(&hda->chip);
1553 }
1554
1555 /*
1556  * constructor
1557  */
1558 static const struct hdac_io_ops pci_hda_io_ops;
1559 static const struct hda_controller_ops pci_hda_ops;
1560
1561 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1562                       int dev, unsigned int driver_caps,
1563                       struct azx **rchip)
1564 {
1565         static struct snd_device_ops ops = {
1566                 .dev_disconnect = azx_dev_disconnect,
1567                 .dev_free = azx_dev_free,
1568         };
1569         struct hda_intel *hda;
1570         struct azx *chip;
1571         int err;
1572
1573         *rchip = NULL;
1574
1575         err = pci_enable_device(pci);
1576         if (err < 0)
1577                 return err;
1578
1579         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1580         if (!hda) {
1581                 pci_disable_device(pci);
1582                 return -ENOMEM;
1583         }
1584
1585         chip = &hda->chip;
1586         mutex_init(&chip->open_mutex);
1587         chip->card = card;
1588         chip->pci = pci;
1589         chip->ops = &pci_hda_ops;
1590         chip->driver_caps = driver_caps;
1591         chip->driver_type = driver_caps & 0xff;
1592         check_msi(chip);
1593         chip->dev_index = dev;
1594         chip->jackpoll_ms = jackpoll_ms;
1595         INIT_LIST_HEAD(&chip->pcm_list);
1596         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1597         INIT_LIST_HEAD(&hda->list);
1598         init_vga_switcheroo(chip);
1599         init_completion(&hda->probe_wait);
1600
1601         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1602
1603         check_probe_mask(chip, dev);
1604
1605         chip->single_cmd = single_cmd;
1606         azx_check_snoop_available(chip);
1607
1608         if (bdl_pos_adj[dev] < 0) {
1609                 switch (chip->driver_type) {
1610                 case AZX_DRIVER_ICH:
1611                 case AZX_DRIVER_PCH:
1612                         bdl_pos_adj[dev] = 1;
1613                         break;
1614                 default:
1615                         bdl_pos_adj[dev] = 32;
1616                         break;
1617                 }
1618         }
1619         chip->bdl_pos_adj = bdl_pos_adj;
1620
1621         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1622         if (err < 0) {
1623                 kfree(hda);
1624                 pci_disable_device(pci);
1625                 return err;
1626         }
1627
1628         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1629         if (err < 0) {
1630                 dev_err(card->dev, "Error creating device [card]!\n");
1631                 azx_free(chip);
1632                 return err;
1633         }
1634
1635         /* continue probing in work context as may trigger request module */
1636         INIT_WORK(&hda->probe_work, azx_probe_work);
1637
1638         *rchip = chip;
1639
1640         return 0;
1641 }
1642
1643 static int azx_first_init(struct azx *chip)
1644 {
1645         int dev = chip->dev_index;
1646         struct pci_dev *pci = chip->pci;
1647         struct snd_card *card = chip->card;
1648         struct hdac_bus *bus = azx_bus(chip);
1649         int err;
1650         unsigned short gcap;
1651         unsigned int dma_bits = 64;
1652
1653 #if BITS_PER_LONG != 64
1654         /* Fix up base address on ULI M5461 */
1655         if (chip->driver_type == AZX_DRIVER_ULI) {
1656                 u16 tmp3;
1657                 pci_read_config_word(pci, 0x40, &tmp3);
1658                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1659                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1660         }
1661 #endif
1662
1663         err = pci_request_regions(pci, "ICH HD audio");
1664         if (err < 0)
1665                 return err;
1666         chip->region_requested = 1;
1667
1668         bus->addr = pci_resource_start(pci, 0);
1669         bus->remap_addr = pci_ioremap_bar(pci, 0);
1670         if (bus->remap_addr == NULL) {
1671                 dev_err(card->dev, "ioremap error\n");
1672                 return -ENXIO;
1673         }
1674
1675         if (chip->msi) {
1676                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1677                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1678                         pci->no_64bit_msi = true;
1679                 }
1680                 if (pci_enable_msi(pci) < 0)
1681                         chip->msi = 0;
1682         }
1683
1684         if (azx_acquire_irq(chip, 0) < 0)
1685                 return -EBUSY;
1686
1687         pci_set_master(pci);
1688         synchronize_irq(bus->irq);
1689
1690         gcap = azx_readw(chip, GCAP);
1691         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1692
1693         /* AMD devices support 40 or 48bit DMA, take the safe one */
1694         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1695                 dma_bits = 40;
1696
1697         /* disable SB600 64bit support for safety */
1698         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1699                 struct pci_dev *p_smbus;
1700                 dma_bits = 40;
1701                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1702                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1703                                          NULL);
1704                 if (p_smbus) {
1705                         if (p_smbus->revision < 0x30)
1706                                 gcap &= ~AZX_GCAP_64OK;
1707                         pci_dev_put(p_smbus);
1708                 }
1709         }
1710
1711         /* disable 64bit DMA address on some devices */
1712         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1713                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1714                 gcap &= ~AZX_GCAP_64OK;
1715         }
1716
1717         /* disable buffer size rounding to 128-byte multiples if supported */
1718         if (align_buffer_size >= 0)
1719                 chip->align_buffer_size = !!align_buffer_size;
1720         else {
1721                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1722                         chip->align_buffer_size = 0;
1723                 else
1724                         chip->align_buffer_size = 1;
1725         }
1726
1727         /* allow 64bit DMA address if supported by H/W */
1728         if (!(gcap & AZX_GCAP_64OK))
1729                 dma_bits = 32;
1730         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1731                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1732         } else {
1733                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1734                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1735         }
1736
1737         /* read number of streams from GCAP register instead of using
1738          * hardcoded value
1739          */
1740         chip->capture_streams = (gcap >> 8) & 0x0f;
1741         chip->playback_streams = (gcap >> 12) & 0x0f;
1742         if (!chip->playback_streams && !chip->capture_streams) {
1743                 /* gcap didn't give any info, switching to old method */
1744
1745                 switch (chip->driver_type) {
1746                 case AZX_DRIVER_ULI:
1747                         chip->playback_streams = ULI_NUM_PLAYBACK;
1748                         chip->capture_streams = ULI_NUM_CAPTURE;
1749                         break;
1750                 case AZX_DRIVER_ATIHDMI:
1751                 case AZX_DRIVER_ATIHDMI_NS:
1752                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1753                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1754                         break;
1755                 case AZX_DRIVER_GENERIC:
1756                 default:
1757                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1758                         chip->capture_streams = ICH6_NUM_CAPTURE;
1759                         break;
1760                 }
1761         }
1762         chip->capture_index_offset = 0;
1763         chip->playback_index_offset = chip->capture_streams;
1764         chip->num_streams = chip->playback_streams + chip->capture_streams;
1765
1766         /* initialize streams */
1767         err = azx_init_streams(chip);
1768         if (err < 0)
1769                 return err;
1770
1771         err = azx_alloc_stream_pages(chip);
1772         if (err < 0)
1773                 return err;
1774
1775         /* initialize chip */
1776         azx_init_pci(chip);
1777
1778         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1779                 struct hda_intel *hda;
1780
1781                 hda = container_of(chip, struct hda_intel, chip);
1782                 haswell_set_bclk(hda);
1783         }
1784
1785         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1786
1787         /* codec detection */
1788         if (!azx_bus(chip)->codec_mask) {
1789                 dev_err(card->dev, "no codecs found!\n");
1790                 return -ENODEV;
1791         }
1792
1793         strcpy(card->driver, "HDA-Intel");
1794         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1795                 sizeof(card->shortname));
1796         snprintf(card->longname, sizeof(card->longname),
1797                  "%s at 0x%lx irq %i",
1798                  card->shortname, bus->addr, bus->irq);
1799
1800         return 0;
1801 }
1802
1803 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1804 /* callback from request_firmware_nowait() */
1805 static void azx_firmware_cb(const struct firmware *fw, void *context)
1806 {
1807         struct snd_card *card = context;
1808         struct azx *chip = card->private_data;
1809         struct pci_dev *pci = chip->pci;
1810
1811         if (!fw) {
1812                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1813                 goto error;
1814         }
1815
1816         chip->fw = fw;
1817         if (!chip->disabled) {
1818                 /* continue probing */
1819                 if (azx_probe_continue(chip))
1820                         goto error;
1821         }
1822         return; /* OK */
1823
1824  error:
1825         snd_card_free(card);
1826         pci_set_drvdata(pci, NULL);
1827 }
1828 #endif
1829
1830 /*
1831  * HDA controller ops.
1832  */
1833
1834 /* PCI register access. */
1835 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1836 {
1837         writel(value, addr);
1838 }
1839
1840 static u32 pci_azx_readl(u32 __iomem *addr)
1841 {
1842         return readl(addr);
1843 }
1844
1845 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1846 {
1847         writew(value, addr);
1848 }
1849
1850 static u16 pci_azx_readw(u16 __iomem *addr)
1851 {
1852         return readw(addr);
1853 }
1854
1855 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1856 {
1857         writeb(value, addr);
1858 }
1859
1860 static u8 pci_azx_readb(u8 __iomem *addr)
1861 {
1862         return readb(addr);
1863 }
1864
1865 static int disable_msi_reset_irq(struct azx *chip)
1866 {
1867         struct hdac_bus *bus = azx_bus(chip);
1868         int err;
1869
1870         free_irq(bus->irq, chip);
1871         bus->irq = -1;
1872         pci_disable_msi(chip->pci);
1873         chip->msi = 0;
1874         err = azx_acquire_irq(chip, 1);
1875         if (err < 0)
1876                 return err;
1877
1878         return 0;
1879 }
1880
1881 /* DMA page allocation helpers.  */
1882 static int dma_alloc_pages(struct hdac_bus *bus,
1883                            int type,
1884                            size_t size,
1885                            struct snd_dma_buffer *buf)
1886 {
1887         struct azx *chip = bus_to_azx(bus);
1888         int err;
1889
1890         err = snd_dma_alloc_pages(type,
1891                                   bus->dev,
1892                                   size, buf);
1893         if (err < 0)
1894                 return err;
1895         mark_pages_wc(chip, buf, true);
1896         return 0;
1897 }
1898
1899 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1900 {
1901         struct azx *chip = bus_to_azx(bus);
1902
1903         mark_pages_wc(chip, buf, false);
1904         snd_dma_free_pages(buf);
1905 }
1906
1907 static int substream_alloc_pages(struct azx *chip,
1908                                  struct snd_pcm_substream *substream,
1909                                  size_t size)
1910 {
1911         struct azx_dev *azx_dev = get_azx_dev(substream);
1912         int ret;
1913
1914         mark_runtime_wc(chip, azx_dev, substream, false);
1915         ret = snd_pcm_lib_malloc_pages(substream, size);
1916         if (ret < 0)
1917                 return ret;
1918         mark_runtime_wc(chip, azx_dev, substream, true);
1919         return 0;
1920 }
1921
1922 static int substream_free_pages(struct azx *chip,
1923                                 struct snd_pcm_substream *substream)
1924 {
1925         struct azx_dev *azx_dev = get_azx_dev(substream);
1926         mark_runtime_wc(chip, azx_dev, substream, false);
1927         return snd_pcm_lib_free_pages(substream);
1928 }
1929
1930 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1931                              struct vm_area_struct *area)
1932 {
1933 #ifdef CONFIG_X86
1934         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1935         struct azx *chip = apcm->chip;
1936         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1937                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1938 #endif
1939 }
1940
1941 static const struct hdac_io_ops pci_hda_io_ops = {
1942         .reg_writel = pci_azx_writel,
1943         .reg_readl = pci_azx_readl,
1944         .reg_writew = pci_azx_writew,
1945         .reg_readw = pci_azx_readw,
1946         .reg_writeb = pci_azx_writeb,
1947         .reg_readb = pci_azx_readb,
1948         .dma_alloc_pages = dma_alloc_pages,
1949         .dma_free_pages = dma_free_pages,
1950 };
1951
1952 static const struct hda_controller_ops pci_hda_ops = {
1953         .disable_msi_reset_irq = disable_msi_reset_irq,
1954         .substream_alloc_pages = substream_alloc_pages,
1955         .substream_free_pages = substream_free_pages,
1956         .pcm_mmap_prepare = pcm_mmap_prepare,
1957         .position_check = azx_position_check,
1958         .link_power = azx_intel_link_power,
1959 };
1960
1961 static int azx_probe(struct pci_dev *pci,
1962                      const struct pci_device_id *pci_id)
1963 {
1964         static int dev;
1965         struct snd_card *card;
1966         struct hda_intel *hda;
1967         struct azx *chip;
1968         bool schedule_probe;
1969         int err;
1970
1971         if (dev >= SNDRV_CARDS)
1972                 return -ENODEV;
1973         if (!enable[dev]) {
1974                 dev++;
1975                 return -ENOENT;
1976         }
1977
1978         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1979                            0, &card);
1980         if (err < 0) {
1981                 dev_err(&pci->dev, "Error creating card!\n");
1982                 return err;
1983         }
1984
1985         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1986         if (err < 0)
1987                 goto out_free;
1988         card->private_data = chip;
1989         hda = container_of(chip, struct hda_intel, chip);
1990
1991         pci_set_drvdata(pci, card);
1992
1993         err = register_vga_switcheroo(chip);
1994         if (err < 0) {
1995                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
1996                 goto out_free;
1997         }
1998
1999         if (check_hdmi_disabled(pci)) {
2000                 dev_info(card->dev, "VGA controller is disabled\n");
2001                 dev_info(card->dev, "Delaying initialization\n");
2002                 chip->disabled = true;
2003         }
2004
2005         schedule_probe = !chip->disabled;
2006
2007 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2008         if (patch[dev] && *patch[dev]) {
2009                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2010                          patch[dev]);
2011                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2012                                               &pci->dev, GFP_KERNEL, card,
2013                                               azx_firmware_cb);
2014                 if (err < 0)
2015                         goto out_free;
2016                 schedule_probe = false; /* continued in azx_firmware_cb() */
2017         }
2018 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2019
2020 #ifndef CONFIG_SND_HDA_I915
2021         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2022                 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
2023 #endif
2024
2025         if (schedule_probe)
2026                 schedule_work(&hda->probe_work);
2027
2028         dev++;
2029         if (chip->disabled)
2030                 complete_all(&hda->probe_wait);
2031         return 0;
2032
2033 out_free:
2034         snd_card_free(card);
2035         return err;
2036 }
2037
2038 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2039 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2040         [AZX_DRIVER_NVIDIA] = 8,
2041         [AZX_DRIVER_TERA] = 1,
2042 };
2043
2044 static int azx_probe_continue(struct azx *chip)
2045 {
2046         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2047         struct hdac_bus *bus = azx_bus(chip);
2048         struct pci_dev *pci = chip->pci;
2049         int dev = chip->dev_index;
2050         int err;
2051
2052         hda->probe_continued = 1;
2053
2054         /* Request display power well for the HDA controller or codec. For
2055          * Haswell/Broadwell, both the display HDA controller and codec need
2056          * this power. For other platforms, like Baytrail/Braswell, only the
2057          * display codec needs the power and it can be released after probe.
2058          */
2059         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2060                 /* HSW/BDW controllers need this power */
2061                 if (CONTROLLER_IN_GPU(pci))
2062                         hda->need_i915_power = 1;
2063
2064                 err = snd_hdac_i915_init(bus);
2065                 if (err < 0) {
2066                         /* if the controller is bound only with HDMI/DP
2067                          * (for HSW and BDW), we need to abort the probe;
2068                          * for other chips, still continue probing as other
2069                          * codecs can be on the same link.
2070                          */
2071                         if (CONTROLLER_IN_GPU(pci))
2072                                 goto out_free;
2073                         else
2074                                 goto skip_i915;
2075                 }
2076
2077                 err = snd_hdac_display_power(bus, true);
2078                 if (err < 0) {
2079                         dev_err(chip->card->dev,
2080                                 "Cannot turn on display power on i915\n");
2081                         goto i915_power_fail;
2082                 }
2083         }
2084
2085  skip_i915:
2086         err = azx_first_init(chip);
2087         if (err < 0)
2088                 goto out_free;
2089
2090 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2091         chip->beep_mode = beep_mode[dev];
2092 #endif
2093
2094         /* create codec instances */
2095         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2096         if (err < 0)
2097                 goto out_free;
2098
2099 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2100         if (chip->fw) {
2101                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2102                                          chip->fw->data);
2103                 if (err < 0)
2104                         goto out_free;
2105 #ifndef CONFIG_PM
2106                 release_firmware(chip->fw); /* no longer needed */
2107                 chip->fw = NULL;
2108 #endif
2109         }
2110 #endif
2111         if ((probe_only[dev] & 1) == 0) {
2112                 err = azx_codec_configure(chip);
2113                 if (err < 0)
2114                         goto out_free;
2115         }
2116
2117         err = snd_card_register(chip->card);
2118         if (err < 0)
2119                 goto out_free;
2120
2121         chip->running = 1;
2122         azx_add_card_list(chip);
2123         snd_hda_set_power_save(&chip->bus, power_save * 1000);
2124         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2125                 pm_runtime_put_noidle(&pci->dev);
2126
2127 out_free:
2128         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2129                 && !hda->need_i915_power)
2130                 snd_hdac_display_power(bus, false);
2131
2132 i915_power_fail:
2133         if (err < 0)
2134                 hda->init_failed = 1;
2135         complete_all(&hda->probe_wait);
2136         return err;
2137 }
2138
2139 static void azx_remove(struct pci_dev *pci)
2140 {
2141         struct snd_card *card = pci_get_drvdata(pci);
2142         struct azx *chip;
2143         struct hda_intel *hda;
2144
2145         if (card) {
2146                 /* cancel the pending probing work */
2147                 chip = card->private_data;
2148                 hda = container_of(chip, struct hda_intel, chip);
2149                 cancel_work_sync(&hda->probe_work);
2150
2151                 snd_card_free(card);
2152         }
2153 }
2154
2155 static void azx_shutdown(struct pci_dev *pci)
2156 {
2157         struct snd_card *card = pci_get_drvdata(pci);
2158         struct azx *chip;
2159
2160         if (!card)
2161                 return;
2162         chip = card->private_data;
2163         if (chip && chip->running)
2164                 azx_stop_chip(chip);
2165 }
2166
2167 /* PCI IDs */
2168 static const struct pci_device_id azx_ids[] = {
2169         /* CPT */
2170         { PCI_DEVICE(0x8086, 0x1c20),
2171           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2172         /* PBG */
2173         { PCI_DEVICE(0x8086, 0x1d20),
2174           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2175         /* Panther Point */
2176         { PCI_DEVICE(0x8086, 0x1e20),
2177           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2178         /* Lynx Point */
2179         { PCI_DEVICE(0x8086, 0x8c20),
2180           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2181         /* 9 Series */
2182         { PCI_DEVICE(0x8086, 0x8ca0),
2183           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2184         /* Wellsburg */
2185         { PCI_DEVICE(0x8086, 0x8d20),
2186           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2187         { PCI_DEVICE(0x8086, 0x8d21),
2188           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2189         /* Lewisburg */
2190         { PCI_DEVICE(0x8086, 0xa1f0),
2191           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2192         { PCI_DEVICE(0x8086, 0xa270),
2193           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2194         /* Lynx Point-LP */
2195         { PCI_DEVICE(0x8086, 0x9c20),
2196           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2197         /* Lynx Point-LP */
2198         { PCI_DEVICE(0x8086, 0x9c21),
2199           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2200         /* Wildcat Point-LP */
2201         { PCI_DEVICE(0x8086, 0x9ca0),
2202           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2203         /* Sunrise Point */
2204         { PCI_DEVICE(0x8086, 0xa170),
2205           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2206         /* Sunrise Point-LP */
2207         { PCI_DEVICE(0x8086, 0x9d70),
2208           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2209         /* Broxton-P(Apollolake) */
2210         { PCI_DEVICE(0x8086, 0x5a98),
2211           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2212         /* Haswell */
2213         { PCI_DEVICE(0x8086, 0x0a0c),
2214           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2215         { PCI_DEVICE(0x8086, 0x0c0c),
2216           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2217         { PCI_DEVICE(0x8086, 0x0d0c),
2218           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2219         /* Broadwell */
2220         { PCI_DEVICE(0x8086, 0x160c),
2221           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2222         /* 5 Series/3400 */
2223         { PCI_DEVICE(0x8086, 0x3b56),
2224           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2225         /* Poulsbo */
2226         { PCI_DEVICE(0x8086, 0x811b),
2227           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2228         /* Oaktrail */
2229         { PCI_DEVICE(0x8086, 0x080a),
2230           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2231         /* BayTrail */
2232         { PCI_DEVICE(0x8086, 0x0f04),
2233           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2234         /* Braswell */
2235         { PCI_DEVICE(0x8086, 0x2284),
2236           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2237         /* ICH6 */
2238         { PCI_DEVICE(0x8086, 0x2668),
2239           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2240         /* ICH7 */
2241         { PCI_DEVICE(0x8086, 0x27d8),
2242           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2243         /* ESB2 */
2244         { PCI_DEVICE(0x8086, 0x269a),
2245           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2246         /* ICH8 */
2247         { PCI_DEVICE(0x8086, 0x284b),
2248           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2249         /* ICH9 */
2250         { PCI_DEVICE(0x8086, 0x293e),
2251           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2252         /* ICH9 */
2253         { PCI_DEVICE(0x8086, 0x293f),
2254           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2255         /* ICH10 */
2256         { PCI_DEVICE(0x8086, 0x3a3e),
2257           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2258         /* ICH10 */
2259         { PCI_DEVICE(0x8086, 0x3a6e),
2260           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2261         /* Generic Intel */
2262         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2263           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2264           .class_mask = 0xffffff,
2265           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2266         /* ATI SB 450/600/700/800/900 */
2267         { PCI_DEVICE(0x1002, 0x437b),
2268           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2269         { PCI_DEVICE(0x1002, 0x4383),
2270           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2271         /* AMD Hudson */
2272         { PCI_DEVICE(0x1022, 0x780d),
2273           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2274         /* ATI HDMI */
2275         { PCI_DEVICE(0x1002, 0x1308),
2276           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2277         { PCI_DEVICE(0x1002, 0x157a),
2278           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2279         { PCI_DEVICE(0x1002, 0x793b),
2280           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2281         { PCI_DEVICE(0x1002, 0x7919),
2282           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2283         { PCI_DEVICE(0x1002, 0x960f),
2284           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2285         { PCI_DEVICE(0x1002, 0x970f),
2286           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2287         { PCI_DEVICE(0x1002, 0x9840),
2288           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2289         { PCI_DEVICE(0x1002, 0xaa00),
2290           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2291         { PCI_DEVICE(0x1002, 0xaa08),
2292           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2293         { PCI_DEVICE(0x1002, 0xaa10),
2294           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2295         { PCI_DEVICE(0x1002, 0xaa18),
2296           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2297         { PCI_DEVICE(0x1002, 0xaa20),
2298           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2299         { PCI_DEVICE(0x1002, 0xaa28),
2300           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2301         { PCI_DEVICE(0x1002, 0xaa30),
2302           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2303         { PCI_DEVICE(0x1002, 0xaa38),
2304           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2305         { PCI_DEVICE(0x1002, 0xaa40),
2306           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2307         { PCI_DEVICE(0x1002, 0xaa48),
2308           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2309         { PCI_DEVICE(0x1002, 0xaa50),
2310           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2311         { PCI_DEVICE(0x1002, 0xaa58),
2312           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2313         { PCI_DEVICE(0x1002, 0xaa60),
2314           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2315         { PCI_DEVICE(0x1002, 0xaa68),
2316           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2317         { PCI_DEVICE(0x1002, 0xaa80),
2318           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2319         { PCI_DEVICE(0x1002, 0xaa88),
2320           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2321         { PCI_DEVICE(0x1002, 0xaa90),
2322           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2323         { PCI_DEVICE(0x1002, 0xaa98),
2324           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2325         { PCI_DEVICE(0x1002, 0x9902),
2326           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2327         { PCI_DEVICE(0x1002, 0xaaa0),
2328           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2329         { PCI_DEVICE(0x1002, 0xaaa8),
2330           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2331         { PCI_DEVICE(0x1002, 0xaab0),
2332           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2333         { PCI_DEVICE(0x1002, 0xaac0),
2334           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2335         { PCI_DEVICE(0x1002, 0xaac8),
2336           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2337         { PCI_DEVICE(0x1002, 0xaad8),
2338           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2339         { PCI_DEVICE(0x1002, 0xaae8),
2340           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2341         /* VIA VT8251/VT8237A */
2342         { PCI_DEVICE(0x1106, 0x3288),
2343           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2344         /* VIA GFX VT7122/VX900 */
2345         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2346         /* VIA GFX VT6122/VX11 */
2347         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2348         /* SIS966 */
2349         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2350         /* ULI M5461 */
2351         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2352         /* NVIDIA MCP */
2353         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2354           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2355           .class_mask = 0xffffff,
2356           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2357         /* Teradici */
2358         { PCI_DEVICE(0x6549, 0x1200),
2359           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2360         { PCI_DEVICE(0x6549, 0x2200),
2361           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2362         /* Creative X-Fi (CA0110-IBG) */
2363         /* CTHDA chips */
2364         { PCI_DEVICE(0x1102, 0x0010),
2365           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2366         { PCI_DEVICE(0x1102, 0x0012),
2367           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2368 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2369         /* the following entry conflicts with snd-ctxfi driver,
2370          * as ctxfi driver mutates from HD-audio to native mode with
2371          * a special command sequence.
2372          */
2373         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2374           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2375           .class_mask = 0xffffff,
2376           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2377           AZX_DCAPS_NO_64BIT |
2378           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2379 #else
2380         /* this entry seems still valid -- i.e. without emu20kx chip */
2381         { PCI_DEVICE(0x1102, 0x0009),
2382           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2383           AZX_DCAPS_NO_64BIT |
2384           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2385 #endif
2386         /* CM8888 */
2387         { PCI_DEVICE(0x13f6, 0x5011),
2388           .driver_data = AZX_DRIVER_CMEDIA |
2389           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2390         /* Vortex86MX */
2391         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2392         /* VMware HDAudio */
2393         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2394         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2395         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2396           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2397           .class_mask = 0xffffff,
2398           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2399         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2400           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2401           .class_mask = 0xffffff,
2402           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2403         { 0, }
2404 };
2405 MODULE_DEVICE_TABLE(pci, azx_ids);
2406
2407 /* pci_driver definition */
2408 static struct pci_driver azx_driver = {
2409         .name = KBUILD_MODNAME,
2410         .id_table = azx_ids,
2411         .probe = azx_probe,
2412         .remove = azx_remove,
2413         .shutdown = azx_shutdown,
2414         .driver = {
2415                 .pm = AZX_PM_OPS,
2416         },
2417 };
2418
2419 module_pci_driver(azx_driver);