3 * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd
5 * Mark Yao <yzq@rock-chips.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #ifndef _UAPI_ROCKCHIP_DRM_H
16 #define _UAPI_ROCKCHIP_DRM_H
20 /* memory type definitions. */
21 enum drm_rockchip_gem_mem_type {
22 /* Physically Continuous memory. */
23 ROCKCHIP_BO_CONTIG = 1 << 0,
24 /* cachable mapping. */
25 ROCKCHIP_BO_CACHABLE = 1 << 1,
26 /* write-combine mapping. */
27 ROCKCHIP_BO_WC = 1 << 2,
28 ROCKCHIP_BO_MASK = ROCKCHIP_BO_CONTIG | ROCKCHIP_BO_CACHABLE |
33 * User-desired buffer creation information structure.
35 * @size: user-desired memory allocation size.
36 * @flags: user request for setting memory type or cache attributes.
37 * @handle: returned a handle to created gem object.
38 * - this handle will be set by gem module of kernel side.
40 struct drm_rockchip_gem_create {
46 struct drm_rockchip_gem_phys {
52 * A structure for getting buffer offset.
54 * @handle: a pointer to gem object created.
55 * @pad: just padding to be 64-bit aligned.
56 * @offset: relatived offset value of the memory region allocated.
57 * - this value should be set by user.
59 struct drm_rockchip_gem_map_off {
65 /* acquire type definitions. */
66 enum drm_rockchip_gem_cpu_acquire_type {
67 DRM_ROCKCHIP_GEM_CPU_ACQUIRE_SHARED = 0x0,
68 DRM_ROCKCHIP_GEM_CPU_ACQUIRE_EXCLUSIVE = 0x1,
72 * A structure for acquiring buffer for CPU access.
74 * @handle: a handle to gem object created.
75 * @flags: acquire flag
77 struct drm_rockchip_gem_cpu_acquire {
83 * A structure for releasing buffer for GPU access.
85 * @handle: a handle to gem object created.
87 struct drm_rockchip_gem_cpu_release {
91 struct drm_rockchip_rga_get_ver {
96 struct drm_rockchip_rga_cmd {
101 enum drm_rockchip_rga_buf_type {
102 RGA_BUF_TYPE_USERPTR = 1 << 31,
103 RGA_BUF_TYPE_GEMFD = 1 << 30,
104 RGA_BUF_TYPE_FLUSH = 1 << 29,
107 struct drm_rockchip_rga_set_cmdlist {
115 struct drm_rockchip_rga_exec {
119 enum rockchip_plane_feture {
120 ROCKCHIP_DRM_PLANE_FEATURE_SCALE,
121 ROCKCHIP_DRM_PLANE_FEATURE_ALPHA,
122 ROCKCHIP_DRM_PLANE_FEATURE_MAX,
125 enum rockchip_crtc_feture {
126 ROCKCHIP_DRM_CRTC_FEATURE_AFBDC,
129 enum rockchip_cabc_mode {
130 ROCKCHIP_DRM_CABC_MODE_DISABLE,
131 ROCKCHIP_DRM_CABC_MODE_NORMAL,
132 ROCKCHIP_DRM_CABC_MODE_LOWPOWER,
133 ROCKCHIP_DRM_CABC_MODE_USERSPACE,
136 #define DRM_ROCKCHIP_GEM_CREATE 0x00
137 #define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01
138 #define DRM_ROCKCHIP_GEM_CPU_ACQUIRE 0x02
139 #define DRM_ROCKCHIP_GEM_CPU_RELEASE 0x03
140 #define DRM_ROCKCHIP_GEM_GET_PHYS 0x04
142 #define DRM_ROCKCHIP_RGA_GET_VER 0x20
143 #define DRM_ROCKCHIP_RGA_SET_CMDLIST 0x21
144 #define DRM_ROCKCHIP_RGA_EXEC 0x22
146 #define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
147 DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create)
149 #define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
150 DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off)
152 #define DRM_IOCTL_ROCKCHIP_GEM_CPU_ACQUIRE DRM_IOWR(DRM_COMMAND_BASE + \
153 DRM_ROCKCHIP_GEM_CPU_ACQUIRE, struct drm_rockchip_gem_cpu_acquire)
155 #define DRM_IOCTL_ROCKCHIP_GEM_CPU_RELEASE DRM_IOWR(DRM_COMMAND_BASE + \
156 DRM_ROCKCHIP_GEM_CPU_RELEASE, struct drm_rockchip_gem_cpu_release)
158 #define DRM_IOCTL_ROCKCHIP_GEM_GET_PHYS DRM_IOWR(DRM_COMMAND_BASE + \
159 DRM_ROCKCHIP_GEM_GET_PHYS, struct drm_rockchip_gem_phys)
161 #define DRM_IOCTL_ROCKCHIP_RGA_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
162 DRM_ROCKCHIP_RGA_GET_VER, struct drm_rockchip_rga_get_ver)
164 #define DRM_IOCTL_ROCKCHIP_RGA_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
165 DRM_ROCKCHIP_RGA_SET_CMDLIST, struct drm_rockchip_rga_set_cmdlist)
167 #define DRM_IOCTL_ROCKCHIP_RGA_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
168 DRM_ROCKCHIP_RGA_EXEC, struct drm_rockchip_rga_exec)
170 #endif /* _UAPI_ROCKCHIP_DRM_H */