ab033722ef6b27a71e3cdd25a0cab8ab059a43ec
[firefly-linux-kernel-4.4.55.git] / include / linux / rockchip / grf.h
1 #ifndef __MACH_ROCKCHIP_GRF_H
2 #define __MACH_ROCKCHIP_GRF_H
3
4 #define RK3188_GRF_GPIO0L_DIR           0x0000
5 #define RK3188_GRF_GPIO0H_DIR           0x0004
6 #define RK3188_GRF_GPIO1L_DIR           0x0008
7 #define RK3188_GRF_GPIO1H_DIR           0x000c
8 #define RK3188_GRF_GPIO2L_DIR           0x0010
9 #define RK3188_GRF_GPIO2H_DIR           0x0014
10 #define RK3188_GRF_GPIO3L_DIR           0x0018
11 #define RK3188_GRF_GPIO3H_DIR           0x001c
12 #define RK3188_GRF_GPIO0L_DO            0x0020
13 #define RK3188_GRF_GPIO0H_DO            0x0024
14 #define RK3188_GRF_GPIO1L_DO            0x0028
15 #define RK3188_GRF_GPIO1H_DO            0x002c
16 #define RK3188_GRF_GPIO2L_DO            0x0030
17 #define RK3188_GRF_GPIO2H_DO            0x0034
18 #define RK3188_GRF_GPIO3L_DO            0x0038
19 #define RK3188_GRF_GPIO3H_DO            0x003c
20 #define RK3188_GRF_GPIO0L_EN            0x0040
21 #define RK3188_GRF_GPIO0H_EN            0x0044
22 #define RK3188_GRF_GPIO1L_EN            0x0048
23 #define RK3188_GRF_GPIO1H_EN            0x004c
24 #define RK3188_GRF_GPIO2L_EN            0x0050
25 #define RK3188_GRF_GPIO2H_EN            0x0054
26 #define RK3188_GRF_GPIO3L_EN            0x0058
27 #define RK3188_GRF_GPIO3H_EN            0x005c
28
29 #define RK3188_GRF_GPIO0C_IOMUX         0x0068
30 #define RK3188_GRF_GPIO0D_IOMUX         0x006c
31 #define RK3188_GRF_GPIO1A_IOMUX         0x0070
32 #define RK3188_GRF_GPIO1B_IOMUX         0x0074
33 #define RK3188_GRF_GPIO1C_IOMUX         0x0078
34 #define RK3188_GRF_GPIO1D_IOMUX         0x007c
35 #define RK3188_GRF_GPIO2A_IOMUX         0x0080
36 #define RK3188_GRF_GPIO2B_IOMUX         0x0084
37 #define RK3188_GRF_GPIO2C_IOMUX         0x0088
38 #define RK3188_GRF_GPIO2D_IOMUX         0x008c
39 #define RK3188_GRF_GPIO3A_IOMUX         0x0090
40 #define RK3188_GRF_GPIO3B_IOMUX         0x0094
41 #define RK3188_GRF_GPIO3C_IOMUX         0x0098
42 #define RK3188_GRF_GPIO3D_IOMUX         0x009c
43 #define RK3188_GRF_SOC_CON0             0x00a0
44 #define RK3188_GRF_SOC_CON1             0x00a4
45 #define RK3188_GRF_SOC_CON2             0x00a8
46 #define RK3188_GRF_SOC_STATUS0          0x00ac
47 #define RK3188_GRF_DMAC1_CON0           0x00b0
48 #define RK3188_GRF_DMAC1_CON1           0x00b4
49 #define RK3188_GRF_DMAC1_CON2           0x00b8
50 #define RK3188_GRF_DMAC2_CON0           0x00bc
51 #define RK3188_GRF_DMAC2_CON1           0x00c0
52 #define RK3188_GRF_DMAC2_CON2           0x00c4
53 #define RK3188_GRF_DMAC2_CON3           0x00c8
54 #define RK3188_GRF_CPU_CON0             0x00cc
55 #define RK3188_GRF_CPU_CON1             0x00d0
56 #define RK3188_GRF_CPU_CON2             0x00d4
57 #define RK3188_GRF_CPU_CON3             0x00d8
58 #define RK3188_GRF_CPU_CON4             0x00dc
59 #define RK3188_GRF_CPU_CON5             0x00e0
60
61 #define RK3188_GRF_DDRC_CON0            0x00ec
62 #define RK3188_GRF_DDRC_STAT            0x00f0
63 #define RK3188_GRF_IO_CON0              0x00f4
64 #define RK3188_GRF_IO_CON1              0x00f8
65 #define RK3188_GRF_IO_CON2              0x00fc
66 #define RK3188_GRF_IO_CON3              0x0100
67 #define RK3188_GRF_IO_CON4              0x0104
68 #define RK3188_GRF_SOC_STATUS1          0x0108
69 #define RK3188_GRF_UOC0_CON0            0x010c
70 #define RK3188_GRF_UOC0_CON1            0x0110
71 #define RK3188_GRF_UOC0_CON2            0x0114
72 #define RK3188_GRF_UOC0_CON3            0x0118
73 #define RK3188_GRF_UOC1_CON0            0x011c
74 #define RK3188_GRF_UOC1_CON1            0x0120
75 #define RK3188_GRF_UOC1_CON2            0x0124
76 #define RK3188_GRF_UOC1_CON3            0x0128
77 #define RK3188_GRF_UOC2_CON0            0x012c
78 #define RK3188_GRF_UOC2_CON1            0x0130
79
80 #define RK3188_GRF_UOC3_CON0            0x0138
81 #define RK3188_GRF_UOC3_CON1            0x013c
82 #define RK3188_GRF_EHCI_STAT            0x0140
83 #define RK3188_GRF_OS_REG0              0x0144
84 #define RK3188_GRF_OS_REG1              0x0148
85 #define RK3188_GRF_OS_REG2              0x014c
86 #define RK3188_GRF_OS_REG3              0x0150
87 #define RK3188_GRF_OS_REG4              0x0154
88 #define RK3188_GRF_OS_REG5              0x0158
89 #define RK3188_GRF_OS_REG6              0x015c
90 #define RK3188_GRF_OS_REG7              0x0160
91 #define RK3188_GRF_GPIO0B_PULL          0x0164
92 #define RK3188_GRF_GPIO0C_PULL          0x0168
93 #define RK3188_GRF_GPIO0D_PULL          0x016c
94 #define RK3188_GRF_GPIO1A_PULL          0x0170
95 #define RK3188_GRF_GPIO1B_PULL          0x0174
96 #define RK3188_GRF_GPIO1C_PULL          0x0178
97 #define RK3188_GRF_GPIO1D_PULL          0x017c
98 #define RK3188_GRF_GPIO2A_PULL          0x0180
99 #define RK3188_GRF_GPIO2B_PULL          0x0184
100 #define RK3188_GRF_GPIO2C_PULL          0x0188
101 #define RK3188_GRF_GPIO2D_PULL          0x018c
102 #define RK3188_GRF_GPIO3A_PULL          0x0190
103 #define RK3188_GRF_GPIO3B_PULL          0x0194
104 #define RK3188_GRF_GPIO3C_PULL          0x0198
105 #define RK3188_GRF_GPIO3D_PULL          0x019c
106 #define RK3188_GRF_FLASH_DATA_PULL      0x01a0
107 #define RK3188_GRF_FLASH_CMD_PULL       0x01a4
108
109
110 #define RK3288_GRF_GPIO0_A_IOMUX        0x0084
111 #define RK3288_GRF_GPIO0_B_IOMUX        0x0088
112 #define RK3288_GRF_GPIO0_C_IOMUX        0x008c
113
114 #define RK3288_GRF_GPIO1D_IOMUX         0x000c
115 #define RK3288_GRF_GPIO2A_IOMUX         0x0010
116 #define RK3288_GRF_GPIO2B_IOMUX         0x0014
117 #define RK3288_GRF_GPIO2C_IOMUX         0x0018
118
119 #define RK3288_GRF_GPIO3A_IOMUX         0x0020
120 #define RK3288_GRF_GPIO3B_IOMUX         0x0024
121 #define RK3288_GRF_GPIO3C_IOMUX         0x0028
122 #define RK3288_GRF_GPIO3DL_IOMUX        0x002c
123 #define RK3288_GRF_GPIO3DH_IOMUX        0x0030
124 #define RK3288_GRF_GPIO4AL_IOMUX        0x0034
125 #define RK3288_GRF_GPIO4AH_IOMUX        0x0038
126 #define RK3288_GRF_GPIO4BL_IOMUX        0x003c
127
128 #define RK3288_GRF_GPIO4C_IOMUX         0x0044
129 #define RK3288_GRF_GPIO4D_IOMUX         0x0048
130
131 #define RK3288_GRF_GPIO5B_IOMUX         0x0050
132 #define RK3288_GRF_GPIO5C_IOMUX         0x0054
133
134 #define RK3288_GRF_GPIO6A_IOMUX         0x005c
135 #define RK3288_GRF_GPIO6B_IOMUX         0x0060
136 #define RK3288_GRF_GPIO6C_IOMUX         0x0064
137
138 #define RK3288_GRF_GPIO7A_IOMUX         0x006c
139 #define RK3288_GRF_GPIO7B_IOMUX         0x0070
140 #define RK3288_GRF_GPIO7CL_IOMUX        0x0074
141 #define RK3288_GRF_GPIO7CH_IOMUX        0x0078
142
143 #define RK3288_GRF_GPIO8A_IOMUX         0x0080
144 #define RK3288_GRF_GPIO8B_IOMUX         0x0084
145
146 #define RK3288_GRF_GPIO1H_SR            0x0104
147 #define RK3288_GRF_GPIO2L_SR            0x0108
148 #define RK3288_GRF_GPIO2H_SR            0x010c
149 #define RK3288_GRF_GPIO3L_SR            0x0110
150 #define RK3288_GRF_GPIO3H_SR            0x0114
151 #define RK3288_GRF_GPIO4L_SR            0x0118
152 #define RK3288_GRF_GPIO4H_SR            0x011c
153 #define RK3288_GRF_GPIO5L_SR            0x0120
154 #define RK3288_GRF_GPIO5H_SR            0x0124
155 #define RK3288_GRF_GPIO6L_SR            0x0128
156 #define RK3288_GRF_GPIO6H_SR            0x012c
157 #define RK3288_GRF_GPIO7L_SR            0x0130
158 #define RK3288_GRF_GPIO7H_SR            0x0134
159 #define RK3288_GRF_GPIO8L_SR            0x0138
160
161 #define RK3288_GRF_GPIO1D_P             0x014c
162 #define RK3288_GRF_GPIO2A_P             0x0150
163 #define RK3288_GRF_GPIO2B_P             0x0154
164 #define RK3288_GRF_GPIO2C_P             0x0158
165
166 #define RK3288_GRF_GPIO3A_P             0x0160
167 #define RK3288_GRF_GPIO3B_P             0x0164
168 #define RK3288_GRF_GPIO3C_P             0x0168
169 #define RK3288_GRF_GPIO3D_P             0x016c
170 #define RK3288_GRF_GPIO4A_P             0x0170
171 #define RK3288_GRF_GPIO4B_P             0x0174
172 #define RK3288_GRF_GPIO4C_P             0x0178
173 #define RK3288_GRF_GPIO4D_P             0x017c
174
175 #define RK3288_GRF_GPIO5B_P             0x0184
176 #define RK3288_GRF_GPIO5C_P             0x0188
177
178 #define RK3288_GRF_GPIO6A_P             0x0190
179 #define RK3288_GRF_GPIO6B_P             0x0194
180 #define RK3288_GRF_GPIO6C_P             0x0198
181
182 #define RK3288_GRF_GPIO7A_P             0x01a0
183 #define RK3288_GRF_GPIO7B_P             0x01a4
184 #define RK3288_GRF_GPIO7C_P             0x01a8
185
186 #define RK3288_GRF_GPIO8A_P             0x01b0
187 #define RK3288_GRF_GPIO8B_P             0x01b4
188
189 #define RK3288_GRF_GPIO1D_E             0x01cc
190 #define RK3288_GRF_GPIO2A_E             0x01d0
191 #define RK3288_GRF_GPIO2B_E             0x01d4
192 #define RK3288_GRF_GPIO2C_E             0x01d8
193
194 #define RK3288_GRF_GPIO3A_E             0x01e0
195 #define RK3288_GRF_GPIO3B_E             0x01e4
196 #define RK3288_GRF_GPIO3C_E             0x01e8
197 #define RK3288_GRF_GPIO3D_E             0x01ec
198 #define RK3288_GRF_GPIO4A_E             0x01f0
199 #define RK3288_GRF_GPIO4B_E             0x01f4
200 #define RK3288_GRF_GPIO4C_E             0x01f8
201 #define RK3288_GRF_GPIO4D_E             0x01fc
202
203 #define RK3288_GRF_GPIO5B_E             0x0204
204 #define RK3288_GRF_GPIO5C_E             0x0208
205
206 #define RK3288_GRF_GPIO6A_E             0x0210
207 #define RK3288_GRF_GPIO6B_E             0x0214
208 #define RK3288_GRF_GPIO6C_E             0x0218
209
210 #define RK3288_GRF_GPIO7A_E             0x0220
211 #define RK3288_GRF_GPIO7B_E             0x0224
212 #define RK3288_GRF_GPIO7C_E             0x0228
213
214 #define RK3288_GRF_GPIO8A_E             0x0230
215 #define RK3288_GRF_GPIO8B_E             0x0234
216
217 #define RK3288_GRF_GPIO_SMT             0x0240
218 #define RK3288_GRF_SOC_CON0             0x0244
219 #define RK3288_GRF_SOC_CON1             0x0248
220 #define RK3288_GRF_SOC_CON2             0x024c
221 #define RK3288_GRF_SOC_CON3             0x0250
222 #define RK3288_GRF_SOC_CON4             0x0254
223 #define RK3288_GRF_SOC_CON5             0x0258
224 #define RK3288_GRF_SOC_CON6             0x025c
225 #define RK3288_GRF_SOC_CON7             0x0260
226 #define RK3288_GRF_SOC_CON8             0x0264
227 #define RK3288_GRF_SOC_CON9             0x0268
228 #define RK3288_GRF_SOC_CON10            0x026c
229 #define RK3288_GRF_SOC_CON11            0x0270
230 #define RK3288_GRF_SOC_CON12            0x0274
231 #define RK3288_GRF_SOC_CON13            0x0278
232 #define RK3288_GRF_SOC_CON14            0x027c
233 #define RK3288_GRF_SOC_STATUS0          0x0280
234 #define RK3288_GRF_SOC_STATUS1          0x0284
235 #define RK3288_GRF_SOC_STATUS2          0x0288
236 #define RK3288_GRF_SOC_STATUS3          0x028c
237 #define RK3288_GRF_SOC_STATUS4          0x0290
238 #define RK3288_GRF_SOC_STATUS5          0x0294
239 #define RK3288_GRF_SOC_STATUS6          0x0298
240 #define RK3288_GRF_SOC_STATUS7          0x029c
241 #define RK3288_GRF_SOC_STATUS8          0x02a0
242 #define RK3288_GRF_SOC_STATUS9          0x02a4
243 #define RK3288_GRF_SOC_STATUS10         0x02a8
244 #define RK3288_GRF_SOC_STATUS11         0x02ac
245 #define RK3288_GRF_SOC_STATUS12         0x02b0
246 #define RK3288_GRF_SOC_STATUS13         0x02b4
247 #define RK3288_GRF_SOC_STATUS14         0x02b8
248 #define RK3288_GRF_SOC_STATUS15         0x02bc
249 #define RK3288_GRF_SOC_STATUS16         0x02c0
250 #define RK3288_GRF_SOC_STATUS17         0x02c4
251 #define RK3288_GRF_SOC_STATUS18         0x02c8
252 #define RK3288_GRF_SOC_STATUS19         0x02cc
253 #define RK3288_GRF_SOC_STATUS20         0x02d0
254 #define RK3288_GRF_SOC_STATUS21         0x02d4
255
256 #define RK3288_GRF_PERIDMAC_CON0        0x02e0
257 #define RK3288_GRF_PERIDMAC_CON1        0x02e4
258 #define RK3288_GRF_PERIDMAC_CON2        0x02e8
259 #define RK3288_GRF_PERIDMAC_CON3        0x02ec
260 #define RK3288_GRF_DDRC0_CON0           0x02f0
261 #define RK3288_GRF_DDRC1_CON0           0x02f4
262 #define RK3288_GRF_CPU_CON0             0x02f8
263 #define RK3288_GRF_CPU_CON1             0x02fc
264 #define RK3288_GRF_CPU_CON2             0x0300
265 #define RK3288_GRF_CPU_CON3             0x0304
266 #define RK3288_GRF_CPU_CON4             0x0308
267
268 #define RK3288_GRF_CPU_STATUS0          0x0318
269
270 #define RK3288_GRF_UOC0_CON0            0x0320
271 #define RK3288_GRF_UOC0_CON1            0x0324
272 #define RK3288_GRF_UOC0_CON2            0x0328
273 #define RK3288_GRF_UOC0_CON3            0x032c
274 #define RK3288_GRF_UOC0_CON4            0x0330
275 #define RK3288_GRF_UOC1_CON0            0x0334
276 #define RK3288_GRF_UOC1_CON1            0x0338
277 #define RK3288_GRF_UOC1_CON2            0x033c
278 #define RK3288_GRF_UOC1_CON3            0x0340
279 #define RK3288_GRF_UOC1_CON4            0x0344
280 #define RK3288_GRF_UOC2_CON0            0x0348
281 #define RK3288_GRF_UOC2_CON1            0x034c
282 #define RK3288_GRF_UOC2_CON2            0x0350
283 #define RK3288_GRF_UOC2_CON3            0x0354
284 #define RK3288_GRF_UOC3_CON0            0x0358
285 #define RK3288_GRF_UOC3_CON1            0x035c
286 #define RK3288_GRF_UOC4_CON0            0x0360
287 #define RK3288_GRF_UOC4_CON1            0x0364
288 #define RK3288_GRF_PVTM_CON0            0x0368
289 #define RK3288_GRF_PVTM_CON1            0x036c
290 #define RK3288_GRF_PVTM_CON2            0x0370
291 #define RK3288_GRF_PVTM_STATUS0         0x0374
292 #define RK3288_GRF_PVTM_STATUS1         0x0378
293 #define RK3288_GRF_PVTM_STATUS2         0x037c
294 #define RK3288_GRF_IO_VSEL              0x0380
295 #define RK3288_GRF_SARADC_TESTBIT       0x0384
296 #define RK3288_GRF_TSADC_TESTBIT_L      0x0388
297 #define RK3288_GRF_TSADC_TESTBIT_H      0x038c
298 #define RK3288_GRF_OS_REG0              0x0390
299 #define RK3288_GRF_OS_REG1              0x0394
300 #define RK3288_GRF_OS_REG2              0x0398
301 #define RK3288_GRF_OS_REG3              0x039c
302
303 #define RK3288_GRF_SOC_CON15            0x03a4
304 #define RK3288_GRF_SOC_CON16            0x03a8
305
306 #define RK3288_SGRF_SOC_CON0            0x0000
307 #define RK3288_SGRF_SOC_CON1            0x0004
308 #define RK3288_SGRF_SOC_CON2            0x0008
309 #define RK3288_SGRF_SOC_CON3            0x000c
310 #define RK3288_SGRF_SOC_CON4            0x0010
311 #define RK3288_SGRF_SOC_CON5            0x0014
312
313 #define RK3288_SGRF_BUSDMAC_CON0        0x0020
314 #define RK3288_SGRF_BUSDMAC_CON1        0x0024
315
316 #define RK3288_SGRF_CPU_CON0            0x0040
317 #define RK3288_SGRF_CPU_CON1            0x0044
318 #define RK3288_SGRF_CPU_CON2            0x0048
319
320 #define RK3288_SGRF_SOC_CON6            0x0050
321 #define RK3288_SGRF_SOC_CON7            0x0054
322 #define RK3288_SGRF_SOC_CON8            0x0058
323 #define RK3288_SGRF_SOC_CON9            0x005c
324 #define RK3288_SGRF_SOC_CON10           0x0060
325 #define RK3288_SGRF_SOC_CON11           0x0064
326 #define RK3288_SGRF_SOC_CON12           0x0068
327 #define RK3288_SGRF_SOC_CON13           0x006c
328 #define RK3288_SGRF_SOC_CON14           0x0070
329 #define RK3288_SGRF_SOC_CON15           0x0074
330 #define RK3288_SGRF_SOC_CON16           0x0078
331 #define RK3288_SGRF_SOC_CON17           0x007c
332 #define RK3288_SGRF_SOC_CON18           0x0080
333 #define RK3288_SGRF_SOC_CON19           0x0084
334 #define RK3288_SGRF_SOC_CON20           0x0088
335 #define RK3288_SGRF_SOC_CON21           0x008c
336
337 #define RK3288_SGRF_SOC_STATUS0         0x0100
338 #define RK3288_SGRF_SOC_STATUS1         0x0104
339
340 #define RK3288_SGRF_FAST_BOOT_ADDR      0x0120
341
342
343 #define RK3036_GRF_GPIO0A_IOMUX         0x000a8
344 #define RK3036_GRF_GPIO0B_IOMUX         0x000ac
345 #define RK3036_GRF_GPIO0C_IOMUX         0x000b0
346 #define RK3036_GRF_GPIO0D_IOMUX         0x000b4
347 #define RK3036_GRF_GPIO1A_IOMUX         0x000b8
348 #define RK3036_GRF_GPIO1B_IOMUX         0x000bc
349 #define RK3036_GRF_GPIO1C_IOMUX         0x000c0
350 #define RK3036_GRF_GPIO1D_IOMUX         0x000c4
351 #define RK3036_GRF_GPIO2A_IOMUX         0x000c8
352 #define RK3036_GRF_GPIO2B_IOMUX         0x000cc
353 #define RK3036_GRF_GPIO2C_IOMUX         0x000d0
354 #define RK3036_GRF_GPIO2D_IOMUX         0x000d4
355 #define RK3036_GRF_GPIO_DS              0x00100
356 #define RK3036_GRF_GPIO0L_PULL          0x00118
357 #define RK3036_GRF_GPIO0H_PULL          0x0011c
358 #define RK3036_GRF_GPIO1L_PULL          0x00120
359 #define RK3036_GRF_GPIO1H_PULL          0x00124
360
361 #define RK3036_GRF_GPIO2L_PULL 0x00128
362 #define RK3036_GRF_GPIO2H_PULL 0x0012c
363 #define RK3036_GRF_SOC_CON0 0x00140
364 #define RK3036_GRF_SOC_CON1 0x00144
365 #define RK3036_GRF_SOC_CON2 0x00148
366 #define RK3036_GRF_SOC_STATUS0 0x0014c
367 #define RK3036_GRF_SOC_CON3 0x00154
368 #define RK3036_GRF_DMAC_CON0 0x0015c
369 #define RK3036_GRF_DMAC_CON1 0x00160
370 #define RK3036_GRF_DMAC_CON2 0x00164
371 #define RK3036_GRF_UOC0_CON5 0x0017c
372 #define RK3036_GRF_UOC1_CON4 0x00190
373 #define RK3036_GRF_UOC1_CON5 0x00194
374 #define RK3036_GRF_DDRC_STAT 0x0019c
375 #define RK3036_GRF_UOC_CON6 0x001a0
376 #define RK3036_GRF_SOC_STATUS1 0x001a4
377 #define RK3036_GRF_CPU_CON0 0x001a8
378 #define RK3036_GRF_CPU_CON1 0x001ac
379 #define RK3036_GRF_CPU_CON2 0x001b0
380 #define RK3036_GRF_CPU_CON3 0x001b4
381 #define RK3036_GRF_CPU_STATUS0 0x001c0
382 #define RK3036_GRF_CPU_STATUS1 0x001c4
383 #define RK3036_GRF_OS_REG0 0x001c8
384 #define RK3036_GRF_OS_REG1 0x001cc
385 #define RK3036_GRF_OS_REG2 0x001d0
386 #define RK3036_GRF_OS_REG3 0x001d4
387 #define RK3036_GRF_OS_REG4 0x001d8
388 #define RK3036_GRF_OS_REG5 0x001dc
389 #define RK3036_GRF_OS_REG6 0x001e0
390 #define RK3036_GRF_OS_REG7 0x001e4
391 #define RK3036_GRF_DLL_CON0 0x00200
392 #define RK3036_GRF_DLL_CON1 0x00204
393 #define RK3036_GRF_DLL_CON2 0x00208
394 #define RK3036_GRF_DLL_CON3 0x0020c
395 #define RK3036_GRF_DLL_STATUS0 0x00210
396 #define RK3036_GRF_DLL_STATUS1 0x00214
397
398 #define RK3036_GRF_DLL_STATUS2 0x00218
399 #define RK3036_GRF_DLL_STATUS3 0x0021c
400 #define RK3036_GRF_DFI_WRNUM 0x00220
401 #define RK3036_GRF_DFI_RDNUM 0x00224
402 #define RK3036_GRF_DFI_ACTNUM 0x00228
403 #define RK3036_GRF_DFI_TIMERVAL 0x0022c
404 #define RK3036_GRF_NIF_FIFO0 0x00230
405 #define RK3036_GRF_NIF_FIFO1 0x00234
406 #define RK3036_GRF_NIF_FIFO2 0x00238
407 #define RK3036_GRF_NIF_FIFO3 0x0023c
408 #define RK3036_GRF_USBPHY0_CON0 0x00280
409 #define RK3036_GRF_USBPHY0_CON1 0x00284
410 #define RK3036_GRF_USBPHY0_CON2 0x00288
411 #define RK3036_GRF_USBPHY0_CON3 0x0028c
412 #define RK3036_GRF_USBPHY0_CON4 0x00290
413 #define RK3036_GRF_USBPHY0_CON5 0x00294
414 #define RK3036_GRF_USBPHY0_CON6 0x00298
415 #define RK3036_GRF_USBPHY0_CON7 0x0029c
416 #define RK3036_GRF_USBPHY1_CON0 0x002a0
417 #define RK3036_GRF_USBPHY1_CON1 0x002a4
418 #define RK3036_GRF_USBPHY1_CON2 0x002a8
419 #define RK3036_GRF_USBPHY1_CON3 0x002ac
420 #define RK3036_GRF_USBPHY1_CON4 0x002b0
421 #define RK3036_GRF_USBPHY1_CON5 0x002b4
422 #define RK3036_GRF_USBPHY1_CON6 0x002b8
423
424 #define RK3036_GRF_USBPHY1_CON7 0x002bc
425 #define RK3036_GRF_CHIP_TAG 0x00300
426 #define RK3036_GRF_SDMMC_DET_CNT 0x00304
427
428 #define RK312X_GRF_GPIO0A_IOMUX         0x000a8
429 #define RK312X_GRF_GPIO0B_IOMUX         0x000ac
430 #define RK312X_GRF_GPIO0C_IOMUX         0x000b0
431 #define RK312X_GRF_GPIO0D_IOMUX         0x000b4
432 #define RK312X_GRF_GPIO1A_IOMUX         0x000b8
433 #define RK312X_GRF_GPIO1B_IOMUX         0x000bc
434 #define RK312X_GRF_GPIO1C_IOMUX         0x000c0
435 #define RK312X_GRF_GPIO1D_IOMUX         0x000c4
436 #define RK312X_GRF_GPIO2A_IOMUX         0x000c8
437 #define RK312X_GRF_GPIO2B_IOMUX         0x000cc
438 #define RK312X_GRF_GPIO2C_IOMUX         0x000d0
439 #define RK312X_GRF_GPIO2D_IOMUX         0x000d4
440 #define RK312X_GRF_GPIO3A_IOMUX         0x000d8
441 #define RK312X_GRF_GPIO3B_IOMUX         0x000dc
442 #define RK312X_GRF_GPIO3C_IOMUX         0x000e0
443 #define RK312X_GRF_GPIO3D_IOMUX         0x000e4
444 #define RK312X_GRF_CIF_IOMUX            0x000ec
445 #define RK312X_GRF_CIF_IOMUX1           0x000f0
446 #define RK312X_GRF_GPIO_DS              0x00100
447 #define RK312X_GRF_GPIO0L_PULL          0x00118
448 #define RK312X_GRF_GPIO0H_PULL          0x0011c
449 #define RK312X_GRF_GPIO1L_PULL          0x00120
450 #define RK312X_GRF_GPIO1H_PULL          0x00124
451 #define RK312X_GRF_GPIO2L_PULL          0x00128
452 #define RK312X_GRF_GPIO2H_PULL          0x0012c
453 #define RK312X_GRF_GPIO3L_PULL          0x00130
454 #define RK312X_GRF_GPIO3H_PULL          0x00134
455 #define RK312X_GRF_ACODEC_CON           0x0013c
456
457 #define RK312X_GRF_SOC_CON0 0x00140
458 #define RK312X_GRF_SOC_CON1 0x00144
459 #define RK312X_GRF_SOC_CON2 0x00148
460 #define RK312X_GRF_SOC_STATUS0 0x0014c
461 #define RK312X_GRF_LVDS_CON0 0x00150
462 #define RK312X_GRF_SOC_CON3 0x00154
463 #define RK312X_GRF_DMAC_CON0 0x0015c
464 #define RK312X_GRF_DMAC_CON1 0x00160
465 #define RK312X_GRF_DMAC_CON2 0x00164
466 #define RK312X_GRF_MAC_CON0 0x00168
467 #define RK312X_GRF_MAC_CON1 0x0016c
468 #define RK312X_GRF_TVE_CON 0x00170
469 #define RK312X_GRF_UOC0_CON0 0x0017c
470 #define RK312X_GRF_UOC1_CON1 0x00184
471 #define RK312X_GRF_UOC1_CON2 0x00188
472 #define RK312X_GRF_UOC1_CON3 0x0018c
473 #define RK312X_GRF_UOC1_CON4 0x00190
474 #define RK312X_GRF_UOC1_CON5 0x00194
475 #define RK312X_GRF_DDRC_STAT 0x0019c
476 #define RK312X_GRF_SOC_STATUS1 0x001a4
477 #define RK312X_GRF_CPU_CON0 0x001a8
478 #define RK312X_GRF_CPU_CON1 0x001ac
479 #define RK312X_GRF_CPU_CON2 0x001b0
480 #define RK312X_GRF_CPU_CON3 0x001b4
481 #define RK312X_GRF_CPU_STATUS0 0x001c0
482 #define RK312X_GRF_CPU_STATUS1 0x001c4
483 #define RK312X_GRF_OS_REG0 0x001c8
484 #define RK312X_GRF_OS_REG1 0x001cc
485 #define RK312X_GRF_OS_REG2 0x001d0
486 #define RK312X_GRF_OS_REG3 0x001d4
487 #define RK312X_GRF_OS_REG4 0x001d8
488 #define RK312X_GRF_OS_REG5 0x001dc
489 #define RK312X_GRF_OS_REG6 0x001e0
490 #define RK312X_GRF_OS_REG7 0x001e4
491 #define RK312X_GRF_PVTM_CON0 0x00200
492 #define RK312X_GRF_PVTM_CON1 0x00204
493 #define RK312X_GRF_PVTM_CON2 0x00208
494 #define RK312X_GRF_PVTM_CON3 0x0020c
495 #define RK312X_GRF_PVTM_STATUS0 0x00210
496 #define RK312X_GRF_PVTM_STATUS1 0x00214
497 #define RK312X_GRF_PVTM_STATUS2 0x00218
498 #define RK312X_GRF_PVTM_STATUS3 0x0021c
499 #define RK312X_GRF_DFI_WRNUM 0x00220
500 #define RK312X_GRF_DFI_RDNUM 0x00224
501 #define RK312X_GRF_DFI_ACTNUM 0x00228
502 #define RK312X_GRF_DFI_TIMERVAL 0x0022c
503 #define RK312X_GRF_NIF_FIFO0 0x00230
504 #define RK312X_GRF_NIF_FIFO1 0x00234
505 #define RK312X_GRF_NIF_FIFO2 0x00238
506 #define RK312X_GRF_NIF_FIFO3 0x0023c
507 #define RK312X_GRF_USBPHY0_CON0 0x00280
508 #define RK312X_GRF_USBPHY0_CON1 0x00284
509 #define RK312X_GRF_USBPHY0_CON2 0x00288
510 #define RK312X_GRF_USBPHY0_CON3 0x0028c
511 #define RK312X_GRF_USBPHY0_CON4 0x00290
512 #define RK312X_GRF_USBPHY0_CON5 0x00294
513 #define RK312X_GRF_USBPHY0_CON6 0x00298
514 #define RK312X_GRF_USBPHY0_CON7 0x0029c
515 #define RK312X_GRF_USBPHY1_CON0 0x002a0
516 #define RK312X_GRF_USBPHY1_CON1 0x002a4
517 #define RK312X_GRF_USBPHY1_CON2 0x002a8
518 #define RK312X_GRF_USBPHY1_CON3 0x002ac
519 #define RK312X_GRF_USBPHY1_CON4 0x002b0
520 #define RK312X_GRF_USBPHY1_CON5 0x002b4
521 #define RK312X_GRF_USBPHY1_CON6 0x002b8
522 #define RK312X_GRF_USBPHY1_CON7 0x002bc
523 #define RK312X_GRF_UOC_STATUS0 0x002c0
524 #define RK312X_GRF_CHIP_TAG 0x00300
525 #define RK312X_GRF_SDMMC_DET_CNT 0x00304
526 #define RK312X_GRF_EFUSE_PRG_EN 0x0037c
527
528 #define RK3228_GRF_GPIO0A_IOMUX         0x0000
529 #define RK3228_GRF_GPIO0B_IOMUX         0x0004
530 #define RK3228_GRF_GPIO0C_IOMUX         0x0008
531 #define RK3228_GRF_GPIO0D_IOMUX         0x000c
532 #define RK3228_GRF_GPIO1A_IOMUX         0x0010
533 #define RK3228_GRF_GPIO1B_IOMUX         0x0014
534 #define RK3228_GRF_GPIO1C_IOMUX         0x0018
535 #define RK3228_GRF_GPIO1D_IOMUX         0x001c
536 #define RK3228_GRF_GPIO2A_IOMUX         0x0020
537 #define RK3228_GRF_GPIO2B_IOMUX         0x0024
538 #define RK3228_GRF_GPIO2C_IOMUX         0x0028
539 #define RK3228_GRF_GPIO2D_IOMUX         0x002c
540 #define RK3228_GRF_GPIO3A_IOMUX         0x0030
541 #define RK3228_GRF_GPIO3B_IOMUX         0x0034
542 #define RK3228_GRF_GPIO3C_IOMUX         0x0038
543 #define RK3228_GRF_GPIO3D_IOMUX         0x003c
544 #define RK3228_GRF_COM_IOMUX            0x0050
545 #define RK3228_GRF_GPIO0A_P             0x0100
546 #define RK3228_GRF_GPIO0B_P             0x0104
547 #define RK3228_GRF_GPIO0C_P             0x0108
548 #define RK3228_GRF_GPIO0D_P             0x010c
549 #define RK3228_GRF_GPIO1A_P             0x0110
550 #define RK3228_GRF_GPIO1B_P             0x0114
551 #define RK3228_GRF_GPIO1C_P             0x0118
552 #define RK3228_GRF_GPIO1D_P             0x011c
553 #define RK3228_GRF_GPIO2A_P             0x0120
554 #define RK3228_GRF_GPIO2B_P             0x0124
555 #define RK3228_GRF_GPIO2C_P             0x0128
556 #define RK3228_GRF_GPIO2D_P             0x012c
557 #define RK3228_GRF_GPIO3A_P             0x0130
558 #define RK3228_GRF_GPIO3B_P             0x0134
559 #define RK3228_GRF_GPIO3C_P             0x0138
560 #define RK3228_GRF_GPIO3D_P             0x013c
561 #define RK3228_GRF_GPIO0A_E             0x0200
562 #define RK3228_GRF_GPIO0B_E             0x0204
563 #define RK3228_GRF_GPIO0C_E             0x0208
564 #define RK3228_GRF_GPIO0D_E             0x020c
565 #define RK3228_GRF_GPIO1A_E             0x0210
566 #define RK3228_GRF_GPIO1B_E             0x0214
567 #define RK3228_GRF_GPIO1C_E             0x0218
568 #define RK3228_GRF_GPIO1D_E             0x021c
569 #define RK3228_GRF_GPIO2A_E             0x0220
570 #define RK3228_GRF_GPIO2B_E             0x0224
571 #define RK3228_GRF_GPIO2C_E             0x0228
572 #define RK3228_GRF_GPIO2D_E             0x022c
573 #define RK3228_GRF_GPIO3A_E             0x0230
574 #define RK3228_GRF_GPIO3B_E             0x0234
575 #define RK3228_GRF_GPIO3C_E             0x0238
576 #define RK3228_GRF_GPIO3D_E             0x023c
577 #define RK3228_GRF_GPIO0L_SR            0x0300
578 #define RK3228_GRF_GPIO0H_SR            0x0304
579 #define RK3228_GRF_GPIO1L_SR            0x0308
580 #define RK3228_GRF_GPIO1H_SR            0x030c
581 #define RK3228_GRF_GPIO2L_SR            0x0310
582 #define RK3228_GRF_GPIO2H_SR            0x0314
583 #define RK3228_GRF_GPIO3L_SR            0x0318
584 #define RK3228_GRF_GPIO3H_SR            0x031c
585 #define RK3228_GRF_GPIO0L_SMT           0x0380
586 #define RK3228_GRF_GPIO0H_SMT           0x0384
587 #define RK3228_GRF_GPIO1L_SMT           0x0388
588 #define RK3228_GRF_GPIO1H_SMT           0x038c
589 #define RK3228_GRF_GPIO2L_SMT           0x0390
590 #define RK3228_GRF_GPIO2H_SMT           0x0394
591 #define RK3228_GRF_GPIO3L_SMT           0x0398
592 #define RK3228_GRF_GPIO3H_SMT           0x039c
593 #define RK3228_GRF_SOC_CON0             0x0400
594 #define RK3228_GRF_SOC_CON1             0x0404
595 #define RK3228_GRF_SOC_CON2             0x0408
596 #define RK3228_GRF_SOC_CON3             0x040c
597 #define RK3228_GRF_SOC_CON4             0x0410
598 #define RK3228_GRF_SOC_CON5             0x0414
599 #define RK3228_GRF_SOC_CON6             0x0418
600 #define RK3228_GRF_SOC_STATUS0          0x0480
601 #define RK3228_GRF_SOC_STATUS1          0x0484
602 #define RK3228_GRF_SOC_STATUS2          0x0488
603 #define RK3228_GRF_CHIP_ID              0x048c
604 #define RK3228_GRF_CPU_CON0             0x0500
605 #define RK3228_GRF_CPU_CON1             0x0504
606 #define RK3228_GRF_CPU_CON2             0x0508
607 #define RK3228_GRF_CPU_CON3             0x050c
608 #define RK3228_GRF_CPU_STATUS0          0x0520
609 #define RK3228_GRF_CPU_STATUS1          0x0524
610 #define RK3228_GRF_OS_REG0              0x05c8
611 #define RK3228_GRF_OS_REG1              0x05cc
612 #define RK3228_GRF_OS_REG2              0x05d0
613 #define RK3228_GRF_OS_REG3              0x05d4
614 #define RK3228_GRF_OS_REG4              0x05d8
615 #define RK3228_GRF_OS_REG5              0x05dc
616 #define RK3228_GRF_OS_REG6              0x05e0
617 #define RK3228_GRF_OS_REG7              0x05e4
618 #define RK3228_GRF_DDRC_STAT            0x0604
619 #define RK3228_GRF_SIG_DETECT_CON       0x0680
620 #define RK3228_GRF_SIG_DETECT_CON1      0x0684
621 #define RK3228_GRF_SIG_DETECT_STATUS    0x0690
622 #define RK3228_GRF_SIG_DETECT_STATUS1   0x0694
623 #define RK3228_GRF_SIG_DETECT_CLR       0x06a0
624 #define RK3228_GRF_SIG_DETECT_CLR1      0x06a4
625 #define RK3228_GRF_EMMC_DET             0x06b0
626 #define RK3228_GRF_HOST0_CON0           0x0700
627 #define RK3228_GRF_HOST0_CON1           0x0704
628 #define RK3228_GRF_HOST0_CON2           0x0708
629 #define RK3228_GRF_HOST1_CON0           0x0710
630 #define RK3228_GRF_HOST1_CON1           0x0714
631 #define RK3228_GRF_HOST1_CON2           0x0718
632 #define RK3228_GRF_HOST2_CON0           0x0720
633 #define RK3228_GRF_HOST2_CON1           0x0724
634 #define RK3228_GRF_HOST2_CON2           0x0728
635 #define RK3228_GRF_USBPHY0_CON0         0x0760
636 #define RK3228_GRF_USBPHY0_CON1         0x0764
637 #define RK3228_GRF_USBPHY0_CON2         0x0768
638 #define RK3228_GRF_USBPHY0_CON3         0x076c
639 #define RK3228_GRF_USBPHY0_CON4         0x0770
640 #define RK3228_GRF_USBPHY0_CON5         0x0774
641 #define RK3228_GRF_USBPHY0_CON6         0x0778
642 #define RK3228_GRF_USBPHY0_CON7         0x077c
643 #define RK3228_GRF_USBPHY0_CON8         0x0780
644 #define RK3228_GRF_USBPHY0_CON9         0x0784
645 #define RK3228_GRF_USBPHY0_CON10        0x0788
646 #define RK3228_GRF_USBPHY0_CON11        0x078c
647 #define RK3228_GRF_USBPHY0_CON12        0x0790
648 #define RK3228_GRF_USBPHY0_CON13        0x0794
649 #define RK3228_GRF_USBPHY0_CON14        0x0798
650 #define RK3228_GRF_USBPHY0_CON15        0x079c
651 #define RK3228_GRF_USBPHY0_CON16        0x07a0
652 #define RK3228_GRF_USBPHY0_CON17        0x07a4
653 #define RK3228_GRF_USBPHY0_CON18        0x07a8
654 #define RK3228_GRF_USBPHY0_CON19        0x07ac
655 #define RK3228_GRF_USBPHY0_CON20        0x07b0
656 #define RK3228_GRF_USBPHY0_CON21        0x07b4
657 #define RK3228_GRF_USBPHY0_CON22        0x07b8
658 #define RK3228_GRF_USBPHY0_CON23        0x07bc
659 #define RK3228_GRF_USBPHY0_CON24        0x07c0
660 #define RK3228_GRF_USBPHY0_CON25        0x07c4
661 #define RK3228_GRF_USBPHY0_CON26        0x07c8
662 #define RK3228_GRF_USBPHY1_CON0         0x0800
663 #define RK3228_GRF_USBPHY1_CON1         0x0804
664 #define RK3228_GRF_USBPHY1_CON2         0x0808
665 #define RK3228_GRF_USBPHY1_CON3         0x080c
666 #define RK3228_GRF_USBPHY1_CON4         0x0810
667 #define RK3228_GRF_USBPHY1_CON5         0x0814
668 #define RK3228_GRF_USBPHY1_CON6         0x0818
669 #define RK3228_GRF_USBPHY1_CON7         0x081c
670 #define RK3228_GRF_USBPHY1_CON8         0x0820
671 #define RK3228_GRF_USBPHY1_CON9         0x0824
672 #define RK3228_GRF_USBPHY1_CON10        0x0828
673 #define RK3228_GRF_USBPHY1_CON11        0x082c
674 #define RK3228_GRF_USBPHY1_CON12        0x0830
675 #define RK3228_GRF_USBPHY1_CON13        0x0834
676 #define RK3228_GRF_USBPHY1_CON14        0x0838
677 #define RK3228_GRF_USBPHY1_CON15        0x083c
678 #define RK3228_GRF_USBPHY1_CON16        0x0840
679 #define RK3228_GRF_USBPHY1_CON17        0x0844
680 #define RK3228_GRF_USBPHY1_CON18        0x0848
681 #define RK3228_GRF_USBPHY1_CON19        0x084c
682 #define RK3228_GRF_USBPHY1_CON20        0x0850
683 #define RK3228_GRF_USBPHY1_CON21        0x0854
684 #define RK3228_GRF_USBPHY1_CON22        0x0858
685 #define RK3228_GRF_USBPHY1_CON23        0x085c
686 #define RK3228_GRF_USBPHY1_CON24        0x0860
687 #define RK3228_GRF_USBPHY1_CON25        0x0864
688 #define RK3228_GRF_USBPHY1_CON26        0x0868
689 #define RK3228_GRF_OTG_CON0             0x0880
690 #define RK3228_GRF_UOC_CON0             0x0884
691 #define RK3228_GRF_MAC_CON0             0x0900
692 #define RK3228_GRF_MAC_CON1             0x0904
693 #define RK3228_GRF_MACPHY_CON0          0x0b00
694 #define RK3228_GRF_MACPHY_CON1          0x0b04
695 #define RK3228_GRF_MACPHY_CON2          0x0b08
696 #define RK3228_GRF_MACPHY_CON3          0x0b0c
697 #define RK3228_GRF_MACPHY_STATUS        0x0b10
698
699 #endif