include/linux/rockchip/cru.h

   1 #ifndef __MACH_ROCKCHIP_CRU_H
   2 #define __MACH_ROCKCHIP_CRU_H
   3
   4 #include <dt-bindings/clock/rockchip,rk3188.h>
   5
   6
   7 /*******************CRU BITS*******************************/
   8
   9 #define CRU_W_MSK(bits_shift, msk)      ((msk) << ((bits_shift) + 16))
  10
  11 #define CRU_SET_BITS(val, bits_shift, msk)      (((val)&(msk)) << (bits_shift))
  12
  13 #define CRU_W_MSK_SETBITS(val, bits_shift,msk) \
  14         (CRU_W_MSK(bits_shift, msk) | CRU_SET_BITS(val, bits_shift, msk))
  15
  16 /*******************RK3188********************************/
  17 /*******************CRU OFFSET*********************/
  18 #define RK3188_CRU_MODE_CON             0x40
  19 #define RK3188_CRU_CLKSEL_CON           0x44
  20 #define RK3188_CRU_CLKGATE_CON          0xd0
  21 #define RK3188_CRU_GLB_SRST_FST         0x100
  22 #define RK3188_CRU_GLB_SRST_SND         0x104
  23 #define RK3188_CRU_SOFTRST_CON          0x110
  24
  25 #define RK3188_PLL_CONS(id, i)          ((id) * 0x10 + ((i) * 4))
  26
  27 #define RK3188_CRU_CLKSELS_CON_CNT      (35)
  28 #define RK3188_CRU_CLKSELS_CON(i)       (RK3188_CRU_CLKSEL_CON + ((i) * 4))
  29
  30 #define RK3188_CRU_CLKGATES_CON_CNT     (10)
  31 #define RK3188_CRU_CLKGATES_CON(i)      (RK3188_CRU_CLKGATE_CON + ((i) * 4))
  32
  33 #define RK3188_CRU_SOFTRSTS_CON_CNT     (9)
  34 #define RK3188_CRU_SOFTRSTS_CON(i)      (RK3188_CRU_SOFTRST_CON + ((i) * 4))
  35
  36 #define RK3188_CRU_MISC_CON             (0x134)
  37 #define RK3188_CRU_GLB_CNT_TH           (0x140)
  38
  39 /******************PLL MODE BITS*******************/
  40 #define RK3188_PLL_MODE_MSK(id)         (0x3 << ((id) * 4))
  41 #define RK3188_PLL_MODE_SLOW(id)        ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
  42 #define RK3188_PLL_MODE_NORM(id)        ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
  43 #define RK3188_PLL_MODE_DEEP(id)        ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
  44
  45 /******************CRU GATINGS**********************************/
  46 #define RK3188_CRU_GATEID_CONS(ID) (RK3188_CRU_CLKGATE_CON+(ID/16)*4)
  47
  48 /*************************RK3288********************************/
  49
  50 /*******************CRU OFFSET*********************/
  51 #define RK3288_CRU_MODE_CON             0x50
  52 #define RK3288_CRU_CLKSEL_CON           0x60
  53 #define RK3288_CRU_CLKGATE_CON          0x160
  54
  55 #define RK3288_PLL_CONS(id, i)          ((id) * 0x10 + ((i) * 4))
  56 #define RK3288_CRU_CLKSELS_CON(i)       (RK3288_CRU_CLKSEL_CON + ((i) * 4))
  57 #define RK3288_CRU_CLKGATES_CON(i)      (RK3288_CRU_CLKGATE_CON + ((i) * 4))
  58
  59 /******************PLL MODE BITS*******************/
  60 // apll dpll,cpll,gpll,npll 0~4
  61 #define RK3288_PLLS_MODE_OFFSET(id) ((id)<=3 ? (id*4) : 14)
  62 #define RK3288_PLL_MODE_MSK(id)         (0x3 << RK3288_PLLS_MODE_OFFSET(id))
  63 #define RK3288_PLL_MODE_SLOW(id)        ((0x0<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
  64 #define RK3288_PLL_MODE_NORM(id)        ((0x1<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
  65 #define RK3288_PLL_MODE_DEEP(id)        ((0x2<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
  66
  67 /*******************CRU GATING*********************/
  68 #define RK3288_CRU_CLKGATES_CON_CNT (19)
  69 #define RK3288_CRU_CONS_GATEID(i)       (16 * (i))
  70 #define RK3288_CRU_GATEID_CONS(ID)      (RK3288_CRU_CLKGATE_CON+(ID/16)*4)
  71
  72 enum rk3288_cru_clk_gate {
  73         /* SCU CLK GATE 0 CON */
  74         //gate0
  75         RK3288_CLKGATE_UART0_SRC    =   (RK3288_CRU_CONS_GATEID(1)+8),
  76
  77         RK3288_CLKGATE_UART4_SRC    =   (RK3288_CRU_CONS_GATEID(2)+12),
  78
  79         RK3288_CLKGATE_PCLK_UART0= (RK3288_CRU_CONS_GATEID(6)+8),
  80         RK3288_CLKGATE_PCLK_UART1,
  81         RK3288_CLKGATE6_DUMP1,
  82         RK3288_CLKGATE_PCLK_UART3,
  83         RK3288_CLKGATE_PCLK_I2C2,
  84         RK3288_CLKGATE_PCLK_I2C3,
  85         RK3288_CLKGATE_PCLK_I2C4,
  86
  87         RK3288_CLKGATE_PCLK_I2C0    =   (RK3288_CRU_CONS_GATEID(10)+2),
  88         RK3288_CLKGATE_PCLK_I2C1,
  89
  90         RK3288_CLKGATE_PCLK_UART2    =   (RK3288_CRU_CONS_GATEID(11)+9),
  91
  92
  93         RK3288_CLKGATE_PCLK_GPIO1   =   (RK3288_CRU_CONS_GATEID(14)+1),
  94
  95         RK3288_CLKGATE_PCLK_GPIO0   =   (RK3288_CRU_CONS_GATEID(17)+4),
  96         //gate6
  97 };
  98
  99 #define RK3288_CRU_GLB_SRST_FST_VALUE   0x1b0
 100 #define RK3288_CRU_GLB_SRST_SND_VALUE   0x1b4
 101 #define RK3288_CRU_MISC_CON             0x1e8
 102 #define RK3288_CRU_GLB_CNT_TH           0x1ec
 103 #define RK3288_CRU_GLB_RST_CON          0x1f0
 104 #define RK3288_CRU_GLB_RST_ST           0x1f8
 105 #define RK3288_CRU_SDMMC_CON0           0x200
 106 #define RK3288_CRU_SDMMC_CON1           0x204
 107 #define RK3288_CRU_SDIO0_CON0           0x208
 108 #define RK3288_CRU_SDIO0_CON1           0x20c
 109 #define RK3288_CRU_SDIO1_CON0           0x210
 110 #define RK3288_CRU_SDIO1_CON1           0x214
 111 #define RK3288_CRU_EMMC_CON0            0x218
 112 #define RK3288_CRU_EMMC_CON1            0x21c
 113
 114 #endif