include/linux/rockchip/cru.h

   1 #ifndef __MACH_ROCKCHIP_CRU_H
   2 #define __MACH_ROCKCHIP_CRU_H
   3
   4 #include <dt-bindings/clock/rockchip,rk3188.h>
   5
   6
   7 /*******************CRU BITS*******************************/
   8 #define CRU_W_MSK(bits_shift, msk)      ((msk) << ((bits_shift) + 16))
   9 #define CRU_SET_BITS(val, bits_shift, msk)      (((val)&(msk)) << (bits_shift))
  10 #define CRU_W_MSK_SETBITS(val, bits_shift,msk) \
  11         (CRU_W_MSK(bits_shift, msk) | CRU_SET_BITS(val, bits_shift, msk))
  12
  13 /*******************RK3188********************************/
  14 /*******************CRU OFFSET*********************/
  15 #define RK3188_CRU_MODE_CON             0x40
  16 #define RK3188_CRU_CLKSEL_CON           0x44
  17 #define RK3188_CRU_CLKGATE_CON          0xd0
  18 #define RK3188_CRU_GLB_SRST_FST         0x100
  19 #define RK3188_CRU_GLB_SRST_SND         0x104
  20 #define RK3188_CRU_SOFTRST_CON          0x110
  21
  22 #define RK3188_PLL_CONS(id, i)          ((id) * 0x10 + ((i) * 4))
  23
  24 #define RK3188_CRU_CLKSELS_CON_CNT      (35)
  25 #define RK3188_CRU_CLKSELS_CON(i)       (RK3188_CRU_CLKSEL_CON + ((i) * 4))
  26
  27 #define RK3188_CRU_CLKGATES_CON_CNT     (10)
  28 #define RK3188_CRU_CLKGATES_CON(i)      (RK3188_CRU_CLKGATE_CON + ((i) * 4))
  29
  30 #define RK3188_CRU_SOFTRSTS_CON_CNT     (9)
  31 #define RK3188_CRU_SOFTRSTS_CON(i)      (RK3188_CRU_SOFTRST_CON + ((i) * 4))
  32
  33 #define RK3188_CRU_MISC_CON             (0x134)
  34 #define RK3188_CRU_GLB_CNT_TH           (0x140)
  35
  36 /******************PLL MODE BITS*******************/
  37 #define RK3188_PLL_MODE_MSK(id)         (0x3 << ((id) * 4))
  38 #define RK3188_PLL_MODE_SLOW(id)        ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
  39 #define RK3188_PLL_MODE_NORM(id)        ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
  40 #define RK3188_PLL_MODE_DEEP(id)        ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
  41
  42 #define RK3288_CRU_GLB_SRST_FST_VALUE   0x1b0
  43 #define RK3288_CRU_GLB_SRST_SND_VALUE   0x1b4
  44 #define RK3288_CRU_MISC_CON             0x1e8
  45 #define RK3288_CRU_GLB_CNT_TH           0x1ec
  46 #define RK3288_CRU_GLB_RST_CON          0x1f0
  47 #define RK3288_CRU_GLB_RST_ST           0x1f8
  48 #define RK3288_CRU_SDMMC_CON0           0x200
  49 #define RK3288_CRU_SDMMC_CON1           0x204
  50 #define RK3288_CRU_SDIO0_CON0           0x208
  51 #define RK3288_CRU_SDIO0_CON1           0x20c
  52 #define RK3288_CRU_SDIO1_CON0           0x210
  53 #define RK3288_CRU_SDIO1_CON1           0x214
  54 #define RK3288_CRU_EMMC_CON0            0x218
  55 #define RK3288_CRU_EMMC_CON1            0x21c
  56
  57 #endif