include/linux/platform_data/rk_isp10_platform.h

   1 /*
   2  *************************************************************************
   3  * Rockchip driver for CIF ISP 1.0
   4  * (Based on Intel driver for sofiaxxx)
   5  *
   6  * Copyright (C) 2015 Intel Mobile Communications GmbH
   7  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd.
   8  *
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *************************************************************************
  15  */
  16 #ifndef _CIF_ISP10_PLATFORM_H
  17 #define _CIF_ISP10_PLATFORM_H
  18 #include <linux/videodev2.h>
  19
  20 #define CIF_ISP10_SOC_RK3288    "rk3288"
  21 #define CIF_ISP10_SOC_RK3368    "rk3368"
  22 #define CIF_ISP10_SOC_RK3399    "rk3399"
  23
  24 #define DRIVER_NAME "rkisp10"
  25 #define ISP_VDEV_NAME DRIVER_NAME  "_ispdev"
  26 #define SP_VDEV_NAME DRIVER_NAME   "_selfpath"
  27 #define MP_VDEV_NAME DRIVER_NAME   "_mainpath"
  28 #define DMA_VDEV_NAME DRIVER_NAME  "_dmapath"
  29
  30 enum pltfrm_cam_signal_polarity {
  31         PLTFRM_CAM_SIGNAL_HIGH_LEVEL = 0,
  32         PLTFRM_CAM_SIGNAL_LOW_LEVEL = 1,
  33 };
  34
  35 enum pltfrm_cam_sample_type {
  36         PLTFRM_CAM_SDR_NEG_EDG = 0x10000001,
  37         PLTFRM_CAM_SDR_POS_EDG = 0x10000002,
  38         PLTFRM_CAM_DDR         = 0x20000000
  39 };
  40
  41 enum pltfrm_cam_itf_type {
  42         PLTFRM_CAM_ITF_MIPI     = 0x10000000,
  43         PLTFRM_CAM_ITF_BT601_8  = 0x20000071,
  44         PLTFRM_CAM_ITF_BT656_8  = 0x20000072,
  45         PLTFRM_CAM_ITF_BT601_10 = 0x20000091,
  46         PLTFRM_CAM_ITF_BT656_10 = 0x20000092,
  47         PLTFRM_CAM_ITF_BT601_12 = 0x200000B1,
  48         PLTFRM_CAM_ITF_BT656_12 = 0x200000B2,
  49         PLTFRM_CAM_ITF_BT601_16 = 0x200000F1,
  50         PLTFRM_CAM_ITF_BT656_16 = 0x200000F2
  51 };
  52
  53 #define PLTFRM_CAM_ITF_MAIN_MASK   0xf0000000
  54 #define PLTFRM_CAM_ITF_SUB_MASK    0x0000000f
  55 #define PLTFRM_CAM_ITF_DVP_BW_MASK 0x000000f0
  56
  57 #define PLTFRM_CAM_ITF_IS_MIPI(a)    \
  58                 (((a) & PLTFRM_CAM_ITF_MAIN_MASK) == 0x10000000)
  59 #define PLTFRM_CAM_ITF_IS_DVP(a)    \
  60                 (((a) & PLTFRM_CAM_ITF_MAIN_MASK) == 0x20000000)
  61 #define PLTFRM_CAM_ITF_IS_BT656(a)      (PLTFRM_CAM_ITF_IS_DVP(a) &&\
  62                 (((a) & PLTFRM_CAM_ITF_SUB_MASK) == 0x02))
  63 #define PLTFRM_CAM_ITF_IS_BT601(a)      (PLTFRM_CAM_ITF_IS_DVP(a) &&\
  64                 (((a) & PLTFRM_CAM_ITF_SUB_MASK) == 0x01))
  65 #define PLTFRM_CAM_ITF_DVP_BW(a)    \
  66                 ((((a) & PLTFRM_CAM_ITF_DVP_BW_MASK) >> 4) + 1)
  67
  68 struct pltfrm_cam_mipi_config {
  69         u32 dphy_index;
  70         u32 vc;
  71         u32 nb_lanes;
  72         u32 bit_rate;
  73 };
  74
  75 struct pltfrm_cam_dvp_config {
  76         enum pltfrm_cam_signal_polarity vsync;
  77         enum pltfrm_cam_signal_polarity hsync;
  78         enum pltfrm_cam_sample_type pclk;
  79 };
  80
  81 struct pltfrm_cam_itf {
  82         enum pltfrm_cam_itf_type type;
  83
  84         union {
  85                 struct pltfrm_cam_mipi_config mipi;
  86                 struct pltfrm_cam_dvp_config dvp;
  87         } cfg;
  88         unsigned int mclk_hz;
  89 };
  90
  91 #define PLTFRM_CAM_ITF_MIPI_CFG(v, nb, br, mk)\
  92         .itf_cfg = {\
  93                 .type =  PLTFRM_CAM_ITF_MIPI,\
  94                         .cfg = {\
  95                                 .mipi = {\
  96                                         .dphy_index = 0,\
  97                                         .vc = v,\
  98                                         .nb_lanes = nb,\
  99                                         .bit_rate = br,\
 100                                 } \
 101                         },\
 102                 .mclk_hz = mk\
 103         }
 104 #define PLTFRM_CAM_ITF_DVP_CFG(ty, vs, hs, ck, mk)\
 105         .itf_cfg = {\
 106                 .type =  ty,\
 107                 .cfg = {\
 108                         .dvp = {\
 109                                 .vsync = vs,\
 110                                 .hsync = hs,\
 111                                 .pclk = ck,\
 112                         } \
 113                 },\
 114                 .mclk_hz = mk\
 115         }
 116
 117 #define PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE    0x00
 118 #define PLTFRM_CIFCAM_G_ITF_CFG    \
 119                                 (PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 1)
 120 #define PLTFRM_CIFCAM_G_DEFRECT    \
 121                                 (PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 2)
 122 #define PLTFRM_CIFCAM_ATTACH    \
 123                                 (PLTFRM_CIFCAM_IOCTL_INTERNAL_BASE + 3)
 124
 125 struct pltfrm_cam_defrect {
 126         unsigned int width;
 127         unsigned int height;
 128         struct v4l2_rect defrect;
 129 };
 130
 131 enum pltfrm_soc_cfg_cmd {
 132         PLTFRM_MCLK_CFG = 0,
 133         PLTFRM_MIPI_DPHY_CFG,
 134
 135         PLTFRM_CLKEN,
 136         PLTFRM_CLKDIS,
 137         PLTFRM_CLKRST,
 138
 139         PLTFRM_SOC_INIT
 140 };
 141
 142 enum pltfrm_soc_io_voltage {
 143         PLTFRM_IO_1V8 = 0,
 144         PLTFRM_IO_3V3 = 1
 145 };
 146
 147 enum pltfrm_soc_drv_strength {
 148         PLTFRM_DRV_STRENGTH_0 = 0,
 149         PLTFRM_DRV_STRENGTH_1 = 1,
 150         PLTFRM_DRV_STRENGTH_2 = 2,
 151         PLTFRM_DRV_STRENGTH_3 = 3
 152
 153 };
 154
 155 struct pltfrm_soc_init_para {
 156         struct platform_device *pdev;
 157         void __iomem *isp_base;
 158 };
 159
 160 struct pltfrm_soc_mclk_para {
 161         enum pltfrm_soc_io_voltage io_voltage;
 162         enum pltfrm_soc_drv_strength drv_strength;
 163 };
 164
 165 struct pltfrm_soc_cfg_para {
 166         enum pltfrm_soc_cfg_cmd cmd;
 167         void *cfg_para;
 168 };
 169
 170 struct pltfrm_soc_cfg {
 171         char name[32];
 172         int (*soc_cfg)(struct pltfrm_soc_cfg_para *cfg);
 173 };
 174
 175 int pltfrm_rk3288_cfg(
 176                 struct pltfrm_soc_cfg_para *cfg);
 177 int pltfrm_rk3399_cfg(
 178                 struct pltfrm_soc_cfg_para *cfg);
 179
 180 #endif