include/linux/mfd/rtsx_pci.h

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG <wei_wang@realsil.com.cn>
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  */
  22
  23 #ifndef __RTSX_PCI_H
  24 #define __RTSX_PCI_H
  25
  26 #include <linux/sched.h>
  27 #include <linux/pci.h>
  28
  29 #include "rtsx_common.h"
  30
  31 #define MAX_RW_REG_CNT                  1024
  32
  33 /* PCI Operation Register Address */
  34 #define RTSX_HCBAR                      0x00
  35 #define RTSX_HCBCTLR                    0x04
  36 #define RTSX_HDBAR                      0x08
  37 #define RTSX_HDBCTLR                    0x0C
  38 #define RTSX_HAIMR                      0x10
  39 #define RTSX_BIPR                       0x14
  40 #define RTSX_BIER                       0x18
  41
  42 /* Host command buffer control register */
  43 #define STOP_CMD                        (0x01 << 28)
  44
  45 /* Host data buffer control register */
  46 #define SDMA_MODE                       0x00
  47 #define ADMA_MODE                       (0x02 << 26)
  48 #define STOP_DMA                        (0x01 << 28)
  49 #define TRIG_DMA                        (0x01 << 31)
  50
  51 /* Host access internal memory register */
  52 #define HAIMR_TRANS_START               (0x01 << 31)
  53 #define HAIMR_READ                      0x00
  54 #define HAIMR_WRITE                     (0x01 << 30)
  55 #define HAIMR_READ_START                (HAIMR_TRANS_START | HAIMR_READ)
  56 #define HAIMR_WRITE_START               (HAIMR_TRANS_START | HAIMR_WRITE)
  57 #define HAIMR_TRANS_END                 (HAIMR_TRANS_START)
  58
  59 /* Bus interrupt pending register */
  60 #define CMD_DONE_INT                    (1 << 31)
  61 #define DATA_DONE_INT                   (1 << 30)
  62 #define TRANS_OK_INT                    (1 << 29)
  63 #define TRANS_FAIL_INT                  (1 << 28)
  64 #define XD_INT                          (1 << 27)
  65 #define MS_INT                          (1 << 26)
  66 #define SD_INT                          (1 << 25)
  67 #define GPIO0_INT                       (1 << 24)
  68 #define OC_INT                          (1 << 23)
  69 #define SD_WRITE_PROTECT                (1 << 19)
  70 #define XD_EXIST                        (1 << 18)
  71 #define MS_EXIST                        (1 << 17)
  72 #define SD_EXIST                        (1 << 16)
  73 #define DELINK_INT                      GPIO0_INT
  74 #define MS_OC_INT                       (1 << 23)
  75 #define SD_OC_INT                       (1 << 22)
  76
  77 #define CARD_INT                (XD_INT | MS_INT | SD_INT)
  78 #define NEED_COMPLETE_INT       (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
  79 #define RTSX_INT                (CMD_DONE_INT | NEED_COMPLETE_INT | \
  80                                         CARD_INT | GPIO0_INT | OC_INT)
  81
  82 #define CARD_EXIST              (XD_EXIST | MS_EXIST | SD_EXIST)
  83
  84 /* Bus interrupt enable register */
  85 #define CMD_DONE_INT_EN         (1 << 31)
  86 #define DATA_DONE_INT_EN        (1 << 30)
  87 #define TRANS_OK_INT_EN         (1 << 29)
  88 #define TRANS_FAIL_INT_EN       (1 << 28)
  89 #define XD_INT_EN               (1 << 27)
  90 #define MS_INT_EN               (1 << 26)
  91 #define SD_INT_EN               (1 << 25)
  92 #define GPIO0_INT_EN            (1 << 24)
  93 #define OC_INT_EN               (1 << 23)
  94 #define DELINK_INT_EN           GPIO0_INT_EN
  95 #define MS_OC_INT_EN            (1 << 23)
  96 #define SD_OC_INT_EN            (1 << 22)
  97
  98 #define READ_REG_CMD            0
  99 #define WRITE_REG_CMD           1
 100 #define CHECK_REG_CMD           2
 101
 102 /*
 103  * macros for easy use
 104  */
 105 #define rtsx_pci_writel(pcr, reg, value) \
 106         iowrite32(value, (pcr)->remap_addr + reg)
 107 #define rtsx_pci_readl(pcr, reg) \
 108         ioread32((pcr)->remap_addr + reg)
 109 #define rtsx_pci_writew(pcr, reg, value) \
 110         iowrite16(value, (pcr)->remap_addr + reg)
 111 #define rtsx_pci_readw(pcr, reg) \
 112         ioread16((pcr)->remap_addr + reg)
 113 #define rtsx_pci_writeb(pcr, reg, value) \
 114         iowrite8(value, (pcr)->remap_addr + reg)
 115 #define rtsx_pci_readb(pcr, reg) \
 116         ioread8((pcr)->remap_addr + reg)
 117
 118 #define rtsx_pci_read_config_byte(pcr, where, val) \
 119         pci_read_config_byte((pcr)->pci, where, val)
 120
 121 #define rtsx_pci_write_config_byte(pcr, where, val) \
 122         pci_write_config_byte((pcr)->pci, where, val)
 123
 124 #define rtsx_pci_read_config_dword(pcr, where, val) \
 125         pci_read_config_dword((pcr)->pci, where, val)
 126
 127 #define rtsx_pci_write_config_dword(pcr, where, val) \
 128         pci_write_config_dword((pcr)->pci, where, val)
 129
 130 #define STATE_TRANS_NONE        0
 131 #define STATE_TRANS_CMD         1
 132 #define STATE_TRANS_BUF         2
 133 #define STATE_TRANS_SG          3
 134
 135 #define TRANS_NOT_READY         0
 136 #define TRANS_RESULT_OK         1
 137 #define TRANS_RESULT_FAIL       2
 138 #define TRANS_NO_DEVICE         3
 139
 140 #define RTSX_RESV_BUF_LEN       4096
 141 #define HOST_CMDS_BUF_LEN       1024
 142 #define HOST_SG_TBL_BUF_LEN     (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
 143 #define HOST_SG_TBL_ITEMS       (HOST_SG_TBL_BUF_LEN / 8)
 144 #define MAX_SG_ITEM_LEN         0x80000
 145
 146 #define HOST_TO_DEVICE          0
 147 #define DEVICE_TO_HOST          1
 148
 149 #define MAX_PHASE               31
 150 #define RX_TUNING_CNT           3
 151
 152 /* SG descriptor */
 153 #define SG_INT                  0x04
 154 #define SG_END                  0x02
 155 #define SG_VALID                0x01
 156
 157 #define SG_NO_OP                0x00
 158 #define SG_TRANS_DATA           (0x02 << 4)
 159 #define SG_LINK_DESC            (0x03 << 4)
 160
 161 /* Output voltage */
 162 #define OUTPUT_3V3              0
 163 #define OUTPUT_1V8              1
 164
 165 /* Card Clock Enable Register */
 166 #define SD_CLK_EN                       0x04
 167 #define MS_CLK_EN                       0x08
 168
 169 /* Card Select Register */
 170 #define SD_MOD_SEL                      2
 171 #define MS_MOD_SEL                      3
 172
 173 /* Card Output Enable Register */
 174 #define SD_OUTPUT_EN                    0x04
 175 #define MS_OUTPUT_EN                    0x08
 176
 177 /* CARD_SHARE_MODE */
 178 #define CARD_SHARE_MASK                 0x0F
 179 #define CARD_SHARE_MULTI_LUN            0x00
 180 #define CARD_SHARE_NORMAL               0x00
 181 #define CARD_SHARE_48_SD                0x04
 182 #define CARD_SHARE_48_MS                0x08
 183 /* CARD_SHARE_MODE for barossa */
 184 #define CARD_SHARE_BAROSSA_SD           0x01
 185 #define CARD_SHARE_BAROSSA_MS           0x02
 186
 187 /* SD30_DRIVE_SEL */
 188 #define DRIVER_TYPE_A                   0x05
 189 #define DRIVER_TYPE_B                   0x03
 190 #define DRIVER_TYPE_C                   0x02
 191 #define DRIVER_TYPE_D                   0x01
 192
 193 /* FPDCTL */
 194 #define SSC_POWER_DOWN                  0x01
 195 #define SD_OC_POWER_DOWN                0x02
 196 #define ALL_POWER_DOWN                  0x07
 197 #define OC_POWER_DOWN                   0x06
 198
 199 /* CLK_CTL */
 200 #define CHANGE_CLK                      0x01
 201
 202 /* LDO_CTL */
 203 #define BPP_ASIC_1V7                    0x00
 204 #define BPP_ASIC_1V8                    0x01
 205 #define BPP_ASIC_1V9                    0x02
 206 #define BPP_ASIC_2V0                    0x03
 207 #define BPP_ASIC_2V7                    0x04
 208 #define BPP_ASIC_2V8                    0x05
 209 #define BPP_ASIC_3V2                    0x06
 210 #define BPP_ASIC_3V3                    0x07
 211 #define BPP_REG_TUNED18                 0x07
 212 #define BPP_TUNED18_SHIFT_8402          5
 213 #define BPP_TUNED18_SHIFT_8411          4
 214 #define BPP_PAD_MASK                    0x04
 215 #define BPP_PAD_3V3                     0x04
 216 #define BPP_PAD_1V8                     0x00
 217 #define BPP_LDO_POWB                    0x03
 218 #define BPP_LDO_ON                      0x00
 219 #define BPP_LDO_SUSPEND                 0x02
 220 #define BPP_LDO_OFF                     0x03
 221
 222 /* CD_PAD_CTL */
 223 #define CD_DISABLE_MASK                 0x07
 224 #define MS_CD_DISABLE                   0x04
 225 #define SD_CD_DISABLE                   0x02
 226 #define XD_CD_DISABLE                   0x01
 227 #define CD_DISABLE                      0x07
 228 #define CD_ENABLE                       0x00
 229 #define MS_CD_EN_ONLY                   0x03
 230 #define SD_CD_EN_ONLY                   0x05
 231 #define XD_CD_EN_ONLY                   0x06
 232 #define FORCE_CD_LOW_MASK               0x38
 233 #define FORCE_CD_XD_LOW                 0x08
 234 #define FORCE_CD_SD_LOW                 0x10
 235 #define FORCE_CD_MS_LOW                 0x20
 236 #define CD_AUTO_DISABLE                 0x40
 237
 238 /* SD_STAT1 */
 239 #define SD_CRC7_ERR                     0x80
 240 #define SD_CRC16_ERR                    0x40
 241 #define SD_CRC_WRITE_ERR                0x20
 242 #define SD_CRC_WRITE_ERR_MASK           0x1C
 243 #define GET_CRC_TIME_OUT                0x02
 244 #define SD_TUNING_COMPARE_ERR           0x01
 245
 246 /* SD_STAT2 */
 247 #define SD_RSP_80CLK_TIMEOUT            0x01
 248
 249 /* SD_BUS_STAT */
 250 #define SD_CLK_TOGGLE_EN                0x80
 251 #define SD_CLK_FORCE_STOP               0x40
 252 #define SD_DAT3_STATUS                  0x10
 253 #define SD_DAT2_STATUS                  0x08
 254 #define SD_DAT1_STATUS                  0x04
 255 #define SD_DAT0_STATUS                  0x02
 256 #define SD_CMD_STATUS                   0x01
 257
 258 /* SD_PAD_CTL */
 259 #define SD_IO_USING_1V8                 0x80
 260 #define SD_IO_USING_3V3                 0x7F
 261 #define TYPE_A_DRIVING                  0x00
 262 #define TYPE_B_DRIVING                  0x01
 263 #define TYPE_C_DRIVING                  0x02
 264 #define TYPE_D_DRIVING                  0x03
 265
 266 /* SD_SAMPLE_POINT_CTL */
 267 #define DDR_FIX_RX_DAT                  0x00
 268 #define DDR_VAR_RX_DAT                  0x80
 269 #define DDR_FIX_RX_DAT_EDGE             0x00
 270 #define DDR_FIX_RX_DAT_14_DELAY         0x40
 271 #define DDR_FIX_RX_CMD                  0x00
 272 #define DDR_VAR_RX_CMD                  0x20
 273 #define DDR_FIX_RX_CMD_POS_EDGE         0x00
 274 #define DDR_FIX_RX_CMD_14_DELAY         0x10
 275 #define SD20_RX_POS_EDGE                0x00
 276 #define SD20_RX_14_DELAY                0x08
 277 #define SD20_RX_SEL_MASK                0x08
 278
 279 /* SD_PUSH_POINT_CTL */
 280 #define DDR_FIX_TX_CMD_DAT              0x00
 281 #define DDR_VAR_TX_CMD_DAT              0x80
 282 #define DDR_FIX_TX_DAT_14_TSU           0x00
 283 #define DDR_FIX_TX_DAT_12_TSU           0x40
 284 #define DDR_FIX_TX_CMD_NEG_EDGE         0x00
 285 #define DDR_FIX_TX_CMD_14_AHEAD         0x20
 286 #define SD20_TX_NEG_EDGE                0x00
 287 #define SD20_TX_14_AHEAD                0x10
 288 #define SD20_TX_SEL_MASK                0x10
 289 #define DDR_VAR_SDCLK_POL_SWAP          0x01
 290
 291 /* SD_TRANSFER */
 292 #define SD_TRANSFER_START               0x80
 293 #define SD_TRANSFER_END                 0x40
 294 #define SD_STAT_IDLE                    0x20
 295 #define SD_TRANSFER_ERR                 0x10
 296 /* SD Transfer Mode definition */
 297 #define SD_TM_NORMAL_WRITE              0x00
 298 #define SD_TM_AUTO_WRITE_3              0x01
 299 #define SD_TM_AUTO_WRITE_4              0x02
 300 #define SD_TM_AUTO_READ_3               0x05
 301 #define SD_TM_AUTO_READ_4               0x06
 302 #define SD_TM_CMD_RSP                   0x08
 303 #define SD_TM_AUTO_WRITE_1              0x09
 304 #define SD_TM_AUTO_WRITE_2              0x0A
 305 #define SD_TM_NORMAL_READ               0x0C
 306 #define SD_TM_AUTO_READ_1               0x0D
 307 #define SD_TM_AUTO_READ_2               0x0E
 308 #define SD_TM_AUTO_TUNING               0x0F
 309
 310 /* SD_VPTX_CTL / SD_VPRX_CTL */
 311 #define PHASE_CHANGE                    0x80
 312 #define PHASE_NOT_RESET                 0x40
 313
 314 /* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */
 315 #define DCMPS_CHANGE                    0x80
 316 #define DCMPS_CHANGE_DONE               0x40
 317 #define DCMPS_ERROR                     0x20
 318 #define DCMPS_CURRENT_PHASE             0x1F
 319
 320 /* SD Configure 1 Register */
 321 #define SD_CLK_DIVIDE_0                 0x00
 322 #define SD_CLK_DIVIDE_256               0xC0
 323 #define SD_CLK_DIVIDE_128               0x80
 324 #define SD_BUS_WIDTH_1BIT               0x00
 325 #define SD_BUS_WIDTH_4BIT               0x01
 326 #define SD_BUS_WIDTH_8BIT               0x02
 327 #define SD_ASYNC_FIFO_NOT_RST           0x10
 328 #define SD_20_MODE                      0x00
 329 #define SD_DDR_MODE                     0x04
 330 #define SD_30_MODE                      0x08
 331
 332 #define SD_CLK_DIVIDE_MASK              0xC0
 333
 334 /* SD_CMD_STATE */
 335 #define SD_CMD_IDLE                     0x80
 336
 337 /* SD_DATA_STATE */
 338 #define SD_DATA_IDLE                    0x80
 339
 340 /* DCM_DRP_CTL */
 341 #define DCM_RESET                       0x08
 342 #define DCM_LOCKED                      0x04
 343 #define DCM_208M                        0x00
 344 #define DCM_TX                          0x01
 345 #define DCM_RX                          0x02
 346
 347 /* DCM_DRP_TRIG */
 348 #define DRP_START                       0x80
 349 #define DRP_DONE                        0x40
 350
 351 /* DCM_DRP_CFG */
 352 #define DRP_WRITE                       0x80
 353 #define DRP_READ                        0x00
 354 #define DCM_WRITE_ADDRESS_50            0x50
 355 #define DCM_WRITE_ADDRESS_51            0x51
 356 #define DCM_READ_ADDRESS_00             0x00
 357 #define DCM_READ_ADDRESS_51             0x51
 358
 359 /* IRQSTAT0 */
 360 #define DMA_DONE_INT                    0x80
 361 #define SUSPEND_INT                     0x40
 362 #define LINK_RDY_INT                    0x20
 363 #define LINK_DOWN_INT                   0x10
 364
 365 /* DMACTL */
 366 #define DMA_RST                         0x80
 367 #define DMA_BUSY                        0x04
 368 #define DMA_DIR_TO_CARD                 0x00
 369 #define DMA_DIR_FROM_CARD               0x02
 370 #define DMA_EN                          0x01
 371 #define DMA_128                         (0 << 4)
 372 #define DMA_256                         (1 << 4)
 373 #define DMA_512                         (2 << 4)
 374 #define DMA_1024                        (3 << 4)
 375 #define DMA_PACK_SIZE_MASK              0x30
 376
 377 /* SSC_CTL1 */
 378 #define SSC_RSTB                        0x80
 379 #define SSC_8X_EN                       0x40
 380 #define SSC_FIX_FRAC                    0x20
 381 #define SSC_SEL_1M                      0x00
 382 #define SSC_SEL_2M                      0x08
 383 #define SSC_SEL_4M                      0x10
 384 #define SSC_SEL_8M                      0x18
 385
 386 /* SSC_CTL2 */
 387 #define SSC_DEPTH_MASK                  0x07
 388 #define SSC_DEPTH_DISALBE               0x00
 389 #define SSC_DEPTH_4M                    0x01
 390 #define SSC_DEPTH_2M                    0x02
 391 #define SSC_DEPTH_1M                    0x03
 392 #define SSC_DEPTH_500K                  0x04
 393 #define SSC_DEPTH_250K                  0x05
 394
 395 /* System Clock Control Register */
 396 #define CLK_LOW_FREQ                    0x01
 397
 398 /* System Clock Divider Register */
 399 #define CLK_DIV_1                       0x01
 400 #define CLK_DIV_2                       0x02
 401 #define CLK_DIV_4                       0x03
 402 #define CLK_DIV_8                       0x04
 403
 404 /* MS_CFG */
 405 #define SAMPLE_TIME_RISING              0x00
 406 #define SAMPLE_TIME_FALLING             0x80
 407 #define PUSH_TIME_DEFAULT               0x00
 408 #define PUSH_TIME_ODD                   0x40
 409 #define NO_EXTEND_TOGGLE                0x00
 410 #define EXTEND_TOGGLE_CHK               0x20
 411 #define MS_BUS_WIDTH_1                  0x00
 412 #define MS_BUS_WIDTH_4                  0x10
 413 #define MS_BUS_WIDTH_8                  0x18
 414 #define MS_2K_SECTOR_MODE               0x04
 415 #define MS_512_SECTOR_MODE              0x00
 416 #define MS_TOGGLE_TIMEOUT_EN            0x00
 417 #define MS_TOGGLE_TIMEOUT_DISEN         0x01
 418 #define MS_NO_CHECK_INT                 0x02
 419
 420 /* MS_TRANS_CFG */
 421 #define WAIT_INT                        0x80
 422 #define NO_WAIT_INT                     0x00
 423 #define NO_AUTO_READ_INT_REG            0x00
 424 #define AUTO_READ_INT_REG               0x40
 425 #define MS_CRC16_ERR                    0x20
 426 #define MS_RDY_TIMEOUT                  0x10
 427 #define MS_INT_CMDNK                    0x08
 428 #define MS_INT_BREQ                     0x04
 429 #define MS_INT_ERR                      0x02
 430 #define MS_INT_CED                      0x01
 431
 432 /* MS_TRANSFER */
 433 #define MS_TRANSFER_START               0x80
 434 #define MS_TRANSFER_END                 0x40
 435 #define MS_TRANSFER_ERR                 0x20
 436 #define MS_BS_STATE                     0x10
 437 #define MS_TM_READ_BYTES                0x00
 438 #define MS_TM_NORMAL_READ               0x01
 439 #define MS_TM_WRITE_BYTES               0x04
 440 #define MS_TM_NORMAL_WRITE              0x05
 441 #define MS_TM_AUTO_READ                 0x08
 442 #define MS_TM_AUTO_WRITE                0x0C
 443
 444 /* SD Configure 2 Register */
 445 #define SD_CALCULATE_CRC7               0x00
 446 #define SD_NO_CALCULATE_CRC7            0x80
 447 #define SD_CHECK_CRC16                  0x00
 448 #define SD_NO_CHECK_CRC16               0x40
 449 #define SD_NO_CHECK_WAIT_CRC_TO         0x20
 450 #define SD_WAIT_BUSY_END                0x08
 451 #define SD_NO_WAIT_BUSY_END             0x00
 452 #define SD_CHECK_CRC7                   0x00
 453 #define SD_NO_CHECK_CRC7                0x04
 454 #define SD_RSP_LEN_0                    0x00
 455 #define SD_RSP_LEN_6                    0x01
 456 #define SD_RSP_LEN_17                   0x02
 457 /* SD/MMC Response Type Definition */
 458 #define SD_RSP_TYPE_R0                  0x04
 459 #define SD_RSP_TYPE_R1                  0x01
 460 #define SD_RSP_TYPE_R1b                 0x09
 461 #define SD_RSP_TYPE_R2                  0x02
 462 #define SD_RSP_TYPE_R3                  0x05
 463 #define SD_RSP_TYPE_R4                  0x05
 464 #define SD_RSP_TYPE_R5                  0x01
 465 #define SD_RSP_TYPE_R6                  0x01
 466 #define SD_RSP_TYPE_R7                  0x01
 467
 468 /* SD_CONFIGURE3 */
 469 #define SD_RSP_80CLK_TIMEOUT_EN         0x01
 470
 471 /* Card Transfer Reset Register */
 472 #define SPI_STOP                        0x01
 473 #define XD_STOP                         0x02
 474 #define SD_STOP                         0x04
 475 #define MS_STOP                         0x08
 476 #define SPI_CLR_ERR                     0x10
 477 #define XD_CLR_ERR                      0x20
 478 #define SD_CLR_ERR                      0x40
 479 #define MS_CLR_ERR                      0x80
 480
 481 /* Card Data Source Register */
 482 #define PINGPONG_BUFFER                 0x01
 483 #define RING_BUFFER                     0x00
 484
 485 /* Card Power Control Register */
 486 #define PMOS_STRG_MASK                  0x10
 487 #define PMOS_STRG_800mA                 0x10
 488 #define PMOS_STRG_400mA                 0x00
 489 #define SD_POWER_OFF                    0x03
 490 #define SD_PARTIAL_POWER_ON             0x01
 491 #define SD_POWER_ON                     0x00
 492 #define SD_POWER_MASK                   0x03
 493 #define MS_POWER_OFF                    0x0C
 494 #define MS_PARTIAL_POWER_ON             0x04
 495 #define MS_POWER_ON                     0x00
 496 #define MS_POWER_MASK                   0x0C
 497 #define BPP_POWER_OFF                   0x0F
 498 #define BPP_POWER_5_PERCENT_ON          0x0E
 499 #define BPP_POWER_10_PERCENT_ON         0x0C
 500 #define BPP_POWER_15_PERCENT_ON         0x08
 501 #define BPP_POWER_ON                    0x00
 502 #define BPP_POWER_MASK                  0x0F
 503 #define SD_VCC_PARTIAL_POWER_ON         0x02
 504 #define SD_VCC_POWER_ON                 0x00
 505
 506 /* PWR_GATE_CTRL */
 507 #define PWR_GATE_EN                     0x01
 508 #define LDO3318_PWR_MASK                0x06
 509 #define LDO_ON                          0x00
 510 #define LDO_SUSPEND                     0x04
 511 #define LDO_OFF                         0x06
 512
 513 /* CARD_CLK_SOURCE */
 514 #define CRC_FIX_CLK                     (0x00 << 0)
 515 #define CRC_VAR_CLK0                    (0x01 << 0)
 516 #define CRC_VAR_CLK1                    (0x02 << 0)
 517 #define SD30_FIX_CLK                    (0x00 << 2)
 518 #define SD30_VAR_CLK0                   (0x01 << 2)
 519 #define SD30_VAR_CLK1                   (0x02 << 2)
 520 #define SAMPLE_FIX_CLK                  (0x00 << 4)
 521 #define SAMPLE_VAR_CLK0                 (0x01 << 4)
 522 #define SAMPLE_VAR_CLK1                 (0x02 << 4)
 523
 524 #define MS_CFG                          0xFD40
 525 #define MS_TPC                          0xFD41
 526 #define MS_TRANS_CFG                    0xFD42
 527 #define MS_TRANSFER                     0xFD43
 528 #define MS_INT_REG                      0xFD44
 529 #define MS_BYTE_CNT                     0xFD45
 530 #define MS_SECTOR_CNT_L                 0xFD46
 531 #define MS_SECTOR_CNT_H                 0xFD47
 532 #define MS_DBUS_H                       0xFD48
 533
 534 #define SD_CFG1                         0xFDA0
 535 #define SD_CFG2                         0xFDA1
 536 #define SD_CFG3                         0xFDA2
 537 #define SD_STAT1                        0xFDA3
 538 #define SD_STAT2                        0xFDA4
 539 #define SD_BUS_STAT                     0xFDA5
 540 #define SD_PAD_CTL                      0xFDA6
 541 #define SD_SAMPLE_POINT_CTL             0xFDA7
 542 #define SD_PUSH_POINT_CTL               0xFDA8
 543 #define SD_CMD0                         0xFDA9
 544 #define SD_CMD1                         0xFDAA
 545 #define SD_CMD2                         0xFDAB
 546 #define SD_CMD3                         0xFDAC
 547 #define SD_CMD4                         0xFDAD
 548 #define SD_CMD5                         0xFDAE
 549 #define SD_BYTE_CNT_L                   0xFDAF
 550 #define SD_BYTE_CNT_H                   0xFDB0
 551 #define SD_BLOCK_CNT_L                  0xFDB1
 552 #define SD_BLOCK_CNT_H                  0xFDB2
 553 #define SD_TRANSFER                     0xFDB3
 554 #define SD_CMD_STATE                    0xFDB5
 555 #define SD_DATA_STATE                   0xFDB6
 556
 557 #define SRCTL                           0xFC13
 558
 559 #define DCM_DRP_CTL                     0xFC23
 560 #define DCM_DRP_TRIG                    0xFC24
 561 #define DCM_DRP_CFG                     0xFC25
 562 #define DCM_DRP_WR_DATA_L               0xFC26
 563 #define DCM_DRP_WR_DATA_H               0xFC27
 564 #define DCM_DRP_RD_DATA_L               0xFC28
 565 #define DCM_DRP_RD_DATA_H               0xFC29
 566 #define SD_VPCLK0_CTL                   0xFC2A
 567 #define SD_VPCLK1_CTL                   0xFC2B
 568 #define SD_DCMPS0_CTL                   0xFC2C
 569 #define SD_DCMPS1_CTL                   0xFC2D
 570 #define SD_VPTX_CTL                     SD_VPCLK0_CTL
 571 #define SD_VPRX_CTL                     SD_VPCLK1_CTL
 572 #define SD_DCMPS_TX_CTL                 SD_DCMPS0_CTL
 573 #define SD_DCMPS_RX_CTL                 SD_DCMPS1_CTL
 574 #define CARD_CLK_SOURCE                 0xFC2E
 575
 576 #define CARD_PWR_CTL                    0xFD50
 577 #define CARD_CLK_SWITCH                 0xFD51
 578 #define CARD_SHARE_MODE                 0xFD52
 579 #define CARD_DRIVE_SEL                  0xFD53
 580 #define CARD_STOP                       0xFD54
 581 #define CARD_OE                         0xFD55
 582 #define CARD_AUTO_BLINK                 0xFD56
 583 #define CARD_GPIO_DIR                   0xFD57
 584 #define CARD_GPIO                       0xFD58
 585 #define CARD_DATA_SOURCE                0xFD5B
 586 #define SD30_CLK_DRIVE_SEL              0xFD5A
 587 #define CARD_SELECT                     0xFD5C
 588 #define SD30_DRIVE_SEL                  0xFD5E
 589 #define SD30_CMD_DRIVE_SEL              0xFD5E
 590 #define SD30_DAT_DRIVE_SEL              0xFD5F
 591 #define CARD_CLK_EN                     0xFD69
 592 #define SDIO_CTRL                       0xFD6B
 593 #define CD_PAD_CTL                      0xFD73
 594
 595 #define FPDCTL                          0xFC00
 596 #define PDINFO                          0xFC01
 597
 598 #define CLK_CTL                         0xFC02
 599 #define CLK_DIV                         0xFC03
 600 #define CLK_SEL                         0xFC04
 601
 602 #define SSC_DIV_N_0                     0xFC0F
 603 #define SSC_DIV_N_1                     0xFC10
 604 #define SSC_CTL1                        0xFC11
 605 #define SSC_CTL2                        0xFC12
 606
 607 #define RCCTL                           0xFC14
 608
 609 #define FPGA_PULL_CTL                   0xFC1D
 610 #define OLT_LED_CTL                     0xFC1E
 611 #define GPIO_CTL                        0xFC1F
 612
 613 #define LDO_CTL                         0xFC1E
 614 #define SYS_VER                         0xFC32
 615
 616 #define CARD_PULL_CTL1                  0xFD60
 617 #define CARD_PULL_CTL2                  0xFD61
 618 #define CARD_PULL_CTL3                  0xFD62
 619 #define CARD_PULL_CTL4                  0xFD63
 620 #define CARD_PULL_CTL5                  0xFD64
 621 #define CARD_PULL_CTL6                  0xFD65
 622
 623 /* PCI Express Related Registers */
 624 #define IRQEN0                          0xFE20
 625 #define IRQSTAT0                        0xFE21
 626 #define IRQEN1                          0xFE22
 627 #define IRQSTAT1                        0xFE23
 628 #define TLPRIEN                         0xFE24
 629 #define TLPRISTAT                       0xFE25
 630 #define TLPTIEN                         0xFE26
 631 #define TLPTISTAT                       0xFE27
 632 #define DMATC0                          0xFE28
 633 #define DMATC1                          0xFE29
 634 #define DMATC2                          0xFE2A
 635 #define DMATC3                          0xFE2B
 636 #define DMACTL                          0xFE2C
 637 #define BCTL                            0xFE2D
 638 #define RBBC0                           0xFE2E
 639 #define RBBC1                           0xFE2F
 640 #define RBDAT                           0xFE30
 641 #define RBCTL                           0xFE34
 642 #define CFGADDR0                        0xFE35
 643 #define CFGADDR1                        0xFE36
 644 #define CFGDATA0                        0xFE37
 645 #define CFGDATA1                        0xFE38
 646 #define CFGDATA2                        0xFE39
 647 #define CFGDATA3                        0xFE3A
 648 #define CFGRWCTL                        0xFE3B
 649 #define PHYRWCTL                        0xFE3C
 650 #define PHYDATA0                        0xFE3D
 651 #define PHYDATA1                        0xFE3E
 652 #define PHYADDR                         0xFE3F
 653 #define MSGRXDATA0                      0xFE40
 654 #define MSGRXDATA1                      0xFE41
 655 #define MSGRXDATA2                      0xFE42
 656 #define MSGRXDATA3                      0xFE43
 657 #define MSGTXDATA0                      0xFE44
 658 #define MSGTXDATA1                      0xFE45
 659 #define MSGTXDATA2                      0xFE46
 660 #define MSGTXDATA3                      0xFE47
 661 #define MSGTXCTL                        0xFE48
 662 #define PETXCFG                         0xFE49
 663 #define LTR_CTL                         0xFE4A
 664 #define OBFF_CFG                        0xFE4C
 665
 666 #define CDRESUMECTL                     0xFE52
 667 #define WAKE_SEL_CTL                    0xFE54
 668 #define PME_FORCE_CTL                   0xFE56
 669 #define ASPM_FORCE_CTL                  0xFE57
 670 #define PM_CLK_FORCE_CTL                0xFE58
 671 #define PERST_GLITCH_WIDTH              0xFE5C
 672 #define CHANGE_LINK_STATE               0xFE5B
 673 #define RESET_LOAD_REG                  0xFE5E
 674 #define EFUSE_CONTENT                   0xFE5F
 675 #define HOST_SLEEP_STATE                0xFE60
 676 #define SDIO_CFG                        0xFE70
 677
 678 #define NFTS_TX_CTRL                    0xFE72
 679
 680 #define PWR_GATE_CTRL                   0xFE75
 681 #define PWD_SUSPEND_EN                  0xFE76
 682 #define LDO_PWR_SEL                     0xFE78
 683
 684 #define DUMMY_REG_RESET_0               0xFE90
 685
 686 /* Memory mapping */
 687 #define SRAM_BASE                       0xE600
 688 #define RBUF_BASE                       0xF400
 689 #define PPBUF_BASE1                     0xF800
 690 #define PPBUF_BASE2                     0xFA00
 691 #define IMAGE_FLAG_ADDR0                0xCE80
 692 #define IMAGE_FLAG_ADDR1                0xCE81
 693
 694 /* Phy register */
 695 #define PHY_PCR                         0x00
 696 #define PHY_RCR0                        0x01
 697 #define PHY_RCR1                        0x02
 698 #define PHY_RCR2                        0x03
 699 #define PHY_RTCR                        0x04
 700 #define PHY_RDR                         0x05
 701 #define PHY_TCR0                        0x06
 702 #define PHY_TCR1                        0x07
 703 #define PHY_TUNE                        0x08
 704 #define PHY_IMR                         0x09
 705 #define PHY_BPCR                        0x0A
 706 #define PHY_BIST                        0x0B
 707 #define PHY_RAW_L                       0x0C
 708 #define PHY_RAW_H                       0x0D
 709 #define PHY_RAW_DATA                    0x0E
 710 #define PHY_HOST_CLK_CTRL               0x0F
 711 #define PHY_DMR                         0x10
 712 #define PHY_BACR                        0x11
 713 #define PHY_IER                         0x12
 714 #define PHY_BCSR                        0x13
 715 #define PHY_BPR                         0x14
 716 #define PHY_BPNR2                       0x15
 717 #define PHY_BPNR                        0x16
 718 #define PHY_BRNR2                       0x17
 719 #define PHY_BENR                        0x18
 720 #define PHY_REG_REV                     0x19
 721 #define PHY_FLD0                        0x1A
 722 #define PHY_FLD1                        0x1B
 723 #define PHY_FLD2                        0x1C
 724 #define PHY_FLD3                        0x1D
 725 #define PHY_FLD4                        0x1E
 726 #define PHY_DUM_REG                     0x1F
 727
 728 #define rtsx_pci_init_cmd(pcr)          ((pcr)->ci = 0)
 729
 730 struct rtsx_pcr;
 731
 732 struct pcr_handle {
 733         struct rtsx_pcr                 *pcr;
 734 };
 735
 736 struct pcr_ops {
 737         int             (*extra_init_hw)(struct rtsx_pcr *pcr);
 738         int             (*optimize_phy)(struct rtsx_pcr *pcr);
 739         int             (*turn_on_led)(struct rtsx_pcr *pcr);
 740         int             (*turn_off_led)(struct rtsx_pcr *pcr);
 741         int             (*enable_auto_blink)(struct rtsx_pcr *pcr);
 742         int             (*disable_auto_blink)(struct rtsx_pcr *pcr);
 743         int             (*card_power_on)(struct rtsx_pcr *pcr, int card);
 744         int             (*card_power_off)(struct rtsx_pcr *pcr, int card);
 745         int             (*switch_output_voltage)(struct rtsx_pcr *pcr,
 746                                                 u8 voltage);
 747         unsigned int    (*cd_deglitch)(struct rtsx_pcr *pcr);
 748         int             (*conv_clk_and_div_n)(int clk, int dir);
 749 };
 750
 751 enum PDEV_STAT  {PDEV_STAT_IDLE, PDEV_STAT_RUN};
 752
 753 struct rtsx_pcr {
 754         struct pci_dev                  *pci;
 755         unsigned int                    id;
 756
 757         /* pci resources */
 758         unsigned long                   addr;
 759         void __iomem                    *remap_addr;
 760         int                             irq;
 761
 762         /* host reserved buffer */
 763         void                            *rtsx_resv_buf;
 764         dma_addr_t                      rtsx_resv_buf_addr;
 765
 766         void                            *host_cmds_ptr;
 767         dma_addr_t                      host_cmds_addr;
 768         int                             ci;
 769
 770         void                            *host_sg_tbl_ptr;
 771         dma_addr_t                      host_sg_tbl_addr;
 772         int                             sgi;
 773
 774         u32                             bier;
 775         char                            trans_result;
 776
 777         unsigned int                    card_inserted;
 778         unsigned int                    card_removed;
 779         unsigned int                    card_exist;
 780
 781         struct delayed_work             carddet_work;
 782         struct delayed_work             idle_work;
 783
 784         spinlock_t                      lock;
 785         struct mutex                    pcr_mutex;
 786         struct completion               *done;
 787         struct completion               *finish_me;
 788
 789         unsigned int                    cur_clock;
 790         bool                            ms_pmos;
 791         bool                            remove_pci;
 792         bool                            msi_en;
 793
 794 #define EXTRA_CAPS_SD_SDR50             (1 << 0)
 795 #define EXTRA_CAPS_SD_SDR104            (1 << 1)
 796 #define EXTRA_CAPS_SD_DDR50             (1 << 2)
 797 #define EXTRA_CAPS_MMC_HSDDR            (1 << 3)
 798 #define EXTRA_CAPS_MMC_HS200            (1 << 4)
 799 #define EXTRA_CAPS_MMC_8BIT             (1 << 5)
 800         u32                             extra_caps;
 801
 802 #define IC_VER_A                        0
 803 #define IC_VER_B                        1
 804 #define IC_VER_C                        2
 805 #define IC_VER_D                        3
 806         u8                              ic_version;
 807
 808         const u32                       *sd_pull_ctl_enable_tbl;
 809         const u32                       *sd_pull_ctl_disable_tbl;
 810         const u32                       *ms_pull_ctl_enable_tbl;
 811         const u32                       *ms_pull_ctl_disable_tbl;
 812
 813         const struct pcr_ops            *ops;
 814         enum PDEV_STAT                  state;
 815
 816         int                             num_slots;
 817         struct rtsx_slot                *slots;
 818 };
 819
 820 #define CHK_PCI_PID(pcr, pid)           ((pcr)->pci->device == (pid))
 821 #define PCI_VID(pcr)                    ((pcr)->pci->vendor)
 822 #define PCI_PID(pcr)                    ((pcr)->pci->device)
 823
 824 void rtsx_pci_start_run(struct rtsx_pcr *pcr);
 825 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
 826 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
 827 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
 828 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
 829 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
 830 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
 831                 u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
 832 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
 833 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
 834 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
 835                 int num_sg, bool read, int timeout);
 836 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
 837 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
 838 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
 839 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
 840 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
 841                 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
 842 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
 843 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
 844 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
 845 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
 846 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
 847 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
 848
 849 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
 850 {
 851         return (u8 *)(pcr->host_cmds_ptr);
 852 }
 853
 854 #endif