include/dt-bindings/display/screen-timing/lcd-lq070m1sx01-mipi.dtsi

   1 /*
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * arch/arm/boot/dts/lcd-lq070m1sx01-mipi.dtsi
   4  * author: libing@rock-chips.com
   5  * create date: 2014-04-15
   6  * lcd model: lq070m1sx01
   7  * resolution: 1920 X 1200
   8  * mipi channel: dual
   9  */
  10
  11 /* about mipi */
  12 disp_mipi_init: mipi_dsi_init{
  13                         compatible = "rockchip,mipi_dsi_init";
  14                         rockchip,screen_init    = <1>;
  15                         rockchip,dsi_lane               = <2>;
  16                         rockchip,dsi_hs_clk             = <1000>;
  17                         rockchip,mipi_dsi_num   = <2>;
  18 };
  19 disp_mipi_power_ctr: mipi_power_ctr {
  20                         compatible = "rockchip,mipi_power_ctr";
  21                         mipi_lcd_rst:mipi_lcd_rst{
  22                                         compatible = "rockchip,lcd_rst";
  23                                         rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_HIGH>;
  24                                         rockchip,delay = <10>;
  25                         };
  26                         mipi_lcd_en:mipi_lcd_en {
  27                                         compatible = "rockchip,lcd_en";
  28                                         rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
  29                                         rockchip,delay = <10>;
  30                         };
  31 };
  32 disp_mipi_init_cmds: screen-on-cmds {
  33                         rockchip,cmd_debug = <0>;
  34                         compatible = "rockchip,screen-on-cmds";
  35                         rockchip,on-cmds1 {
  36                                         compatible = "rockchip,on-cmds";
  37                                         rockchip,cmd_type = <LPDT>;
  38                                         rockchip,dsi_id = <2>;
  39                                         rockchip,cmd = <0x15 0xb0 0x02>;
  40                                         rockchip,cmd_delay = <0>;
  41                         };
  42
  43                         rockchip,on-cmds2 {
  44                                         compatible = "rockchip,on-cmds";
  45                                         rockchip,cmd_type = <LPDT>;
  46                                         rockchip,dsi_id = <2>;
  47                                         rockchip,cmd = <0x15 0xb1 0x21>;
  48                                         rockchip,cmd_delay = <0>;
  49                         };
  50                         rockchip,on-cmds3 {
  51                                         compatible = "rockchip,on-cmds";
  52                                         rockchip,cmd_type = <LPDT>;
  53                                         rockchip,dsi_id = <2>;
  54                                         rockchip,cmd = <0x15 0xb0 0x06>;
  55                                         rockchip,cmd_delay = <0>;
  56                         };
  57                         rockchip,on-cmds4 {
  58                                         compatible = "rockchip,on-cmds";
  59                                         rockchip,cmd_type = <LPDT>;
  60                                         rockchip,dsi_id = <2>;
  61                                         rockchip,cmd = <0x15 0xb1 0x21>;
  62                                         rockchip,cmd_delay = <0>;
  63                         };
  64                         rockchip,on-cmds5 {
  65                                         compatible = "rockchip,on-cmds";
  66                                         rockchip,cmd_type = <LPDT>;
  67                                         rockchip,dsi_id = <2>;
  68                                         rockchip,cmd = <0x15 0xb4 0x15>;
  69                                         rockchip,cmd_delay = <0>;
  70                         };
  71                         rockchip,on-cmds6 {
  72                                         compatible = "rockchip,on-cmds";
  73                                         rockchip,cmd_type = <LPDT>;
  74                                         rockchip,dsi_id = <2>;
  75                                         rockchip,cmd = <0x15 0xb9 0x40>;
  76                                         rockchip,cmd_delay = <0>;
  77                         };
  78                         rockchip,on-cmds7 {
  79                                         compatible = "rockchip,on-cmds";
  80                                         rockchip,cmd_type = <LPDT>;
  81                                         rockchip,dsi_id = <2>;
  82                                         rockchip,cmd = <0x15 0xb0 0x00>;
  83                                         rockchip,cmd_delay = <0>;
  84                         };
  85                         rockchip,on-cmds8 {
  86                                         compatible = "rockchip,on-cmds";
  87                                         rockchip,cmd_type = <LPDT>;
  88                                         rockchip,dsi_id = <2>;
  89                                         rockchip,cmd = <0x05 dcs_set_display_on>;
  90                                         rockchip,cmd_delay = <10>;
  91                         };
  92                         rockchip,on-cmds9 {
  93                                         compatible = "rockchip,on-cmds";
  94                                         rockchip,cmd_type = <LPDT>;
  95                                         rockchip,data_type = <DATA_TYPE_DCS>;
  96                                         rockchip,dsi_id = <2>;
  97                                         rockchip,cmd = <0x05 dcs_exit_sleep_mode>;
  98                                         rockchip,cmd_delay = <10>;
  99                         };
 100 };
 101
 102 disp_timings: display-timings {
 103         native-mode = <&timing0>;
 104         compatible = "rockchip,display-timings";
 105         timing0: timing0 {
 106                 screen-type = <SCREEN_DUAL_MIPI>;
 107                 lvds-format = <LVDS_8BIT_2>;
 108                 out-face    = <OUT_P888>;
 109                 clock-frequency = <150000000>;
 110                 hactive = <1200>;
 111                 vactive = <1920>;
 112                 hsync-len = <8>;
 113                 hback-porch = <32>;
 114                 hfront-porch = <156>;
 115
 116                 vsync-len = <2>;
 117                 vback-porch = <6>;
 118                 vfront-porch = <12>;
 119
 120                 hsync-active = <0>;
 121                 vsync-active = <0>;
 122                 de-active = <0>;
 123                 pixelclk-active = <0>;
 124                 swap-rb = <0>;
 125                 swap-rg = <0>;
 126                 swap-gb = <0>;
 127         };
 128 };