include/dt-bindings/display/rk_fb.h

   1 #ifndef _DT_BINDINGS_RKFB_H_
   2 #define _DT_BINDINGS_RKFB_H_
   3 #define GPIO            0
   4 #define REGULATOR       1
   5
   6 #define PRMRY           1               /*primary display device*/
   7 #define EXTEND          2               /*extend display device*/
   8
   9 #define DISPLAY_SOURCE_LCDC0    0
  10 #define DISPLAY_SOURCE_LCDC1    1
  11
  12 #define NO_DUAL         0
  13 #define ONE_DUAL        1
  14 #define DUAL            2
  15 #define DUAL_LCD        3
  16 /********************************************************************
  17 **          display output interface supported by rockchip         **
  18 ********************************************************************/
  19 #define OUT_P888            0   //24bit screen,connect to lcdc D0~D23
  20 #define OUT_P666            1   //18bit screen,connect to lcdc D0~D17
  21 #define OUT_P565            2
  22 #define OUT_S888x           4
  23 #define OUT_CCIR656         6
  24 #define OUT_S888            8
  25 #define OUT_S888DUMY        12
  26 #define OUT_YUV_420         14
  27 #define OUT_P101010         15
  28 #define OUT_YUV_420_10BIT   16
  29 #define OUT_YUV_422         12
  30 #define OUT_YUV_422_10BIT   17
  31 #define OUT_P16BPP4         24
  32 #define OUT_D888_P666       0x21        //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
  33 #define OUT_D888_P565       0x22
  34
  35 #define SCREEN_NULL        0
  36 #define SCREEN_RGB         1
  37 #define SCREEN_LVDS        2
  38 #define SCREEN_DUAL_LVDS   3
  39 #define SCREEN_MCU         4
  40 #define SCREEN_TVOUT       5
  41 #define SCREEN_HDMI        6
  42 #define SCREEN_MIPI        7
  43 #define SCREEN_DUAL_MIPI   8
  44 #define SCREEN_EDP         9
  45 #define SCREEN_TVOUT_TEST  10
  46 #define SCREEN_LVDS_10BIT        11
  47 #define SCREEN_DUAL_LVDS_10BIT   12
  48 #define SCREEN_DP               13
  49
  50 #define LVDS_8BIT_1     0
  51 #define LVDS_8BIT_2     1
  52 #define LVDS_8BIT_3     2
  53 #define LVDS_6BIT       3
  54 #define LVDS_10BIT_1    4
  55 #define LVDS_10BIT_2    5
  56
  57 /* x y mirror or rotate mode */
  58 #define NO_MIRROR       0
  59 #define X_MIRROR        1 /* up-down flip*/
  60 #define Y_MIRROR        2 /* left-right flip */
  61 #define X_Y_MIRROR      3 /* the same as rotate 180 degrees */
  62 #define ROTATE_90       4 /* clockwise rotate 90 degrees */
  63 #define ROTATE_180      8 /* rotate 180 degrees
  64                            * It is recommended to use X_Y_MIRROR
  65                            * rather than ROTATE_180
  66                            */
  67 #define ROTATE_270      12/* clockwise rotate 270 degrees */
  68
  69 #define COLOR_RGB               0
  70 #define COLOR_RGB_BT2020        1
  71 /* default colorspace is bt601 */
  72 #define COLOR_YCBCR             2
  73 #define COLOR_YCBCR_BT709       3
  74 #define COLOR_YCBCR_BT2020      4
  75
  76 #define IS_YUV_COLOR(x)                ((x) >= COLOR_YCBCR)
  77
  78 /* fb win map */
  79 #define FB_DEFAULT_ORDER                0
  80 #define FB0_WIN2_FB1_WIN1_FB2_WIN0      12
  81 #define FB0_WIN1_FB1_WIN2_FB2_WIN0      21
  82 #define FB0_WIN2_FB1_WIN0_FB2_WIN1      102
  83 #define FB0_WIN0_FB1_WIN2_FB2_WIN1      120
  84 #define FB0_WIN0_FB1_WIN1_FB2_WIN2      210
  85 #define FB0_WIN1_FB1_WIN0_FB2_WIN2      201
  86 #define FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3         3210
  87 #define FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC 43210
  88
  89 #define DISPLAY_POLICY_SDK      0
  90 #define DISPLAY_POLICY_BOX      1
  91
  92 /*              lvds connect config
  93  *
  94  *              LVDS_8BIT_1    LVDS_8BIT_2     LVDS_8BIT_3     LVDS_6BIT
  95 ----------------------------------------------------------------------
  96         TX0     R0              R2              R2              R0
  97         TX1     R1              R3              R3              R1
  98         TX2     R2              R4              R4              R2
  99 Y       TX3     R3              R5              R5              R3
 100 0       TX4     R4              R6              R6              R4
 101         TX6     R5              R7              R7              R5
 102         TX7     G0              G2              G2              G0
 103 ----------------------------------------------------------------------
 104         TX8     G1              G3              G3              G1
 105         TX9     G2              G4              G4              G2
 106 Y       TX12    G3              G5              G5              G3
 107 1       TX13    G4              G6              G6              G4
 108         TX14    G5              G7              G7              G5
 109         TX15    B0              B2              B2              B0
 110         TX18    B1              B3              B3              B1
 111 ----------------------------------------------------------------------
 112         TX19    B2              B4              B4              B2
 113         TX20    B3              B5              B5              B3
 114         TX21    B4              B6              B6              B4
 115 Y       TX22    B5              B7              B7              B5
 116 2       TX24    HSYNC           HSYNC           HSYNC           HSYNC
 117         TX25    VSYNC           VSYNC           VSYNC           VSYNC
 118         TX26    ENABLE          ENABLE          ENABLE          ENABLE
 119 ----------------------------------------------------------------------
 120         TX27    R6              R0              GND             GND
 121         TX5     R7              R1              GND             GND
 122         TX10    G6              G0              GND             GND
 123 Y       TX11    G7              G1              GND             GND
 124 3       TX16    B6              B0              GND             GND
 125         TX17    B7              B1              GND             GND
 126         TX23    RSVD            RSVD            RSVD            RSVD
 127 ----------------------------------------------------------------------
 128
 129  *              LVDS_10BIT_1    LVDS_10BIT_2
 130 ----------------------------------------------------------------------
 131         TX0     R0              R4
 132         TX1     R1              R5
 133         TX2     R2              R6
 134 Y       TX3     R3              R7
 135 0       TX4     R4              R8
 136         TX6     R5              R9
 137         TX7     G0              G4
 138 ----------------------------------------------------------------------
 139         TX8     G1              G5
 140         TX9     G2              G6
 141 Y       TX12    G3              G7
 142 1       TX13    G4              G8
 143         TX14    G5              G9
 144         TX15    B0              B4
 145         TX18    B1              B5
 146 ----------------------------------------------------------------------
 147         TX19    B2              B6
 148         TX20    B3              B7
 149         TX21    B4              B8
 150 Y       TX22    B5              B9
 151 2       TX24    HSYNC           HSYNC
 152         TX25    VSYNC           VSYNC
 153         TX26    ENABLE          ENABLE
 154 ----------------------------------------------------------------------
 155         TX27    R6              R2
 156         TX5     R7              R3
 157         TX10    G6              G2
 158 Y       TX11    G7              G3
 159 3       TX16    B6              B2
 160         TX17    B7              B3
 161         TX23    GND             GND
 162 ----------------------------------------------------------------------
 163         TX27    R8              R0
 164         TX5     R9              R1
 165         TX10    G8              G0
 166 Y       TX11    G9              G1
 167 4       TX16    B8              B0
 168         TX17    B9              B1
 169         TX23    GND             GND
 170 ------------------------------------------------------------------------
 171 */
 172
 173 #endif