2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
16 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
28 /* sclk gates (special clocks) */
29 #define SCLK_GPU_CORE 64
37 #define SCLK_SARADC 73
38 #define SCLK_NANDC0 75
44 #define SCLK_I2S_8CH 82
45 #define SCLK_SPDIF_8CH 83
46 #define SCLK_I2S_2CH 84
47 #define SCLK_TIMER00 85
48 #define SCLK_TIMER01 86
49 #define SCLK_TIMER02 87
50 #define SCLK_TIMER03 88
51 #define SCLK_TIMER04 89
52 #define SCLK_TIMER05 90
53 #define SCLK_OTGPHY0 93
54 #define SCLK_OTG_ADP 96
55 #define SCLK_HSICPHY480M 97
56 #define SCLK_HSICPHY12M 98
57 #define SCLK_MACREF 99
58 #define SCLK_VOP0_PWM 100
59 #define SCLK_MAC_RX 102
60 #define SCLK_MAC_TX 103
61 #define SCLK_EDP_24M 104
66 #define SCLK_HDMI_HDCP 109
67 #define SCLK_HDMI_CEC 110
68 #define SCLK_HEVC_CABAC 111
69 #define SCLK_HEVC_CORE 112
70 #define SCLK_I2S_8CH_OUT 113
71 #define SCLK_SDMMC_DRV 114
72 #define SCLK_SDIO0_DRV 115
73 #define SCLK_EMMC_DRV 117
74 #define SCLK_SDMMC_SAMPLE 118
75 #define SCLK_SDIO0_SAMPLE 119
76 #define SCLK_EMMC_SAMPLE 121
77 #define SCLK_USBPHY480M 122
78 #define SCLK_PVTM_CORE 123
79 #define SCLK_PVTM_GPU 124
80 #define SCLK_PVTM_PMU 125
83 #define SCLK_MACREF_OUT 128
84 #define SCLK_MIPIDSI_24M 129
85 #define SCLK_CRYPTO 130
86 #define SCLK_VIP_SRC 131
87 #define SCLK_VIP_OUT 132
88 #define SCLK_TIMER10 133
89 #define SCLK_TIMER11 134
90 #define SCLK_TIMER12 135
91 #define SCLK_TIMER13 136
92 #define SCLK_TIMER14 137
93 #define SCLK_TIMER15 138
94 #define SCLK_DDRCLK 139
97 #define MCLK_CRYPTO 191
100 #define ACLK_GPU_MEM 192
101 #define ACLK_GPU_CFG 193
102 #define ACLK_DMAC_BUS 194
103 #define ACLK_DMAC_PERI 195
104 #define ACLK_PERI_MMU 196
105 #define ACLK_GMAC 197
107 #define ACLK_VOP_IEP 199
109 #define ACLK_HDCP 201
111 #define ACLK_VIO0_NOC 203
114 #define ACLK_VIO1_NOC 206
115 #define ACLK_VIDEO 208
117 #define ACLK_PERI 210
120 #define PCLK_GPIO0 320
121 #define PCLK_GPIO1 321
122 #define PCLK_GPIO2 322
123 #define PCLK_GPIO3 323
124 #define PCLK_PMUGRF 324
125 #define PCLK_MAILBOX 325
127 #define PCLK_SGRF 330
129 #define PCLK_I2C0 332
130 #define PCLK_I2C1 333
131 #define PCLK_I2C2 334
132 #define PCLK_I2C3 335
133 #define PCLK_I2C4 336
134 #define PCLK_I2C5 337
135 #define PCLK_SPI0 338
136 #define PCLK_SPI1 339
137 #define PCLK_SPI2 340
138 #define PCLK_UART0 341
139 #define PCLK_UART1 342
140 #define PCLK_UART2 343
141 #define PCLK_UART3 344
142 #define PCLK_UART4 345
143 #define PCLK_TSADC 346
144 #define PCLK_SARADC 347
146 #define PCLK_GMAC 349
147 #define PCLK_PWM0 350
148 #define PCLK_PWM1 351
149 #define PCLK_TIMER0 353
150 #define PCLK_TIMER1 354
151 #define PCLK_EDP_CTRL 355
152 #define PCLK_MIPI_DSI0 356
153 #define PCLK_MIPI_CSI 358
154 #define PCLK_HDCP 359
155 #define PCLK_HDMI_CTRL 360
156 #define PCLK_VIO_H2P 361
158 #define PCLK_PERI 363
159 #define PCLK_DDRUPCTL 364
160 #define PCLK_DDRPHY 365
164 #define PCLK_DPHYRX 369
165 #define PCLK_DPHYTX0 370
166 #define PCLK_EFUSE256 371
167 #define PCLK_EFUSE1024 372
170 #define HCLK_USB_PERI 447
172 #define HCLK_OTG0 449
173 #define HCLK_HOST0 450
174 #define HCLK_HOST1 451
175 #define HCLK_HSIC 452
176 #define HCLK_NANDC0 453
178 #define HCLK_SDMMC 456
179 #define HCLK_SDIO0 457
180 #define HCLK_EMMC 459
181 #define HCLK_HSADC 460
182 #define HCLK_CRYPTO 461
183 #define HCLK_I2S_2CH 462
184 #define HCLK_I2S_8CH 463
185 #define HCLK_SPDIF 464
191 #define HCLK_VIO_AHB_ARBI 471
192 #define HCLK_VIO_NOC 472
194 #define HCLK_VIO_H2P 474
195 #define HCLK_VIO_HDCPMMU 475
196 #define HCLK_VIDEO 476
198 #define HCLK_PERI 478
200 #define CLK_NR_CLKS (HCLK_PERI + 1)
202 /* soft-reset indices */
203 #define SRST_CORE_B0 0
204 #define SRST_CORE_B1 1
205 #define SRST_CORE_B2 2
206 #define SRST_CORE_B3 3
207 #define SRST_CORE_B0_PO 4
208 #define SRST_CORE_B1_PO 5
209 #define SRST_CORE_B2_PO 6
210 #define SRST_CORE_B3_PO 7
213 #define SRST_PD_CORE_B_NIU 10
214 #define SRST_PDBUS_STRSYS 11
215 #define SRST_SOCDBG_B 14
216 #define SRST_CORE_B_DBG 15
218 #define SRST_DMAC1 18
219 #define SRST_INTMEM 19
221 #define SRST_SPDIF8CH 21
222 #define SRST_I2S8CH 23
223 #define SRST_MAILBOX 24
224 #define SRST_I2S2CH 25
225 #define SRST_EFUSE_256 26
226 #define SRST_MCU_SYS 28
227 #define SRST_MCU_PO 29
228 #define SRST_MCU_NOC 30
229 #define SRST_EFUSE 31
231 #define SRST_GPIO0 32
232 #define SRST_GPIO1 33
233 #define SRST_GPIO2 34
234 #define SRST_GPIO3 35
235 #define SRST_GPIO4 36
236 #define SRST_PMUGRF 41
244 #define SRST_DWPWM 48
245 #define SRST_MMC_PERI 49
246 #define SRST_PERIPH_MMU 50
249 #define SRST_PERIPH_AXI 57
250 #define SRST_PERIPH_AHB 58
251 #define SRST_PERIPH_APB 59
252 #define SRST_PERIPH_NIU 60
253 #define SRST_PDPERI_AHB_ARBI 61
255 #define SRST_USB_PERI 63
257 #define SRST_DMAC2 64
260 #define SRST_RKPWM 69
261 #define SRST_USBHOST0 72
263 #define SRST_HSIC_AUX 74
264 #define SRST_HSIC_PHY 75
265 #define SRST_HSADC 76
266 #define SRST_NANDC0 77
272 #define SRST_SARADC 87
273 #define SRST_PDALIVE_NIU 88
274 #define SRST_PDPMU_INTMEM 89
275 #define SRST_PDPMU_NIU 90
278 #define SRST_VIO_ARBI 96
279 #define SRST_RGA_NIU 97
280 #define SRST_VIO0_NIU_AXI 98
281 #define SRST_VIO_NIU_AHB 99
282 #define SRST_LCDC0_AXI 100
283 #define SRST_LCDC0_AHB 101
284 #define SRST_LCDC0_DCLK 102
286 #define SRST_RGA_CORE 105
287 #define SRST_IEP_AXI 106
288 #define SRST_IEP_AHB 107
289 #define SRST_RGA_AXI 108
290 #define SRST_RGA_AHB 109
292 #define SRST_EDP_24M 111
294 #define SRST_VIDEO_AXI 112
295 #define SRST_VIDEO_AHB 113
296 #define SRST_MIPIDPHYTX 114
297 #define SRST_MIPIDSI0 115
298 #define SRST_MIPIDPHYRX 116
299 #define SRST_MIPICSI 117
301 #define SRST_HDMI 121
303 #define SRST_PMU_PVTM 123
304 #define SRST_CORE_PVTM 124
305 #define SRST_GPU_PVTM 125
306 #define SRST_GPU_SYS 126
307 #define SRST_GPU_MEM_NIU 127
309 #define SRST_MMC0 128
310 #define SRST_SDIO0 129
311 #define SRST_EMMC 131
312 #define SRST_USBOTG_AHB 132
313 #define SRST_USBOTG_PHY 133
314 #define SRST_USBOTG_CON 134
315 #define SRST_USBHOST0_AHB 135
316 #define SRST_USBHOST0_PHY 136
317 #define SRST_USBHOST0_CON 137
318 #define SRST_USBOTG_UTMI 138
319 #define SRST_USBHOST1_UTMI 139
320 #define SRST_USB_ADP 141
322 #define SRST_CORESIGHT 144
323 #define SRST_PD_CORE_AHB_NOC 145
324 #define SRST_PD_CORE_APB_NOC 146
326 #define SRST_LCDC_PWM0 149
327 #define SRST_RGA_H2P_BRG 153
328 #define SRST_VIDEO 154
329 #define SRST_GPU_CFG_NIU 157
330 #define SRST_TSADC 159
332 #define SRST_DDRPHY0 160
333 #define SRST_DDRPHY0_APB 161
334 #define SRST_DDRCTRL0 162
335 #define SRST_DDRCTRL0_APB 163
336 #define SRST_VIDEO_NIU 165
337 #define SRST_VIDEO_NIU_AHB 167
338 #define SRST_DDRMSCH0 170
339 #define SRST_PDBUS_AHB 173
340 #define SRST_CRYPTO 174
342 #define SRST_UART0 179
343 #define SRST_UART1 180
344 #define SRST_UART2 181
345 #define SRST_UART3 182
346 #define SRST_UART4 183
347 #define SRST_SIMC 186
349 #define SRST_TSP_CLKIN0 189
351 #define SRST_CORE_L0 192
352 #define SRST_CORE_L1 193
353 #define SRST_CORE_L2 194
354 #define SRST_CORE_L3 195
355 #define SRST_CORE_L0_PO 195
356 #define SRST_CORE_L1_PO 197
357 #define SRST_CORE_L2_PO 198
358 #define SRST_CORE_L3_PO 199
359 #define SRST_L2_L 200
360 #define SRST_ADB_L 201
361 #define SRST_PD_CORE_L_NIU 202
362 #define SRST_CCI_SYS 203
363 #define SRST_CCI_DDR 204
365 #define SRST_SOCDBG_L 206
366 #define SRST_CORE_L_DBG 207
368 #define SRST_CORE_B0_NC 208
369 #define SRST_CORE_B0_PO_NC 209
370 #define SRST_L2_B_NC 210
371 #define SRST_ADB_B_NC 211
372 #define SRST_PD_CORE_B_NIU_NC 212
373 #define SRST_PDBUS_STRSYS_NC 213
374 #define SRST_CORE_L0_NC 214
375 #define SRST_CORE_L0_PO_NC 215
376 #define SRST_L2_L_NC 216
377 #define SRST_ADB_L_NC 217
378 #define SRST_PD_CORE_L_NIU_NC 218
379 #define SRST_CCI_SYS_NC 219
380 #define SRST_CCI_DDR_NC 220
381 #define SRST_CCI_NC 221
382 #define SRST_TRACE_NC 222
384 #define SRST_TIMER00 224
385 #define SRST_TIMER01 225
386 #define SRST_TIMER02 226
387 #define SRST_TIMER03 227
388 #define SRST_TIMER04 228
389 #define SRST_TIMER05 229
390 #define SRST_TIMER10 230
391 #define SRST_TIMER11 231
392 #define SRST_TIMER12 232
393 #define SRST_TIMER13 233
394 #define SRST_TIMER14 234
395 #define SRST_TIMER15 235
396 #define SRST_TIMER0_APB 236
397 #define SRST_TIMER1_APB 237