1 #ifndef __REG2_INFO_H__
\r
2 #define __REG2_INFO_H__
\r
5 //#include "chip_register.h"
\r
7 //#include "rga_struct.h"
\r
11 #define MIN(X, Y) ((X)<(Y)?(X):(Y))
\r
15 #define MAX(X, Y) ((X)>(Y)?(X):(Y))
\r
19 #define ABS(X) (((X) < 0) ? (-(X)) : (X))
\r
23 #define CLIP(x, a, b) ((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x))
\r
26 #define rRGA_SYS_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_SYS_CTRL_OFFSET ))
\r
27 #define rRGA_CMD_CTRL (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_CTRL_OFFSET ))
\r
28 #define rRGA_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_BASE_OFFSET ))
\r
29 #define rRGA_STATUS (*(volatile u32 *)(RGA2_BASE + RGA2_STATUS_OFFSET ))
\r
30 #define rRGA_INT (*(volatile u32 *)(RGA2_BASE + RGA2_INT_OFFSET ))
\r
31 #define rRGA_MMU_CTRL0 (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CTRL0_OFFSET ))
\r
32 #define rRGA_MMU_CMD_BASE (*(volatile u32 *)(RGA2_BASE + RGA2_MMU_CMD_BASE_OFFSET))
\r
33 #define rRGA_CMD_ADDR (*(volatile u32 *)(RGA2_BASE + RGA2_CMD_ADDR))
\r
36 #define m_RGA2_INT_ALL_CMD_DONE_INT_EN ( 1<<10 )
\r
37 #define m_RGA2_INT_MMU_INT_EN ( 1<<9 )
\r
38 #define m_RGA2_INT_ERROR_INT_EN ( 1<<8 )
\r
39 #define m_RGA2_INT_NOW_CMD_DONE_INT_CLEAR ( 1<<7 )
\r
40 #define m_RGA2_INT_ALL_CMD_DONE_INT_CLEAR ( 1<<6 )
\r
41 #define m_RGA2_INT_MMU_INT_CLEAR ( 1<<5 )
\r
42 #define m_RGA2_INT_ERROR_INT_CLEAR ( 1<<4 )
\r
43 #define m_RGA2_INT_CUR_CMD_DONE_INT_FLAG ( 1<<3 )
\r
44 #define m_RGA2_INT_ALL_CMD_DONE_INT_FLAG ( 1<<2 )
\r
45 #define m_RGA2_INT_MMU_INT_FLAG ( 1<<1 )
\r
46 #define m_RGA2_INT_ERROR_INT_FLAG ( 1<<0 )
\r
48 #define s_RGA2_INT_ALL_CMD_DONE_INT_EN(x) ( (x&0x1)<<10 )
\r
49 #define s_RGA2_INT_MMU_INT_EN(x) ( (x&0x1)<<9 )
\r
50 #define s_RGA2_INT_ERROR_INT_EN(x) ( (x&0x1)<<8 )
\r
51 #define s_RGA2_INT_NOW_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<7 )
\r
52 #define s_RGA2_INT_ALL_CMD_DONE_INT_CLEAR(x) ( (x&0x1)<<6 )
\r
53 #define s_RGA2_INT_MMU_INT_CLEAR(x) ( (x&0x1)<<5 )
\r
54 #define s_RGA2_INT_ERROR_INT_CLEAR(x) ( (x&0x1)<<4 )
\r
59 #define m_RGA2_MODE_CTRL_SW_RENDER_MODE ( 0x7<<0 )
\r
60 #define m_RGA2_MODE_CTRL_SW_BITBLT_MODE ( 0x1<<3 )
\r
61 #define m_RGA2_MODE_CTRL_SW_CF_ROP4_PAT ( 0x1<<4 )
\r
62 #define m_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET ( 0x1<<5 )
\r
63 #define m_RGA2_MODE_CTRL_SW_GRADIENT_SAT ( 0x1<<6 )
\r
64 #define m_RGA2_MODE_CTRL_SW_INTR_CF_E ( 0x1<<7 )
\r
66 #define s_RGA2_MODE_CTRL_SW_RENDER_MODE(x) ( (x&0x7)<<0 )
\r
67 #define s_RGA2_MODE_CTRL_SW_BITBLT_MODE(x) ( (x&0x1)<<3 )
\r
68 #define s_RGA2_MODE_CTRL_SW_CF_ROP4_PAT(x) ( (x&0x1)<<4 )
\r
69 #define s_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET(x) ( (x&0x1)<<5 )
\r
70 #define s_RGA2_MODE_CTRL_SW_GRADIENT_SAT(x) ( (x&0x1)<<6 )
\r
71 #define s_RGA2_MODE_CTRL_SW_INTR_CF_E(x) ( (x&0x1)<<7 )
\r
74 #define m_RGA2_SRC_INFO_SW_SRC_FMT ( 0xf<<0 )
\r
75 #define m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP ( 0x1<<4 )
\r
76 #define m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP ( 0x1<<5 )
\r
77 #define m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP ( 0x1<<6 )
\r
78 #define m_RGA2_SRC_INFO_SW_SW_CP_ENDAIN ( 0x1<<7 )
\r
79 #define m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE ( 0x3<<8 )
\r
80 #define m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE ( 0x3<<10 )
\r
81 #define m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE ( 0x3<<12 )
\r
82 #define m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE ( 0x3<<14 )
\r
83 #define m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE ( 0x3<<16 )
\r
84 #define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE ( 0x1<<18 )
\r
85 #define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E ( 0xf<<19 )
\r
86 #define m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E ( 0x1<<23 )
\r
87 #define m_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER ( 0x3<<24 )
\r
88 #define m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL ( 0x1<<26 )
\r
92 #define s_RGA2_SRC_INFO_SW_SRC_FMT(x) ( (x&0xf)<<0 )
\r
93 #define s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(x) ( (x&0x1)<<4 )
\r
94 #define s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(x) ( (x&0x1)<<5 )
\r
95 #define s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(x) ( (x&0x1)<<6 )
\r
96 #define s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(x) ( (x&0x1)<<7 )
\r
97 #define s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(x) ( (x&0x3)<<8 )
\r
98 #define s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(x) ( (x&0x3)<<10 )
\r
99 #define s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE(x) ( (x&0x3)<<12 )
\r
100 #define s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE(x) ( (x&0x3)<<14 )
\r
101 #define s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE(x) ( (x&0x3)<<16 )
\r
103 #define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE(x) ( (x&0x1)<<18 )
\r
104 #define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(x) ( (x&0xf)<<19 )
\r
105 #define s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E(x) ( (x&0x1)<<23 )
\r
106 #define s_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER(x) ( (x&0x3)<<24 )
\r
107 #define s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL(x) ( (x&0x1)<<26 )
\r
110 /* RGA_SRC_VIR_INFO */
\r
111 #define m_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE ( 0x7fff<<0 ) //modify
\r
112 #define m_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE ( 0x3ff<<16 ) //modify
\r
114 #define s_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE(x) ( (x&0x7fff)<<0 ) //modify
\r
115 #define s_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE(x) ( (x&0x3ff)<<16 ) //modify
\r
118 /* RGA_SRC_ACT_INFO */
\r
119 #define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH ( 0x1fff<<0 )
\r
120 #define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT ( 0x1fff<<16 )
\r
122 #define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH(x) ( (x&0x1fff)<<0 )
\r
123 #define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT(x) ( (x&0x1fff<)<16 )
\r
127 #define m_RGA2_DST_INFO_SW_DST_FMT ( 0xf<<0 )
\r
128 #define m_RGA2_DST_INFO_SW_DST_RB_SWAP ( 0x1<<4 )
\r
129 #define m_RGA2_DST_INFO_SW_ALPHA_SWAP ( 0x1<<5 )
\r
130 #define m_RGA2_DST_INFO_SW_DST_UV_SWAP ( 0x1<<6 )
\r
131 #define m_RGA2_DST_INFO_SW_SRC1_FMT ( 0x7<<7 )
\r
132 #define m_RGA2_DST_INFO_SW_SRC1_RB_SWP ( 0x1<<10)
\r
133 #define m_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP ( 0x1<<11)
\r
134 #define m_RGA2_DST_INFO_SW_DITHER_UP_E ( 0x1<<12)
\r
135 #define m_RGA2_DST_INFO_SW_DITHER_DOWN_E ( 0x1<<13)
\r
136 #define m_RGA2_DST_INFO_SW_DITHER_MODE ( 0x3<<14)
\r
137 #define m_RGA2_DST_INFO_SW_DST_CSC_MODE ( 0x3<<16) //add
\r
138 #define m_RGA2_DST_INFO_SW_CSC_CLIP_MODE ( 0x1<<18)
\r
140 #define s_RGA2_DST_INFO_SW_DST_FMT(x) ( (x&0xf)<<0 )
\r
141 #define s_RGA2_DST_INFO_SW_DST_RB_SWAP(x) ( (x&0x1)<<4 )
\r
142 #define s_RGA2_DST_INFO_SW_ALPHA_SWAP(x) ( (x&0x1)<<5 )
\r
143 #define s_RGA2_DST_INFO_SW_DST_UV_SWAP(x) ( (x&0x1)<<6 )
\r
144 #define s_RGA2_DST_INFO_SW_SRC1_FMT(x) ( (x&0x7)<<7 )
\r
145 #define s_RGA2_DST_INFO_SW_SRC1_RB_SWP(x) ( (x&0x1)<<10)
\r
146 #define s_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP(x) ( (x&0x1)<<11)
\r
147 #define s_RGA2_DST_INFO_SW_DITHER_UP_E(x) ( (x&0x1)<<12)
\r
148 #define s_RGA2_DST_INFO_SW_DITHER_DOWN_E(x) ( (x&0x1)<<13)
\r
149 #define s_RGA2_DST_INFO_SW_DITHER_MODE(x) ( (x&0x3)<<14)
\r
150 #define s_RGA2_DST_INFO_SW_DST_CSC_MODE(x) ( (x&0x3)<<16) //add
\r
151 #define s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(x) ( (x&0x1)<<18)
\r
154 /* RGA_ALPHA_CTRL0 */
\r
155 #define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0 ( 0x1<<0 )
\r
156 #define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL ( 0x1<<1 )
\r
157 #define m_RGA2_ALPHA_CTRL0_SW_ROP_MODE ( 0x3<<2 )
\r
158 #define m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA ( 0xff<<4 )
\r
159 #define m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA ( 0xff<<12 )
\r
160 #define m_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN ( 0x1<<20 ) //add
\r
162 #define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(x) ( (x&0x1)<<0 )
\r
163 #define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL(x) ( (x&0x1)<<1 )
\r
164 #define s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(x) ( (x&0x3)<<2 )
\r
165 #define s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA(x) ( (x&0xff)<<4 )
\r
166 #define s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA(x) ( (x&0xff)<<12 )
\r
167 #define s_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN(x) ( (x&0x1)<<20 ) //add
\r
171 /* RGA_ALPHA_CTRL1 */
\r
172 #define m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0 ( 0x1<<0 )
\r
173 #define m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0 ( 0x1<<1 )
\r
174 #define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0 ( 0x7<<2 )
\r
175 #define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0 ( 0x7<<5 )
\r
176 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0 ( 0x1<<8 )
\r
177 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0 ( 0x1<<9 )
\r
178 #define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0 ( 0x3<<10)
\r
179 #define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0 ( 0x3<<12)
\r
180 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0 ( 0x1<<14)
\r
181 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0 ( 0x1<<15)
\r
182 #define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1 ( 0x7<<16)
\r
183 #define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1 ( 0x7<<19)
\r
184 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1 ( 0x1<<22)
\r
185 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1 ( 0x1<<23)
\r
186 #define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1 ( 0x3<<24)
\r
187 #define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1 ( 0x3<<26)
\r
188 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1 ( 0x1<<28)
\r
189 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1 ( 0x1<<29)
\r
191 #define s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0(x) ( (x&0x1)<<0 )
\r
192 #define s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0(x) ( (x&0x1)<<1 )
\r
193 #define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0(x) ( (x&0x7)<<2 )
\r
194 #define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0(x) ( (x&0x7)<<5 )
\r
195 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0(x) ( (x&0x1)<<8 )
\r
196 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0(x) ( (x&0x1)<<9 )
\r
197 #define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(x) ( (x&0x3)<<10)
\r
198 #define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0(x) ( (x&0x3)<<12)
\r
199 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0(x) ( (x&0x1)<<14)
\r
200 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0(x) ( (x&0x1)<<15)
\r
201 #define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1(x) ( (x&0x7)<<16)
\r
202 #define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1(x) ( (x&0x7)<<19)
\r
203 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1(x) ( (x&0x1)<<22)
\r
204 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1(x) ( (x&0x1)<<23)
\r
205 #define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(x) ( (x&0x3)<<24)
\r
206 #define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(x) ( (x&0x3)<<26)
\r
207 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(x) ( (x&0x1)<<28)
\r
208 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(x) ( (x&0x1)<<29)
\r
212 /* RGA_MMU_CTRL1 */
\r
213 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_EN ( 0x1<<0 )
\r
214 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH ( 0x1<<1 )
\r
215 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN ( 0x1<<2 )
\r
216 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR ( 0x1<<3 )
\r
217 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN ( 0x1<<4 )
\r
218 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH ( 0x1<<5 )
\r
219 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN ( 0x1<<6 )
\r
220 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR ( 0x1<<7 )
\r
221 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_EN ( 0x1<<8 )
\r
222 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH ( 0x1<<9 )
\r
223 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN ( 0x1<<10 )
\r
224 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR ( 0x1<<11 )
\r
225 #define m_RGA2_MMU_CTRL1_SW_ELS_MMU_EN ( 0x1<<12 )
\r
226 #define m_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH ( 0x1<<13 )
\r
228 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_EN(x) ( (x&0x1)<<0 )
\r
229 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH(x) ( (x&0x1)<<1 )
\r
230 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN(x) ( (x&0x1)<<2 )
\r
231 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR(x) ( (x&0x1)<<3 )
\r
232 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN(x) ( (x&0x1)<<4 )
\r
233 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH(x) ( (x&0x1)<<5 )
\r
234 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN(x) ( (x&0x1)<<6 )
\r
235 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR(x) ( (x&0x1)<<7 )
\r
236 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_EN(x) ( (x&0x1)<<8 )
\r
237 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH(x) ( (x&0x1)<<9 )
\r
238 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN(x) ( (x&0x1)<<10 )
\r
239 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR(x) ( (x&0x1)<<11 )
\r
240 #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_EN(x) ( (x&0x1)<<12 )
\r
241 #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH(x) ( (x&0x1)<<13 )
\r
244 #define RGA2_SYS_CTRL_OFFSET 0x0
\r
245 #define RGA2_CMD_CTRL_OFFSET 0x4
\r
246 #define RGA2_CMD_BASE_OFFSET 0x8
\r
247 #define RGA2_STATUS_OFFSET 0xc
\r
248 #define RGA2_INT_OFFSET 0x10
\r
249 #define RGA2_MMU_CTRL0_OFFSET 0x14
\r
250 #define RGA2_MMU_CMD_BASE_OFFSET 0x18
\r
252 #define RGA2_MODE_CTRL_OFFSET 0x00
\r
253 #define RGA2_SRC_INFO_OFFSET 0x04
\r
254 #define RGA2_SRC_BASE0_OFFSET 0x08
\r
255 #define RGA2_SRC_BASE1_OFFSET 0x0c
\r
256 #define RGA2_SRC_BASE2_OFFSET 0x10
\r
257 #define RGA2_SRC_BASE3_OFFSET 0x14
\r
258 #define RGA2_SRC_VIR_INFO_OFFSET 0x18
\r
259 #define RGA2_SRC_ACT_INFO_OFFSET 0x1c
\r
260 #define RGA2_SRC_X_FACTOR_OFFSET 0x20
\r
261 #define RGA2_SRC_Y_FACTOR_OFFSET 0x24
\r
262 #define RGA2_SRC_BG_COLOR_OFFSET 0x28
\r
263 #define RGA2_SRC_FG_COLOR_OFFSET 0x2c
\r
264 #define RGA2_SRC_TR_COLOR0_OFFSET 0x30
\r
265 #define RGA2_CF_GR_A_OFFSET 0x30 // repeat
\r
266 #define RGA2_SRC_TR_COLOR1_OFFSET 0x34
\r
267 #define RGA2_CF_GR_B_OFFSET 0x34 // repeat
\r
268 #define RGA2_DST_INFO_OFFSET 0x38
\r
269 #define RGA2_DST_BASE0_OFFSET 0x3c
\r
270 #define RGA2_DST_BASE1_OFFSET 0x40
\r
271 #define RGA2_DST_BASE2_OFFSET 0x44
\r
272 #define RGA2_DST_VIR_INFO_OFFSET 0x48
\r
273 #define RGA2_DST_ACT_INFO_OFFSET 0x4c
\r
274 #define RGA2_ALPHA_CTRL0_OFFSET 0x50
\r
275 #define RGA2_ALPHA_CTRL1_OFFSET 0x54
\r
276 #define RGA2_FADING_CTRL_OFFSET 0x58
\r
277 #define RGA2_PAT_CON_OFFSET 0x5c
\r
278 #define RGA2_ROP_CTRL0_OFFSET 0x60
\r
279 #define RGA2_CF_GR_G_OFFSET 0x60 // repeat
\r
280 #define RGA2_ROP_CTRL1_OFFSET 0x64
\r
281 #define RGA2_CF_GR_R_OFFSET 0x64 // repeat
\r
282 #define RGA2_MASK_BASE_OFFSET 0x68
\r
283 #define RGA2_MMU_CTRL1_OFFSET 0x6c
\r
284 #define RGA2_MMU_SRC_BASE_OFFSET 0x70
\r
285 #define RGA2_MMU_SRC1_BASE_OFFSET 0x74
\r
286 #define RGA2_MMU_DST_BASE_OFFSET 0x78
\r
287 #define RGA2_MMU_ELS_BASE_OFFSET 0x7c
\r
289 int RGA2_gen_reg_info(unsigned char *base, struct rga2_req *msg);
\r
290 void RGA_MSG_2_RGA2_MSG(struct rga_req *req_rga, struct rga2_req *req);
\r
291 void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req);
\r
projects / firefly-linux-kernel-4.4.55.git / blob