1 #ifndef _RGA_DRIVER_H_
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2 #define _RGA_DRIVER_H_
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4 #include <linux/mutex.h>
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5 #include <linux/scatterlist.h>
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9 #define RGA_BLIT_SYNC 0x5017
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10 #define RGA_BLIT_ASYNC 0x5018
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11 #define RGA_FLUSH 0x5019
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12 #define RGA_GET_RESULT 0x501a
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13 #define RGA_GET_VERSION 0x501b
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15 #define RGA2_BLIT_SYNC 0x6017
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16 #define RGA2_BLIT_ASYNC 0x6018
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17 #define RGA2_FLUSH 0x6019
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18 #define RGA2_GET_RESULT 0x601a
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19 #define RGA2_GET_VERSION 0x601b
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22 #define RGA2_REG_CTRL_LEN 0x8 /* 8 */
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23 #define RGA2_REG_CMD_LEN 0x20 /* 32 */
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24 #define RGA2_CMD_BUF_SIZE 0x700 /* 16*28*4 */
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26 #define RGA2_OUT_OF_RESOURCES -10
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27 #define RGA2_MALLOC_ERROR -11
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29 #define SCALE_DOWN_LARGE 1
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31 #define rgaIS_ERROR(status) (status < 0)
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32 #define rgaNO_ERROR(status) (status >= 0)
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33 #define rgaIS_SUCCESS(status) (status == 0)
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35 /* RGA2 process mode enum */
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39 color_palette_mode = 0x1,
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40 color_fill_mode = 0x2,
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41 update_palette_table_mode = 0x3,
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42 update_patten_buff_mode = 0x4,
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49 }; //bitblt_mode select
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53 rop_enable_mask = 0x2,
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54 dither_enable_mask = 0x8,
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55 fading_enable_mask = 0x10,
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56 PD_enbale_mask = 0x20,
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62 // Alpha Red Green Blue
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63 { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888
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64 { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888
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65 { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888
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66 { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888
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67 { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565
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68 { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551
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69 { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444
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70 { 2, 16, {{ 0, 0, 5, 0 11, 5, 16,11}}, GGL_BGR }, // RK_FORMAT_BGR_565
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71 { 2, 16, {{ 1, 0, 6, 1, 11, 6, 16,11}}, GGL_BGRA }, // RK_FORMAT_BGRA_5551
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72 { 2, 16, {{ 4, 0, 8, 4, 12, 8, 16,12}}, GGL_BGRA }, // RK_FORMAT_BGRA_4444
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77 RGA2_FORMAT_RGBA_8888 = 0x0,
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78 RGA2_FORMAT_RGBX_8888 = 0x1,
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79 RGA2_FORMAT_RGB_888 = 0x2,
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80 RGA2_FORMAT_BGRA_8888 = 0x3,
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81 RGA2_FORMAT_BGRX_8888 = 0x4,
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82 RGA2_FORMAT_BGR_888 = 0x5,
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83 RGA2_FORMAT_RGB_565 = 0x6,
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84 RGA2_FORMAT_RGBA_5551 = 0x7,
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85 RGA2_FORMAT_RGBA_4444 = 0x8,
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86 RGA2_FORMAT_BGR_565 = 0x9,
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87 RGA2_FORMAT_BGRA_5551 = 0xa,
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88 RGA2_FORMAT_BGRA_4444 = 0xb,
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90 RGA2_FORMAT_YCbCr_422_SP = 0x10,
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91 RGA2_FORMAT_YCbCr_422_P = 0x11,
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92 RGA2_FORMAT_YCbCr_420_SP = 0x12,
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93 RGA2_FORMAT_YCbCr_420_P = 0x13,
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94 RGA2_FORMAT_YCrCb_422_SP = 0x14,
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95 RGA2_FORMAT_YCrCb_422_P = 0x15,
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96 RGA2_FORMAT_YCrCb_420_SP = 0x16,
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97 RGA2_FORMAT_YCrCb_420_P = 0x17,
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100 typedef struct mdp_img
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109 typedef struct mdp_img_act
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111 u16 width; // width
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112 u16 height; // height
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113 s16 x_off; // x offset for the vir
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114 s16 y_off; // y offset for the vir
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120 typedef struct mdp_img_vir
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132 typedef struct MMU_INFO
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134 u32 src0_base_addr;
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135 u32 src1_base_addr;
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139 u8 src0_mmu_flag; /* [0] src0 mmu enable [1] src0_flush [2] src0_prefetch_en [3] src0_prefetch dir */
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140 u8 src1_mmu_flag; /* [0] src1 mmu enable [1] src1_flush [2] src1_prefetch_en [3] src1_prefetch dir */
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141 u8 dst_mmu_flag; /* [0] dst mmu enable [1] dst_flush [2] dst_prefetch_en [3] dst_prefetch dir */
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142 u8 els_mmu_flag; /* [0] els mmu enable [1] els_flush [2] els_prefetch_en [3] els_prefetch dir */
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153 MMU_FLUSH_DIS = 0x0,
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163 MMU_PRE_DIR_FORW = 0x0,
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164 MMU_PRE_DIR_BACK = 0x8
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166 typedef struct COLOR_FILL
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181 ALPHA_ORIGINAL = 0x0,
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189 R2_MASKNOTPEN = 0x0a,
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191 R2_MASKPENNOT = 0x50,
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192 R2_MERGENOTPEN = 0xaf,
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193 R2_MERGEPEN = 0xfa,
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194 R2_MERGEPENNOT = 0xf5,
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197 R2_NOTCOPYPEN = 0x0f,
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198 R2_NOTMASKPEN = 0x5f,
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199 R2_NOTMERGEPEN = 0x05,
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200 R2_NOTXORPEN = 0xa5,
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206 /***************************************/
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207 /* porting from rga.h for msg convert */
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208 /***************************************/
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210 typedef struct FADING
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221 unsigned char mmu_en;
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222 uint32_t base_addr;
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223 uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/
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227 typedef struct RECT
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229 unsigned short xmin;
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230 unsigned short xmax; // width - 1
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231 unsigned short ymin;
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232 unsigned short ymax; // height - 1
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235 typedef struct POINT
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242 typedef struct line_draw_t
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244 POINT start_point; /* LineDraw_start_point */
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245 POINT end_point; /* LineDraw_end_point */
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246 uint32_t color; /* LineDraw_color */
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247 uint32_t flag; /* (enum) LineDrawing mode sel */
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248 uint32_t line_width; /* range 1~16 */
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252 typedef struct rga_img_info_t
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254 unsigned int yrgb_addr; /* yrgb mem addr */
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255 unsigned int uv_addr; /* cb/cr mem addr */
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256 unsigned int v_addr; /* cr mem addr */
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257 unsigned int format; //definition by RK_FORMAT
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259 unsigned short act_w;
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260 unsigned short act_h;
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261 unsigned short x_offset;
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262 unsigned short y_offset;
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264 unsigned short vir_w;
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265 unsigned short vir_h;
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267 unsigned short endian_mode; //for BPP
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268 unsigned short alpha_swap;
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270 //unsigned short uv_x_off;
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271 //unsigned short uv_y_off;
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276 uint8_t render_mode; /* (enum) process mode sel */
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278 rga_img_info_t src; /* src image info */
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279 rga_img_info_t dst; /* dst image info */
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280 rga_img_info_t pat; /* patten image info */
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282 uint32_t rop_mask_addr; /* rop4 mask addr */
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283 uint32_t LUT_addr; /* LUT addr */
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285 RECT clip; /* dst clip window default value is dst_vir */
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286 /* value from [0, w-1] / [0, h-1]*/
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288 int32_t sina; /* dst angle default value 0 16.16 scan from table */
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289 int32_t cosa; /* dst angle default value 0 16.16 scan from table */
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291 uint16_t alpha_rop_flag; /* alpha rop process flag */
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292 /* ([0] = 1 alpha_rop_enable) */
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293 /* ([1] = 1 rop enable) */
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294 /* ([2] = 1 fading_enable) */
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295 /* ([3] = 1 PD_enable) */
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296 /* ([4] = 1 alpha cal_mode_sel) */
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297 /* ([5] = 1 dither_enable) */
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298 /* ([6] = 1 gradient fill mode sel) */
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299 /* ([7] = 1 AA_enable) */
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301 uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
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303 uint32_t color_key_max; /* color key max */
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304 uint32_t color_key_min; /* color key min */
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306 uint32_t fg_color; /* foreground color */
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307 uint32_t bg_color; /* background color */
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309 COLOR_FILL gr_color; /* color fill use gradient */
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311 line_draw_t line_draw_info;
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315 uint8_t PD_mode; /* porter duff alpha mode sel */
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317 uint8_t alpha_global_value; /* global alpha value */
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319 uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
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321 uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
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323 uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
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325 uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
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327 uint8_t endian_mode; /* 0/big endian 1/little endian*/
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329 uint8_t rotate_mode; /* (enum) rotate mode */
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330 /* 0x0, no rotate */
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332 /* 0x2, x_mirror */
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333 /* 0x3, y_mirror */
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335 uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
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337 MMU mmu_info; /* mmu information */
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339 uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
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340 /* ([2~3] rop mode) */
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341 /* ([4] zero mode en) */
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342 /* ([5] dst alpha mode) */
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343 /* ([6] alpha output mode sel) 0 src / 1 dst*/
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345 uint8_t src_trans_mode;
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352 u8 render_mode; /* (enum) process mode sel */
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354 rga_img_info_t src; // src active window
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355 rga_img_info_t src1; // src1 active window
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356 rga_img_info_t dst; // dst active window
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357 rga_img_info_t pat; // patten active window
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359 u32 rop_mask_addr; // rop4 mask addr
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360 u32 LUT_addr; // LUT addr
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362 u32 rop_mask_stride;
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364 u8 bitblt_mode; /* 0: SRC + DST => DST */
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365 /* 1: SRC + SRC1 => DST */
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367 u8 rotate_mode; /* [1:0] */
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369 /* 90 degree 0x1 */
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370 /* 180 degree 0x2 */
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371 /* 270 degree 0x3 */
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376 /* x_mirror + y_mirror 0x3 */
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378 u16 alpha_rop_flag; /* alpha rop process flag */
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379 /* ([0] = 1 alpha_rop_enable) */
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380 /* ([1] = 1 rop enable) */
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381 /* ([2] = 1 fading_enable) */
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382 /* ([3] = 1 alpha cal_mode_sel) */
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383 /* ([4] = 1 src_dither_up_enable) */
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384 /* ([5] = 1 dst_dither_up_enable) */
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385 /* ([6] = 1 dither_down_enable) */
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386 /* ([7] = 1 gradient fill mode sel) */
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389 u16 alpha_mode_0; /* [0] SrcAlphaMode0 */
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390 /* [2:1] SrcGlobalAlphaMode0 */
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391 /* [3] SrcAlphaSelectMode0 */
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392 /* [6:4] SrcFactorMode0 */
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393 /* [7] SrcColorMode */
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395 /* [8] DstAlphaMode0 */
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396 /* [10:9] DstGlobalAlphaMode0 */
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397 /* [11] DstAlphaSelectMode0 */
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398 /* [14:12] DstFactorMode0 */
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399 /* [15] DstColorMode0 */
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401 u16 alpha_mode_1; /* [0] SrcAlphaMode1 */
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402 /* [2:1] SrcGlobalAlphaMode1 */
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403 /* [3] SrcAlphaSelectMode1 */
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404 /* [6:4] SrcFactorMode1 */
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406 /* [8] DstAlphaMode1 */
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407 /* [10:9] DstGlobalAlphaMode1 */
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408 /* [11] DstAlphaSelectMode1 */
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409 /* [14:12] DstFactorMode1 */
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411 u8 scale_bicu_mode; /* 0 1 2 3 */
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413 u32 color_key_max; /* color key max */
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414 u32 color_key_min; /* color key min */
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416 u32 fg_color; /* foreground color */
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417 u32 bg_color; /* background color */
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419 u8 color_fill_mode;
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420 COLOR_FILL gr_color; /* color fill use gradient */
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422 u8 fading_alpha_value; /* Fading value */
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427 u8 src_a_global_val; /* src global alpha value */
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428 u8 dst_a_global_val; /* dst global alpha value */
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432 u16 rop_code; /* rop2/3/4 code */
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434 u8 palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
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436 u8 yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
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438 u8 endian_mode; /* 0/little endian 1/big endian */
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440 u8 CMD_fin_int_enable;
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442 MMU_INFO mmu_info; /* mmu infomation */
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452 struct sg_table *sg_src0;
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453 struct sg_table *sg_src1;
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454 struct sg_table *sg_dst;
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455 struct sg_table *sg_els;
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458 struct rga2_mmu_buf_t {
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464 unsigned int *buf_virtual;
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467 //add for FPGA test ,by hxx & luj
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471 BB_ROTATE_OFF = 0x0, /* no rotate */
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472 BB_ROTATE_90 = 0x1, /* rotate 90 */
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473 BB_ROTATE_180 = 0x2, /* rotate 180 */
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474 BB_ROTATE_270 = 0x3, /* rotate 270 */
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479 BB_MIRROR_OFF = (0x0 << 4), /* no mirror */
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480 BB_MIRROR_X = (0x1 << 4), /* x mirror */
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481 BB_MIRROR_Y = (0x2 << 4), /* y mirror */
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482 BB_MIRROR_XY = (0x3 << 4), /* xy mirror */
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487 BB_COPY_USE_TILE = (0x1 << 6), /* bitblt mode copy but use Tile mode */
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493 BT_601_RANGE0 = 0x1,
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494 BT_601_RANGE1 = 0x2,
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495 BT_709_RANGE0 = 0x3,
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496 }; /*yuv2rgb_mode*/
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500 BPP1 = 0x0, /* BPP1 */
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501 BPP2 = 0x1, /* BPP2 */
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502 BPP4 = 0x2, /* BPP4 */
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503 BPP8 = 0x3 /* BPP8 */
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504 }; /*palette_mode*/
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508 SOLID_COLOR = 0x0, //color fill mode; ROP4: SOLID_rop4_mask_addr COLOR
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509 PATTERN_COLOR = 0x1 //pattern_fill_mode;ROP4:PATTERN_COLOR
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510 }; /*color fill mode*/
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514 COLOR_FILL_CLIP = 0x0,
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515 COLOR_FILL_NOT_CLIP = 0x1
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524 }; /*bicubic coefficient*/
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536 LITTLE_ENDIAN = 0x1
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541 MMU_TABLE_4KB = 0x0,
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542 MMU_TABLE_64KB = 0x1,
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543 }; /*MMU table size*/
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551 }; /*dither down mode*/
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556 * struct for process session which connect to rga
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558 * @author ZhangShengqin (2012-2-15)
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560 typedef struct rga2_session {
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561 /* a linked list of data so we can access them for debugging */
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562 struct list_head list_session;
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563 /* a linked list of register data waiting for process */
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564 struct list_head waiting;
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565 /* a linked list of register data in processing */
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566 struct list_head running;
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567 /* all coommand this thread done */
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569 wait_queue_head_t wait;
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571 atomic_t task_running;
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576 rga2_session *session;
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577 struct list_head session_link; /* link to rga service session */
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578 struct list_head status_link; /* link to register set list */
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579 uint32_t sys_reg[8];
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580 uint32_t cmd_reg[32];
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582 uint32_t *MMU_base;
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584 //atomic_t int_enable;
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586 //struct rga_req req;
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591 struct rga2_service_info {
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593 struct timer_list timer; /* timer for power off */
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594 struct list_head waiting; /* link to link_reg in struct vpu_reg */
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595 struct list_head running; /* link to link_reg in struct vpu_reg */
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596 struct list_head done; /* link to link_reg in struct vpu_reg */
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597 struct list_head session; /* link to list_session in struct vpu_session */
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598 atomic_t total_running;
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600 struct rga2_reg *reg;
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602 uint32_t cmd_buff[32*8];/* cmd_buff for rga */
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603 uint32_t *pre_scale_buf;
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604 atomic_t int_disable; /* 0 int enable 1 int disable */
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606 atomic_t src_format_swt;
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607 int last_prc_src_format;
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608 atomic_t rga_working;
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611 //struct rga_req req[10];
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613 struct mutex mutex; // mutex
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616 #define RGA2_TEST_CASE 0
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617 #define RGA2_TEST 0
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618 #define RGA2_TEST_MSG 0
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619 #define RGA2_TEST_TIME 0
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621 //General Registers
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622 #define RGA2_SYS_CTRL 0x000
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623 #define RGA2_CMD_CTRL 0x004
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624 #define RGA2_CMD_BASE 0x008
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625 #define RGA2_STATUS 0x00c
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626 #define RGA2_INT 0x010
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627 #define RGA2_MMU_CTRL0 0x018
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628 #define RGA2_MMU_CMD_BASE 0x01c
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630 //Command code start
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631 #define RGA2_MODE_CTRL 0x100
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632 #define RGA_BLIT_COMPLETE_EVENT 1
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634 long rga_ioctl_kernel(struct rga_req *req);
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637 #endif /*_RK29_IPP_DRIVER_H_*/
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