drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 static struct rk_lcdc_win lcdc_win[] = {
  54         [0] = {
  55                .name = "win0",
  56                .id = 0,
  57                .support_3d = false,
  58                },
  59         [1] = {
  60                .name = "win1",
  61                .id = 1,
  62                .support_3d = false,
  63                },
  64         [2] = {
  65                .name = "win2",
  66                .id = 2,
  67                .support_3d = false,
  68                },
  69         [3] = {
  70                .name = "win3",
  71                .id = 3,
  72                .support_3d = false,
  73                },
  74         [4] = {
  75                .name = "hwc",
  76                .id = 4,
  77                .support_3d = false,
  78                }
  79 };
  80
  81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  82
  83 /*#define WAIT_FOR_SYNC 1*/
  84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  85 {
  86         u32 vscalednmult;
  87
  88         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  89                 vscalednmult = 4;
  90         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  91                 vscalednmult = 2;
  92         else
  93                 vscalednmult = 1;
  94
  95         return vscalednmult;
  96 }
  97
  98 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
  99 {
 100         int i;
 101         int __iomem *c;
 102         u32 v;
 103         struct lcdc_device *lcdc_dev =
 104             container_of(dev_drv, struct lcdc_device, driver);
 105         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
 106         lcdc_cfg_done(lcdc_dev);
 107         mdelay(25);
 108         for (i = 0; i < 256; i++) {
 109                 v = dsp_lut[i];
 110                 c = lcdc_dev->dsp_lut_addr_base + i;
 111                 writel_relaxed(v, c);
 112         }
 113         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
 114
 115         return 0;
 116 }
 117
 118 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 119 {
 120 #ifdef CONFIG_RK_FPGA
 121         lcdc_dev->clk_on = 1;
 122         return 0;
 123 #endif
 124         if (!lcdc_dev->clk_on) {
 125                 clk_prepare_enable(lcdc_dev->hclk);
 126                 clk_prepare_enable(lcdc_dev->dclk);
 127                 clk_prepare_enable(lcdc_dev->aclk);
 128                 /*clk_prepare_enable(lcdc_dev->pd);*/
 129                 spin_lock(&lcdc_dev->reg_lock);
 130                 lcdc_dev->clk_on = 1;
 131                 spin_unlock(&lcdc_dev->reg_lock);
 132         }
 133
 134         return 0;
 135 }
 136
 137 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 138 {
 139 #ifdef CONFIG_RK_FPGA
 140         lcdc_dev->clk_on = 0;
 141         return 0;
 142 #endif
 143         if (lcdc_dev->clk_on) {
 144                 spin_lock(&lcdc_dev->reg_lock);
 145                 lcdc_dev->clk_on = 0;
 146                 spin_unlock(&lcdc_dev->reg_lock);
 147                 mdelay(25);
 148                 clk_disable_unprepare(lcdc_dev->dclk);
 149                 clk_disable_unprepare(lcdc_dev->hclk);
 150                 clk_disable_unprepare(lcdc_dev->aclk);
 151                 /*clk_disable_unprepare(lcdc_dev->pd);*/
 152         }
 153
 154         return 0;
 155 }
 156
 157 static int rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 158 {
 159         u32 mask, val;
 160
 161         spin_lock(&lcdc_dev->reg_lock);
 162         if (likely(lcdc_dev->clk_on)) {
 163                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 164                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 165                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 166                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 167                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 168                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 169                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 170                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 171                     v_ADDR_SAME_INTR_EN(0) |
 172                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 173                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 174                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 175                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 176                     v_POST_BUF_EMPTY_INTR_EN(0) |
 177                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 178                 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
 179
 180                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 181                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 182                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 183                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 184                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 185                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 186                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 187                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 188                     v_ADDR_SAME_INTR_CLR(1) |
 189                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 190                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 191                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 192                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 193                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 194                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 195                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
 196                 lcdc_cfg_done(lcdc_dev);
 197                 spin_unlock(&lcdc_dev->reg_lock);
 198         } else {
 199                 spin_unlock(&lcdc_dev->reg_lock);
 200         }
 201         mdelay(1);
 202         return 0;
 203 }
 204
 205 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 206 {
 207         struct lcdc_device *lcdc_dev =
 208             container_of(dev_drv, struct lcdc_device, driver);
 209         int *cbase = (int *)lcdc_dev->regs;
 210         int *regsbak = (int *)lcdc_dev->regsbak;
 211         int i, j, val;
 212         char dbg_message[30];
 213         char buf[10];
 214
 215         pr_info("lcd back up reg:\n");
 216         memset(dbg_message, 0, sizeof(dbg_message));
 217         memset(buf, 0, sizeof(buf));
 218         for (i = 0; i <= (0x200 >> 4); i++) {
 219                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 220                 for (j = 0; j < 4; j++) {
 221                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 222                         strcat(dbg_message, buf);
 223                 }
 224                 pr_info("%s\n", dbg_message);
 225                 memset(dbg_message, 0, sizeof(dbg_message));
 226                 memset(buf, 0, sizeof(buf));
 227         }
 228
 229         pr_info("lcdc reg:\n");
 230         for (i = 0; i <= (0x200 >> 4); i++) {
 231                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 232                 for (j = 0; j < 4; j++) {
 233                         sprintf(buf, "%08x  ",
 234                                 readl_relaxed(cbase + i * 4 + j));
 235                         strcat(dbg_message, buf);
 236                 }
 237                 pr_info("%s\n", dbg_message);
 238                 memset(dbg_message, 0, sizeof(dbg_message));
 239                 memset(buf, 0, sizeof(buf));
 240         }
 241
 242         return 0;
 243 }
 244
 245 #define WIN_EN(id)              \
 246 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 247 { \
 248         u32 msk, val;                                                   \
 249         spin_lock(&lcdc_dev->reg_lock);                                 \
 250         msk =  m_WIN##id##_EN;                                          \
 251         val  =  v_WIN##id##_EN(en);                                     \
 252         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 253         lcdc_cfg_done(lcdc_dev);                                        \
 254         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 255         while (val !=  (!!en))  {                                       \
 256                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 257         }                                                               \
 258         spin_unlock(&lcdc_dev->reg_lock);                               \
 259         return 0;                                                       \
 260 }
 261
 262 WIN_EN(0);
 263 WIN_EN(1);
 264 WIN_EN(2);
 265 WIN_EN(3);
 266 /*enable/disable win directly*/
 267 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 268                                      int win_id, int en)
 269 {
 270         struct lcdc_device *lcdc_dev =
 271             container_of(drv, struct lcdc_device, driver);
 272         if (win_id == 0)
 273                 win0_enable(lcdc_dev, en);
 274         else if (win_id == 1)
 275                 win1_enable(lcdc_dev, en);
 276         else if (win_id == 2)
 277                 win2_enable(lcdc_dev, en);
 278         else if (win_id == 3)
 279                 win3_enable(lcdc_dev, en);
 280         else
 281                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 282         return 0;
 283 }
 284
 285 #define SET_WIN_ADDR(id) \
 286 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 287 {                                                       \
 288         u32 msk, val;                                   \
 289         spin_lock(&lcdc_dev->reg_lock);                 \
 290         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 291         msk =  m_WIN##id##_EN;                          \
 292         val  =  v_WIN0_EN(1);                           \
 293         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 294         lcdc_cfg_done(lcdc_dev);                        \
 295         spin_unlock(&lcdc_dev->reg_lock);               \
 296         return 0;                                       \
 297 }
 298
 299 SET_WIN_ADDR(0);
 300 SET_WIN_ADDR(1);
 301 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 302                                     int win_id, u32 addr)
 303 {
 304         struct lcdc_device *lcdc_dev =
 305             container_of(dev_drv, struct lcdc_device, driver);
 306         if (win_id == 0)
 307                 set_win0_addr(lcdc_dev, addr);
 308         else
 309                 set_win1_addr(lcdc_dev, addr);
 310
 311         return 0;
 312 }
 313
 314 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 315 {
 316         int reg = 0;
 317         u32 val = 0;
 318         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 319         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 320         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 321         u32 st_x, st_y;
 322         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 323
 324         spin_lock(&lcdc_dev->reg_lock);
 325         for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
 326                 val = lcdc_readl_backup(lcdc_dev, reg);
 327                 switch (reg) {
 328                 case WIN0_ACT_INFO:
 329                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 330                         win0->area[0].yact =
 331                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 332                         break;
 333                 case WIN0_DSP_INFO:
 334                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 335                         win0->area[0].ysize =
 336                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 337                         break;
 338                 case WIN0_DSP_ST:
 339                         st_x = val & m_WIN0_DSP_XST;
 340                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 341                         win0->area[0].xpos = st_x - h_pw_bp;
 342                         win0->area[0].ypos = st_y - v_pw_bp;
 343                         break;
 344                 case WIN0_CTRL0:
 345                         win0->state = val & m_WIN0_EN;
 346                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 347                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 348                         win0->area[0].format = win0->area[0].fmt_cfg;
 349                         break;
 350                 case WIN0_VIR:
 351                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 352                         win0->area[0].uv_vir_stride =
 353                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 354                         if (win0->area[0].format == ARGB888)
 355                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 356                         else if (win0->area[0].format == RGB888)
 357                                 win0->area[0].xvir =
 358                                     win0->area[0].y_vir_stride * 4 / 3;
 359                         else if (win0->area[0].format == RGB565)
 360                                 win0->area[0].xvir =
 361                                     2 * win0->area[0].y_vir_stride;
 362                         else    /* YUV */
 363                                 win0->area[0].xvir =
 364                                     4 * win0->area[0].y_vir_stride;
 365                         break;
 366                 case WIN0_YRGB_MST:
 367                         win0->area[0].smem_start = val;
 368                         break;
 369                 case WIN0_CBR_MST:
 370                         win0->area[0].cbr_start = val;
 371                         break;
 372                 default:
 373                         break;
 374                 }
 375         }
 376         spin_unlock(&lcdc_dev->reg_lock);
 377 }
 378
 379 /********do basic init*********/
 380 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 381 {
 382         u32 mask, val, v;
 383         struct lcdc_device *lcdc_dev =
 384             container_of(dev_drv, struct lcdc_device, driver);
 385         if (lcdc_dev->pre_init)
 386                 return 0;
 387
 388         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 389         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 390         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 391         /*lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");*/
 392
 393         if (/*IS_ERR(lcdc_dev->pd) || */(IS_ERR(lcdc_dev->aclk)) ||
 394             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 395                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 396                         lcdc_dev->id);
 397         }
 398
 399         rk_disp_pwr_enable(dev_drv);
 400         rk3368_lcdc_clk_enable(lcdc_dev);
 401
 402         /*backup reg config at uboot */
 403         lcdc_read_reg_defalut_cfg(lcdc_dev);
 404         if (lcdc_dev->pwr18 == 1) {
 405                 v = 0x00200020; /*bit5: 1,1.8v;0,3.3v*/
 406                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 407                                 PMUGRF_SOC_CON0_VOP, v);
 408         } else {
 409                 v = 0x00200000; /*bit5: 1,1.8v;0,3.3v*/
 410                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 411                                 PMUGRF_SOC_CON0_VOP, v);
 412         }
 413         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
 414         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
 415         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
 416         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
 417         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
 418         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
 419
 420         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 421         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 422         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 423         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 424         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 425         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 426
 427         mask = m_AUTO_GATING_EN;
 428         val = v_AUTO_GATING_EN(0);
 429         lcdc_cfg_done(lcdc_dev);
 430         /*disable win0 to workaround iommu pagefault */
 431         /*if (dev_drv->iommu_enabled) */
 432         /*      win0_enable(lcdc_dev, 0); */
 433         lcdc_dev->pre_init = true;
 434
 435         return 0;
 436 }
 437
 438 static void __maybe_unused
 439         rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 440 {
 441         rk3368_lcdc_disable_irq(lcdc_dev);
 442         spin_lock(&lcdc_dev->reg_lock);
 443         if (likely(lcdc_dev->clk_on)) {
 444                 lcdc_dev->clk_on = 0;
 445                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN);
 446                 lcdc_cfg_done(lcdc_dev);
 447                 spin_unlock(&lcdc_dev->reg_lock);
 448         } else {
 449                 spin_unlock(&lcdc_dev->reg_lock);
 450         }
 451         mdelay(1);
 452 }
 453
 454 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 455 {
 456         struct lcdc_device *lcdc_dev =
 457             container_of(dev_drv, struct lcdc_device, driver);
 458         struct rk_screen *screen = dev_drv->cur_screen;
 459         u16 x_res = screen->mode.xres;
 460         u16 y_res = screen->mode.yres;
 461         u32 mask, val;
 462         u16 h_total, v_total;
 463         u16 post_hsd_en, post_vsd_en;
 464         u16 post_dsp_hact_st, post_dsp_hact_end;
 465         u16 post_dsp_vact_st, post_dsp_vact_end;
 466         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 467         u16 post_h_fac, post_v_fac;
 468
 469         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 470             x_res + screen->mode.right_margin;
 471         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 472             y_res + screen->mode.lower_margin;
 473
 474         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 475                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 476                          screen->post_dsp_stx, screen->post_xsize, x_res);
 477                 screen->post_dsp_stx = x_res - screen->post_xsize;
 478         }
 479         if (screen->x_mirror == 0) {
 480                 post_dsp_hact_st = screen->post_dsp_stx +
 481                     screen->mode.hsync_len + screen->mode.left_margin;
 482                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 483         } else {
 484                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 485                     screen->post_dsp_stx;
 486                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 487         }
 488         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 489                 post_hsd_en = 1;
 490                 post_h_fac =
 491                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 492         } else {
 493                 post_hsd_en = 0;
 494                 post_h_fac = 0x1000;
 495         }
 496
 497         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 498                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 499                          screen->post_dsp_sty, screen->post_ysize, y_res);
 500                 screen->post_dsp_sty = y_res - screen->post_ysize;
 501         }
 502
 503         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 504                 post_vsd_en = 1;
 505                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 506                                                       screen->post_ysize);
 507         } else {
 508                 post_vsd_en = 0;
 509                 post_v_fac = 0x1000;
 510         }
 511
 512         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 513                 post_dsp_vact_st = screen->post_dsp_sty +
 514                     screen->mode.vsync_len + screen->mode.upper_margin;
 515                 post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize;
 516
 517                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
 518                                       screen->mode.upper_margin +
 519                                       y_res/2 +
 520                                       screen->mode.lower_margin +
 521                                       screen->mode.vsync_len +
 522                                       screen->mode.upper_margin + 1;
 523                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
 524                                         screen->post_ysize/2;
 525         } else {
 526                 if (screen->y_mirror == 0) {
 527                         post_dsp_vact_st = screen->post_dsp_sty +
 528                             screen->mode.vsync_len +
 529                             screen->mode.upper_margin;
 530                         post_dsp_vact_end = post_dsp_vact_st +
 531                                 screen->post_ysize;
 532                 } else {
 533                         post_dsp_vact_end = v_total -
 534                                 screen->mode.lower_margin -
 535                             screen->post_dsp_sty;
 536                         post_dsp_vact_st = post_dsp_vact_end -
 537                                 screen->post_ysize;
 538                 }
 539                 post_dsp_vact_st_f1 = 0;
 540                 post_dsp_vact_end_f1 = 0;
 541         }
 542         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 543             screen->post_xsize, screen->post_ysize, screen->xpos);
 544         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 545             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 546         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 547         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 548             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 549         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 550
 551         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 552         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 553             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 554         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 555
 556         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 557         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 558             v_POST_VS_FACTOR_YRGB(post_v_fac);
 559         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 560
 561         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 562         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 563             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 564         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 565
 566         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 567         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 568         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 569         return 0;
 570 }
 571
 572 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 573 {
 574         struct lcdc_device *lcdc_dev =
 575             container_of(dev_drv, struct lcdc_device, driver);
 576         struct rk_lcdc_win *win;
 577         u32 colorkey_r, colorkey_g, colorkey_b;
 578         int i, key_val;
 579
 580         for (i = 0; i < 4; i++) {
 581                 win = dev_drv->win[i];
 582                 key_val = win->color_key_val;
 583                 colorkey_r = (key_val & 0xff) << 2;
 584                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 585                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 586                 /*color key dither 565/888->aaa */
 587                 key_val = colorkey_r | colorkey_g | colorkey_b;
 588                 switch (i) {
 589                 case 0:
 590                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 591                         break;
 592                 case 1:
 593                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 594                         break;
 595                 case 2:
 596                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 597                         break;
 598                 case 3:
 599                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 600                         break;
 601                 default:
 602                         pr_info("%s:un support win num:%d\n",
 603                                 __func__, i);
 604                         break;
 605                 }
 606         }
 607         return 0;
 608 }
 609
 610 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 611 {
 612         struct lcdc_device *lcdc_dev =
 613             container_of(dev_drv, struct lcdc_device, driver);
 614         struct rk_lcdc_win *win = dev_drv->win[win_id];
 615         struct alpha_config alpha_config;
 616         u32 mask, val;
 617         int ppixel_alpha = 0, global_alpha = 0, i;
 618         u32 src_alpha_ctl, dst_alpha_ctl;
 619
 620         for (i = 0; i < win->area_num; i++) {
 621                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 622                                  (win->area[i].format == FBDC_ARGB_888) ||
 623                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 624         }
 625         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 626         alpha_config.src_global_alpha_val = win->g_alpha_val;
 627         win->alpha_mode = AB_SRC_OVER;
 628         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 629            __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
 630            global_alpha); */
 631         switch (win->alpha_mode) {
 632         case AB_USER_DEFINE:
 633                 break;
 634         case AB_CLEAR:
 635                 alpha_config.src_factor_mode = AA_ZERO;
 636                 alpha_config.dst_factor_mode = AA_ZERO;
 637                 break;
 638         case AB_SRC:
 639                 alpha_config.src_factor_mode = AA_ONE;
 640                 alpha_config.dst_factor_mode = AA_ZERO;
 641                 break;
 642         case AB_DST:
 643                 alpha_config.src_factor_mode = AA_ZERO;
 644                 alpha_config.dst_factor_mode = AA_ONE;
 645                 break;
 646         case AB_SRC_OVER:
 647                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 648                 if (global_alpha)
 649                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 650                 else
 651                         alpha_config.src_factor_mode = AA_ONE;
 652                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 653                 break;
 654         case AB_DST_OVER:
 655                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 656                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 657                 alpha_config.dst_factor_mode = AA_ONE;
 658                 break;
 659         case AB_SRC_IN:
 660                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 661                 alpha_config.src_factor_mode = AA_SRC;
 662                 alpha_config.dst_factor_mode = AA_ZERO;
 663                 break;
 664         case AB_DST_IN:
 665                 alpha_config.src_factor_mode = AA_ZERO;
 666                 alpha_config.dst_factor_mode = AA_SRC;
 667                 break;
 668         case AB_SRC_OUT:
 669                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 670                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 671                 alpha_config.dst_factor_mode = AA_ZERO;
 672                 break;
 673         case AB_DST_OUT:
 674                 alpha_config.src_factor_mode = AA_ZERO;
 675                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 676                 break;
 677         case AB_SRC_ATOP:
 678                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 679                 alpha_config.src_factor_mode = AA_SRC;
 680                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 681                 break;
 682         case AB_DST_ATOP:
 683                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 684                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 685                 alpha_config.dst_factor_mode = AA_SRC;
 686                 break;
 687         case XOR:
 688                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 689                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 690                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 691                 break;
 692         case AB_SRC_OVER_GLOBAL:
 693                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 694                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 695                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 696                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 697                 break;
 698         default:
 699                 pr_err("alpha mode error\n");
 700                 break;
 701         }
 702         if ((ppixel_alpha == 1) && (global_alpha == 1))
 703                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 704         else if (ppixel_alpha == 1)
 705                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 706         else if (global_alpha == 1)
 707                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 708         else
 709                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 710         alpha_config.src_alpha_mode = AA_STRAIGHT;
 711         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 712
 713         switch (win_id) {
 714         case 0:
 715                 src_alpha_ctl = 0x60;
 716                 dst_alpha_ctl = 0x64;
 717                 break;
 718         case 1:
 719                 src_alpha_ctl = 0xa0;
 720                 dst_alpha_ctl = 0xa4;
 721                 break;
 722         case 2:
 723                 src_alpha_ctl = 0xdc;
 724                 dst_alpha_ctl = 0xec;
 725                 break;
 726         case 3:
 727                 src_alpha_ctl = 0x12c;
 728                 dst_alpha_ctl = 0x13c;
 729                 break;
 730         case 4:
 731                 src_alpha_ctl = 0x160;
 732                 dst_alpha_ctl = 0x164;
 733                 break;
 734         }
 735         mask = m_WIN0_DST_FACTOR_M0;
 736         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 737         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 738         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 739             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 740             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 741             m_WIN0_SRC_GLOBAL_ALPHA;
 742         val = v_WIN0_SRC_ALPHA_EN(1) |
 743             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 744             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 745             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 746             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 747             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 748             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 749         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 750
 751         return 0;
 752 }
 753
 754 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 755 {
 756         struct rk_lcdc_win_area area_temp;
 757         int i, j;
 758
 759         for (i = 0; i < area_num; i++) {
 760                 for (j = i + 1; j < area_num; j++) {
 761                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 762                                 memcpy(&area_temp, &win->area[i],
 763                                        sizeof(struct rk_lcdc_win_area));
 764                                 memcpy(&win->area[i], &win->area[j],
 765                                        sizeof(struct rk_lcdc_win_area));
 766                                 memcpy(&win->area[j], &area_temp,
 767                                        sizeof(struct rk_lcdc_win_area));
 768                         }
 769                 }
 770         }
 771
 772         return 0;
 773 }
 774
 775 static int __maybe_unused
 776         rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 777 {
 778         struct rk_lcdc_win_area area_temp;
 779
 780         switch (area_num) {
 781         case 2:
 782                 area_temp = win->area[0];
 783                 win->area[0] = win->area[1];
 784                 win->area[1] = area_temp;
 785                 break;
 786         case 3:
 787                 area_temp = win->area[0];
 788                 win->area[0] = win->area[2];
 789                 win->area[2] = area_temp;
 790                 break;
 791         case 4:
 792                 area_temp = win->area[0];
 793                 win->area[0] = win->area[3];
 794                 win->area[3] = area_temp;
 795
 796                 area_temp = win->area[1];
 797                 win->area[1] = win->area[2];
 798                 win->area[2] = area_temp;
 799                 break;
 800         default:
 801                 pr_info("un supported area num!\n");
 802                 break;
 803         }
 804         return 0;
 805 }
 806
 807 static int rk3368_win_area_check_var(int win_id, int area_num,
 808                                      struct rk_lcdc_win_area *area_pre,
 809                                      struct rk_lcdc_win_area *area_now)
 810 {
 811         if ((area_pre->xpos > area_now->xpos) ||
 812             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 813              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 814                 area_now->state = 0;
 815                 pr_err("win[%d]:\n"
 816                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 817                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 818                        win_id,
 819                        area_num - 1, area_pre->xpos, area_pre->xsize,
 820                        area_pre->ypos, area_pre->ysize,
 821                        area_num, area_now->xpos, area_now->xsize,
 822                        area_now->ypos, area_now->ysize);
 823                 return -EINVAL;
 824         }
 825         return 0;
 826 }
 827
 828 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 829 {
 830         struct lcdc_device *lcdc_dev =
 831             container_of(dev_drv, struct lcdc_device, driver);
 832         u32 val, i;
 833
 834         for (i = 0; i < 100; i++) {
 835                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 836                 val &= m_DBG_IFBDC_IDLE;
 837                 if (val)
 838                         continue;
 839                 else
 840                         mdelay(10);
 841         };
 842         return val;
 843 }
 844
 845 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 846 {
 847         struct lcdc_device *lcdc_dev =
 848             container_of(dev_drv, struct lcdc_device, driver);
 849         struct rk_lcdc_win *win = dev_drv->win[win_id];
 850         u32 mask, val;
 851
 852         mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
 853             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 854             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 855         val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
 856             v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 857             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 858             v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
 859             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 860             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 861         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 862
 863         mask = m_IFBDC_TILES_NUM;
 864         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 865         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 866
 867         mask = m_IFBDC_BASE_ADDR;
 868         val = v_IFBDC_BASE_ADDR(win->area[0].y_addr);
 869         lcdc_msk_reg(lcdc_dev, IFBDC_BASE_ADDR, mask, val);
 870
 871         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 872         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 873             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 874         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 875
 876         mask = m_IFBDC_CMP_INDEX_INIT;
 877         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 878         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 879
 880         mask = m_IFBDC_MB_VIR_WIDTH;
 881         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 882         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 883
 884         return 0;
 885 }
 886
 887 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 888 {
 889         struct lcdc_device *lcdc_dev =
 890             container_of(dev_drv, struct lcdc_device, driver);
 891         struct rk_lcdc_win *win = dev_drv->win[win_id];
 892         u8 fbdc_dsp_width_ratio;
 893         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 894         u16 fbdc_mb_width, fbdc_mb_height;
 895         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 896         u16 fbdc_cmp_index_init;
 897         u8 mb_w_size, mb_h_size;
 898         struct rk_screen *screen = dev_drv->cur_screen;
 899
 900         if (screen->mode.flag == FB_VMODE_INTERLACED) {
 901                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
 902                 return 0;
 903         }
 904
 905         switch (win->area[0].fmt_cfg) {
 906         case VOP_FORMAT_ARGB888:
 907                 fbdc_dsp_width_ratio = 0;
 908                 mb_w_size = 16;
 909                 break;
 910         case VOP_FORMAT_RGB888:
 911                 fbdc_dsp_width_ratio = 0;
 912                 mb_w_size = 16;
 913                 break;
 914         case VOP_FORMAT_RGB565:
 915                 fbdc_dsp_width_ratio = 1;
 916                 mb_w_size = 32;
 917                 break;
 918         default:
 919                 dev_err(lcdc_dev->dev,
 920                         "in fbdc mode,unsupport fmt:%d!\n",
 921                         win->area[0].fmt_cfg);
 922                 break;
 923         }
 924         mb_h_size = 4;
 925
 926         /*macro block xvir and yvir */
 927         if ((win->area[0].xvir % mb_w_size == 0) &&
 928             (win->area[0].yvir % mb_h_size == 0)) {
 929                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
 930                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
 931         } else {
 932                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 933                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
 934                        win->area[0].xvir, win->area[0].yvir,
 935                        mb_w_size, mb_h_size);
 936         }
 937         /*macro block xact and yact */
 938         if ((win->area[0].xact % mb_w_size == 0) &&
 939             (win->area[0].yact % mb_h_size == 0)) {
 940                 fbdc_mb_width = win->area[0].xact / mb_w_size;
 941                 fbdc_mb_height = win->area[0].yact / mb_h_size;
 942         } else {
 943                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 944                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
 945                        win->area[0].xact, win->area[0].yact,
 946                        mb_w_size, mb_h_size);
 947         }
 948         /*macro block xoff and yoff */
 949         if ((win->area[0].xoff % mb_w_size == 0) &&
 950             (win->area[0].yoff % mb_h_size == 0)) {
 951                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
 952                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
 953         } else {
 954                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 955                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
 956                        win->area[0].xoff, win->area[0].yoff,
 957                        mb_w_size, mb_h_size);
 958         }
 959
 960         /*FBDC tiles */
 961         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
 962
 963         /*
 964            switch (fbdc_rotation_mode)  {
 965            case FBDC_ROT_NONE:
 966            fbdc_cmp_index_init =
 967            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
 968            break;
 969            case FBDC_X_MIRROR:
 970            fbdc_cmp_index_init =
 971            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
 972            (fbdc_mb_width-1));
 973            break;
 974            case FBDC_Y_MIRROR:
 975            fbdc_cmp_index_init =
 976            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
 977            fbdc_mb_xst;
 978            break;
 979            case FBDC_ROT_180:
 980            fbdc_cmp_index_init =
 981            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
 982            (fbdc_mb_xst+(fbdc_mb_width-1));
 983            break;
 984            }
 985          */
 986         if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
 987                 fbdc_cmp_index_init =
 988                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
 989                     (fbdc_mb_xst + (fbdc_mb_width - 1));
 990         } else {
 991                 fbdc_cmp_index_init =
 992                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
 993         }
 994         /*fbdc fmt maybe need to change*/
 995         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
 996         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
 997         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
 998         win->area[0].fbdc_mb_width = fbdc_mb_width;
 999         win->area[0].fbdc_mb_height = fbdc_mb_height;
1000         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1001         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1002         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1003         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1004
1005         return 0;
1006 }
1007
1008 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1009                                  struct rk_lcdc_win *win)
1010 {
1011         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1012         struct rk_screen *screen = dev_drv->cur_screen;
1013
1014         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1015                 switch (win->area[0].fmt_cfg) {
1016                 case VOP_FORMAT_ARGB888:
1017                 case VOP_FORMAT_RGB888:
1018                 case VOP_FORMAT_RGB565:
1019                         if ((screen->mode.xres < 1280) &&
1020                             (screen->mode.yres < 720)) {
1021                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1022                         } else {
1023                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1024                         }
1025                         break;
1026                 default:
1027                         break;
1028                 }
1029         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1030                 switch (win->area[0].fmt_cfg) {
1031                 case VOP_FORMAT_YCBCR420:
1032                         if ((win->id == 0) || (win->id == 1))
1033                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1034                         break;
1035                 default:
1036                         break;
1037                 }
1038         }
1039 }
1040
1041 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1042 {
1043         struct lcdc_device *lcdc_dev =
1044             container_of(dev_drv, struct lcdc_device, driver);
1045         struct rk_lcdc_win *win = dev_drv->win[win_id];
1046         unsigned int mask, val, off;
1047
1048         off = win_id * 0x40;
1049         /*if(win->win_lb_mode == 5)
1050            win->win_lb_mode = 4;
1051            for rk3288 to fix hw bug? */
1052
1053         if (win->state == 1) {
1054                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1055                 if (win->area[0].fbdc_en) {
1056                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1057                 } else {
1058                         mask = m_IFBDC_CTRL_FBDC_EN;
1059                         val = v_IFBDC_CTRL_FBDC_EN(0);
1060                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1061                 }
1062                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1063                     m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1064                     m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE;
1065                 val = v_WIN0_EN(win->state) |
1066                     v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1067                     v_WIN0_FMT_10(win->fmt_10) |
1068                     v_WIN0_LB_MODE(win->win_lb_mode) |
1069                     v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1070                     v_WIN0_X_MIRROR(win->mirror_en) |
1071                     v_WIN0_Y_MIRROR(win->mirror_en) |
1072                     v_WIN0_CSC_MODE(win->csc_mode);
1073                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1074
1075                 mask = m_WIN0_BIC_COE_SEL |
1076                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1077                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1078                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1079                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1080                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1081                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1082                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1083                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1084                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1085                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1086                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1087                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1088                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1089                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1090                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1091                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1092                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1093                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1094                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1095                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1096                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1097                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1098                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1099                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1100                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1101                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1102                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1103                                 win->area[0].y_addr);
1104                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1105                                 win->area[0].uv_addr); */
1106                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1107                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1108                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1109
1110                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1111                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1112                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1113
1114                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1115                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1116                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1117
1118                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1119                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1120                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1121
1122                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1123                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1124                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1125                 if (win->alpha_en == 1) {
1126                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1127                 } else {
1128                         mask = m_WIN0_SRC_ALPHA_EN;
1129                         val = v_WIN0_SRC_ALPHA_EN(0);
1130                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1131                                      mask, val);
1132                 }
1133         } else {
1134                 mask = m_WIN0_EN;
1135                 val = v_WIN0_EN(win->state);
1136                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1137         }
1138         return 0;
1139 }
1140
1141 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1142 {
1143         struct lcdc_device *lcdc_dev =
1144             container_of(dev_drv, struct lcdc_device, driver);
1145         struct rk_lcdc_win *win = dev_drv->win[win_id];
1146         unsigned int mask, val, off;
1147
1148         off = (win_id - 2) * 0x50;
1149         rk3368_lcdc_area_xst(win, win->area_num);
1150
1151         if (win->state == 1) {
1152                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1153                 if (win->area[0].fbdc_en) {
1154                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1155                 } else {
1156                         mask = m_IFBDC_CTRL_FBDC_EN;
1157                         val = v_IFBDC_CTRL_FBDC_EN(0);
1158                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1159                 }
1160
1161                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1162                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1163                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1164                 /*area 0 */
1165                 if (win->area[0].state == 1) {
1166                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1167                             m_WIN2_RB_SWAP0;
1168                         val = v_WIN2_MST0_EN(win->area[0].state) |
1169                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1170                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1171                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1172
1173                         mask = m_WIN2_VIR_STRIDE0;
1174                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1175                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1176
1177                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1178                            win->area[0].y_addr); */
1179                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1180                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1181                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1182                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1183                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1184                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1185                 } else {
1186                         mask = m_WIN2_MST0_EN;
1187                         val = v_WIN2_MST0_EN(0);
1188                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1189                 }
1190                 /*area 1 */
1191                 if (win->area[1].state == 1) {
1192                         rk3368_win_area_check_var(win_id, 1,
1193                                                   &win->area[0], &win->area[1]);
1194
1195                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1196                             m_WIN2_RB_SWAP1;
1197                         val = v_WIN2_MST1_EN(win->area[1].state) |
1198                             v_WIN2_DATA_FMT0(win->area[1].fmt_cfg) |
1199                             v_WIN2_RB_SWAP0(win->area[1].swap_rb);
1200                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1201
1202                         mask = m_WIN2_VIR_STRIDE1;
1203                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1204                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1205
1206                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1207                            win->area[1].y_addr); */
1208                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1209                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1210                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1211                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1212                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1213                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1214                 } else {
1215                         mask = m_WIN2_MST1_EN;
1216                         val = v_WIN2_MST1_EN(0);
1217                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1218                 }
1219                 /*area 2 */
1220                 if (win->area[2].state == 1) {
1221                         rk3368_win_area_check_var(win_id, 2,
1222                                                   &win->area[1], &win->area[2]);
1223
1224                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1225                             m_WIN2_RB_SWAP2;
1226                         val = v_WIN2_MST2_EN(win->area[2].state) |
1227                             v_WIN2_DATA_FMT0(win->area[2].fmt_cfg) |
1228                             v_WIN2_RB_SWAP0(win->area[2].swap_rb);
1229                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1230
1231                         mask = m_WIN2_VIR_STRIDE2;
1232                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1233                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1234
1235                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1236                            win->area[2].y_addr); */
1237                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1238                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1239                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1240                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1241                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1242                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1243                 } else {
1244                         mask = m_WIN2_MST2_EN;
1245                         val = v_WIN2_MST2_EN(0);
1246                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1247                 }
1248                 /*area 3 */
1249                 if (win->area[3].state == 1) {
1250                         rk3368_win_area_check_var(win_id, 3,
1251                                                   &win->area[2], &win->area[3]);
1252
1253                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1254                             m_WIN2_RB_SWAP3;
1255                         val = v_WIN2_MST3_EN(win->area[3].state) |
1256                             v_WIN2_DATA_FMT0(win->area[3].fmt_cfg) |
1257                             v_WIN2_RB_SWAP0(win->area[3].swap_rb);
1258                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1259
1260                         mask = m_WIN2_VIR_STRIDE3;
1261                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1262                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1263
1264                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1265                            win->area[3].y_addr); */
1266                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1267                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1268                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1269                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1270                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1271                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1272                 } else {
1273                         mask = m_WIN2_MST3_EN;
1274                         val = v_WIN2_MST3_EN(0);
1275                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1276                 }
1277
1278                 if (win->alpha_en == 1) {
1279                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1280                 } else {
1281                         mask = m_WIN2_SRC_ALPHA_EN;
1282                         val = v_WIN2_SRC_ALPHA_EN(0);
1283                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1284                                      mask, val);
1285                 }
1286         } else {
1287                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1288                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1289                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1290                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1291                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1292         }
1293         return 0;
1294 }
1295
1296 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1297 {
1298         struct lcdc_device *lcdc_dev =
1299             container_of(dev_drv, struct lcdc_device, driver);
1300         struct rk_lcdc_win *win = dev_drv->win[win_id];
1301         unsigned int mask, val, hwc_size = 0;
1302
1303         if (win->state == 1) {
1304                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1305                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1306                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1307                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1308                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1309                     v_WIN0_CSC_MODE(win->csc_mode);
1310                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1311
1312                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1313                         hwc_size = 0;
1314                 else if ((win->area[0].xsize == 64) &&
1315                          (win->area[0].ysize == 64))
1316                         hwc_size = 1;
1317                 else if ((win->area[0].xsize == 96) &&
1318                          (win->area[0].ysize == 96))
1319                         hwc_size = 2;
1320                 else if ((win->area[0].xsize == 128) &&
1321                          (win->area[0].ysize == 128))
1322                         hwc_size = 3;
1323                 else
1324                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1325
1326                 mask = m_HWC_SIZE;
1327                 val = v_HWC_SIZE(hwc_size);
1328                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1329
1330                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1331                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1332                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1333                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1334
1335                 if (win->alpha_en == 1) {
1336                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1337                 } else {
1338                         mask = m_WIN2_SRC_ALPHA_EN;
1339                         val = v_WIN2_SRC_ALPHA_EN(0);
1340                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1341                 }
1342         } else {
1343                 mask = m_HWC_EN;
1344                 val = v_HWC_EN(win->state);
1345                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1346         }
1347         return 0;
1348 }
1349
1350 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1351                                          struct rk_lcdc_win *win)
1352 {
1353         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1354         int timeout;
1355         unsigned long flags;
1356
1357         spin_lock(&lcdc_dev->reg_lock);
1358         if (likely(lcdc_dev->clk_on)) {
1359                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1360                              v_STANDBY_EN(lcdc_dev->standby));
1361                 if ((win->id == 0) || (win->id == 1))
1362                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1363                 else if ((win->id == 2) || (win->id == 3))
1364                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1365                 else if (win->id == 4)
1366                         rk3368_hwc_reg_update(dev_drv, win->id);
1367                 /*rk3368_lcdc_post_cfg(dev_drv); */
1368                 lcdc_cfg_done(lcdc_dev);
1369         }
1370         spin_unlock(&lcdc_dev->reg_lock);
1371
1372         /*if (dev_drv->wait_fs) { */
1373         if (0) {
1374                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1375                 init_completion(&dev_drv->frame_done);
1376                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1377                 timeout =
1378                     wait_for_completion_timeout(&dev_drv->frame_done,
1379                                                 msecs_to_jiffies
1380                                                 (dev_drv->cur_screen->ft + 5));
1381                 if (!timeout && (!dev_drv->frame_done.done)) {
1382                         dev_warn(lcdc_dev->dev,
1383                                  "wait for new frame start time out!\n");
1384                         return -ETIMEDOUT;
1385                 }
1386         }
1387         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1388         return 0;
1389 }
1390
1391 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1392 {
1393         if (lcdc_dev->driver.iommu_enabled)
1394                 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x330);
1395         else
1396                 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x260);
1397         return 0;
1398 }
1399
1400 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1401 {
1402         u32 mask, val;
1403         struct lcdc_device *lcdc_dev =
1404             container_of(dev_drv, struct lcdc_device, driver);
1405         /*spin_lock(&lcdc_dev->reg_lock); */
1406         if (likely(lcdc_dev->clk_on)) {
1407                 mask = m_MMU_EN;
1408                 val = v_MMU_EN(1);
1409                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1410                 mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM;
1411                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1412                     v_AXI_MAX_OUTSTANDING_EN(1);
1413                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1414         }
1415         /*spin_unlock(&lcdc_dev->reg_lock); */
1416 #if defined(CONFIG_ROCKCHIP_IOMMU)
1417         if (dev_drv->iommu_enabled) {
1418                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1419                         lcdc_dev->iommu_status = 1;
1420                         rockchip_iovmm_activate(dev_drv->dev);
1421                 }
1422         }
1423 #endif
1424         return 0;
1425 }
1426
1427 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
1428 {
1429         int ret = 0, fps = 0;
1430         struct lcdc_device *lcdc_dev =
1431             container_of(dev_drv, struct lcdc_device, driver);
1432         struct rk_screen *screen = dev_drv->cur_screen;
1433 #ifdef CONFIG_RK_FPGA
1434         return 0;
1435 #endif
1436
1437         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1438         if (ret)
1439                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1440         lcdc_dev->pixclock =
1441             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1442         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1443
1444         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1445         screen->ft = 1000 / fps;
1446         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1447                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1448         return 0;
1449 }
1450
1451 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1452 {
1453         struct lcdc_device *lcdc_dev =
1454             container_of(dev_drv, struct lcdc_device, driver);
1455         struct rk_screen *screen = dev_drv->cur_screen;
1456         u16 hsync_len = screen->mode.hsync_len;
1457         u16 left_margin = screen->mode.left_margin;
1458         u16 right_margin = screen->mode.right_margin;
1459         u16 vsync_len = screen->mode.vsync_len;
1460         u16 upper_margin = screen->mode.upper_margin;
1461         u16 lower_margin = screen->mode.lower_margin;
1462         u16 x_res = screen->mode.xres;
1463         u16 y_res = screen->mode.yres;
1464         u32 mask, val;
1465         u16 h_total, v_total;
1466         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1467
1468         h_total = hsync_len + left_margin + x_res + right_margin;
1469         v_total = vsync_len + upper_margin + y_res + lower_margin;
1470
1471         screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1472         screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1473         screen->post_xsize = x_res *
1474             (screen->overscan.left + screen->overscan.right) / 200;
1475         screen->post_ysize = y_res *
1476             (screen->overscan.top + screen->overscan.bottom) / 200;
1477
1478         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1479         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1480         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1481
1482         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1483         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1484             v_DSP_HACT_ST(hsync_len + left_margin);
1485         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1486
1487         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1488                 /* First Field Timing */
1489                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1490                 val = v_DSP_VS_PW(vsync_len) |
1491                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1492                                       lower_margin) + y_res + 1);
1493                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1494
1495                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1496                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1497                     v_DSP_VACT_ST(vsync_len + upper_margin);
1498                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1499
1500                 /* Second Field Timing */
1501                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1502                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1503                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1504                     lower_margin;
1505                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1506                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1507
1508                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1509                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1510                     lower_margin + 1;
1511                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1512                     lower_margin + 1;
1513                 val =
1514                     v_DSP_VACT_END_F1(vact_end_f1) |
1515                     v_DSP_VAC_ST_F1(vact_st_f1);
1516                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1517
1518                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1519                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1520                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1521                 mask =
1522                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1523                     m_WIN0_CBR_DEFLICK;
1524                 val =
1525                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1526                     v_WIN0_CBR_DEFLICK(1);
1527                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1528
1529                 mask =
1530                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1531                     m_WIN1_CBR_DEFLICK;
1532                 val =
1533                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1534                     v_WIN1_CBR_DEFLICK(1);
1535                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1536
1537                 mask = m_WIN2_INTERLACE_READ;
1538                 val = v_WIN2_INTERLACE_READ(1);
1539                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1540
1541                 mask = m_WIN3_INTERLACE_READ;
1542                 val = v_WIN3_INTERLACE_READ(1);
1543                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1544
1545                 mask = m_HWC_INTERLACE_READ;
1546                 val = v_HWC_INTERLACE_READ(1);
1547                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1548
1549                 mask = m_DSP_LINE_FLAG0_NUM;
1550                 val =
1551                     v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2);
1552                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1553         } else {
1554                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1555                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1556                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1557
1558                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1559                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1560                     v_DSP_VACT_ST(vsync_len + upper_margin);
1561                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1562
1563                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1564                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1565                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1566
1567                 mask =
1568                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1569                     m_WIN0_CBR_DEFLICK;
1570                 val =
1571                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1572                     v_WIN0_CBR_DEFLICK(0);
1573                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1574
1575                 mask =
1576                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1577                     m_WIN1_CBR_DEFLICK;
1578                 val =
1579                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1580                     v_WIN1_CBR_DEFLICK(0);
1581                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1582
1583                 mask = m_WIN2_INTERLACE_READ;
1584                 val = v_WIN2_INTERLACE_READ(0);
1585                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1586
1587                 mask = m_WIN3_INTERLACE_READ;
1588                 val = v_WIN3_INTERLACE_READ(0);
1589                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1590
1591                 mask = m_HWC_INTERLACE_READ;
1592                 val = v_HWC_INTERLACE_READ(0);
1593                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1594
1595                 mask = m_DSP_LINE_FLAG0_NUM;
1596                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res);
1597                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1598         }
1599         rk3368_lcdc_post_cfg(dev_drv);
1600         return 0;
1601 }
1602
1603 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1604 {
1605         struct lcdc_device *lcdc_dev =
1606             container_of(dev_drv, struct lcdc_device, driver);
1607         u32 bcsh_ctrl;
1608
1609         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1610                      v_OVERLAY_MODE(dev_drv->overlay_mode));
1611         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1612                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1613                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1614                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1615                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1616                 else            /* YUV2RGB */
1617                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1618                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1619                                      m_BCSH_R2Y_EN,
1620                                      v_BCSH_Y2R_EN(1) |
1621                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1622                                      v_BCSH_R2Y_EN(0));
1623         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1624                 /* bypass  --need check,if bcsh close? */
1625                 if (dev_drv->output_color == COLOR_RGB) {
1626                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1627                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1628                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1629                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1630                                              m_BCSH_R2Y_EN |
1631                                              m_BCSH_Y2R_EN,
1632                                              v_BCSH_R2Y_EN(1) |
1633                                              v_BCSH_Y2R_EN(1));
1634                         else
1635                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1636                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1637                                              v_BCSH_R2Y_EN(0) |
1638                                              v_BCSH_Y2R_EN(0));
1639                 } else          /* RGB2YUV */
1640                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1641                                      m_BCSH_R2Y_EN |
1642                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1643                                      v_BCSH_R2Y_EN(1) |
1644                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1645                                      v_BCSH_Y2R_EN(0));
1646         }
1647 }
1648
1649 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1650 {
1651         u16 face = 0;
1652         u16 dclk_ddr = 0;
1653         u32 v = 0;
1654         struct lcdc_device *lcdc_dev =
1655             container_of(dev_drv, struct lcdc_device, driver);
1656         struct rk_screen *screen = dev_drv->cur_screen;
1657         u32 mask, val;
1658
1659         spin_lock(&lcdc_dev->reg_lock);
1660         if (likely(lcdc_dev->clk_on)) {
1661                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1662                 if (!lcdc_dev->standby && !initscreen) {
1663                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1664                                      v_STANDBY_EN(1));
1665                         lcdc_cfg_done(lcdc_dev);
1666                         mdelay(50);
1667                 }
1668                 switch (screen->face) {
1669                 case OUT_P565:
1670                         face = OUT_P565;
1671                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1672                             m_DITHER_DOWN_SEL;
1673                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1674                             v_DITHER_DOWN_SEL(1);
1675                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1676                         break;
1677                 case OUT_P666:
1678                         face = OUT_P666;
1679                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1680                             m_DITHER_DOWN_SEL;
1681                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1682                             v_DITHER_DOWN_SEL(1);
1683                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1684                         break;
1685                 case OUT_D888_P565:
1686                         face = OUT_P888;
1687                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1688                             m_DITHER_DOWN_SEL;
1689                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1690                             v_DITHER_DOWN_SEL(1);
1691                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1692                         break;
1693                 case OUT_D888_P666:
1694                         face = OUT_P888;
1695                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1696                             m_DITHER_DOWN_SEL;
1697                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1698                             v_DITHER_DOWN_SEL(1);
1699                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1700                         break;
1701                 case OUT_P888:
1702                         face = OUT_P888;
1703                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1704                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1705                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1706                         break;
1707                 case OUT_YUV_420:
1708                         /*yuv420 output prefer yuv domain overlay */
1709                         face = OUT_YUV_420;
1710                         dclk_ddr = 1;
1711                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1712                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1713                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1714                         break;
1715                 default:
1716                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1717                         break;
1718                 }
1719                 switch (screen->type) {
1720                 case SCREEN_RGB:
1721                         mask = m_RGB_OUT_EN;
1722                         val = v_RGB_OUT_EN(1);
1723                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1724                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1725                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1726                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1727                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1728                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1729                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1730                         v = 1 << 15 | (1 << (15 + 16));
1731
1732                         break;
1733                 case SCREEN_LVDS:
1734                         mask = m_RGB_OUT_EN;
1735                         val = v_RGB_OUT_EN(1);
1736                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1737                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1738                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1739                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1740                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1741                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1742                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1743                         v = 0 << 15 | (1 << (15 + 16));
1744                         break;
1745                 case SCREEN_HDMI:
1746                         /*face = OUT_RGB_AAA;*/
1747                         dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1748                         mask = m_HDMI_OUT_EN  | m_RGB_OUT_EN;
1749                         val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
1750                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1751                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1752                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1753                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1754                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
1755                             v_HDMI_DEN_POL(screen->pin_den) |
1756                             v_HDMI_DCLK_POL(screen->pin_dclk);
1757                         break;
1758                 case SCREEN_MIPI:
1759                         mask = m_MIPI_OUT_EN  | m_RGB_OUT_EN;
1760                         val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
1761                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1762                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1763                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1764                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1765                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1766                             v_MIPI_DEN_POL(screen->pin_den) |
1767                             v_MIPI_DCLK_POL(screen->pin_dclk);
1768                         break;
1769                 case SCREEN_DUAL_MIPI:
1770                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN  |
1771                                 m_RGB_OUT_EN;
1772                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
1773                                 v_RGB_OUT_EN(0);
1774                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1775                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1776                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1777                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1778                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1779                             v_MIPI_DEN_POL(screen->pin_den) |
1780                             v_MIPI_DCLK_POL(screen->pin_dclk);
1781                         break;
1782                 case SCREEN_EDP:
1783                         face = OUT_P888;        /*RGB 888 output */
1784
1785                         mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
1786                         val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
1787                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1788                         /*because edp have to sent aaa fmt */
1789                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1790                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1791
1792                         mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
1793                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
1794                         val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
1795                             v_EDP_VSYNC_POL(screen->pin_vsync) |
1796                             v_EDP_DEN_POL(screen->pin_den) |
1797                             v_EDP_DCLK_POL(screen->pin_dclk);
1798                         break;
1799                 }
1800                 /*hsync vsync den dclk polo,dither */
1801                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1802 #ifndef CONFIG_RK_FPGA
1803                 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
1804                 move to  lvds driver*/
1805                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1806 #endif
1807                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
1808                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1809                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1810                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1811                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
1812                     v_DSP_BG_SWAP(screen->swap_gb) |
1813                     v_DSP_RB_SWAP(screen->swap_rb) |
1814                     v_DSP_RG_SWAP(screen->swap_rg) |
1815                     v_DSP_DELTA_SWAP(screen->swap_delta) |
1816                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1817                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1818                     v_DSP_X_MIR_EN(screen->x_mirror) |
1819                     v_DSP_Y_MIR_EN(screen->y_mirror);
1820                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1821                 /*BG color */
1822                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1823                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
1824                         val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
1825                                 v_DSP_BG_RED(0x80);
1826                 else
1827                         val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
1828                                 v_DSP_BG_RED(0);
1829                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1830                 dev_drv->output_color = screen->color_mode;
1831                 if (screen->dsp_lut == NULL)
1832                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1833                                      v_DSP_LUT_EN(0));
1834                 else
1835                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1836                                      v_DSP_LUT_EN(1));
1837                 rk3368_lcdc_bcsh_path_sel(dev_drv);
1838                 rk3368_config_timing(dev_drv);
1839         }
1840         spin_unlock(&lcdc_dev->reg_lock);
1841         rk3368_lcdc_set_dclk(dev_drv);
1842         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1843             dev_drv->trsm_ops->enable)
1844                 dev_drv->trsm_ops->enable();
1845         if (screen->init)
1846                 screen->init();
1847         if (!lcdc_dev->standby)
1848                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
1849         return 0;
1850 }
1851
1852
1853 /*enable layer,open:1,enable;0 disable*/
1854 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
1855                                      unsigned int win_id, bool open)
1856 {
1857         spin_lock(&lcdc_dev->reg_lock);
1858         if (likely(lcdc_dev->clk_on) &&
1859             lcdc_dev->driver.win[win_id]->state != open) {
1860                 if (open) {
1861                         if (!lcdc_dev->atv_layer_cnt) {
1862                                 dev_info(lcdc_dev->dev,
1863                                          "wakeup from standby!\n");
1864                                 lcdc_dev->standby = 0;
1865                         }
1866                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
1867                 } else {
1868                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
1869                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
1870                 }
1871                 lcdc_dev->driver.win[win_id]->state = open;
1872                 if (!open) {
1873                         /*rk3368_lcdc_reg_update(dev_drv);*/
1874                         rk3368_lcdc_layer_update_regs
1875                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
1876                         lcdc_cfg_done(lcdc_dev);
1877                 }
1878                 /*if no layer used,disable lcdc */
1879                 if (!lcdc_dev->atv_layer_cnt) {
1880                         dev_info(lcdc_dev->dev,
1881                                  "no layer is used,go to standby!\n");
1882                         lcdc_dev->standby = 1;
1883                 }
1884         }
1885         spin_unlock(&lcdc_dev->reg_lock);
1886 }
1887
1888 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1889 {
1890         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1891                                                     struct lcdc_device, driver);
1892         u32 mask, val;
1893         /*struct rk_screen *screen = dev_drv->cur_screen; */
1894
1895         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
1896             m_LINE_FLAG1_INTR_CLR;
1897         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
1898             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
1899         lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
1900
1901         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN | m_BUS_ERROR_INTR_EN;
1902         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
1903             v_BUS_ERROR_INTR_EN(1);
1904         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1905
1906 #ifdef LCDC_IRQ_EMPTY_DEBUG
1907         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
1908             m_WIN2_EMPTY_INTR_EN |
1909             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
1910             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
1911         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
1912             v_WIN2_EMPTY_INTR_EN(1) |
1913             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
1914             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
1915         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1916 #endif
1917         return 0;
1918 }
1919
1920 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1921                             bool open)
1922 {
1923         struct lcdc_device *lcdc_dev =
1924             container_of(dev_drv, struct lcdc_device, driver);
1925 #if 0/*ndef CONFIG_RK_FPGA*/
1926         int sys_status =
1927             (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
1928 #endif
1929         /*enable clk,when first layer open */
1930         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1931                 /*rockchip_set_system_status(sys_status);*/
1932                 rk3368_lcdc_pre_init(dev_drv);
1933                 rk3368_lcdc_clk_enable(lcdc_dev);
1934 #if defined(CONFIG_ROCKCHIP_IOMMU)
1935                 if (dev_drv->iommu_enabled) {
1936                         if (!dev_drv->mmu_dev) {
1937                                 dev_drv->mmu_dev =
1938                                     rk_fb_get_sysmmu_device_by_compatible
1939                                     (dev_drv->mmu_dts_name);
1940                                 if (dev_drv->mmu_dev) {
1941                                         rk_fb_platform_set_sysmmu
1942                                             (dev_drv->mmu_dev, dev_drv->dev);
1943                                 } else {
1944                                         dev_err(dev_drv->dev,
1945                                                 "fail get rk iommu device\n");
1946                                         return -1;
1947                                 }
1948                         }
1949                         /*if (dev_drv->mmu_dev)
1950                            rockchip_iovmm_activate(dev_drv->dev); */
1951                 }
1952 #endif
1953                 rk3368_lcdc_reg_restore(lcdc_dev);
1954                 /*if (dev_drv->iommu_enabled)
1955                    rk3368_lcdc_mmu_en(dev_drv); */
1956                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
1957                         /*rk3368_lcdc_set_dclk(dev_drv); */
1958                         rk3368_lcdc_enable_irq(dev_drv);
1959                 } else {
1960                         rk3368_load_screen(dev_drv, 1);
1961                 }
1962                 if (dev_drv->bcsh.enable)
1963                         rk3368_lcdc_set_bcsh(dev_drv, 1);
1964                 spin_lock(&lcdc_dev->reg_lock);
1965                 if (dev_drv->cur_screen->dsp_lut)
1966                         rk3368_lcdc_set_lut(dev_drv,
1967                                             dev_drv->cur_screen->dsp_lut);
1968                 spin_unlock(&lcdc_dev->reg_lock);
1969         }
1970
1971         if (win_id < ARRAY_SIZE(lcdc_win))
1972                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
1973         else
1974                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1975
1976
1977         /* when all layer closed,disable clk */
1978         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1979            rk3368_lcdc_disable_irq(lcdc_dev);
1980            rk3368_lcdc_reg_update(dev_drv);
1981            #if defined(CONFIG_ROCKCHIP_IOMMU)
1982            if (dev_drv->iommu_enabled) {
1983            if (dev_drv->mmu_dev)
1984            rockchip_iovmm_deactivate(dev_drv->dev);
1985            }
1986            #endif
1987            rk3368_lcdc_clk_disable(lcdc_dev);
1988            #ifndef CONFIG_RK_FPGA
1989            rockchip_clear_system_status(sys_status);
1990            #endif
1991            } */
1992
1993         return 0;
1994 }
1995
1996 static int win_0_1_display(struct lcdc_device *lcdc_dev,
1997                            struct rk_lcdc_win *win)
1998 {
1999         u32 y_addr;
2000         u32 uv_addr;
2001         unsigned int off;
2002
2003         off = win->id * 0x40;
2004         /*win->smem_start + win->y_offset; */
2005         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2006         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2007         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2008             lcdc_dev->id, win->id, y_addr, uv_addr);
2009         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2010             win->area[0].y_offset, win->area[0].c_offset);
2011         spin_lock(&lcdc_dev->reg_lock);
2012         if (likely(lcdc_dev->clk_on)) {
2013                 win->area[0].y_addr = y_addr;
2014                 win->area[0].uv_addr = uv_addr;
2015                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2016                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2017                 /*lcdc_cfg_done(lcdc_dev); */
2018         }
2019         spin_unlock(&lcdc_dev->reg_lock);
2020
2021         return 0;
2022 }
2023
2024 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2025                            struct rk_lcdc_win *win)
2026 {
2027         u32 i, y_addr;
2028         unsigned int off;
2029
2030         off = (win->id - 2) * 0x50;
2031         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2032         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2033
2034         spin_lock(&lcdc_dev->reg_lock);
2035         if (likely(lcdc_dev->clk_on)) {
2036                 for (i = 0; i < win->area_num; i++) {
2037                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2038                             i, win->area[i].y_addr, win->area[i].y_offset);
2039                         win->area[i].y_addr =
2040                             win->area[i].smem_start + win->area[i].y_offset;
2041                         }
2042                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2043                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2044                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2045                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2046         }
2047         spin_unlock(&lcdc_dev->reg_lock);
2048         return 0;
2049 }
2050
2051 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2052 {
2053         u32 y_addr;
2054
2055         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2056         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2057             lcdc_dev->id, __func__, y_addr);
2058         spin_lock(&lcdc_dev->reg_lock);
2059         if (likely(lcdc_dev->clk_on)) {
2060                 win->area[0].y_addr = y_addr;
2061                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2062         }
2063         spin_unlock(&lcdc_dev->reg_lock);
2064
2065         return 0;
2066 }
2067
2068 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2069 {
2070         struct lcdc_device *lcdc_dev =
2071             container_of(dev_drv, struct lcdc_device, driver);
2072         struct rk_lcdc_win *win = NULL;
2073         struct rk_screen *screen = dev_drv->cur_screen;
2074
2075 #if defined(WAIT_FOR_SYNC)
2076         int timeout;
2077         unsigned long flags;
2078 #endif
2079         win = dev_drv->win[win_id];
2080         if (!screen) {
2081                 dev_err(dev_drv->dev, "screen is null!\n");
2082                 return -ENOENT;
2083         }
2084         if (win_id == 0) {
2085                 win_0_1_display(lcdc_dev, win);
2086         } else if (win_id == 1) {
2087                 win_0_1_display(lcdc_dev, win);
2088         } else if (win_id == 2) {
2089                 win_2_3_display(lcdc_dev, win);
2090         } else if (win_id == 3) {
2091                 win_2_3_display(lcdc_dev, win);
2092         } else if (win_id == 4) {
2093                 hwc_display(lcdc_dev, win);
2094         } else {
2095                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2096                 return -EINVAL;
2097         }
2098
2099         /*this is the first frame of the system ,enable frame start interrupt */
2100         if ((dev_drv->first_frame)) {
2101                 dev_drv->first_frame = 0;
2102                 rk3368_lcdc_enable_irq(dev_drv);
2103         }
2104 #if defined(WAIT_FOR_SYNC)
2105         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2106         init_completion(&dev_drv->frame_done);
2107         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2108         timeout =
2109             wait_for_completion_timeout(&dev_drv->frame_done,
2110                                         msecs_to_jiffies(dev_drv->
2111                                                          cur_screen->ft + 5));
2112         if (!timeout && (!dev_drv->frame_done.done)) {
2113                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2114                 return -ETIMEDOUT;
2115         }
2116 #endif
2117         return 0;
2118 }
2119
2120 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2121 {
2122         u16 srcW;
2123         u16 srcH;
2124         u16 dstW;
2125         u16 dstH;
2126         u16 yrgb_srcW;
2127         u16 yrgb_srcH;
2128         u16 yrgb_dstW;
2129         u16 yrgb_dstH;
2130         u32 yrgb_vscalednmult;
2131         u32 yrgb_xscl_factor;
2132         u32 yrgb_yscl_factor;
2133         u8 yrgb_vsd_bil_gt2 = 0;
2134         u8 yrgb_vsd_bil_gt4 = 0;
2135
2136         u16 cbcr_srcW;
2137         u16 cbcr_srcH;
2138         u16 cbcr_dstW;
2139         u16 cbcr_dstH;
2140         u32 cbcr_vscalednmult;
2141         u32 cbcr_xscl_factor;
2142         u32 cbcr_yscl_factor;
2143         u8 cbcr_vsd_bil_gt2 = 0;
2144         u8 cbcr_vsd_bil_gt4 = 0;
2145         u8 yuv_fmt = 0;
2146
2147         srcW = win->area[0].xact;
2148         srcH = win->area[0].yact;
2149         dstW = win->area[0].xsize;
2150         dstH = win->area[0].ysize;
2151
2152         /*yrgb scl mode */
2153         yrgb_srcW = srcW;
2154         yrgb_srcH = srcH;
2155         yrgb_dstW = dstW;
2156         yrgb_dstH = dstH;
2157         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2158                 pr_err("ERROR: yrgb scale exceed 8,");
2159                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2160                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2161         }
2162         if (yrgb_srcW < yrgb_dstW)
2163                 win->yrgb_hor_scl_mode = SCALE_UP;
2164         else if (yrgb_srcW > yrgb_dstW)
2165                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2166         else
2167                 win->yrgb_hor_scl_mode = SCALE_NONE;
2168
2169         if (yrgb_srcH < yrgb_dstH)
2170                 win->yrgb_ver_scl_mode = SCALE_UP;
2171         else if (yrgb_srcH > yrgb_dstH)
2172                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2173         else
2174                 win->yrgb_ver_scl_mode = SCALE_NONE;
2175
2176         /*cbcr scl mode */
2177         switch (win->area[0].format) {
2178         case YUV422:
2179         case YUV422_A:
2180                 cbcr_srcW = srcW / 2;
2181                 cbcr_dstW = dstW;
2182                 cbcr_srcH = srcH;
2183                 cbcr_dstH = dstH;
2184                 yuv_fmt = 1;
2185                 break;
2186         case YUV420:
2187         case YUV420_A:
2188                 cbcr_srcW = srcW / 2;
2189                 cbcr_dstW = dstW;
2190                 cbcr_srcH = srcH / 2;
2191                 cbcr_dstH = dstH;
2192                 yuv_fmt = 1;
2193                 break;
2194         case YUV444:
2195         case YUV444_A:
2196                 cbcr_srcW = srcW;
2197                 cbcr_dstW = dstW;
2198                 cbcr_srcH = srcH;
2199                 cbcr_dstH = dstH;
2200                 yuv_fmt = 1;
2201                 break;
2202         default:
2203                 cbcr_srcW = 0;
2204                 cbcr_dstW = 0;
2205                 cbcr_srcH = 0;
2206                 cbcr_dstH = 0;
2207                 yuv_fmt = 0;
2208                 break;
2209         }
2210         if (yuv_fmt) {
2211                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2212                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2213                         pr_err("ERROR: cbcr scale exceed 8,");
2214                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2215                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2216                 }
2217         }
2218
2219         if (cbcr_srcW < cbcr_dstW)
2220                 win->cbr_hor_scl_mode = SCALE_UP;
2221         else if (cbcr_srcW > cbcr_dstW)
2222                 win->cbr_hor_scl_mode = SCALE_DOWN;
2223         else
2224                 win->cbr_hor_scl_mode = SCALE_NONE;
2225
2226         if (cbcr_srcH < cbcr_dstH)
2227                 win->cbr_ver_scl_mode = SCALE_UP;
2228         else if (cbcr_srcH > cbcr_dstH)
2229                 win->cbr_ver_scl_mode = SCALE_DOWN;
2230         else
2231                 win->cbr_ver_scl_mode = SCALE_NONE;
2232
2233         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2234             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2235             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2236             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2237             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2238             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2239             win->cbr_ver_scl_mode);*/
2240
2241         /*line buffer mode */
2242         if ((win->area[0].format == YUV422) ||
2243             (win->area[0].format == YUV420) ||
2244             (win->area[0].format == YUV422_A) ||
2245             (win->area[0].format == YUV420_A)) {
2246                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2247                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2248                             (cbcr_dstW == 0))
2249                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2250                                        cbcr_dstW);
2251                         else if (cbcr_dstW > 1280)
2252                                 win->win_lb_mode = LB_YUV_3840X5;
2253                         else
2254                                 win->win_lb_mode = LB_YUV_2560X8;
2255                 } else {        /*SCALE_UP or SCALE_NONE */
2256                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2257                             (cbcr_srcW == 0))
2258                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2259                                        cbcr_srcW);
2260                         else if (cbcr_srcW > 1280)
2261                                 win->win_lb_mode = LB_YUV_3840X5;
2262                         else
2263                                 win->win_lb_mode = LB_YUV_2560X8;
2264                 }
2265         } else {
2266                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2267                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2268                             (yrgb_dstW == 0))
2269                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2270                         else if (yrgb_dstW > 2560)
2271                                 win->win_lb_mode = LB_RGB_3840X2;
2272                         else if (yrgb_dstW > 1920)
2273                                 win->win_lb_mode = LB_RGB_2560X4;
2274                         else if (yrgb_dstW > 1280)
2275                                 win->win_lb_mode = LB_RGB_1920X5;
2276                         else
2277                                 win->win_lb_mode = LB_RGB_1280X8;
2278                 } else {        /*SCALE_UP or SCALE_NONE */
2279                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2280                             (yrgb_srcW == 0))
2281                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2282                         else if (yrgb_srcW > 2560)
2283                                 win->win_lb_mode = LB_RGB_3840X2;
2284                         else if (yrgb_srcW > 1920)
2285                                 win->win_lb_mode = LB_RGB_2560X4;
2286                         else if (yrgb_srcW > 1280)
2287                                 win->win_lb_mode = LB_RGB_1920X5;
2288                         else
2289                                 win->win_lb_mode = LB_RGB_1280X8;
2290                 }
2291         }
2292         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2293
2294         /*vsd/vsu scale ALGORITHM */
2295         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2296         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2297         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2298         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2299         switch (win->win_lb_mode) {
2300         case LB_YUV_3840X5:
2301         case LB_YUV_2560X8:
2302         case LB_RGB_1920X5:
2303         case LB_RGB_1280X8:
2304                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2305                 win->cbr_vsu_mode = SCALE_UP_BIC;
2306                 break;
2307         case LB_RGB_3840X2:
2308                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2309                         pr_err("ERROR : not allow yrgb ver scale\n");
2310                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2311                         pr_err("ERROR : not allow cbcr ver scale\n");
2312                 break;
2313         case LB_RGB_2560X4:
2314                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2315                 win->cbr_vsu_mode = SCALE_UP_BIL;
2316                 break;
2317         default:
2318                 pr_info("%s:un supported win_lb_mode:%d\n",
2319                         __func__, win->win_lb_mode);
2320                 break;
2321         }
2322         if (win->mirror_en == 1) {      /*interlace mode must bill */
2323                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2324         }
2325
2326         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2327             (win->area[0].fbdc_en == 1)) {
2328                 /*in this pattern,use bil mode,not support souble scd,
2329                 use avg mode, support double scd, but aclk should be
2330                 bigger than dclk,aclk>>dclk */
2331                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2332                         pr_err("ERROR : fbdc mode,not support y scale down:");
2333                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2334                                yrgb_srcH, yrgb_dstH);
2335                 }
2336         }
2337         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2338             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2339             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2340
2341         /*SCALE FACTOR */
2342
2343         /*(1.1)YRGB HOR SCALE FACTOR */
2344         switch (win->yrgb_hor_scl_mode) {
2345         case SCALE_NONE:
2346                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2347                 break;
2348         case SCALE_UP:
2349                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2350                 break;
2351         case SCALE_DOWN:
2352                 switch (win->yrgb_hsd_mode) {
2353                 case SCALE_DOWN_BIL:
2354                         yrgb_xscl_factor =
2355                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2356                         break;
2357                 case SCALE_DOWN_AVG:
2358                         yrgb_xscl_factor =
2359                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2360                         break;
2361                 default:
2362                         pr_info(
2363                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2364                                win->yrgb_hsd_mode);
2365                         break;
2366                 }
2367                 break;
2368         default:
2369                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2370                         __func__, win->yrgb_hor_scl_mode);
2371                 break;
2372         }                       /*win->yrgb_hor_scl_mode */
2373
2374         /*(1.2)YRGB VER SCALE FACTOR */
2375         switch (win->yrgb_ver_scl_mode) {
2376         case SCALE_NONE:
2377                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2378                 break;
2379         case SCALE_UP:
2380                 switch (win->yrgb_vsu_mode) {
2381                 case SCALE_UP_BIL:
2382                         yrgb_yscl_factor =
2383                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2384                         break;
2385                 case SCALE_UP_BIC:
2386                         if (yrgb_srcH < 3) {
2387                                 pr_err("yrgb_srcH should be");
2388                                 pr_err(" greater than 3 !!!\n");
2389                         }
2390                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2391                                                                 yrgb_dstH);
2392                         break;
2393                 default:
2394                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2395                                 __func__, win->yrgb_vsu_mode);
2396                         break;
2397                 }
2398                 break;
2399         case SCALE_DOWN:
2400                 switch (win->yrgb_vsd_mode) {
2401                 case SCALE_DOWN_BIL:
2402                         yrgb_vscalednmult =
2403                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2404                                                             yrgb_dstH);
2405                         yrgb_yscl_factor =
2406                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2407                                                            yrgb_vscalednmult);
2408                         if (yrgb_yscl_factor >= 0x2000) {
2409                                 pr_err("yrgb_yscl_factor should be ");
2410                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2411                                        yrgb_yscl_factor);
2412                         }
2413                         if (yrgb_vscalednmult == 4) {
2414                                 yrgb_vsd_bil_gt4 = 1;
2415                                 yrgb_vsd_bil_gt2 = 0;
2416                         } else if (yrgb_vscalednmult == 2) {
2417                                 yrgb_vsd_bil_gt4 = 0;
2418                                 yrgb_vsd_bil_gt2 = 1;
2419                         } else {
2420                                 yrgb_vsd_bil_gt4 = 0;
2421                                 yrgb_vsd_bil_gt2 = 0;
2422                         }
2423                         break;
2424                 case SCALE_DOWN_AVG:
2425                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2426                                                                  yrgb_dstH);
2427                         break;
2428                 default:
2429                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2430                                 __func__, win->yrgb_vsd_mode);
2431                         break;
2432                 }               /*win->yrgb_vsd_mode */
2433                 break;
2434         default:
2435                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2436                         __func__, win->yrgb_ver_scl_mode);
2437                 break;
2438         }
2439         win->scale_yrgb_x = yrgb_xscl_factor;
2440         win->scale_yrgb_y = yrgb_yscl_factor;
2441         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2442         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2443         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2444             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2445
2446         /*(2.1)CBCR HOR SCALE FACTOR */
2447         switch (win->cbr_hor_scl_mode) {
2448         case SCALE_NONE:
2449                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2450                 break;
2451         case SCALE_UP:
2452                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2453                 break;
2454         case SCALE_DOWN:
2455                 switch (win->cbr_hsd_mode) {
2456                 case SCALE_DOWN_BIL:
2457                         cbcr_xscl_factor =
2458                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2459                         break;
2460                 case SCALE_DOWN_AVG:
2461                         cbcr_xscl_factor =
2462                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2463                         break;
2464                 default:
2465                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2466                                 __func__, win->cbr_hsd_mode);
2467                         break;
2468                 }
2469                 break;
2470         default:
2471                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2472                         __func__, win->cbr_hor_scl_mode);
2473                 break;
2474         }                       /*win->cbr_hor_scl_mode */
2475
2476         /*(2.2)CBCR VER SCALE FACTOR */
2477         switch (win->cbr_ver_scl_mode) {
2478         case SCALE_NONE:
2479                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2480                 break;
2481         case SCALE_UP:
2482                 switch (win->cbr_vsu_mode) {
2483                 case SCALE_UP_BIL:
2484                         cbcr_yscl_factor =
2485                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2486                         break;
2487                 case SCALE_UP_BIC:
2488                         if (cbcr_srcH < 3) {
2489                                 pr_err("cbcr_srcH should be ");
2490                                 pr_err("greater than 3 !!!\n");
2491                         }
2492                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2493                                                                 cbcr_dstH);
2494                         break;
2495                 default:
2496                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2497                                 __func__, win->cbr_vsu_mode);
2498                         break;
2499                 }
2500                 break;
2501         case SCALE_DOWN:
2502                 switch (win->cbr_vsd_mode) {
2503                 case SCALE_DOWN_BIL:
2504                         cbcr_vscalednmult =
2505                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2506                                                             cbcr_dstH);
2507                         cbcr_yscl_factor =
2508                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2509                                                            cbcr_vscalednmult);
2510                         if (cbcr_yscl_factor >= 0x2000) {
2511                                 pr_err("cbcr_yscl_factor should be less ");
2512                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2513                                        cbcr_yscl_factor);
2514                         }
2515
2516                         if (cbcr_vscalednmult == 4) {
2517                                 cbcr_vsd_bil_gt4 = 1;
2518                                 cbcr_vsd_bil_gt2 = 0;
2519                         } else if (cbcr_vscalednmult == 2) {
2520                                 cbcr_vsd_bil_gt4 = 0;
2521                                 cbcr_vsd_bil_gt2 = 1;
2522                         } else {
2523                                 cbcr_vsd_bil_gt4 = 0;
2524                                 cbcr_vsd_bil_gt2 = 0;
2525                         }
2526                         break;
2527                 case SCALE_DOWN_AVG:
2528                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2529                                                                  cbcr_dstH);
2530                         break;
2531                 default:
2532                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2533                                 __func__, win->cbr_vsd_mode);
2534                         break;
2535                 }
2536                 break;
2537         default:
2538                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2539                         __func__, win->cbr_ver_scl_mode);
2540                 break;
2541         }
2542         win->scale_cbcr_x = cbcr_xscl_factor;
2543         win->scale_cbcr_y = cbcr_yscl_factor;
2544         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2545         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2546
2547         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2548             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2549         return 0;
2550 }
2551
2552 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2553                      struct rk_lcdc_win_area *area)
2554 {
2555         int pos;
2556
2557         if (screen->x_mirror && mirror_en)
2558                 pr_err("not support both win and global mirror\n");
2559
2560         if ((!mirror_en) && (!screen->x_mirror))
2561                 pos = area->xpos + screen->mode.left_margin +
2562                         screen->mode.hsync_len;
2563         else
2564                 pos = screen->mode.xres - area->xpos -
2565                         area->xsize + screen->mode.left_margin +
2566                         screen->mode.hsync_len;
2567
2568         return pos;
2569 }
2570
2571 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2572                      struct rk_lcdc_win_area *area)
2573 {
2574         int pos;
2575
2576         if (screen->y_mirror && mirror_en)
2577                 pr_err("not support both win and global mirror\n");
2578
2579         if ((!mirror_en) && (!screen->y_mirror))
2580                 pos = area->ypos + screen->mode.upper_margin +
2581                         screen->mode.vsync_len;
2582         else
2583                 pos = screen->mode.yres - area->ypos -
2584                         area->ysize + screen->mode.upper_margin +
2585                         screen->mode.vsync_len;
2586
2587         return pos;
2588 }
2589
2590 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2591                            struct rk_screen *screen, struct rk_lcdc_win *win)
2592 {
2593         u32 xact, yact, xvir, yvir, xpos, ypos;
2594         u8 fmt_cfg = 0, swap_rb;
2595         char fmt[9] = "NULL";
2596
2597         xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2598         ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2599
2600         spin_lock(&lcdc_dev->reg_lock);
2601         if (likely(lcdc_dev->clk_on)) {
2602                 rk3368_lcdc_cal_scl_fac(win);   /*fac,lb,gt2,gt4 */
2603                 switch (win->area[0].format) {
2604                 case FBDC_RGB_565:
2605                         fmt_cfg = 2;
2606                         swap_rb = 0;
2607                         win->fmt_10 = 0;
2608                         win->area[0].fbdc_fmt_cfg = 0x05;
2609                         break;
2610                 case FBDC_ARGB_888:
2611                         fmt_cfg = 0;
2612                         swap_rb = 0;
2613                         win->fmt_10 = 0;
2614                         win->area[0].fbdc_fmt_cfg = 0x0c;
2615                         break;
2616                 case FBDC_RGBX_888:
2617                         fmt_cfg = 0;
2618                         swap_rb = 0;
2619                         win->fmt_10 = 0;
2620                         win->area[0].fbdc_fmt_cfg = 0x3a;
2621                         break;
2622                 case ARGB888:
2623                         fmt_cfg = 0;
2624                         swap_rb = 0;
2625                         win->fmt_10 = 0;
2626                         break;
2627                 case XBGR888:
2628                 case ABGR888:
2629                         fmt_cfg = 0;
2630                         swap_rb = 1;
2631                         win->fmt_10 = 0;
2632                         break;
2633                 case RGB888:
2634                         fmt_cfg = 1;
2635                         swap_rb = 0;
2636                         win->fmt_10 = 0;
2637                         break;
2638                 case RGB565:
2639                         fmt_cfg = 2;
2640                         swap_rb = 0;
2641                         win->fmt_10 = 0;
2642                         break;
2643                 case YUV422:
2644                         fmt_cfg = 5;
2645                         swap_rb = 0;
2646                         win->fmt_10 = 0;
2647                         break;
2648                 case YUV420:
2649                         fmt_cfg = 4;
2650                         swap_rb = 0;
2651                         win->fmt_10 = 0;
2652                         break;
2653                 case YUV444:
2654                         fmt_cfg = 6;
2655                         swap_rb = 0;
2656                         win->fmt_10 = 0;
2657                         break;
2658                 case YUV422_A:
2659                         fmt_cfg = 5;
2660                         swap_rb = 0;
2661                         win->fmt_10 = 1;
2662                         break;
2663                 case YUV420_A:
2664                         fmt_cfg = 4;
2665                         swap_rb = 0;
2666                         win->fmt_10 = 1;
2667                         break;
2668                 case YUV444_A:
2669                         fmt_cfg = 6;
2670                         swap_rb = 0;
2671                         win->fmt_10 = 1;
2672                         break;
2673                 default:
2674                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2675                                 __func__);
2676                         break;
2677                 }
2678                 win->area[0].fmt_cfg = fmt_cfg;
2679                 win->area[0].swap_rb = swap_rb;
2680                 win->area[0].dsp_stx = xpos;
2681                 win->area[0].dsp_sty = ypos;
2682                 xact = win->area[0].xact;
2683                 yact = win->area[0].yact;
2684                 xvir = win->area[0].xvir;
2685                 yvir = win->area[0].yvir;
2686         }
2687         if (win->area[0].fbdc_en)
2688                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2689         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2690         spin_unlock(&lcdc_dev->reg_lock);
2691
2692         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2693             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2694             xact, yact, win->area[0].xsize);
2695         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2696             win->area[0].ysize, xvir, yvir, xpos, ypos);
2697
2698         return 0;
2699 }
2700
2701
2702 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2703                            struct rk_screen *screen, struct rk_lcdc_win *win)
2704 {
2705         int i;
2706         u8 fmt_cfg, swap_rb;
2707         char fmt[9] = "NULL";
2708
2709         if (win->mirror_en)
2710                 pr_err("win[%d] not support y mirror\n", win->id);
2711         spin_lock(&lcdc_dev->reg_lock);
2712         if (likely(lcdc_dev->clk_on)) {
2713                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2714                 for (i = 0; i < win->area_num; i++) {
2715                         switch (win->area[i].format) {
2716                         case FBDC_RGB_565:
2717                                 fmt_cfg = 2;
2718                                 swap_rb = 0;
2719                                 win->fmt_10 = 0;
2720                                 win->area[0].fbdc_fmt_cfg = 0x05;
2721                                 break;
2722                         case FBDC_ARGB_888:
2723                                 fmt_cfg = 0;
2724                                 swap_rb = 0;
2725                                 win->fmt_10 = 0;
2726                                 win->area[0].fbdc_fmt_cfg = 0x0c;
2727                                 break;
2728                         case FBDC_RGBX_888:
2729                                 fmt_cfg = 0;
2730                                 swap_rb = 0;
2731                                 win->fmt_10 = 0;
2732                                 win->area[0].fbdc_fmt_cfg = 0x3a;
2733                                 break;
2734                         case ARGB888:
2735                                 fmt_cfg = 0;
2736                                 swap_rb = 0;
2737                                 break;
2738                         case XBGR888:
2739                         case ABGR888:
2740                                 fmt_cfg = 0;
2741                                 swap_rb = 1;
2742                                 break;
2743                         case RGB888:
2744                                 fmt_cfg = 1;
2745                                 swap_rb = 0;
2746                                 break;
2747                         case RGB565:
2748                                 fmt_cfg = 2;
2749                                 swap_rb = 0;
2750                                 break;
2751                         default:
2752                                 dev_err(lcdc_dev->driver.dev,
2753                                         "%s:un supported format!\n", __func__);
2754                                 break;
2755                         }
2756                         win->area[i].fmt_cfg = fmt_cfg;
2757                         win->area[i].swap_rb = swap_rb;
2758                         win->area[i].dsp_stx =
2759                                         dsp_x_pos(win->mirror_en, screen,
2760                                                   &win->area[i]);
2761                         win->area[i].dsp_sty =
2762                                         dsp_y_pos(win->mirror_en, screen,
2763                                                   &win->area[i]);
2764
2765                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
2766                             get_format_string(win->area[i].format, fmt),
2767                             win->area[i].xsize, win->area[i].ysize,
2768                             win->area[i].xpos, win->area[i].ypos);
2769                 }
2770         }
2771         if (win->area[0].fbdc_en)
2772                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2773         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
2774         spin_unlock(&lcdc_dev->reg_lock);
2775         return 0;
2776 }
2777
2778 static int hwc_set_par(struct lcdc_device *lcdc_dev,
2779                        struct rk_screen *screen, struct rk_lcdc_win *win)
2780 {
2781         u32 xact, yact, xvir, yvir, xpos, ypos;
2782         u8 fmt_cfg = 0, swap_rb;
2783         char fmt[9] = "NULL";
2784
2785         xpos = win->area[0].xpos + screen->mode.left_margin +
2786             screen->mode.hsync_len;
2787         ypos = win->area[0].ypos + screen->mode.upper_margin +
2788             screen->mode.vsync_len;
2789
2790         spin_lock(&lcdc_dev->reg_lock);
2791         if (likely(lcdc_dev->clk_on)) {
2792                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
2793                 switch (win->area[0].format) {
2794                 case ARGB888:
2795                         fmt_cfg = 0;
2796                         swap_rb = 0;
2797                         break;
2798                 case XBGR888:
2799                 case ABGR888:
2800                         fmt_cfg = 0;
2801                         swap_rb = 1;
2802                         break;
2803                 case RGB888:
2804                         fmt_cfg = 1;
2805                         swap_rb = 0;
2806                         break;
2807                 case RGB565:
2808                         fmt_cfg = 2;
2809                         swap_rb = 0;
2810                         break;
2811                 default:
2812                         dev_err(lcdc_dev->driver.dev,
2813                                 "%s:un supported format!\n", __func__);
2814                         break;
2815                 }
2816                 win->area[0].fmt_cfg = fmt_cfg;
2817                 win->area[0].swap_rb = swap_rb;
2818                 win->area[0].dsp_stx = xpos;
2819                 win->area[0].dsp_sty = ypos;
2820                 xact = win->area[0].xact;
2821                 yact = win->area[0].yact;
2822                 xvir = win->area[0].xvir;
2823                 yvir = win->area[0].yvir;
2824         }
2825         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
2826         spin_unlock(&lcdc_dev->reg_lock);
2827
2828         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2829             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2830             xact, yact, win->area[0].xsize);
2831         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2832             win->area[0].ysize, xvir, yvir, xpos, ypos);
2833         return 0;
2834 }
2835
2836 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2837 {
2838         struct lcdc_device *lcdc_dev =
2839             container_of(dev_drv, struct lcdc_device, driver);
2840         struct rk_lcdc_win *win = NULL;
2841         struct rk_screen *screen = dev_drv->cur_screen;
2842
2843         win = dev_drv->win[win_id];
2844         switch (win_id) {
2845         case 0:
2846                 win_0_1_set_par(lcdc_dev, screen, win);
2847                 break;
2848         case 1:
2849                 win_0_1_set_par(lcdc_dev, screen, win);
2850                 break;
2851         case 2:
2852                 win_2_3_set_par(lcdc_dev, screen, win);
2853                 break;
2854         case 3:
2855                 win_2_3_set_par(lcdc_dev, screen, win);
2856                 break;
2857         case 4:
2858                 hwc_set_par(lcdc_dev, screen, win);
2859                 break;
2860         default:
2861                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2862                 break;
2863         }
2864         return 0;
2865 }
2866
2867 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2868                              unsigned long arg, int win_id)
2869 {
2870         struct lcdc_device *lcdc_dev =
2871             container_of(dev_drv, struct lcdc_device, driver);
2872         u32 panel_size[2];
2873         void __user *argp = (void __user *)arg;
2874         struct color_key_cfg clr_key_cfg;
2875
2876         switch (cmd) {
2877         case RK_FBIOGET_PANEL_SIZE:
2878                 panel_size[0] = lcdc_dev->screen->mode.xres;
2879                 panel_size[1] = lcdc_dev->screen->mode.yres;
2880                 if (copy_to_user(argp, panel_size, 8))
2881                         return -EFAULT;
2882                 break;
2883         case RK_FBIOPUT_COLOR_KEY_CFG:
2884                 if (copy_from_user(&clr_key_cfg, argp,
2885                                    sizeof(struct color_key_cfg)))
2886                         return -EFAULT;
2887                 rk3368_lcdc_clr_key_cfg(dev_drv);
2888                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2889                             clr_key_cfg.win0_color_key_cfg);
2890                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2891                             clr_key_cfg.win1_color_key_cfg);
2892                 break;
2893
2894         default:
2895                 break;
2896         }
2897         return 0;
2898 }
2899
2900 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2901 {
2902         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2903                                                     struct lcdc_device, driver);
2904         /*struct device_node *backlight;*/
2905
2906         if (lcdc_dev->backlight)
2907                 return 0;
2908 #if 0
2909         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
2910         if (backlight) {
2911                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
2912                 if (!lcdc_dev->backlight)
2913                         dev_info(lcdc_dev->dev, "No find backlight device\n");
2914         } else {
2915                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
2916         }
2917 #endif
2918         return 0;
2919 }
2920
2921 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
2922 {
2923         u32 reg;
2924         struct lcdc_device *lcdc_dev =
2925             container_of(dev_drv, struct lcdc_device, driver);
2926         if (dev_drv->suspend_flag)
2927                 return 0;
2928         /* close the backlight */
2929         /*rk3368_lcdc_get_backlight_device(dev_drv);
2930         if (lcdc_dev->backlight) {
2931                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
2932                 backlight_update_status(lcdc_dev->backlight);
2933         }*/
2934
2935         dev_drv->suspend_flag = 1;
2936         flush_kthread_worker(&dev_drv->update_regs_worker);
2937
2938         for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg += 4)
2939                 lcdc_readl_backup(lcdc_dev, reg);
2940         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2941                 dev_drv->trsm_ops->disable();
2942
2943         spin_lock(&lcdc_dev->reg_lock);
2944         if (likely(lcdc_dev->clk_on)) {
2945                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2946                              v_DSP_BLANK_EN(1));
2947                 lcdc_msk_reg(lcdc_dev,
2948                              INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
2949                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
2950                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2951                              v_DSP_OUT_ZERO(1));
2952                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
2953                 lcdc_cfg_done(lcdc_dev);
2954
2955                 if (dev_drv->iommu_enabled) {
2956                         if (dev_drv->mmu_dev)
2957                                 rockchip_iovmm_deactivate(dev_drv->dev);
2958                 }
2959
2960                 spin_unlock(&lcdc_dev->reg_lock);
2961         } else {
2962                 spin_unlock(&lcdc_dev->reg_lock);
2963                 return 0;
2964         }
2965         rk3368_lcdc_clk_disable(lcdc_dev);
2966         rk_disp_pwr_disable(dev_drv);
2967         return 0;
2968 }
2969
2970 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
2971 {
2972         struct lcdc_device *lcdc_dev =
2973             container_of(dev_drv, struct lcdc_device, driver);
2974
2975         if (!dev_drv->suspend_flag)
2976                 return 0;
2977         rk_disp_pwr_enable(dev_drv);
2978         dev_drv->suspend_flag = 0;
2979
2980         if (1/*lcdc_dev->atv_layer_cnt*/) {
2981                 rk3368_lcdc_clk_enable(lcdc_dev);
2982                 rk3368_lcdc_reg_restore(lcdc_dev);
2983
2984                 spin_lock(&lcdc_dev->reg_lock);
2985                 if (dev_drv->cur_screen->dsp_lut)
2986                         rk3368_lcdc_set_lut(dev_drv,
2987                                             dev_drv->cur_screen->dsp_lut);
2988
2989                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2990                              v_DSP_OUT_ZERO(0));
2991                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
2992                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2993                              v_DSP_BLANK_EN(0));
2994                 lcdc_cfg_done(lcdc_dev);
2995
2996                 if (dev_drv->iommu_enabled) {
2997                         if (dev_drv->mmu_dev)
2998                                 rockchip_iovmm_activate(dev_drv->dev);
2999                 }
3000
3001                 spin_unlock(&lcdc_dev->reg_lock);
3002         }
3003
3004         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3005                 dev_drv->trsm_ops->enable();
3006
3007         return 0;
3008 }
3009
3010 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
3011                              int win_id, int blank_mode)
3012 {
3013         switch (blank_mode) {
3014         case FB_BLANK_UNBLANK:
3015                 rk3368_lcdc_early_resume(dev_drv);
3016                 break;
3017         case FB_BLANK_NORMAL:
3018                 rk3368_lcdc_early_suspend(dev_drv);
3019                 break;
3020         default:
3021                 rk3368_lcdc_early_suspend(dev_drv);
3022                 break;
3023         }
3024
3025         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3026
3027         return 0;
3028 }
3029
3030 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
3031 {
3032         return 0;
3033 }
3034
3035 /*overlay will be do at regupdate*/
3036 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
3037                                bool set)
3038 {
3039         struct lcdc_device *lcdc_dev =
3040             container_of(dev_drv, struct lcdc_device, driver);
3041         struct rk_lcdc_win *win = NULL;
3042         int i, ovl;
3043         unsigned int mask, val;
3044         int z_order_num = 0;
3045         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3046
3047         if (swap == 0) {
3048                 for (i = 0; i < 4; i++) {
3049                         win = dev_drv->win[i];
3050                         if (win->state == 1)
3051                                 z_order_num++;
3052                 }
3053                 for (i = 0; i < 4; i++) {
3054                         win = dev_drv->win[i];
3055                         if (win->state == 0)
3056                                 win->z_order = z_order_num++;
3057                         switch (win->z_order) {
3058                         case 0:
3059                                 layer0_sel = win->id;
3060                                 break;
3061                         case 1:
3062                                 layer1_sel = win->id;
3063                                 break;
3064                         case 2:
3065                                 layer2_sel = win->id;
3066                                 break;
3067                         case 3:
3068                                 layer3_sel = win->id;
3069                                 break;
3070                         default:
3071                                 break;
3072                         }
3073                 }
3074         } else {
3075                 layer0_sel = swap % 10;
3076                 layer1_sel = swap / 10 % 10;
3077                 layer2_sel = swap / 100 % 10;
3078                 layer3_sel = swap / 1000;
3079         }
3080
3081         spin_lock(&lcdc_dev->reg_lock);
3082         if (lcdc_dev->clk_on) {
3083                 if (set) {
3084                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3085                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3086                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3087                             v_DSP_LAYER1_SEL(layer1_sel) |
3088                             v_DSP_LAYER2_SEL(layer2_sel) |
3089                             v_DSP_LAYER3_SEL(layer3_sel);
3090                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3091                 } else {
3092                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3093                                                    m_DSP_LAYER0_SEL);
3094                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3095                                                    m_DSP_LAYER1_SEL);
3096                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3097                                                    m_DSP_LAYER2_SEL);
3098                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3099                                                    m_DSP_LAYER3_SEL);
3100                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3101                             layer1_sel * 10 + layer0_sel;
3102                 }
3103         } else {
3104                 ovl = -EPERM;
3105         }
3106         spin_unlock(&lcdc_dev->reg_lock);
3107
3108         return ovl;
3109 }
3110
3111 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3112 {
3113         if (!fmt)
3114                 return NULL;
3115
3116         switch (format) {
3117         case 0:
3118                 strcpy(fmt, "ARGB888");
3119                 break;
3120         case 1:
3121                 strcpy(fmt, "RGB888");
3122                 break;
3123         case 2:
3124                 strcpy(fmt, "RGB565");
3125                 break;
3126         case 4:
3127                 strcpy(fmt, "YCbCr420");
3128                 break;
3129         case 5:
3130                 strcpy(fmt, "YCbCr422");
3131                 break;
3132         case 6:
3133                 strcpy(fmt, "YCbCr444");
3134                 break;
3135         default:
3136                 strcpy(fmt, "invalid\n");
3137                 break;
3138         }
3139         return fmt;
3140 }
3141 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3142                                          char *buf, int win_id)
3143 {
3144         struct lcdc_device *lcdc_dev =
3145             container_of(dev_drv, struct lcdc_device, driver);
3146         struct rk_screen *screen = dev_drv->cur_screen;
3147         u16 hsync_len = screen->mode.hsync_len;
3148         u16 left_margin = screen->mode.left_margin;
3149         u16 vsync_len = screen->mode.vsync_len;
3150         u16 upper_margin = screen->mode.upper_margin;
3151         u32 h_pw_bp = hsync_len + left_margin;
3152         u32 v_pw_bp = vsync_len + upper_margin;
3153         u32 fmt_id;
3154         char format_w0[9] = "NULL";
3155         char format_w1[9] = "NULL";
3156         char format_w2_0[9] = "NULL";
3157         char format_w2_1[9] = "NULL";
3158         char format_w2_2[9] = "NULL";
3159         char format_w2_3[9] = "NULL";
3160         char format_w3_0[9] = "NULL";
3161         char format_w3_1[9] = "NULL";
3162         char format_w3_2[9] = "NULL";
3163         char format_w3_3[9] = "NULL";
3164         char dsp_buf[100];
3165         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3166         u32 y_factor, uv_factor;
3167         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3168         u8 w0_state, w1_state, w2_state, w3_state;
3169         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3170         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3171
3172         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3173         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3174         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3175         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3176         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3177         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3178
3179         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3180         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3181         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3182         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3183         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3184         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3185         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3186
3187         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3188         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3189         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3190         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3191         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3192         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3193         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3194         u32 dclk_freq;
3195         int size = 0;
3196
3197         dclk_freq = screen->mode.pixclock;
3198         /*rk3368_lcdc_reg_dump(dev_drv); */
3199
3200         spin_lock(&lcdc_dev->reg_lock);
3201         if (lcdc_dev->clk_on) {
3202                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3203                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3204                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3205                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3206                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3207                 /*WIN0 */
3208                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3209                 w0_state = win_ctrl & m_WIN0_EN;
3210                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3211                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3212                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3213                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3214                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3215                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3216                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3217                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3218                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3219                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3220                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3221                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3222                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3223                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3224                 if (w0_state) {
3225                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3226                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3227                 }
3228                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3229                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3230                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3231                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3232
3233                 /*WIN1 */
3234                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3235                 w1_state = win_ctrl & m_WIN1_EN;
3236                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3237                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3238                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3239                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3240                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3241                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3242                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3243                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3244                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3245                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3246                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3247                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3248                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3249                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3250                 if (w1_state) {
3251                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3252                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3253                 }
3254                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3255                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3256                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3257                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3258                 /*WIN2 */
3259                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3260                 w2_state = win_ctrl & m_WIN2_EN;
3261                 w2_0_state = (win_ctrl & m_WIN2_MST0_EN) >> 4;
3262                 w2_1_state = (win_ctrl & m_WIN2_MST1_EN) >> 5;
3263                 w2_2_state = (win_ctrl & m_WIN2_MST2_EN) >> 6;
3264                 w2_3_state = (win_ctrl & m_WIN2_MST3_EN) >> 7;
3265                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3266                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3267                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3268                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3269                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3270                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3271
3272                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3273                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3274                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3275                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3276                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3277                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3278                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3279                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3280
3281                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3282                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3283                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3284                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3285                 if (w2_0_state) {
3286                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3287                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3288                 }
3289                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3290                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3291                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3292                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3293                 if (w2_1_state) {
3294                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3295                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3296                 }
3297                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3298                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3299                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3300                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3301                 if (w2_2_state) {
3302                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3303                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3304                 }
3305                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3306                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3307                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3308                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3309                 if (w2_3_state) {
3310                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3311                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3312                 }
3313
3314                 /*WIN3 */
3315                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3316                 w3_state = win_ctrl & m_WIN3_EN;
3317                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3318                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 5;
3319                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 6;
3320                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 7;
3321                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3322                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3323                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3324                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3325                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3326                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3327                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3328                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3329                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3330                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3331                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3332                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3333                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3334                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3335                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3336                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3337                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3338                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3339                 if (w3_0_state) {
3340                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3341                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3342                 }
3343
3344                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3345                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3346                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3347                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3348                 if (w3_1_state) {
3349                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3350                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3351                 }
3352
3353                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3354                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3355                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3356                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3357                 if (w3_2_state) {
3358                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3359                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3360                 }
3361
3362                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3363                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3364                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3365                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3366                 if (w3_3_state) {
3367                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3368                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3369                 }
3370
3371         } else {
3372                 spin_unlock(&lcdc_dev->reg_lock);
3373                 return -EPERM;
3374         }
3375         spin_unlock(&lcdc_dev->reg_lock);
3376         size += snprintf(dsp_buf, 80,
3377                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3378                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3379         strcat(buf, dsp_buf);
3380         memset(dsp_buf, 0, sizeof(dsp_buf));
3381         /*win0*/
3382         size += snprintf(dsp_buf, 80,
3383                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3384                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3385         strcat(buf, dsp_buf);
3386         memset(dsp_buf, 0, sizeof(dsp_buf));
3387
3388         size += snprintf(dsp_buf, 80,
3389                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3390                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3391         strcat(buf, dsp_buf);
3392         memset(dsp_buf, 0, sizeof(dsp_buf));
3393
3394         size += snprintf(dsp_buf, 80,
3395                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3396                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3397         strcat(buf, dsp_buf);
3398         memset(dsp_buf, 0, sizeof(dsp_buf));
3399
3400         size += snprintf(dsp_buf, 80,
3401                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3402                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3403                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3404         strcat(buf, dsp_buf);
3405         memset(dsp_buf, 0, sizeof(dsp_buf));
3406
3407         /*win1*/
3408         size += snprintf(dsp_buf, 80,
3409                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3410                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3411         strcat(buf, dsp_buf);
3412         memset(dsp_buf, 0, sizeof(dsp_buf));
3413
3414         size += snprintf(dsp_buf, 80,
3415                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3416                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3417         strcat(buf, dsp_buf);
3418         memset(dsp_buf, 0, sizeof(dsp_buf));
3419
3420         size += snprintf(dsp_buf, 80,
3421                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3422                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3423         strcat(buf, dsp_buf);
3424         memset(dsp_buf, 0, sizeof(dsp_buf));
3425
3426         size += snprintf(dsp_buf, 80,
3427                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3428                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3429                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3430         strcat(buf, dsp_buf);
3431         memset(dsp_buf, 0, sizeof(dsp_buf));
3432
3433         /*win2*/
3434         size += snprintf(dsp_buf, 80,
3435                  "win2:\n  state:%d\n",
3436                  w2_state);
3437         strcat(buf, dsp_buf);
3438         memset(dsp_buf, 0, sizeof(dsp_buf));
3439         /*area 0*/
3440         size += snprintf(dsp_buf, 80,
3441                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3442                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3443         strcat(buf, dsp_buf);
3444         memset(dsp_buf, 0, sizeof(dsp_buf));
3445         size += snprintf(dsp_buf, 80,
3446                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3447                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3448                  lcdc_readl(lcdc_dev, WIN2_MST0));
3449         strcat(buf, dsp_buf);
3450         memset(dsp_buf, 0, sizeof(dsp_buf));
3451
3452         /*area 1*/
3453         size += snprintf(dsp_buf, 80,
3454                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3455                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3456         strcat(buf, dsp_buf);
3457         memset(dsp_buf, 0, sizeof(dsp_buf));
3458         size += snprintf(dsp_buf, 80,
3459                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3460                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3461                  lcdc_readl(lcdc_dev, WIN2_MST1));
3462         strcat(buf, dsp_buf);
3463         memset(dsp_buf, 0, sizeof(dsp_buf));
3464
3465         /*area 2*/
3466         size += snprintf(dsp_buf, 80,
3467                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3468                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3469         strcat(buf, dsp_buf);
3470         memset(dsp_buf, 0, sizeof(dsp_buf));
3471         size += snprintf(dsp_buf, 80,
3472                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3473                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3474                  lcdc_readl(lcdc_dev, WIN2_MST2));
3475         strcat(buf, dsp_buf);
3476         memset(dsp_buf, 0, sizeof(dsp_buf));
3477
3478         /*area 3*/
3479         size += snprintf(dsp_buf, 80,
3480                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3481                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3482         strcat(buf, dsp_buf);
3483         memset(dsp_buf, 0, sizeof(dsp_buf));
3484         size += snprintf(dsp_buf, 80,
3485                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3486                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3487                  lcdc_readl(lcdc_dev, WIN2_MST3));
3488         strcat(buf, dsp_buf);
3489         memset(dsp_buf, 0, sizeof(dsp_buf));
3490
3491         /*win3*/
3492         size += snprintf(dsp_buf, 80,
3493                  "win3:\n  state:%d\n",
3494                  w3_state);
3495         strcat(buf, dsp_buf);
3496         memset(dsp_buf, 0, sizeof(dsp_buf));
3497         /*area 0*/
3498         size += snprintf(dsp_buf, 80,
3499                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3500                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3501         strcat(buf, dsp_buf);
3502         memset(dsp_buf, 0, sizeof(dsp_buf));
3503         size += snprintf(dsp_buf, 80,
3504                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3505                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3506                  lcdc_readl(lcdc_dev, WIN3_MST0));
3507         strcat(buf, dsp_buf);
3508         memset(dsp_buf, 0, sizeof(dsp_buf));
3509
3510         /*area 1*/
3511         size += snprintf(dsp_buf, 80,
3512                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3513                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3514         strcat(buf, dsp_buf);
3515         memset(dsp_buf, 0, sizeof(dsp_buf));
3516         size += snprintf(dsp_buf, 80,
3517                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3518                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3519                  lcdc_readl(lcdc_dev, WIN3_MST1));
3520         strcat(buf, dsp_buf);
3521         memset(dsp_buf, 0, sizeof(dsp_buf));
3522
3523         /*area 2*/
3524         size += snprintf(dsp_buf, 80,
3525                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3526                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3527         strcat(buf, dsp_buf);
3528         memset(dsp_buf, 0, sizeof(dsp_buf));
3529         size += snprintf(dsp_buf, 80,
3530                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3531                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3532                  lcdc_readl(lcdc_dev, WIN3_MST2));
3533         strcat(buf, dsp_buf);
3534         memset(dsp_buf, 0, sizeof(dsp_buf));
3535
3536         /*area 3*/
3537         size += snprintf(dsp_buf, 80,
3538                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3539                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3540         strcat(buf, dsp_buf);
3541         memset(dsp_buf, 0, sizeof(dsp_buf));
3542         size += snprintf(dsp_buf, 80,
3543                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3544                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3545                  lcdc_readl(lcdc_dev, WIN3_MST3));
3546         strcat(buf, dsp_buf);
3547         memset(dsp_buf, 0, sizeof(dsp_buf));
3548
3549         return size;
3550 }
3551
3552 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3553                                bool set)
3554 {
3555         struct lcdc_device *lcdc_dev =
3556             container_of(dev_drv, struct lcdc_device, driver);
3557         struct rk_screen *screen = dev_drv->cur_screen;
3558         u64 ft = 0;
3559         u32 dotclk;
3560         int ret;
3561         u32 pixclock;
3562         u32 x_total, y_total;
3563
3564         if (set) {
3565                 if (fps == 0) {
3566                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3567                         return 0;
3568                 }
3569                 ft = div_u64(1000000000000llu, fps);
3570                 x_total =
3571                     screen->mode.upper_margin + screen->mode.lower_margin +
3572                     screen->mode.yres + screen->mode.vsync_len;
3573                 y_total =
3574                     screen->mode.left_margin + screen->mode.right_margin +
3575                     screen->mode.xres + screen->mode.hsync_len;
3576                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3577                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3578                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3579         }
3580
3581         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3582         lcdc_dev->pixclock = pixclock;
3583         dev_drv->pixclock = lcdc_dev->pixclock;
3584         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3585         screen->ft = 1000 / fps;        /*one frame time in ms */
3586
3587         if (set)
3588                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3589                          clk_get_rate(lcdc_dev->dclk), fps);
3590
3591         return fps;
3592 }
3593
3594 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3595 {
3596         mutex_lock(&dev_drv->fb_win_id_mutex);
3597         if (order == FB_DEFAULT_ORDER)
3598                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3599         dev_drv->fb4_win_id = order / 10000;
3600         dev_drv->fb3_win_id = (order / 1000) % 10;
3601         dev_drv->fb2_win_id = (order / 100) % 10;
3602         dev_drv->fb1_win_id = (order / 10) % 10;
3603         dev_drv->fb0_win_id = order % 10;
3604         mutex_unlock(&dev_drv->fb_win_id_mutex);
3605
3606         return 0;
3607 }
3608
3609 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3610                                   const char *id)
3611 {
3612         int win_id = 0;
3613
3614         mutex_lock(&dev_drv->fb_win_id_mutex);
3615         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3616                 win_id = dev_drv->fb0_win_id;
3617         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3618                 win_id = dev_drv->fb1_win_id;
3619         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3620                 win_id = dev_drv->fb2_win_id;
3621         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3622                 win_id = dev_drv->fb3_win_id;
3623         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3624                 win_id = dev_drv->fb4_win_id;
3625         mutex_unlock(&dev_drv->fb_win_id_mutex);
3626
3627         return win_id;
3628 }
3629
3630 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3631 {
3632         struct lcdc_device *lcdc_dev =
3633             container_of(dev_drv, struct lcdc_device, driver);
3634         int i;
3635         unsigned int mask, val;
3636         struct rk_lcdc_win *win = NULL;
3637
3638         spin_lock(&lcdc_dev->reg_lock);
3639         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3640                      v_STANDBY_EN(lcdc_dev->standby));
3641         for (i = 0; i < 4; i++) {
3642                 win = dev_drv->win[i];
3643                 if ((win->state == 0) && (win->last_state == 1)) {
3644                         switch (win->id) {
3645                         case 0:
3646                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3647                                    for rk3288 to fix hw bug? */
3648                                 mask = m_WIN0_EN;
3649                                 val = v_WIN0_EN(0);
3650                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3651                                 break;
3652                         case 1:
3653                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3654                                    for rk3288 to fix hw bug? */
3655                                 mask = m_WIN1_EN;
3656                                 val = v_WIN1_EN(0);
3657                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3658                                 break;
3659                         case 2:
3660                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3661                                     m_WIN2_MST1_EN |
3662                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3663                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3664                                     v_WIN2_MST1_EN(0) |
3665                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3666                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3667                                 break;
3668                         case 3:
3669                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3670                                     m_WIN3_MST1_EN |
3671                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3672                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3673                                     v_WIN3_MST1_EN(0) |
3674                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3675                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3676                                 break;
3677                         case 4:
3678                                 mask = m_HWC_EN;
3679                                 val = v_HWC_EN(0);
3680                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
3681                                 break;
3682                         default:
3683                                 break;
3684                         }
3685                 }
3686                 win->last_state = win->state;
3687         }
3688         lcdc_cfg_done(lcdc_dev);
3689         spin_unlock(&lcdc_dev->reg_lock);
3690         return 0;
3691 }
3692
3693 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3694 {
3695         struct lcdc_device *lcdc_dev =
3696             container_of(dev_drv, struct lcdc_device, driver);
3697         spin_lock(&lcdc_dev->reg_lock);
3698         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3699                      v_DIRECT_PATH_EN(open));
3700         lcdc_cfg_done(lcdc_dev);
3701         spin_unlock(&lcdc_dev->reg_lock);
3702         return 0;
3703 }
3704
3705 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3706 {
3707         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3708                                                     struct lcdc_device, driver);
3709         spin_lock(&lcdc_dev->reg_lock);
3710         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3711                      v_DIRECT_PATCH_SEL(win_id));
3712         lcdc_cfg_done(lcdc_dev);
3713         spin_unlock(&lcdc_dev->reg_lock);
3714         return 0;
3715 }
3716
3717 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3718 {
3719         struct lcdc_device *lcdc_dev =
3720             container_of(dev_drv, struct lcdc_device, driver);
3721         int ovl;
3722
3723         spin_lock(&lcdc_dev->reg_lock);
3724         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3725         spin_unlock(&lcdc_dev->reg_lock);
3726         return ovl;
3727 }
3728
3729 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
3730                                       int enable)
3731 {
3732         struct lcdc_device *lcdc_dev =
3733             container_of(dev_drv, struct lcdc_device, driver);
3734         if (enable)
3735                 enable_irq(lcdc_dev->irq);
3736         else
3737                 disable_irq(lcdc_dev->irq);
3738         return 0;
3739 }
3740
3741 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3742 {
3743         struct lcdc_device *lcdc_dev =
3744             container_of(dev_drv, struct lcdc_device, driver);
3745         u32 int_reg;
3746         int ret;
3747
3748         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
3749                 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
3750                 if (int_reg & m_LINE_FLAG0_INTR_STS) {
3751                         lcdc_dev->driver.frame_time.last_framedone_t =
3752                             lcdc_dev->driver.frame_time.framedone_t;
3753                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3754                         lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
3755                                      m_LINE_FLAG0_INTR_CLR,
3756                                      v_LINE_FLAG0_INTR_CLR(1));
3757                         ret = RK_LF_STATUS_FC;
3758                 } else {
3759                         ret = RK_LF_STATUS_FR;
3760                 }
3761         } else {
3762                 ret = RK_LF_STATUS_NC;
3763         }
3764
3765         return ret;
3766 }
3767
3768 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3769                                     unsigned int *dsp_addr)
3770 {
3771         struct lcdc_device *lcdc_dev =
3772             container_of(dev_drv, struct lcdc_device, driver);
3773         spin_lock(&lcdc_dev->reg_lock);
3774         if (lcdc_dev->clk_on) {
3775                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3776                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3777                 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3778                 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3779         }
3780         spin_unlock(&lcdc_dev->reg_lock);
3781         return 0;
3782 }
3783
3784 static struct lcdc_cabc_mode cabc_mode[4] = {
3785         /* pixel_num,8 stage_up, stage_down */
3786         {5, 282, 171, 300},     /*mode 1 */
3787         {10, 282, 171, 300},    /*mode 2 */
3788         {15, 282, 171, 300},    /*mode 3 */
3789         {20, 282, 171, 300},    /*mode 4 */
3790 };
3791
3792 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3793 {
3794         struct lcdc_device *lcdc_dev =
3795             container_of(dev_drv, struct lcdc_device, driver);
3796         struct rk_screen *screen = dev_drv->cur_screen;
3797         u32 total_pixel, calc_pixel, stage_up, stage_down;
3798         u32 pixel_num, global_su;
3799         u32 stage_up_rec, stage_down_rec, global_su_rec;
3800         u32 mask = 0, val = 0, cabc_en = 0;
3801
3802         dev_drv->cabc_mode = mode;
3803         cabc_en = (mode > 0) ? 1 : 0;
3804
3805         if (cabc_en == 0) {
3806                 spin_lock(&lcdc_dev->reg_lock);
3807                 if (lcdc_dev->clk_on) {
3808                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3809                                      m_CABC_EN, v_CABC_EN(0));
3810                         lcdc_cfg_done(lcdc_dev);
3811                 }
3812                 spin_unlock(&lcdc_dev->reg_lock);
3813                 return 0;
3814         }
3815
3816         total_pixel = screen->mode.xres * screen->mode.yres;
3817         pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3818         calc_pixel = (total_pixel * pixel_num) / 1000;
3819         stage_up = cabc_mode[mode - 1].stage_up;
3820         stage_down = cabc_mode[mode - 1].stage_down;
3821         global_su = cabc_mode[mode - 1].global_su;
3822
3823         stage_up_rec = 256 * 256 / stage_up;
3824         stage_down_rec = 256 * 256 / stage_down;
3825         global_su_rec = 256 * 256 / global_su;
3826
3827         spin_lock(&lcdc_dev->reg_lock);
3828         if (lcdc_dev->clk_on) {
3829                 mask = m_CABC_CALC_PIXEL_NUM | m_CABC_EN;
3830                 val = v_CABC_CALC_PIXEL_NUM(calc_pixel) |
3831                         v_CABC_EN(cabc_en);
3832                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3833
3834                 mask = m_CABC_TOTAL_PIXEL_NUM | m_CABC_LUT_EN;
3835                 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel) | v_CABC_LUT_EN(0);
3836                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3837
3838                 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
3839                     m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
3840                 val = v_CABC_STAGE_UP(stage_up) |
3841                     v_CABC_STAGE_UP_REC(stage_up_rec) |
3842                     v_CABC_GLOBAL_SU_LIMIT_EN(1) |
3843                     v_CABC_GLOBAL_SU_REC(global_su_rec);
3844                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3845
3846                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
3847                     m_CABC_GLOBAL_SU;
3848                 val = v_CABC_STAGE_DOWN(stage_down) |
3849                     v_CABC_STAGE_DOWN_REC(stage_down_rec) |
3850                     v_CABC_GLOBAL_SU(global_su);
3851                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3852                 lcdc_cfg_done(lcdc_dev);
3853         }
3854         spin_unlock(&lcdc_dev->reg_lock);
3855
3856         return 0;
3857 }
3858
3859 /*
3860         a:[-30~0]:
3861             sin_hue = sin(a)*256 +0x100;
3862             cos_hue = cos(a)*256;
3863         a:[0~30]
3864             sin_hue = sin(a)*256;
3865             cos_hue = cos(a)*256;
3866 */
3867 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3868                                     bcsh_hue_mode mode)
3869 {
3870         struct lcdc_device *lcdc_dev =
3871             container_of(dev_drv, struct lcdc_device, driver);
3872         u32 val;
3873
3874         spin_lock(&lcdc_dev->reg_lock);
3875         if (lcdc_dev->clk_on) {
3876                 val = lcdc_readl(lcdc_dev, BCSH_H);
3877                 switch (mode) {
3878                 case H_SIN:
3879                         val &= m_BCSH_SIN_HUE;
3880                         break;
3881                 case H_COS:
3882                         val &= m_BCSH_COS_HUE;
3883                         val >>= 16;
3884                         break;
3885                 default:
3886                         break;
3887                 }
3888         }
3889         spin_unlock(&lcdc_dev->reg_lock);
3890
3891         return val;
3892 }
3893
3894 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3895                                     int sin_hue, int cos_hue)
3896 {
3897         struct lcdc_device *lcdc_dev =
3898             container_of(dev_drv, struct lcdc_device, driver);
3899         u32 mask, val;
3900
3901         spin_lock(&lcdc_dev->reg_lock);
3902         if (lcdc_dev->clk_on) {
3903                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3904                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3905                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3906                 lcdc_cfg_done(lcdc_dev);
3907         }
3908         spin_unlock(&lcdc_dev->reg_lock);
3909
3910         return 0;
3911 }
3912
3913 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3914                                     bcsh_bcs_mode mode, int value)
3915 {
3916         struct lcdc_device *lcdc_dev =
3917             container_of(dev_drv, struct lcdc_device, driver);
3918         u32 mask, val;
3919
3920         spin_lock(&lcdc_dev->reg_lock);
3921         if (lcdc_dev->clk_on) {
3922                 switch (mode) {
3923                 case BRIGHTNESS:
3924                         /*from 0 to 255,typical is 128 */
3925                         if (value < 0x80)
3926                                 value += 0x80;
3927                         else if (value >= 0x80)
3928                                 value = value - 0x80;
3929                         mask = m_BCSH_BRIGHTNESS;
3930                         val = v_BCSH_BRIGHTNESS(value);
3931                         break;
3932                 case CONTRAST:
3933                         /*from 0 to 510,typical is 256 */
3934                         mask = m_BCSH_CONTRAST;
3935                         val = v_BCSH_CONTRAST(value);
3936                         break;
3937                 case SAT_CON:
3938                         /*from 0 to 1015,typical is 256 */
3939                         mask = m_BCSH_SAT_CON;
3940                         val = v_BCSH_SAT_CON(value);
3941                         break;
3942                 default:
3943                         break;
3944                 }
3945                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
3946                 lcdc_cfg_done(lcdc_dev);
3947         }
3948         spin_unlock(&lcdc_dev->reg_lock);
3949         return val;
3950 }
3951
3952 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3953                                     bcsh_bcs_mode mode)
3954 {
3955         struct lcdc_device *lcdc_dev =
3956             container_of(dev_drv, struct lcdc_device, driver);
3957         u32 val;
3958
3959         spin_lock(&lcdc_dev->reg_lock);
3960         if (lcdc_dev->clk_on) {
3961                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
3962                 switch (mode) {
3963                 case BRIGHTNESS:
3964                         val &= m_BCSH_BRIGHTNESS;
3965                         if (val > 0x80)
3966                                 val -= 0x80;
3967                         else
3968                                 val += 0x80;
3969                         break;
3970                 case CONTRAST:
3971                         val &= m_BCSH_CONTRAST;
3972                         val >>= 8;
3973                         break;
3974                 case SAT_CON:
3975                         val &= m_BCSH_SAT_CON;
3976                         val >>= 20;
3977                         break;
3978                 default:
3979                         break;
3980                 }
3981         }
3982         spin_unlock(&lcdc_dev->reg_lock);
3983         return val;
3984 }
3985
3986 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3987 {
3988         struct lcdc_device *lcdc_dev =
3989             container_of(dev_drv, struct lcdc_device, driver);
3990         u32 mask, val;
3991
3992         spin_lock(&lcdc_dev->reg_lock);
3993         if (lcdc_dev->clk_on) {
3994                 if (open) {
3995                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
3996                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
3997                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
3998                         dev_drv->bcsh.enable = 1;
3999                 } else {
4000                         mask = m_BCSH_EN;
4001                         val = v_BCSH_EN(0);
4002                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4003                         dev_drv->bcsh.enable = 0;
4004                 }
4005                 rk3368_lcdc_bcsh_path_sel(dev_drv);
4006                 lcdc_cfg_done(lcdc_dev);
4007         }
4008         spin_unlock(&lcdc_dev->reg_lock);
4009         return 0;
4010 }
4011
4012 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4013 {
4014         if (!enable || !dev_drv->bcsh.enable) {
4015                 rk3368_lcdc_open_bcsh(dev_drv, false);
4016                 return 0;
4017         }
4018
4019         if (dev_drv->bcsh.brightness <= 255 ||
4020             dev_drv->bcsh.contrast <= 510 ||
4021             dev_drv->bcsh.sat_con <= 1015 ||
4022             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4023                 rk3368_lcdc_open_bcsh(dev_drv, true);
4024                 if (dev_drv->bcsh.brightness <= 255)
4025                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4026                                                  dev_drv->bcsh.brightness);
4027                 if (dev_drv->bcsh.contrast <= 510)
4028                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4029                                                  dev_drv->bcsh.contrast);
4030                 if (dev_drv->bcsh.sat_con <= 1015)
4031                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4032                                                  dev_drv->bcsh.sat_con);
4033                 if (dev_drv->bcsh.sin_hue <= 511 &&
4034                     dev_drv->bcsh.cos_hue <= 511)
4035                         rk3368_lcdc_set_bcsh_hue(dev_drv,
4036                                                  dev_drv->bcsh.sin_hue,
4037                                                  dev_drv->bcsh.cos_hue);
4038         }
4039         return 0;
4040 }
4041
4042 static int rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4043 {
4044         struct lcdc_device *lcdc_dev =
4045             container_of(dev_drv, struct lcdc_device, driver);
4046
4047         if (enable) {
4048                 spin_lock(&lcdc_dev->reg_lock);
4049                 if (likely(lcdc_dev->clk_on)) {
4050                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4051                                      v_DSP_BLACK_EN(1));
4052                         lcdc_cfg_done(lcdc_dev);
4053                 }
4054                 spin_unlock(&lcdc_dev->reg_lock);
4055         } else {
4056                 spin_lock(&lcdc_dev->reg_lock);
4057                 if (likely(lcdc_dev->clk_on)) {
4058                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4059                                      v_DSP_BLACK_EN(0));
4060
4061                         lcdc_cfg_done(lcdc_dev);
4062                 }
4063                 spin_unlock(&lcdc_dev->reg_lock);
4064         }
4065
4066         return 0;
4067 }
4068
4069
4070 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4071                                        int enable)
4072 {
4073         struct lcdc_device *lcdc_dev =
4074             container_of(dev_drv, struct lcdc_device, driver);
4075
4076         rk3368_lcdc_get_backlight_device(dev_drv);
4077
4078         if (enable) {
4079                 /* close the backlight */
4080                 if (lcdc_dev->backlight) {
4081                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4082                         backlight_update_status(lcdc_dev->backlight);
4083                 }
4084                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4085                         dev_drv->trsm_ops->disable();
4086         } else {
4087                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4088                         dev_drv->trsm_ops->enable();
4089                 msleep(100);
4090                 /* open the backlight */
4091                 if (lcdc_dev->backlight) {
4092                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4093                         backlight_update_status(lcdc_dev->backlight);
4094                 }
4095         }
4096
4097         return 0;
4098 }
4099
4100 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4101         .open = rk3368_lcdc_open,
4102         .win_direct_en = rk3368_lcdc_win_direct_en,
4103         .load_screen = rk3368_load_screen,
4104         .set_par = rk3368_lcdc_set_par,
4105         .pan_display = rk3368_lcdc_pan_display,
4106         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4107         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4108         .blank = rk3368_lcdc_blank,
4109         .ioctl = rk3368_lcdc_ioctl,
4110         .suspend = rk3368_lcdc_early_suspend,
4111         .resume = rk3368_lcdc_early_resume,
4112         .get_win_state = rk3368_lcdc_get_win_state,
4113         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4114         .get_disp_info = rk3368_lcdc_get_disp_info,
4115         .fps_mgr = rk3368_lcdc_fps_mgr,
4116         .fb_get_win_id = rk3368_lcdc_get_win_id,
4117         .fb_win_remap = rk3368_fb_win_remap,
4118         .set_dsp_lut = rk3368_lcdc_set_lut,
4119         .poll_vblank = rk3368_lcdc_poll_vblank,
4120         .dpi_open = rk3368_lcdc_dpi_open,
4121         .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4122         .dpi_status = rk3368_lcdc_dpi_status,
4123         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4124         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4125         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4126         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4127         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4128         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4129         .open_bcsh = rk3368_lcdc_open_bcsh,
4130         .dump_reg = rk3368_lcdc_reg_dump,
4131         .cfg_done = rk3368_lcdc_config_done,
4132         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4133         .dsp_black = rk3368_lcdc_dsp_black,
4134         .backlight_close = rk3368_lcdc_backlight_close,
4135         .mmu_en    = rk3368_lcdc_mmu_en,
4136 };
4137
4138 #ifdef LCDC_IRQ_EMPTY_DEBUG
4139 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4140                                  unsigned int intr_status)
4141 {
4142         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4143                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4144                              v_WIN0_EMPTY_INTR_CLR(1));
4145                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4146         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4147                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4148                              v_WIN1_EMPTY_INTR_CLR(1));
4149                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4150         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4151                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4152                              v_WIN2_EMPTY_INTR_CLR(1));
4153                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4154         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4155                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4156                              v_WIN3_EMPTY_INTR_CLR(1));
4157                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4158         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4159                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4160                              v_HWC_EMPTY_INTR_CLR(1));
4161                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4162         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4163                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4164                              v_POST_BUF_EMPTY_INTR_CLR(1));
4165                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4166         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4167                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4168                              v_PWM_GEN_INTR_CLR(1));
4169                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4170         }
4171         return 0;
4172 }
4173 #endif
4174
4175 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4176 {
4177         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4178         ktime_t timestamp = ktime_get();
4179         u32 intr_status;
4180
4181         intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4182
4183         if (intr_status & m_FS_INTR_STS) {
4184                 timestamp = ktime_get();
4185                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4186                              v_FS_INTR_CLR(1));
4187                 /*if(lcdc_dev->driver.wait_fs){ */
4188                 if (0) {
4189                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4190                         complete(&(lcdc_dev->driver.frame_done));
4191                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4192                 }
4193 #ifdef CONFIG_DRM_ROCKCHIP
4194                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4195 #endif
4196                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4197                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4198
4199         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4200                 lcdc_dev->driver.frame_time.last_framedone_t =
4201                     lcdc_dev->driver.frame_time.framedone_t;
4202                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4203                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4204                              v_LINE_FLAG0_INTR_CLR(1));
4205         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4206                 /*line flag1 */
4207                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4208                              v_LINE_FLAG1_INTR_CLR(1));
4209         } else if (intr_status & m_FS_NEW_INTR_STS) {
4210                 /*new frame start */
4211                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4212                              v_FS_NEW_INTR_CLR(1));
4213         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4214                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4215                              v_BUS_ERROR_INTR_CLR(1));
4216                 dev_warn(lcdc_dev->dev, "bus error!");
4217         }
4218
4219         /* for win empty debug */
4220 #ifdef LCDC_IRQ_EMPTY_DEBUG
4221         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4222 #endif
4223         return IRQ_HANDLED;
4224 }
4225
4226 #if defined(CONFIG_PM)
4227 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4228 {
4229         return 0;
4230 }
4231
4232 static int rk3368_lcdc_resume(struct platform_device *pdev)
4233 {
4234         return 0;
4235 }
4236 #else
4237 #define rk3368_lcdc_suspend NULL
4238 #define rk3368_lcdc_resume  NULL
4239 #endif
4240
4241 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4242 {
4243         struct device_node *np = lcdc_dev->dev->of_node;
4244         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4245         int val;
4246
4247         if (of_property_read_u32(np, "rockchip,prop", &val))
4248                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4249         else
4250                 lcdc_dev->prop = val;
4251
4252         if (of_property_read_u32(np, "rockchip,mirror", &val))
4253                 dev_drv->rotate_mode = NO_MIRROR;
4254         else
4255                 dev_drv->rotate_mode = val;
4256
4257         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4258                 dev_drv->cabc_mode = 0; /* default set close cabc */
4259         else
4260                 dev_drv->cabc_mode = val;
4261
4262         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4263                 /*default set it as 3.xv power supply */
4264                 lcdc_dev->pwr18 = false;
4265         else
4266                 lcdc_dev->pwr18 = (val ? true : false);
4267
4268         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4269                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4270         else
4271                 dev_drv->fb_win_map = val;
4272
4273         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4274                 dev_drv->bcsh.enable = false;
4275         else
4276                 dev_drv->bcsh.enable = (val ? true : false);
4277
4278         if (of_property_read_u32(np, "rockchip,brightness", &val))
4279                 dev_drv->bcsh.brightness = 0xffff;
4280         else
4281                 dev_drv->bcsh.brightness = val;
4282
4283         if (of_property_read_u32(np, "rockchip,contrast", &val))
4284                 dev_drv->bcsh.contrast = 0xffff;
4285         else
4286                 dev_drv->bcsh.contrast = val;
4287
4288         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4289                 dev_drv->bcsh.sat_con = 0xffff;
4290         else
4291                 dev_drv->bcsh.sat_con = val;
4292
4293         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4294                 dev_drv->bcsh.sin_hue = 0xffff;
4295                 dev_drv->bcsh.cos_hue = 0xffff;
4296         } else {
4297                 dev_drv->bcsh.sin_hue = val & 0xff;
4298                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4299         }
4300
4301 #if defined(CONFIG_ROCKCHIP_IOMMU)
4302         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4303                 dev_drv->iommu_enabled = 0;
4304         else
4305                 dev_drv->iommu_enabled = val;
4306 #else
4307         dev_drv->iommu_enabled = 0;
4308 #endif
4309         return 0;
4310 }
4311
4312 static int rk3368_lcdc_probe(struct platform_device *pdev)
4313 {
4314         struct lcdc_device *lcdc_dev = NULL;
4315         struct rk_lcdc_driver *dev_drv;
4316         struct device *dev = &pdev->dev;
4317         struct resource *res;
4318         struct device_node *np = pdev->dev.of_node;
4319         int prop;
4320         int ret = 0;
4321
4322         /*if the primary lcdc has not registered ,the extend
4323            lcdc register later */
4324         of_property_read_u32(np, "rockchip,prop", &prop);
4325         if (prop == EXTEND) {
4326                 if (!is_prmry_rk_lcdc_registered())
4327                         return -EPROBE_DEFER;
4328         }
4329         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4330         if (!lcdc_dev) {
4331                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4332                 return -ENOMEM;
4333         }
4334         platform_set_drvdata(pdev, lcdc_dev);
4335         lcdc_dev->dev = dev;
4336         rk3368_lcdc_parse_dt(lcdc_dev);
4337         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4338         lcdc_dev->reg_phy_base = res->start;
4339         lcdc_dev->len = resource_size(res);
4340         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4341         if (IS_ERR(lcdc_dev->regs))
4342                 return PTR_ERR(lcdc_dev->regs);
4343         else
4344                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4345
4346         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4347         if (IS_ERR(lcdc_dev->regsbak))
4348                 return PTR_ERR(lcdc_dev->regsbak);
4349         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4350         lcdc_dev->grf_base =
4351                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4352         if (IS_ERR(lcdc_dev->grf_base)) {
4353                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4354                 return PTR_ERR(lcdc_dev->grf_base);
4355         }
4356         lcdc_dev->pmugrf_base =
4357                 syscon_regmap_lookup_by_phandle(np, "rockchip,pmu");
4358         if (IS_ERR(lcdc_dev->pmugrf_base)) {
4359                 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
4360                 return PTR_ERR(lcdc_dev->pmugrf_base);
4361         }
4362         lcdc_dev->id = 0;
4363         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4364         dev_drv = &lcdc_dev->driver;
4365         dev_drv->dev = dev;
4366         dev_drv->prop = prop;
4367         dev_drv->id = lcdc_dev->id;
4368         dev_drv->ops = &lcdc_drv_ops;
4369         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4370         spin_lock_init(&lcdc_dev->reg_lock);
4371
4372         lcdc_dev->irq = platform_get_irq(pdev, 0);
4373         if (lcdc_dev->irq < 0) {
4374                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4375                         lcdc_dev->id);
4376                 return -ENXIO;
4377         }
4378
4379         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4380                                IRQF_DISABLED | IRQF_SHARED,
4381                                dev_name(dev), lcdc_dev);
4382         if (ret) {
4383                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4384                         lcdc_dev->irq, ret);
4385                 return ret;
4386         }
4387
4388         if (dev_drv->iommu_enabled) {
4389                 if (lcdc_dev->id == 0) {
4390                         strcpy(dev_drv->mmu_dts_name,
4391                                VOPB_IOMMU_COMPATIBLE_NAME);
4392                 } else {
4393                         strcpy(dev_drv->mmu_dts_name,
4394                                VOPL_IOMMU_COMPATIBLE_NAME);
4395                 }
4396         }
4397
4398         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4399         if (ret < 0) {
4400                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4401                 return ret;
4402         }
4403         lcdc_dev->screen = dev_drv->screen0;
4404         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4405                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4406
4407         return 0;
4408 }
4409
4410 static int rk3368_lcdc_remove(struct platform_device *pdev)
4411 {
4412         return 0;
4413 }
4414
4415 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4416 {
4417         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4418
4419         if (0) {/*maybe lead to crash*/
4420                 rk3368_lcdc_deint(lcdc_dev);
4421                 rk_disp_pwr_disable(&lcdc_dev->driver);
4422         } else {
4423                 rk3368_lcdc_early_suspend(&lcdc_dev->driver);
4424         }
4425 }
4426
4427 #if defined(CONFIG_OF)
4428 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4429         {.compatible = "rockchip,rk3368-lcdc",},
4430         {}
4431 };
4432 #endif
4433
4434 static struct platform_driver rk3368_lcdc_driver = {
4435         .probe = rk3368_lcdc_probe,
4436         .remove = rk3368_lcdc_remove,
4437         .driver = {
4438                    .name = "rk3368-lcdc",
4439                    .owner = THIS_MODULE,
4440                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4441                    },
4442         .suspend = rk3368_lcdc_suspend,
4443         .resume = rk3368_lcdc_resume,
4444         .shutdown = rk3368_lcdc_shutdown,
4445 };
4446
4447 static int __init rk3368_lcdc_module_init(void)
4448 {
4449         return platform_driver_register(&rk3368_lcdc_driver);
4450 }
4451
4452 static void __exit rk3368_lcdc_module_exit(void)
4453 {
4454         platform_driver_unregister(&rk3368_lcdc_driver);
4455 }
4456
4457 fs_initcall(rk3368_lcdc_module_init);
4458 module_exit(rk3368_lcdc_module_exit);