drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 static struct rk_lcdc_win lcdc_win[] = {
  54         [0] = {
  55                .name = "win0",
  56                .id = 0,
  57                .support_3d = false,
  58                },
  59         [1] = {
  60                .name = "win1",
  61                .id = 1,
  62                .support_3d = false,
  63                },
  64         [2] = {
  65                .name = "win2",
  66                .id = 2,
  67                .support_3d = false,
  68                },
  69         [3] = {
  70                .name = "win3",
  71                .id = 3,
  72                .support_3d = false,
  73                },
  74         [4] = {
  75                .name = "hwc",
  76                .id = 4,
  77                .support_3d = false,
  78                }
  79 };
  80
  81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  82
  83 /*#define WAIT_FOR_SYNC 1*/
  84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  85 {
  86         u32 vscalednmult;
  87
  88         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  89                 vscalednmult = 4;
  90         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  91                 vscalednmult = 2;
  92         else
  93                 vscalednmult = 1;
  94
  95         return vscalednmult;
  96 }
  97
  98
  99 static int rk3368_set_cabc_lut(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
 100 {
 101         int i;
 102         int __iomem *c;
 103         u32 v;
 104         struct lcdc_device *lcdc_dev =
 105             container_of(dev_drv, struct lcdc_device, driver);
 106
 107         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 108                      v_CABC_LUT_EN(0));
 109         lcdc_cfg_done(lcdc_dev);
 110         mdelay(25);
 111         for (i = 0; i < 256; i++) {
 112                 v = cabc_lut[i];
 113                 c = lcdc_dev->cabc_lut_addr_base + i;
 114                 writel_relaxed(v, c);
 115         }
 116         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 117                      v_CABC_LUT_EN(1));
 118         return 0;
 119 }
 120
 121
 122 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
 123 {
 124         int i;
 125         int __iomem *c;
 126         u32 v;
 127         struct lcdc_device *lcdc_dev =
 128             container_of(dev_drv, struct lcdc_device, driver);
 129
 130         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 131                      v_DSP_LUT_EN(0));
 132         lcdc_cfg_done(lcdc_dev);
 133         mdelay(25);
 134         for (i = 0; i < 256; i++) {
 135                 v = dsp_lut[i];
 136                 c = lcdc_dev->dsp_lut_addr_base + i;
 137                 writel_relaxed(v, c);
 138         }
 139         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 140                      v_DSP_LUT_EN(1));
 141
 142         return 0;
 143 }
 144
 145 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 146 {
 147 #ifdef CONFIG_RK_FPGA
 148         lcdc_dev->clk_on = 1;
 149         return 0;
 150 #endif
 151         if (!lcdc_dev->clk_on) {
 152                 clk_prepare_enable(lcdc_dev->hclk);
 153                 clk_prepare_enable(lcdc_dev->dclk);
 154                 clk_prepare_enable(lcdc_dev->aclk);
 155                 clk_prepare_enable(lcdc_dev->pd);
 156                 spin_lock(&lcdc_dev->reg_lock);
 157                 lcdc_dev->clk_on = 1;
 158                 spin_unlock(&lcdc_dev->reg_lock);
 159         }
 160
 161         return 0;
 162 }
 163
 164 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 165 {
 166 #ifdef CONFIG_RK_FPGA
 167         lcdc_dev->clk_on = 0;
 168         return 0;
 169 #endif
 170         if (lcdc_dev->clk_on) {
 171                 spin_lock(&lcdc_dev->reg_lock);
 172                 lcdc_dev->clk_on = 0;
 173                 spin_unlock(&lcdc_dev->reg_lock);
 174                 mdelay(25);
 175                 clk_disable_unprepare(lcdc_dev->dclk);
 176                 clk_disable_unprepare(lcdc_dev->hclk);
 177                 clk_disable_unprepare(lcdc_dev->aclk);
 178                 clk_disable_unprepare(lcdc_dev->pd);
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int __maybe_unused
 185         rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 186 {
 187         u32 mask, val;
 188
 189         spin_lock(&lcdc_dev->reg_lock);
 190         if (likely(lcdc_dev->clk_on)) {
 191                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 192                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 193                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 194                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 195                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 196                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 197                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 198                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 199                     v_ADDR_SAME_INTR_EN(0) |
 200                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 201                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 202                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 203                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 204                     v_POST_BUF_EMPTY_INTR_EN(0) |
 205                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 206                 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
 207
 208                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 209                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 210                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 211                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 212                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 213                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 214                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 215                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 216                     v_ADDR_SAME_INTR_CLR(1) |
 217                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 218                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 219                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 220                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 221                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 222                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 223                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
 224                 lcdc_cfg_done(lcdc_dev);
 225                 spin_unlock(&lcdc_dev->reg_lock);
 226         } else {
 227                 spin_unlock(&lcdc_dev->reg_lock);
 228         }
 229         mdelay(1);
 230         return 0;
 231 }
 232
 233 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 234 {
 235         struct lcdc_device *lcdc_dev =
 236             container_of(dev_drv, struct lcdc_device, driver);
 237         int *cbase = (int *)lcdc_dev->regs;
 238         int *regsbak = (int *)lcdc_dev->regsbak;
 239         int i, j, val;
 240         char dbg_message[30];
 241         char buf[10];
 242
 243         pr_info("lcd back up reg:\n");
 244         memset(dbg_message, 0, sizeof(dbg_message));
 245         memset(buf, 0, sizeof(buf));
 246         for (i = 0; i <= (0x200 >> 4); i++) {
 247                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 248                 for (j = 0; j < 4; j++) {
 249                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 250                         strcat(dbg_message, buf);
 251                 }
 252                 pr_info("%s\n", dbg_message);
 253                 memset(dbg_message, 0, sizeof(dbg_message));
 254                 memset(buf, 0, sizeof(buf));
 255         }
 256
 257         pr_info("lcdc reg:\n");
 258         for (i = 0; i <= (0x200 >> 4); i++) {
 259                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 260                 for (j = 0; j < 4; j++) {
 261                         sprintf(buf, "%08x  ",
 262                                 readl_relaxed(cbase + i * 4 + j));
 263                         strcat(dbg_message, buf);
 264                 }
 265                 pr_info("%s\n", dbg_message);
 266                 memset(dbg_message, 0, sizeof(dbg_message));
 267                 memset(buf, 0, sizeof(buf));
 268         }
 269
 270         return 0;
 271 }
 272
 273 #define WIN_EN(id)              \
 274 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 275 { \
 276         u32 msk, val;                                                   \
 277         spin_lock(&lcdc_dev->reg_lock);                                 \
 278         msk =  m_WIN##id##_EN;                                          \
 279         val  =  v_WIN##id##_EN(en);                                     \
 280         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 281         lcdc_cfg_done(lcdc_dev);                                        \
 282         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 283         while (val !=  (!!en))  {                                       \
 284                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 285         }                                                               \
 286         spin_unlock(&lcdc_dev->reg_lock);                               \
 287         return 0;                                                       \
 288 }
 289
 290 WIN_EN(0);
 291 WIN_EN(1);
 292 WIN_EN(2);
 293 WIN_EN(3);
 294 /*enable/disable win directly*/
 295 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 296                                      int win_id, int en)
 297 {
 298         struct lcdc_device *lcdc_dev =
 299             container_of(drv, struct lcdc_device, driver);
 300         if (win_id == 0)
 301                 win0_enable(lcdc_dev, en);
 302         else if (win_id == 1)
 303                 win1_enable(lcdc_dev, en);
 304         else if (win_id == 2)
 305                 win2_enable(lcdc_dev, en);
 306         else if (win_id == 3)
 307                 win3_enable(lcdc_dev, en);
 308         else
 309                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 310         return 0;
 311 }
 312
 313 #define SET_WIN_ADDR(id) \
 314 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 315 {                                                       \
 316         u32 msk, val;                                   \
 317         spin_lock(&lcdc_dev->reg_lock);                 \
 318         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 319         msk =  m_WIN##id##_EN;                          \
 320         val  =  v_WIN0_EN(1);                           \
 321         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 322         lcdc_cfg_done(lcdc_dev);                        \
 323         spin_unlock(&lcdc_dev->reg_lock);               \
 324         return 0;                                       \
 325 }
 326
 327 SET_WIN_ADDR(0);
 328 SET_WIN_ADDR(1);
 329 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 330                                     int win_id, u32 addr)
 331 {
 332         struct lcdc_device *lcdc_dev =
 333             container_of(dev_drv, struct lcdc_device, driver);
 334         if (win_id == 0)
 335                 set_win0_addr(lcdc_dev, addr);
 336         else
 337                 set_win1_addr(lcdc_dev, addr);
 338
 339         return 0;
 340 }
 341
 342 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 343 {
 344         int reg = 0;
 345         u32 val = 0;
 346         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 347         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 348         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 349         u32 st_x, st_y;
 350         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 351
 352         spin_lock(&lcdc_dev->reg_lock);
 353         for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
 354                 val = lcdc_readl_backup(lcdc_dev, reg);
 355                 switch (reg) {
 356                 case WIN0_ACT_INFO:
 357                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 358                         win0->area[0].yact =
 359                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 360                         break;
 361                 case WIN0_DSP_INFO:
 362                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 363                         win0->area[0].ysize =
 364                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 365                         break;
 366                 case WIN0_DSP_ST:
 367                         st_x = val & m_WIN0_DSP_XST;
 368                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 369                         win0->area[0].xpos = st_x - h_pw_bp;
 370                         win0->area[0].ypos = st_y - v_pw_bp;
 371                         break;
 372                 case WIN0_CTRL0:
 373                         win0->state = val & m_WIN0_EN;
 374                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 375                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 376                         win0->area[0].format = win0->area[0].fmt_cfg;
 377                         break;
 378                 case WIN0_VIR:
 379                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 380                         win0->area[0].uv_vir_stride =
 381                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 382                         if (win0->area[0].format == ARGB888)
 383                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 384                         else if (win0->area[0].format == RGB888)
 385                                 win0->area[0].xvir =
 386                                     win0->area[0].y_vir_stride * 4 / 3;
 387                         else if (win0->area[0].format == RGB565)
 388                                 win0->area[0].xvir =
 389                                     2 * win0->area[0].y_vir_stride;
 390                         else    /* YUV */
 391                                 win0->area[0].xvir =
 392                                     4 * win0->area[0].y_vir_stride;
 393                         break;
 394                 case WIN0_YRGB_MST:
 395                         win0->area[0].smem_start = val;
 396                         break;
 397                 case WIN0_CBR_MST:
 398                         win0->area[0].cbr_start = val;
 399                         break;
 400                 default:
 401                         break;
 402                 }
 403         }
 404         spin_unlock(&lcdc_dev->reg_lock);
 405 }
 406
 407 /********do basic init*********/
 408 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 409 {
 410         u32 mask, val, v;
 411         struct lcdc_device *lcdc_dev =
 412             container_of(dev_drv, struct lcdc_device, driver);
 413         if (lcdc_dev->pre_init)
 414                 return 0;
 415
 416         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 417         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 418         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 419         lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 420
 421         if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||
 422             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 423                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 424                         lcdc_dev->id);
 425         }
 426
 427         rk_disp_pwr_enable(dev_drv);
 428         rk3368_lcdc_clk_enable(lcdc_dev);
 429
 430         /*backup reg config at uboot */
 431         lcdc_read_reg_defalut_cfg(lcdc_dev);
 432         if (lcdc_dev->pwr18 == 1) {
 433                 v = 0x00200020; /*bit5: 1,1.8v;0,3.3v*/
 434                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 435                                 PMUGRF_SOC_CON0_VOP, v);
 436         } else {
 437                 v = 0x00200000; /*bit5: 1,1.8v;0,3.3v*/
 438                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 439                                 PMUGRF_SOC_CON0_VOP, v);
 440         }
 441 #if 0
 442         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
 443         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
 444         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
 445         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
 446         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
 447         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
 448 #else
 449         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x40000000);
 450         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x0);
 451         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x80000000);
 452         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x0);
 453         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x40000000);
 454         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x0);
 455 #endif
 456         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 457         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 458         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 459         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 460         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 461         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 462
 463         mask = m_AUTO_GATING_EN;
 464         val = v_AUTO_GATING_EN(0);
 465         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 466         mask = m_DITHER_UP_EN;
 467         val = v_DITHER_UP_EN(1);
 468         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
 469         lcdc_cfg_done(lcdc_dev);
 470         /*disable win0 to workaround iommu pagefault */
 471         /*if (dev_drv->iommu_enabled) */
 472         /*      win0_enable(lcdc_dev, 0); */
 473         lcdc_dev->pre_init = true;
 474
 475         return 0;
 476 }
 477
 478 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 479 {
 480         u32 mask, val;
 481
 482         rk3368_lcdc_disable_irq(lcdc_dev);
 483         spin_lock(&lcdc_dev->reg_lock);
 484         mask = m_WIN0_EN;
 485         val = v_WIN0_EN(0);
 486         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
 487         lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
 488
 489         mask = m_WIN2_EN | m_WIN2_MST0_EN |
 490                 m_WIN2_MST1_EN |
 491                 m_WIN2_MST2_EN | m_WIN2_MST3_EN;
 492         val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
 493                 v_WIN2_MST1_EN(0) |
 494                 v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
 495         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
 496         lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
 497         lcdc_cfg_done(lcdc_dev);
 498         spin_unlock(&lcdc_dev->reg_lock);
 499         mdelay(50);
 500
 501 }
 502
 503 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 504 {
 505         struct lcdc_device *lcdc_dev =
 506             container_of(dev_drv, struct lcdc_device, driver);
 507         struct rk_screen *screen = dev_drv->cur_screen;
 508         u16 x_res = screen->mode.xres;
 509         u16 y_res = screen->mode.yres;
 510         u32 mask, val;
 511         u16 h_total, v_total;
 512         u16 post_hsd_en, post_vsd_en;
 513         u16 post_dsp_hact_st, post_dsp_hact_end;
 514         u16 post_dsp_vact_st, post_dsp_vact_end;
 515         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 516         u16 post_h_fac, post_v_fac;
 517
 518         screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
 519         screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
 520         screen->post_xsize = x_res *
 521             (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
 522         screen->post_ysize = y_res *
 523             (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
 524
 525         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 526             x_res + screen->mode.right_margin;
 527         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 528             y_res + screen->mode.lower_margin;
 529
 530         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 531                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 532                          screen->post_dsp_stx, screen->post_xsize, x_res);
 533                 screen->post_dsp_stx = x_res - screen->post_xsize;
 534         }
 535         if (screen->x_mirror == 0) {
 536                 post_dsp_hact_st = screen->post_dsp_stx +
 537                     screen->mode.hsync_len + screen->mode.left_margin;
 538                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 539         } else {
 540                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 541                     screen->post_dsp_stx;
 542                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 543         }
 544         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 545                 post_hsd_en = 1;
 546                 post_h_fac =
 547                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 548         } else {
 549                 post_hsd_en = 0;
 550                 post_h_fac = 0x1000;
 551         }
 552
 553         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 554                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 555                          screen->post_dsp_sty, screen->post_ysize, y_res);
 556                 screen->post_dsp_sty = y_res - screen->post_ysize;
 557         }
 558
 559         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 560                 post_vsd_en = 1;
 561                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 562                                                       screen->post_ysize);
 563         } else {
 564                 post_vsd_en = 0;
 565                 post_v_fac = 0x1000;
 566         }
 567
 568         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 569                 post_dsp_vact_st = screen->post_dsp_sty / 2 +
 570                                         screen->mode.vsync_len +
 571                                         screen->mode.upper_margin;
 572                 post_dsp_vact_end = post_dsp_vact_st +
 573                                         screen->post_ysize / 2;
 574
 575                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
 576                                       screen->mode.upper_margin +
 577                                       y_res/2 +
 578                                       screen->mode.lower_margin +
 579                                       screen->mode.vsync_len +
 580                                       screen->mode.upper_margin +
 581                                       screen->post_dsp_sty / 2 +
 582                                       1;
 583                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
 584                                         screen->post_ysize/2;
 585         } else {
 586                 if (screen->y_mirror == 0) {
 587                         post_dsp_vact_st = screen->post_dsp_sty +
 588                             screen->mode.vsync_len +
 589                             screen->mode.upper_margin;
 590                         post_dsp_vact_end = post_dsp_vact_st +
 591                                 screen->post_ysize;
 592                 } else {
 593                         post_dsp_vact_end = v_total -
 594                                 screen->mode.lower_margin -
 595                             screen->post_dsp_sty;
 596                         post_dsp_vact_st = post_dsp_vact_end -
 597                                 screen->post_ysize;
 598                 }
 599                 post_dsp_vact_st_f1 = 0;
 600                 post_dsp_vact_end_f1 = 0;
 601         }
 602         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 603             screen->post_xsize, screen->post_ysize, screen->xpos);
 604         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 605             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 606         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 607         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 608             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 609         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 610
 611         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 612         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 613             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 614         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 615
 616         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 617         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 618             v_POST_VS_FACTOR_YRGB(post_v_fac);
 619         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 620
 621         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 622         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 623             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 624         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 625
 626         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 627         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 628         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 629         return 0;
 630 }
 631
 632 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 633 {
 634         struct lcdc_device *lcdc_dev =
 635             container_of(dev_drv, struct lcdc_device, driver);
 636         struct rk_lcdc_win *win;
 637         u32 colorkey_r, colorkey_g, colorkey_b;
 638         int i, key_val;
 639
 640         for (i = 0; i < 4; i++) {
 641                 win = dev_drv->win[i];
 642                 key_val = win->color_key_val;
 643                 colorkey_r = (key_val & 0xff) << 2;
 644                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 645                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 646                 /*color key dither 565/888->aaa */
 647                 key_val = colorkey_r | colorkey_g | colorkey_b;
 648                 switch (i) {
 649                 case 0:
 650                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 651                         break;
 652                 case 1:
 653                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 654                         break;
 655                 case 2:
 656                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 657                         break;
 658                 case 3:
 659                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 660                         break;
 661                 default:
 662                         pr_info("%s:un support win num:%d\n",
 663                                 __func__, i);
 664                         break;
 665                 }
 666         }
 667         return 0;
 668 }
 669
 670 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 671 {
 672         struct lcdc_device *lcdc_dev =
 673             container_of(dev_drv, struct lcdc_device, driver);
 674         struct rk_lcdc_win *win = dev_drv->win[win_id];
 675         struct alpha_config alpha_config;
 676         u32 mask, val;
 677         int ppixel_alpha = 0, global_alpha = 0, i;
 678         u32 src_alpha_ctl, dst_alpha_ctl;
 679
 680         for (i = 0; i < win->area_num; i++) {
 681                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 682                                  (win->area[i].format == FBDC_ARGB_888) ||
 683                                  (win->area[i].format == FBDC_ABGR_888) ||
 684                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 685         }
 686         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 687         alpha_config.src_global_alpha_val = win->g_alpha_val;
 688         win->alpha_mode = AB_SRC_OVER;
 689         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 690            __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
 691            global_alpha); */
 692         switch (win->alpha_mode) {
 693         case AB_USER_DEFINE:
 694                 break;
 695         case AB_CLEAR:
 696                 alpha_config.src_factor_mode = AA_ZERO;
 697                 alpha_config.dst_factor_mode = AA_ZERO;
 698                 break;
 699         case AB_SRC:
 700                 alpha_config.src_factor_mode = AA_ONE;
 701                 alpha_config.dst_factor_mode = AA_ZERO;
 702                 break;
 703         case AB_DST:
 704                 alpha_config.src_factor_mode = AA_ZERO;
 705                 alpha_config.dst_factor_mode = AA_ONE;
 706                 break;
 707         case AB_SRC_OVER:
 708                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 709                 if (global_alpha)
 710                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 711                 else
 712                         alpha_config.src_factor_mode = AA_ONE;
 713                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 714                 break;
 715         case AB_DST_OVER:
 716                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 717                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 718                 alpha_config.dst_factor_mode = AA_ONE;
 719                 break;
 720         case AB_SRC_IN:
 721                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 722                 alpha_config.src_factor_mode = AA_SRC;
 723                 alpha_config.dst_factor_mode = AA_ZERO;
 724                 break;
 725         case AB_DST_IN:
 726                 alpha_config.src_factor_mode = AA_ZERO;
 727                 alpha_config.dst_factor_mode = AA_SRC;
 728                 break;
 729         case AB_SRC_OUT:
 730                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 731                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 732                 alpha_config.dst_factor_mode = AA_ZERO;
 733                 break;
 734         case AB_DST_OUT:
 735                 alpha_config.src_factor_mode = AA_ZERO;
 736                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 737                 break;
 738         case AB_SRC_ATOP:
 739                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 740                 alpha_config.src_factor_mode = AA_SRC;
 741                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 742                 break;
 743         case AB_DST_ATOP:
 744                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 745                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 746                 alpha_config.dst_factor_mode = AA_SRC;
 747                 break;
 748         case XOR:
 749                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 750                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 751                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 752                 break;
 753         case AB_SRC_OVER_GLOBAL:
 754                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 755                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 756                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 757                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 758                 break;
 759         default:
 760                 pr_err("alpha mode error\n");
 761                 break;
 762         }
 763         if ((ppixel_alpha == 1) && (global_alpha == 1))
 764                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 765         else if (ppixel_alpha == 1)
 766                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 767         else if (global_alpha == 1)
 768                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 769         else
 770                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 771         alpha_config.src_alpha_mode = AA_STRAIGHT;
 772         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 773
 774         switch (win_id) {
 775         case 0:
 776                 src_alpha_ctl = 0x60;
 777                 dst_alpha_ctl = 0x64;
 778                 break;
 779         case 1:
 780                 src_alpha_ctl = 0xa0;
 781                 dst_alpha_ctl = 0xa4;
 782                 break;
 783         case 2:
 784                 src_alpha_ctl = 0xdc;
 785                 dst_alpha_ctl = 0xec;
 786                 break;
 787         case 3:
 788                 src_alpha_ctl = 0x12c;
 789                 dst_alpha_ctl = 0x13c;
 790                 break;
 791         case 4:
 792                 src_alpha_ctl = 0x160;
 793                 dst_alpha_ctl = 0x164;
 794                 break;
 795         }
 796         mask = m_WIN0_DST_FACTOR_M0;
 797         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 798         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 799         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 800             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 801             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 802             m_WIN0_SRC_GLOBAL_ALPHA;
 803         val = v_WIN0_SRC_ALPHA_EN(1) |
 804             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 805             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 806             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 807             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 808             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 809             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 810         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 811
 812         return 0;
 813 }
 814
 815 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 816 {
 817         struct rk_lcdc_win_area area_temp;
 818         int i, j;
 819
 820         for (i = 0; i < area_num; i++) {
 821                 for (j = i + 1; j < area_num; j++) {
 822                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 823                                 memcpy(&area_temp, &win->area[i],
 824                                        sizeof(struct rk_lcdc_win_area));
 825                                 memcpy(&win->area[i], &win->area[j],
 826                                        sizeof(struct rk_lcdc_win_area));
 827                                 memcpy(&win->area[j], &area_temp,
 828                                        sizeof(struct rk_lcdc_win_area));
 829                         }
 830                 }
 831         }
 832
 833         return 0;
 834 }
 835
 836 static int __maybe_unused
 837         rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 838 {
 839         struct rk_lcdc_win_area area_temp;
 840
 841         switch (area_num) {
 842         case 2:
 843                 area_temp = win->area[0];
 844                 win->area[0] = win->area[1];
 845                 win->area[1] = area_temp;
 846                 break;
 847         case 3:
 848                 area_temp = win->area[0];
 849                 win->area[0] = win->area[2];
 850                 win->area[2] = area_temp;
 851                 break;
 852         case 4:
 853                 area_temp = win->area[0];
 854                 win->area[0] = win->area[3];
 855                 win->area[3] = area_temp;
 856
 857                 area_temp = win->area[1];
 858                 win->area[1] = win->area[2];
 859                 win->area[2] = area_temp;
 860                 break;
 861         default:
 862                 pr_info("un supported area num!\n");
 863                 break;
 864         }
 865         return 0;
 866 }
 867
 868 static int __maybe_unused
 869 rk3368_win_area_check_var(int win_id, int area_num,
 870                           struct rk_lcdc_win_area *area_pre,
 871                           struct rk_lcdc_win_area *area_now)
 872 {
 873         if ((area_pre->xpos > area_now->xpos) ||
 874             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 875              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 876                 area_now->state = 0;
 877                 pr_err("win[%d]:\n"
 878                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 879                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 880                        win_id,
 881                        area_num - 1, area_pre->xpos, area_pre->xsize,
 882                        area_pre->ypos, area_pre->ysize,
 883                        area_num, area_now->xpos, area_now->xsize,
 884                        area_now->ypos, area_now->ysize);
 885                 return -EINVAL;
 886         }
 887         return 0;
 888 }
 889
 890 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 891 {
 892         struct lcdc_device *lcdc_dev =
 893             container_of(dev_drv, struct lcdc_device, driver);
 894         u32 val, i;
 895
 896         for (i = 0; i < 100; i++) {
 897                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 898                 val &= m_DBG_IFBDC_IDLE;
 899                 if (val)
 900                         continue;
 901                 else
 902                         mdelay(10);
 903         };
 904         return val;
 905 }
 906
 907 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 908 {
 909         struct lcdc_device *lcdc_dev =
 910             container_of(dev_drv, struct lcdc_device, driver);
 911         struct rk_lcdc_win *win = dev_drv->win[win_id];
 912         u32 mask, val;
 913
 914         mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
 915             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 916             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 917         val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
 918             v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 919             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 920             v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
 921             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 922             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 923         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 924
 925         mask = m_IFBDC_TILES_NUM;
 926         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 927         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 928
 929         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 930         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 931             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 932         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 933
 934         mask = m_IFBDC_CMP_INDEX_INIT;
 935         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 936         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 937
 938         mask = m_IFBDC_MB_VIR_WIDTH;
 939         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 940         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 941
 942         return 0;
 943 }
 944
 945 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 946 {
 947         struct lcdc_device *lcdc_dev =
 948             container_of(dev_drv, struct lcdc_device, driver);
 949         struct rk_lcdc_win *win = dev_drv->win[win_id];
 950         u8 fbdc_dsp_width_ratio;
 951         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 952         u16 fbdc_mb_width, fbdc_mb_height;
 953         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 954         u16 fbdc_cmp_index_init;
 955         u8 mb_w_size, mb_h_size;
 956         struct rk_screen *screen = dev_drv->cur_screen;
 957
 958         if (screen->mode.flag == FB_VMODE_INTERLACED) {
 959                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
 960                 return 0;
 961         }
 962
 963         switch (win->area[0].fmt_cfg) {
 964         case VOP_FORMAT_ARGB888:
 965                 fbdc_dsp_width_ratio = 0;
 966                 mb_w_size = 16;
 967                 break;
 968         case VOP_FORMAT_RGB888:
 969                 fbdc_dsp_width_ratio = 0;
 970                 mb_w_size = 16;
 971                 break;
 972         case VOP_FORMAT_RGB565:
 973                 fbdc_dsp_width_ratio = 1;
 974                 mb_w_size = 32;
 975                 break;
 976         default:
 977                 dev_err(lcdc_dev->dev,
 978                         "in fbdc mode,unsupport fmt:%d!\n",
 979                         win->area[0].fmt_cfg);
 980                 break;
 981         }
 982         mb_h_size = 4;
 983
 984         /*macro block xvir and yvir */
 985         if ((win->area[0].xvir % mb_w_size == 0) &&
 986             (win->area[0].yvir % mb_h_size == 0)) {
 987                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
 988                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
 989         } else {
 990                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 991                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
 992                        win->area[0].xvir, win->area[0].yvir,
 993                        mb_w_size, mb_h_size);
 994         }
 995         /*macro block xact and yact */
 996         if ((win->area[0].xact % mb_w_size == 0) &&
 997             (win->area[0].yact % mb_h_size == 0)) {
 998                 fbdc_mb_width = win->area[0].xact / mb_w_size;
 999                 fbdc_mb_height = win->area[0].yact / mb_h_size;
1000         } else {
1001                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
1002                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
1003                        win->area[0].xact, win->area[0].yact,
1004                        mb_w_size, mb_h_size);
1005         }
1006         /*macro block xoff and yoff */
1007         if ((win->area[0].xoff % mb_w_size == 0) &&
1008             (win->area[0].yoff % mb_h_size == 0)) {
1009                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
1010                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
1011         } else {
1012                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
1013                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
1014                        win->area[0].xoff, win->area[0].yoff,
1015                        mb_w_size, mb_h_size);
1016         }
1017
1018         /*FBDC tiles */
1019         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
1020
1021         /*
1022            switch (fbdc_rotation_mode)  {
1023            case FBDC_ROT_NONE:
1024            fbdc_cmp_index_init =
1025            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
1026            break;
1027            case FBDC_X_MIRROR:
1028            fbdc_cmp_index_init =
1029            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
1030            (fbdc_mb_width-1));
1031            break;
1032            case FBDC_Y_MIRROR:
1033            fbdc_cmp_index_init =
1034            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
1035            fbdc_mb_xst;
1036            break;
1037            case FBDC_ROT_180:
1038            fbdc_cmp_index_init =
1039            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1040            (fbdc_mb_xst+(fbdc_mb_width-1));
1041            break;
1042            }
1043          */
1044         if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
1045                 fbdc_cmp_index_init =
1046                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
1047                     (fbdc_mb_xst + (fbdc_mb_width - 1));
1048         } else {
1049                 fbdc_cmp_index_init =
1050                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
1051         }
1052         /*fbdc fmt maybe need to change*/
1053         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
1054         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
1055         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
1056         win->area[0].fbdc_mb_width = fbdc_mb_width;
1057         win->area[0].fbdc_mb_height = fbdc_mb_height;
1058         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1059         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1060         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1061         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1062
1063         return 0;
1064 }
1065
1066 static int rk3368_lcdc_axi_gather_cfg(struct lcdc_device *lcdc_dev,
1067                                             struct rk_lcdc_win *win)
1068 {
1069         u32 mask, val;
1070         u16 yrgb_gather_num = 8;
1071         u16 cbcr_gather_num = 2;
1072
1073         switch (win->area[0].format) {
1074         case ARGB888:
1075         case XBGR888:
1076         case ABGR888:
1077                 yrgb_gather_num = 8;
1078                 break;
1079         case RGB888:
1080         case RGB565:
1081                 yrgb_gather_num = 4;
1082                 break;
1083         case YUV444:
1084         case YUV422:
1085         case YUV420:
1086         case YUV420_NV21:
1087                 yrgb_gather_num = 2;
1088                 cbcr_gather_num = 4;
1089                 break;
1090         default:
1091                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
1092                         __func__);
1093                 return -EINVAL;
1094         }
1095
1096         if ((win->id == 0) || (win->id == 1)) {
1097                 mask = m_WIN0_YRGB_AXI_GATHER_EN | m_WIN0_CBR_AXI_GATHER_EN |
1098                         m_WIN0_YRGB_AXI_GATHER_NUM | m_WIN0_CBR_AXI_GATHER_NUM;
1099                 val = v_WIN0_YRGB_AXI_GATHER_EN(1) | v_WIN0_CBR_AXI_GATHER_EN(1) |
1100                         v_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) |
1101                         v_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num);
1102                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + (win->id * 0x40), mask, val);
1103         } else if ((win->id == 2) || (win->id == 3)) {
1104                 mask = m_WIN0_YRGB_AXI_GATHER_EN | m_WIN0_YRGB_AXI_GATHER_NUM;
1105                 val = v_WIN0_YRGB_AXI_GATHER_EN(1) |
1106                         v_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num);
1107                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL1 + ((win->id - 2) * 0x50), mask, val);
1108         } else if (win->id == 4) {
1109                 mask = m_HWC_AXI_GATHER_EN | m_HWC_AXI_GATHER_NUM;
1110                 val = v_HWC_AXI_GATHER_EN(1) |
1111                         v_HWC_AXI_GATHER_NUM(yrgb_gather_num);
1112                 lcdc_msk_reg(lcdc_dev, HWC_CTRL1, mask, val);
1113         }
1114         return 0;
1115 }
1116
1117 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1118                                  struct rk_lcdc_win *win)
1119 {
1120         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1121         struct rk_screen *screen = dev_drv->cur_screen;
1122
1123         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1124                 switch (win->area[0].fmt_cfg) {
1125                 case VOP_FORMAT_ARGB888:
1126                 case VOP_FORMAT_RGB888:
1127                 case VOP_FORMAT_RGB565:
1128                         if ((screen->mode.xres < 1280) &&
1129                             (screen->mode.yres < 720)) {
1130                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1131                         } else {
1132                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1133                         }
1134                         break;
1135                 default:
1136                         break;
1137                 }
1138         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1139                 switch (win->area[0].fmt_cfg) {
1140                 case VOP_FORMAT_YCBCR420:
1141                         if ((win->id == 0) || (win->id == 1))
1142                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1143                         break;
1144                 default:
1145                         break;
1146                 }
1147         }
1148 }
1149
1150 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1151 {
1152         struct lcdc_device *lcdc_dev =
1153             container_of(dev_drv, struct lcdc_device, driver);
1154         struct rk_lcdc_win *win = dev_drv->win[win_id];
1155         unsigned int mask, val, off;
1156
1157         off = win_id * 0x40;
1158         /*if(win->win_lb_mode == 5)
1159            win->win_lb_mode = 4;
1160            for rk3288 to fix hw bug? */
1161
1162         if (win->state == 1) {
1163                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1164                 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1165                 if (win->area[0].fbdc_en) {
1166                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1167                 } else {
1168                         mask = m_IFBDC_CTRL_FBDC_EN;
1169                         val = v_IFBDC_CTRL_FBDC_EN(0);
1170                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1171                 }
1172                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1173                     m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1174                     m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE |m_WIN0_UV_SWAP;
1175                 val = v_WIN0_EN(win->state) |
1176                     v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1177                     v_WIN0_FMT_10(win->fmt_10) |
1178                     v_WIN0_LB_MODE(win->win_lb_mode) |
1179                     v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1180                     v_WIN0_X_MIRROR(win->mirror_en) |
1181                     v_WIN0_Y_MIRROR(win->mirror_en) |
1182                     v_WIN0_CSC_MODE(win->csc_mode) |
1183                     v_WIN0_UV_SWAP(win->area[0].swap_uv);
1184                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1185
1186                 mask = m_WIN0_BIC_COE_SEL |
1187                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1188                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1189                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1190                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1191                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1192                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1193                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1194                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1195                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1196                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1197                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1198                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1199                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1200                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1201                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1202                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1203                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1204                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1205                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1206                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1207                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1208                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1209                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1210                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1211                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1212                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1213                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1214                                 win->area[0].y_addr);
1215                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1216                                 win->area[0].uv_addr); */
1217                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1218                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1219                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1220
1221                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1222                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1223                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1224
1225                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1226                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1227                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1228
1229                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1230                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1231                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1232
1233                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1234                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1235                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1236                 if (win->alpha_en == 1) {
1237                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1238                 } else {
1239                         mask = m_WIN0_SRC_ALPHA_EN;
1240                         val = v_WIN0_SRC_ALPHA_EN(0);
1241                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1242                                      mask, val);
1243                 }
1244         } else {
1245                 mask = m_WIN0_EN;
1246                 val = v_WIN0_EN(win->state);
1247                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1248         }
1249         return 0;
1250 }
1251
1252 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1253 {
1254         struct lcdc_device *lcdc_dev =
1255             container_of(dev_drv, struct lcdc_device, driver);
1256         struct rk_lcdc_win *win = dev_drv->win[win_id];
1257         unsigned int mask, val, off;
1258
1259         off = (win_id - 2) * 0x50;
1260         rk3368_lcdc_area_xst(win, win->area_num);
1261
1262         if (win->state == 1) {
1263                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1264                 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1265                 if (win->area[0].fbdc_en) {
1266                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1267                 } else {
1268                         mask = m_IFBDC_CTRL_FBDC_EN;
1269                         val = v_IFBDC_CTRL_FBDC_EN(0);
1270                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1271                 }
1272
1273                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1274                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1275                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1276                 /*area 0 */
1277                 if (win->area[0].state == 1) {
1278                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1279                             m_WIN2_RB_SWAP0;
1280                         val = v_WIN2_MST0_EN(win->area[0].state) |
1281                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1282                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1283                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1284
1285                         mask = m_WIN2_VIR_STRIDE0;
1286                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1287                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1288
1289                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1290                            win->area[0].y_addr); */
1291                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1292                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1293                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1294                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1295                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1296                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1297                 } else {
1298                         mask = m_WIN2_MST0_EN;
1299                         val = v_WIN2_MST0_EN(0);
1300                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1301                 }
1302                 /*area 1 */
1303                 if (win->area[1].state == 1) {
1304                         /*rk3368_win_area_check_var(win_id, 1,
1305                                                   &win->area[0], &win->area[1]);
1306                         */
1307
1308                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1309                             m_WIN2_RB_SWAP1;
1310                         val = v_WIN2_MST1_EN(win->area[1].state) |
1311                             v_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1312                             v_WIN2_RB_SWAP1(win->area[1].swap_rb);
1313                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1314
1315                         mask = m_WIN2_VIR_STRIDE1;
1316                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1317                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1318
1319                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1320                            win->area[1].y_addr); */
1321                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1322                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1323                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1324                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1325                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1326                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1327                 } else {
1328                         mask = m_WIN2_MST1_EN;
1329                         val = v_WIN2_MST1_EN(0);
1330                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1331                 }
1332                 /*area 2 */
1333                 if (win->area[2].state == 1) {
1334                         /*rk3368_win_area_check_var(win_id, 2,
1335                                                   &win->area[1], &win->area[2]);
1336                         */
1337
1338                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1339                             m_WIN2_RB_SWAP2;
1340                         val = v_WIN2_MST2_EN(win->area[2].state) |
1341                             v_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1342                             v_WIN2_RB_SWAP2(win->area[2].swap_rb);
1343                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1344
1345                         mask = m_WIN2_VIR_STRIDE2;
1346                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1347                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1348
1349                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1350                            win->area[2].y_addr); */
1351                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1352                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1353                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1354                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1355                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1356                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1357                 } else {
1358                         mask = m_WIN2_MST2_EN;
1359                         val = v_WIN2_MST2_EN(0);
1360                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1361                 }
1362                 /*area 3 */
1363                 if (win->area[3].state == 1) {
1364                         /*rk3368_win_area_check_var(win_id, 3,
1365                                                   &win->area[2], &win->area[3]);
1366                         */
1367
1368                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1369                             m_WIN2_RB_SWAP3;
1370                         val = v_WIN2_MST3_EN(win->area[3].state) |
1371                             v_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1372                             v_WIN2_RB_SWAP3(win->area[3].swap_rb);
1373                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1374
1375                         mask = m_WIN2_VIR_STRIDE3;
1376                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1377                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1378
1379                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1380                            win->area[3].y_addr); */
1381                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1382                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1383                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1384                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1385                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1386                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1387                 } else {
1388                         mask = m_WIN2_MST3_EN;
1389                         val = v_WIN2_MST3_EN(0);
1390                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1391                 }
1392
1393                 if (win->alpha_en == 1) {
1394                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1395                 } else {
1396                         mask = m_WIN2_SRC_ALPHA_EN;
1397                         val = v_WIN2_SRC_ALPHA_EN(0);
1398                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1399                                      mask, val);
1400                 }
1401         } else {
1402                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1403                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1404                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1405                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1406                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1407         }
1408         return 0;
1409 }
1410
1411 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1412 {
1413         struct lcdc_device *lcdc_dev =
1414             container_of(dev_drv, struct lcdc_device, driver);
1415         struct rk_lcdc_win *win = dev_drv->win[win_id];
1416         unsigned int mask, val, hwc_size = 0;
1417
1418         if (win->state == 1) {
1419                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1420                 rk3368_lcdc_axi_gather_cfg(lcdc_dev, win);
1421                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1422                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1423                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1424                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1425                     v_WIN0_CSC_MODE(win->csc_mode);
1426                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1427
1428                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1429                         hwc_size = 0;
1430                 else if ((win->area[0].xsize == 64) &&
1431                          (win->area[0].ysize == 64))
1432                         hwc_size = 1;
1433                 else if ((win->area[0].xsize == 96) &&
1434                          (win->area[0].ysize == 96))
1435                         hwc_size = 2;
1436                 else if ((win->area[0].xsize == 128) &&
1437                          (win->area[0].ysize == 128))
1438                         hwc_size = 3;
1439                 else
1440                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1441
1442                 mask = m_HWC_SIZE;
1443                 val = v_HWC_SIZE(hwc_size);
1444                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1445
1446                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1447                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1448                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1449                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1450
1451                 if (win->alpha_en == 1) {
1452                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1453                 } else {
1454                         mask = m_WIN2_SRC_ALPHA_EN;
1455                         val = v_WIN2_SRC_ALPHA_EN(0);
1456                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1457                 }
1458         } else {
1459                 mask = m_HWC_EN;
1460                 val = v_HWC_EN(win->state);
1461                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1462         }
1463         return 0;
1464 }
1465
1466 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1467                                          struct rk_lcdc_win *win)
1468 {
1469         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1470         int timeout;
1471         unsigned long flags;
1472
1473         if (likely(lcdc_dev->clk_on)) {
1474                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1475                              v_STANDBY_EN(lcdc_dev->standby));
1476                 if ((win->id == 0) || (win->id == 1))
1477                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1478                 else if ((win->id == 2) || (win->id == 3))
1479                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1480                 else if (win->id == 4)
1481                         rk3368_hwc_reg_update(dev_drv, win->id);
1482                 /*rk3368_lcdc_post_cfg(dev_drv); */
1483                 lcdc_cfg_done(lcdc_dev);
1484         }
1485
1486         /*if (dev_drv->wait_fs) { */
1487         if (0) {
1488                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1489                 init_completion(&dev_drv->frame_done);
1490                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1491                 timeout =
1492                     wait_for_completion_timeout(&dev_drv->frame_done,
1493                                                 msecs_to_jiffies
1494                                                 (dev_drv->cur_screen->ft + 5));
1495                 if (!timeout && (!dev_drv->frame_done.done)) {
1496                         dev_warn(lcdc_dev->dev,
1497                                  "wait for new frame start time out!\n");
1498                         return -ETIMEDOUT;
1499                 }
1500         }
1501         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1502         return 0;
1503 }
1504
1505 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1506 {
1507         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x270);
1508         return 0;
1509 }
1510
1511 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1512 {
1513         u32 mask, val;
1514         struct lcdc_device *lcdc_dev =
1515             container_of(dev_drv, struct lcdc_device, driver);
1516
1517 #if defined(CONFIG_ROCKCHIP_IOMMU)
1518         if (dev_drv->iommu_enabled) {
1519                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1520                         if (likely(lcdc_dev->clk_on)) {
1521                                 mask = m_MMU_EN;
1522                                 val = v_MMU_EN(1);
1523                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1524                                 mask = m_AXI_MAX_OUTSTANDING_EN |
1525                                         m_AXI_OUTSTANDING_MAX_NUM;
1526                                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1527                                         v_AXI_MAX_OUTSTANDING_EN(1);
1528                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1529                         }
1530                         lcdc_dev->iommu_status = 1;
1531                         rockchip_iovmm_activate(dev_drv->dev);
1532                 }
1533         }
1534 #endif
1535         return 0;
1536 }
1537
1538 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1539 {
1540         int ret = 0, fps = 0;
1541         struct lcdc_device *lcdc_dev =
1542             container_of(dev_drv, struct lcdc_device, driver);
1543         struct rk_screen *screen = dev_drv->cur_screen;
1544 #ifdef CONFIG_RK_FPGA
1545         return 0;
1546 #endif
1547         if (reset_rate)
1548                 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1549         if (ret)
1550                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1551         lcdc_dev->pixclock =
1552             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1553         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1554
1555         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1556         screen->ft = 1000 / fps;
1557         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1558                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1559         return 0;
1560 }
1561
1562 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1563 {
1564         struct lcdc_device *lcdc_dev =
1565             container_of(dev_drv, struct lcdc_device, driver);
1566         struct rk_screen *screen = dev_drv->cur_screen;
1567         u16 hsync_len = screen->mode.hsync_len;
1568         u16 left_margin = screen->mode.left_margin;
1569         u16 right_margin = screen->mode.right_margin;
1570         u16 vsync_len = screen->mode.vsync_len;
1571         u16 upper_margin = screen->mode.upper_margin;
1572         u16 lower_margin = screen->mode.lower_margin;
1573         u16 x_res = screen->mode.xres;
1574         u16 y_res = screen->mode.yres;
1575         u32 mask, val;
1576         u16 h_total, v_total;
1577         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1578
1579         h_total = hsync_len + left_margin + x_res + right_margin;
1580         v_total = vsync_len + upper_margin + y_res + lower_margin;
1581
1582         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1583         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1584         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1585
1586         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1587         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1588             v_DSP_HACT_ST(hsync_len + left_margin);
1589         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1590
1591         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1592                 /* First Field Timing */
1593                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1594                 val = v_DSP_VS_PW(vsync_len) |
1595                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1596                                       lower_margin) + y_res + 1);
1597                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1598
1599                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1600                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1601                     v_DSP_VACT_ST(vsync_len + upper_margin);
1602                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1603
1604                 /* Second Field Timing */
1605                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1606                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1607                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1608                     lower_margin;
1609                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1610                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1611
1612                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1613                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1614                     lower_margin + 1;
1615                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1616                     lower_margin + 1;
1617                 val =
1618                     v_DSP_VACT_END_F1(vact_end_f1) |
1619                     v_DSP_VAC_ST_F1(vact_st_f1);
1620                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1621
1622                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1623                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1624                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1625                 mask =
1626                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1627                     m_WIN0_CBR_DEFLICK;
1628                 val =
1629                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1630                     v_WIN0_CBR_DEFLICK(1);
1631                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1632
1633                 mask =
1634                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1635                     m_WIN1_CBR_DEFLICK;
1636                 val =
1637                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1638                     v_WIN1_CBR_DEFLICK(1);
1639                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1640
1641                 mask = m_WIN2_INTERLACE_READ;
1642                 val = v_WIN2_INTERLACE_READ(1);
1643                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1644
1645                 mask = m_WIN3_INTERLACE_READ;
1646                 val = v_WIN3_INTERLACE_READ(1);
1647                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1648
1649                 mask = m_HWC_INTERLACE_READ;
1650                 val = v_HWC_INTERLACE_READ(1);
1651                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1652
1653                 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1654                 val =
1655                     v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2) |
1656                     v_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res / 2);
1657                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1658         } else {
1659                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1660                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1661                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1662
1663                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1664                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1665                     v_DSP_VACT_ST(vsync_len + upper_margin);
1666                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1667
1668                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1669                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1670                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1671
1672                 mask =
1673                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1674                     m_WIN0_CBR_DEFLICK;
1675                 val =
1676                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1677                     v_WIN0_CBR_DEFLICK(0);
1678                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1679
1680                 mask =
1681                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1682                     m_WIN1_CBR_DEFLICK;
1683                 val =
1684                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1685                     v_WIN1_CBR_DEFLICK(0);
1686                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1687
1688                 mask = m_WIN2_INTERLACE_READ;
1689                 val = v_WIN2_INTERLACE_READ(0);
1690                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1691
1692                 mask = m_WIN3_INTERLACE_READ;
1693                 val = v_WIN3_INTERLACE_READ(0);
1694                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1695
1696                 mask = m_HWC_INTERLACE_READ;
1697                 val = v_HWC_INTERLACE_READ(0);
1698                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1699
1700                 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1701                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res) |
1702                         v_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res);
1703                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1704         }
1705         rk3368_lcdc_post_cfg(dev_drv);
1706         return 0;
1707 }
1708
1709 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1710 {
1711         struct lcdc_device *lcdc_dev =
1712             container_of(dev_drv, struct lcdc_device, driver);
1713         u32 bcsh_ctrl;
1714
1715         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1716                      v_OVERLAY_MODE(dev_drv->overlay_mode));
1717         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1718                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1719                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1720                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1721                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1722                 else            /* YUV2RGB */
1723                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1724                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1725                                      m_BCSH_R2Y_EN,
1726                                      v_BCSH_Y2R_EN(1) |
1727                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1728                                      v_BCSH_R2Y_EN(0));
1729         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1730                 /* bypass  --need check,if bcsh close? */
1731                 if (dev_drv->output_color == COLOR_RGB) {
1732                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1733                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1734                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1735                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1736                                              m_BCSH_R2Y_EN |
1737                                              m_BCSH_Y2R_EN,
1738                                              v_BCSH_R2Y_EN(1) |
1739                                              v_BCSH_Y2R_EN(1));
1740                         else
1741                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1742                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1743                                              v_BCSH_R2Y_EN(0) |
1744                                              v_BCSH_Y2R_EN(0));
1745                 } else          /* RGB2YUV */
1746                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1747                                      m_BCSH_R2Y_EN |
1748                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1749                                      v_BCSH_R2Y_EN(1) |
1750                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1751                                      v_BCSH_Y2R_EN(0));
1752         }
1753 }
1754
1755 static int rk3368_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1756                                   u16 *yact, int *format, u32 *dsp_addr)
1757 {
1758         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1759                                                     struct lcdc_device, driver);
1760         u32 val;
1761
1762         spin_lock(&lcdc_dev->reg_lock);
1763
1764         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1765         *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1766         *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1767
1768         val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1769         *format = (val & m_WIN0_DATA_FMT) >> 1;
1770         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1771
1772         spin_unlock(&lcdc_dev->reg_lock);
1773
1774         return 0;
1775 }
1776
1777 static int rk3368_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1778                               int format, u16 xact, u16 yact, u16 xvir)
1779 {
1780         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1781                                                     struct lcdc_device, driver);
1782         u32 val, mask;
1783         int swap = (format == RGB888) ? 1 : 0;
1784
1785         mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1786         val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1787         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1788
1789         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1790                         v_WIN0_VIR_STRIDE(xvir));
1791         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1792                     v_WIN0_ACT_HEIGHT(yact));
1793
1794         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1795
1796         lcdc_cfg_done(lcdc_dev);
1797
1798         return 0;
1799 }
1800
1801 static int lcdc_reset(struct rk_lcdc_driver *dev_drv, bool initscreen)
1802 {
1803         struct lcdc_device *lcdc_dev =
1804             container_of(dev_drv, struct lcdc_device, driver);
1805         u32 mask, val;
1806         u32 __maybe_unused v;
1807         /*printk("0407:standby=%d,initscreen=%d,dev_drv->first_frame=%d\n",
1808                 lcdc_dev->standby,initscreen,dev_drv->first_frame);*/
1809         if (!lcdc_dev->standby && initscreen && (dev_drv->first_frame != 1)) {
1810                 mdelay(150);
1811                 mask = m_WIN0_EN;
1812                 val = v_WIN0_EN(0);
1813                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1814                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1815
1816                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1817                         m_WIN2_MST1_EN |
1818                         m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1819                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
1820                         v_WIN2_MST1_EN(0) |
1821                         v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1822                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1823                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1824                 mask = m_HDMI_OUT_EN;
1825                 val = v_HDMI_OUT_EN(0);
1826                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1827                 lcdc_cfg_done(lcdc_dev);
1828                 mdelay(50);
1829                 writel_relaxed(0, lcdc_dev->regs + REG_CFG_DONE);
1830 #if 0
1831                 if (dev_drv->iommu_enabled) {
1832                         if (dev_drv->mmu_dev)
1833                                 rockchip_iovmm_deactivate(dev_drv->dev);
1834                 }
1835                 lcdc_cru_writel(lcdc_dev->cru_base, 0x0318,
1836                                 (1 << 4)  | (1 << 5)  | (1 << 6) |
1837                                 (1 << 20) | (1 << 21) | (1 << 22));
1838                 udelay(100);
1839                 v = lcdc_cru_readl(lcdc_dev->cru_base, 0x0318);
1840                 pr_info("cru read = 0x%x\n", v);
1841                 lcdc_cru_writel(lcdc_dev->cru_base, 0x0318,
1842                                 (0 << 4)  | (0 << 5)  | (0 << 6) |
1843                                 (1 << 20) | (1 << 21) | (1 << 22));
1844                 mdelay(100);
1845                 if (dev_drv->iommu_enabled) {
1846                         if (dev_drv->mmu_dev)
1847                                 rockchip_iovmm_activate(dev_drv->dev);
1848                 }
1849                 mdelay(50);
1850                 rk3368_lcdc_reg_restore(lcdc_dev);
1851                 mdelay(50);
1852 #endif
1853         }
1854         return 0;
1855 }
1856
1857 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1858 {
1859         u16 face = 0;
1860         u16 dclk_ddr = 0;
1861         u32 v = 0;
1862         struct lcdc_device *lcdc_dev =
1863             container_of(dev_drv, struct lcdc_device, driver);
1864         struct rk_screen *screen = dev_drv->cur_screen;
1865         u32 mask, val;
1866         if (!lcdc_dev->standby && initscreen && (dev_drv->first_frame != 1))
1867                 flush_kthread_worker(&dev_drv->update_regs_worker);
1868
1869         spin_lock(&lcdc_dev->reg_lock);
1870         if (likely(lcdc_dev->clk_on)) {
1871                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1872 #if 0
1873                 if (!lcdc_dev->standby && !initscreen) {
1874                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1875                                      v_STANDBY_EN(1));
1876                         lcdc_cfg_done(lcdc_dev);
1877                         mdelay(50);
1878                 }
1879 #else
1880         lcdc_reset(dev_drv, initscreen);
1881 #endif
1882                 switch (screen->face) {
1883                 case OUT_P565:
1884                         face = OUT_P565;
1885                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1886                             m_DITHER_DOWN_SEL;
1887                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1888                             v_DITHER_DOWN_SEL(1);
1889                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1890                         break;
1891                 case OUT_P666:
1892                         face = OUT_P666;
1893                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1894                             m_DITHER_DOWN_SEL;
1895                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1896                             v_DITHER_DOWN_SEL(1);
1897                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1898                         break;
1899                 case OUT_D888_P565:
1900                         face = OUT_P888;
1901                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1902                             m_DITHER_DOWN_SEL;
1903                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1904                             v_DITHER_DOWN_SEL(1);
1905                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1906                         break;
1907                 case OUT_D888_P666:
1908                         face = OUT_P888;
1909                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1910                             m_DITHER_DOWN_SEL;
1911                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1912                             v_DITHER_DOWN_SEL(1);
1913                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1914                         break;
1915                 case OUT_P888:
1916                         face = OUT_P888;
1917                         mask = m_DITHER_DOWN_EN;
1918                         val = v_DITHER_DOWN_EN(0);
1919                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1920                         break;
1921                 case OUT_YUV_420:
1922                         /*yuv420 output prefer yuv domain overlay */
1923                         face = OUT_YUV_420;
1924                         dclk_ddr = 1;
1925                         mask = m_DITHER_DOWN_EN;
1926                         val = v_DITHER_DOWN_EN(0);
1927                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1928                         break;
1929                 default:
1930                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1931                         break;
1932                 }
1933                 switch (screen->type) {
1934                 case SCREEN_RGB:
1935                         mask = m_RGB_OUT_EN;
1936                         val = v_RGB_OUT_EN(1);
1937                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1938                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1939                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1940                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1941                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1942                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1943                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1944                         v = 1 << 15 | (1 << (15 + 16));
1945
1946                         break;
1947                 case SCREEN_LVDS:
1948                         mask = m_RGB_OUT_EN;
1949                         val = v_RGB_OUT_EN(1);
1950                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1951                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1952                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1953                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1954                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1955                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1956                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1957                         v = 0 << 15 | (1 << (15 + 16));
1958                         break;
1959                 case SCREEN_HDMI:
1960                         /*face = OUT_RGB_AAA;*/
1961                         if (screen->color_mode == COLOR_RGB)
1962                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1963                         else
1964                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1965                         mask = m_HDMI_OUT_EN  | m_RGB_OUT_EN;
1966                         val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
1967                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1968                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1969                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1970                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1971                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
1972                             v_HDMI_DEN_POL(screen->pin_den) |
1973                             v_HDMI_DCLK_POL(screen->pin_dclk);
1974                         break;
1975                 case SCREEN_MIPI:
1976                         mask = m_MIPI_OUT_EN  | m_RGB_OUT_EN;
1977                         val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
1978                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1979                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1980                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1981                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1982                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1983                             v_MIPI_DEN_POL(screen->pin_den) |
1984                             v_MIPI_DCLK_POL(screen->pin_dclk);
1985                         break;
1986                 case SCREEN_DUAL_MIPI:
1987                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN  |
1988                                 m_RGB_OUT_EN;
1989                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
1990                                 v_RGB_OUT_EN(0);
1991                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1992                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1993                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1994                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1995                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1996                             v_MIPI_DEN_POL(screen->pin_den) |
1997                             v_MIPI_DCLK_POL(screen->pin_dclk);
1998                         break;
1999                 case SCREEN_EDP:
2000                         face = OUT_P888;        /*RGB 888 output */
2001
2002                         mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
2003                         val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
2004                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
2005                         /*because edp have to sent aaa fmt */
2006                         mask = m_DITHER_DOWN_EN;
2007                         val = v_DITHER_DOWN_EN(0);
2008
2009                         mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
2010                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
2011                         val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
2012                             v_EDP_VSYNC_POL(screen->pin_vsync) |
2013                             v_EDP_DEN_POL(screen->pin_den) |
2014                             v_EDP_DCLK_POL(screen->pin_dclk);
2015                         break;
2016                 }
2017                 /*hsync vsync den dclk polo,dither */
2018                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
2019 #ifndef CONFIG_RK_FPGA
2020                 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
2021                 move to  lvds driver*/
2022                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
2023 #endif
2024                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
2025                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
2026                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
2027                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
2028                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
2029                     v_DSP_BG_SWAP(screen->swap_gb) |
2030                     v_DSP_RB_SWAP(screen->swap_rb) |
2031                     v_DSP_RG_SWAP(screen->swap_rg) |
2032                     v_DSP_DELTA_SWAP(screen->swap_delta) |
2033                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
2034                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
2035                     v_DSP_X_MIR_EN(screen->x_mirror) |
2036                     v_DSP_Y_MIR_EN(screen->y_mirror);
2037                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
2038                 /*BG color */
2039                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
2040                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
2041                         val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
2042                                 v_DSP_BG_RED(0x80);
2043                 else
2044                         val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
2045                                 v_DSP_BG_RED(0);
2046                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
2047                 dev_drv->output_color = screen->color_mode;
2048                 if (screen->dsp_lut == NULL)
2049                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2050                                      v_DSP_LUT_EN(0));
2051                 else
2052                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2053                                      v_DSP_LUT_EN(1));
2054                 rk3368_lcdc_bcsh_path_sel(dev_drv);
2055                 rk3368_config_timing(dev_drv);
2056         }
2057         spin_unlock(&lcdc_dev->reg_lock);
2058         rk3368_lcdc_set_dclk(dev_drv, 1);
2059         if (screen->type != SCREEN_HDMI &&
2060             screen->type != SCREEN_TVOUT &&
2061             dev_drv->trsm_ops &&
2062             dev_drv->trsm_ops->enable)
2063                 dev_drv->trsm_ops->enable();
2064         if (screen->init)
2065                 screen->init();
2066         if (!lcdc_dev->standby)
2067                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
2068         return 0;
2069 }
2070
2071
2072 /*enable layer,open:1,enable;0 disable*/
2073 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
2074                                      unsigned int win_id, bool open)
2075 {
2076         spin_lock(&lcdc_dev->reg_lock);
2077         if (likely(lcdc_dev->clk_on) &&
2078             lcdc_dev->driver.win[win_id]->state != open) {
2079                 if (open) {
2080                         if (!lcdc_dev->atv_layer_cnt) {
2081                                 dev_info(lcdc_dev->dev,
2082                                          "wakeup from standby!\n");
2083                                 lcdc_dev->standby = 0;
2084                         }
2085                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
2086                 } else {
2087                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
2088                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
2089                 }
2090                 lcdc_dev->driver.win[win_id]->state = open;
2091                 if (!open) {
2092                         /*rk3368_lcdc_reg_update(dev_drv);*/
2093                         rk3368_lcdc_layer_update_regs
2094                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
2095                         lcdc_cfg_done(lcdc_dev);
2096                 }
2097                 /*if no layer used,disable lcdc */
2098                 if (!lcdc_dev->atv_layer_cnt) {
2099                         dev_info(lcdc_dev->dev,
2100                                  "no layer is used,go to standby!\n");
2101                         lcdc_dev->standby = 1;
2102                 }
2103         }
2104         spin_unlock(&lcdc_dev->reg_lock);
2105 }
2106
2107 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
2108 {
2109         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2110                                                     struct lcdc_device, driver);
2111         u32 mask, val;
2112         /*struct rk_screen *screen = dev_drv->cur_screen; */
2113
2114         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
2115             m_LINE_FLAG1_INTR_CLR;
2116         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
2117             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
2118         lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
2119
2120         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN |
2121                 m_BUS_ERROR_INTR_EN | m_LINE_FLAG1_INTR_EN;
2122         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
2123             v_BUS_ERROR_INTR_EN(1) | v_LINE_FLAG1_INTR_EN(0);
2124         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
2125
2126 #ifdef LCDC_IRQ_EMPTY_DEBUG
2127         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
2128             m_WIN2_EMPTY_INTR_EN |
2129             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
2130             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
2131         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
2132             v_WIN2_EMPTY_INTR_EN(1) |
2133             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
2134             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
2135         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
2136 #endif
2137         return 0;
2138 }
2139
2140 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
2141                             bool open)
2142 {
2143         struct lcdc_device *lcdc_dev =
2144             container_of(dev_drv, struct lcdc_device, driver);
2145 #if 0/*ndef CONFIG_RK_FPGA*/
2146         int sys_status =
2147             (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
2148 #endif
2149         /*enable clk,when first layer open */
2150         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
2151                 /*rockchip_set_system_status(sys_status);*/
2152                 rk3368_lcdc_pre_init(dev_drv);
2153                 rk3368_lcdc_clk_enable(lcdc_dev);
2154                 rk3368_lcdc_enable_irq(dev_drv);
2155 #if defined(CONFIG_ROCKCHIP_IOMMU)
2156                 if (dev_drv->iommu_enabled) {
2157                         if (!dev_drv->mmu_dev) {
2158                                 dev_drv->mmu_dev =
2159                                     rk_fb_get_sysmmu_device_by_compatible
2160                                     (dev_drv->mmu_dts_name);
2161                                 if (dev_drv->mmu_dev) {
2162                                         rk_fb_platform_set_sysmmu
2163                                             (dev_drv->mmu_dev, dev_drv->dev);
2164                                 } else {
2165                                         dev_err(dev_drv->dev,
2166                                                 "fail get rk iommu device\n");
2167                                         return -1;
2168                                 }
2169                         }
2170                         /*if (dev_drv->mmu_dev)
2171                            rockchip_iovmm_activate(dev_drv->dev); */
2172                 }
2173 #endif
2174                 rk3368_lcdc_reg_restore(lcdc_dev);
2175                 /*if (dev_drv->iommu_enabled)
2176                    rk3368_lcdc_mmu_en(dev_drv); */
2177                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
2178                         rk3368_lcdc_set_dclk(dev_drv, 0);
2179                         /*rk3368_lcdc_enable_irq(dev_drv);*/
2180                 } else {
2181                         rk3368_load_screen(dev_drv, 1);
2182                 }
2183                 if (dev_drv->bcsh.enable)
2184                         rk3368_lcdc_set_bcsh(dev_drv, 1);
2185                 spin_lock(&lcdc_dev->reg_lock);
2186                 if (dev_drv->cur_screen->dsp_lut)
2187                         rk3368_lcdc_set_lut(dev_drv,
2188                                             dev_drv->cur_screen->dsp_lut);
2189                 if (dev_drv->cur_screen->cabc_lut)
2190                         rk3368_set_cabc_lut(dev_drv,
2191                                             dev_drv->cur_screen->cabc_lut);
2192                 spin_unlock(&lcdc_dev->reg_lock);
2193         }
2194
2195         if (win_id < ARRAY_SIZE(lcdc_win))
2196                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
2197         else
2198                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
2199
2200
2201         /* when all layer closed,disable clk */
2202         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
2203            rk3368_lcdc_disable_irq(lcdc_dev);
2204            rk3368_lcdc_reg_update(dev_drv);
2205            #if defined(CONFIG_ROCKCHIP_IOMMU)
2206            if (dev_drv->iommu_enabled) {
2207            if (dev_drv->mmu_dev)
2208            rockchip_iovmm_deactivate(dev_drv->dev);
2209            }
2210            #endif
2211            rk3368_lcdc_clk_disable(lcdc_dev);
2212            #ifndef CONFIG_RK_FPGA
2213            rockchip_clear_system_status(sys_status);
2214            #endif
2215            } */
2216         dev_drv->first_frame = 0;
2217         return 0;
2218 }
2219
2220 static int win_0_1_display(struct lcdc_device *lcdc_dev,
2221                            struct rk_lcdc_win *win)
2222 {
2223         u32 y_addr;
2224         u32 uv_addr;
2225         unsigned int off;
2226
2227         off = win->id * 0x40;
2228         /*win->smem_start + win->y_offset; */
2229         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2230         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2231         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2232             lcdc_dev->id, win->id, y_addr, uv_addr);
2233         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2234             win->area[0].y_offset, win->area[0].c_offset);
2235         spin_lock(&lcdc_dev->reg_lock);
2236         if (likely(lcdc_dev->clk_on)) {
2237                 win->area[0].y_addr = y_addr;
2238                 win->area[0].uv_addr = uv_addr;
2239                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2240                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2241                 if (win->area[0].fbdc_en == 1)
2242                         lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2243                                         win->area[0].y_addr);
2244         }
2245         spin_unlock(&lcdc_dev->reg_lock);
2246
2247         return 0;
2248 }
2249
2250 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2251                            struct rk_lcdc_win *win)
2252 {
2253         u32 i, y_addr;
2254         unsigned int off;
2255
2256         off = (win->id - 2) * 0x50;
2257         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2258         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2259
2260         spin_lock(&lcdc_dev->reg_lock);
2261         if (likely(lcdc_dev->clk_on)) {
2262                 for (i = 0; i < win->area_num; i++) {
2263                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2264                             i, win->area[i].y_addr, win->area[i].y_offset);
2265                         win->area[i].y_addr =
2266                             win->area[i].smem_start + win->area[i].y_offset;
2267                         }
2268                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2269                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2270                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2271                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2272                 if (win->area[0].fbdc_en == 1)
2273                         lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2274                                         win->area[0].y_addr);
2275         }
2276         spin_unlock(&lcdc_dev->reg_lock);
2277         return 0;
2278 }
2279
2280 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2281 {
2282         u32 y_addr;
2283
2284         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2285         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2286             lcdc_dev->id, __func__, y_addr);
2287         spin_lock(&lcdc_dev->reg_lock);
2288         if (likely(lcdc_dev->clk_on)) {
2289                 win->area[0].y_addr = y_addr;
2290                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2291         }
2292         spin_unlock(&lcdc_dev->reg_lock);
2293
2294         return 0;
2295 }
2296
2297 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2298 {
2299         struct lcdc_device *lcdc_dev =
2300             container_of(dev_drv, struct lcdc_device, driver);
2301         struct rk_lcdc_win *win = NULL;
2302         struct rk_screen *screen = dev_drv->cur_screen;
2303
2304 #if defined(WAIT_FOR_SYNC)
2305         int timeout;
2306         unsigned long flags;
2307 #endif
2308         win = dev_drv->win[win_id];
2309         if (!screen) {
2310                 dev_err(dev_drv->dev, "screen is null!\n");
2311                 return -ENOENT;
2312         }
2313         if (win_id == 0) {
2314                 win_0_1_display(lcdc_dev, win);
2315         } else if (win_id == 1) {
2316                 win_0_1_display(lcdc_dev, win);
2317         } else if (win_id == 2) {
2318                 win_2_3_display(lcdc_dev, win);
2319         } else if (win_id == 3) {
2320                 win_2_3_display(lcdc_dev, win);
2321         } else if (win_id == 4) {
2322                 hwc_display(lcdc_dev, win);
2323         } else {
2324                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2325                 return -EINVAL;
2326         }
2327
2328 #if defined(WAIT_FOR_SYNC)
2329         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2330         init_completion(&dev_drv->frame_done);
2331         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2332         timeout =
2333             wait_for_completion_timeout(&dev_drv->frame_done,
2334                                         msecs_to_jiffies(dev_drv->
2335                                                          cur_screen->ft + 5));
2336         if (!timeout && (!dev_drv->frame_done.done)) {
2337                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2338                 return -ETIMEDOUT;
2339         }
2340 #endif
2341         return 0;
2342 }
2343
2344 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2345 {
2346         u16 srcW;
2347         u16 srcH;
2348         u16 dstW;
2349         u16 dstH;
2350         u16 yrgb_srcW;
2351         u16 yrgb_srcH;
2352         u16 yrgb_dstW;
2353         u16 yrgb_dstH;
2354         u32 yrgb_vscalednmult;
2355         u32 yrgb_xscl_factor;
2356         u32 yrgb_yscl_factor;
2357         u8 yrgb_vsd_bil_gt2 = 0;
2358         u8 yrgb_vsd_bil_gt4 = 0;
2359
2360         u16 cbcr_srcW;
2361         u16 cbcr_srcH;
2362         u16 cbcr_dstW;
2363         u16 cbcr_dstH;
2364         u32 cbcr_vscalednmult;
2365         u32 cbcr_xscl_factor;
2366         u32 cbcr_yscl_factor;
2367         u8 cbcr_vsd_bil_gt2 = 0;
2368         u8 cbcr_vsd_bil_gt4 = 0;
2369         u8 yuv_fmt = 0;
2370
2371         srcW = win->area[0].xact;
2372         srcH = win->area[0].yact;
2373         dstW = win->area[0].xsize;
2374         dstH = win->area[0].ysize;
2375
2376         /*yrgb scl mode */
2377         yrgb_srcW = srcW;
2378         yrgb_srcH = srcH;
2379         yrgb_dstW = dstW;
2380         yrgb_dstH = dstH;
2381         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2382                 pr_err("ERROR: yrgb scale exceed 8,");
2383                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2384                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2385         }
2386         if (yrgb_srcW < yrgb_dstW)
2387                 win->yrgb_hor_scl_mode = SCALE_UP;
2388         else if (yrgb_srcW > yrgb_dstW)
2389                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2390         else
2391                 win->yrgb_hor_scl_mode = SCALE_NONE;
2392
2393         if (yrgb_srcH < yrgb_dstH)
2394                 win->yrgb_ver_scl_mode = SCALE_UP;
2395         else if (yrgb_srcH > yrgb_dstH)
2396                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2397         else
2398                 win->yrgb_ver_scl_mode = SCALE_NONE;
2399
2400         /*cbcr scl mode */
2401         switch (win->area[0].format) {
2402         case YUV422:
2403         case YUV422_A:
2404                 cbcr_srcW = srcW / 2;
2405                 cbcr_dstW = dstW;
2406                 cbcr_srcH = srcH;
2407                 cbcr_dstH = dstH;
2408                 yuv_fmt = 1;
2409                 break;
2410         case YUV420:
2411         case YUV420_A:
2412         case YUV420_NV21:
2413                 cbcr_srcW = srcW / 2;
2414                 cbcr_dstW = dstW;
2415                 cbcr_srcH = srcH / 2;
2416                 cbcr_dstH = dstH;
2417                 yuv_fmt = 1;
2418                 break;
2419         case YUV444:
2420         case YUV444_A:
2421                 cbcr_srcW = srcW;
2422                 cbcr_dstW = dstW;
2423                 cbcr_srcH = srcH;
2424                 cbcr_dstH = dstH;
2425                 yuv_fmt = 1;
2426                 break;
2427         default:
2428                 cbcr_srcW = 0;
2429                 cbcr_dstW = 0;
2430                 cbcr_srcH = 0;
2431                 cbcr_dstH = 0;
2432                 yuv_fmt = 0;
2433                 break;
2434         }
2435         if (yuv_fmt) {
2436                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2437                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2438                         pr_err("ERROR: cbcr scale exceed 8,");
2439                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2440                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2441                 }
2442         }
2443
2444         if (cbcr_srcW < cbcr_dstW)
2445                 win->cbr_hor_scl_mode = SCALE_UP;
2446         else if (cbcr_srcW > cbcr_dstW)
2447                 win->cbr_hor_scl_mode = SCALE_DOWN;
2448         else
2449                 win->cbr_hor_scl_mode = SCALE_NONE;
2450
2451         if (cbcr_srcH < cbcr_dstH)
2452                 win->cbr_ver_scl_mode = SCALE_UP;
2453         else if (cbcr_srcH > cbcr_dstH)
2454                 win->cbr_ver_scl_mode = SCALE_DOWN;
2455         else
2456                 win->cbr_ver_scl_mode = SCALE_NONE;
2457
2458         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2459             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2460             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2461             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2462             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2463             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2464             win->cbr_ver_scl_mode);*/
2465
2466         /*line buffer mode */
2467         if ((win->area[0].format == YUV422) ||
2468             (win->area[0].format == YUV420) ||
2469             (win->area[0].format == YUV420_NV21) ||
2470             (win->area[0].format == YUV422_A) ||
2471             (win->area[0].format == YUV420_A)) {
2472                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2473                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2474                             (cbcr_dstW == 0))
2475                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2476                                        cbcr_dstW);
2477                         else if (cbcr_dstW > 1280)
2478                                 win->win_lb_mode = LB_YUV_3840X5;
2479                         else
2480                                 win->win_lb_mode = LB_YUV_2560X8;
2481                 } else {        /*SCALE_UP or SCALE_NONE */
2482                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2483                             (cbcr_srcW == 0))
2484                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2485                                        cbcr_srcW);
2486                         else if (cbcr_srcW > 1280)
2487                                 win->win_lb_mode = LB_YUV_3840X5;
2488                         else
2489                                 win->win_lb_mode = LB_YUV_2560X8;
2490                 }
2491         } else {
2492                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2493                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2494                             (yrgb_dstW == 0))
2495                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2496                         else if (yrgb_dstW > 2560)
2497                                 win->win_lb_mode = LB_RGB_3840X2;
2498                         else if (yrgb_dstW > 1920)
2499                                 win->win_lb_mode = LB_RGB_2560X4;
2500                         else if (yrgb_dstW > 1280)
2501                                 win->win_lb_mode = LB_RGB_1920X5;
2502                         else
2503                                 win->win_lb_mode = LB_RGB_1280X8;
2504                 } else {        /*SCALE_UP or SCALE_NONE */
2505                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2506                             (yrgb_srcW == 0))
2507                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2508                         else if (yrgb_srcW > 2560)
2509                                 win->win_lb_mode = LB_RGB_3840X2;
2510                         else if (yrgb_srcW > 1920)
2511                                 win->win_lb_mode = LB_RGB_2560X4;
2512                         else if (yrgb_srcW > 1280)
2513                                 win->win_lb_mode = LB_RGB_1920X5;
2514                         else
2515                                 win->win_lb_mode = LB_RGB_1280X8;
2516                 }
2517         }
2518         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2519
2520         /*vsd/vsu scale ALGORITHM */
2521         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2522         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2523         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2524         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2525         switch (win->win_lb_mode) {
2526         case LB_YUV_3840X5:
2527         case LB_YUV_2560X8:
2528         case LB_RGB_1920X5:
2529         case LB_RGB_1280X8:
2530                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2531                 win->cbr_vsu_mode = SCALE_UP_BIC;
2532                 break;
2533         case LB_RGB_3840X2:
2534                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2535                         pr_err("ERROR : not allow yrgb ver scale\n");
2536                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2537                         pr_err("ERROR : not allow cbcr ver scale\n");
2538                 break;
2539         case LB_RGB_2560X4:
2540                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2541                 win->cbr_vsu_mode = SCALE_UP_BIL;
2542                 break;
2543         default:
2544                 pr_info("%s:un supported win_lb_mode:%d\n",
2545                         __func__, win->win_lb_mode);
2546                 break;
2547         }
2548         if (win->mirror_en == 1) {      /*interlace mode must bill */
2549                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2550         }
2551
2552         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2553             (win->area[0].fbdc_en == 1)) {
2554                 /*in this pattern,use bil mode,not support souble scd,
2555                 use avg mode, support double scd, but aclk should be
2556                 bigger than dclk,aclk>>dclk */
2557                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2558                         pr_err("ERROR : fbdc mode,not support y scale down:");
2559                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2560                                yrgb_srcH, yrgb_dstH);
2561                 }
2562         }
2563         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2564             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2565             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2566
2567         /*SCALE FACTOR */
2568
2569         /*(1.1)YRGB HOR SCALE FACTOR */
2570         switch (win->yrgb_hor_scl_mode) {
2571         case SCALE_NONE:
2572                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2573                 break;
2574         case SCALE_UP:
2575                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2576                 break;
2577         case SCALE_DOWN:
2578                 switch (win->yrgb_hsd_mode) {
2579                 case SCALE_DOWN_BIL:
2580                         yrgb_xscl_factor =
2581                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2582                         break;
2583                 case SCALE_DOWN_AVG:
2584                         yrgb_xscl_factor =
2585                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2586                         break;
2587                 default:
2588                         pr_info(
2589                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2590                                win->yrgb_hsd_mode);
2591                         break;
2592                 }
2593                 break;
2594         default:
2595                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2596                         __func__, win->yrgb_hor_scl_mode);
2597                 break;
2598         }                       /*win->yrgb_hor_scl_mode */
2599
2600         /*(1.2)YRGB VER SCALE FACTOR */
2601         switch (win->yrgb_ver_scl_mode) {
2602         case SCALE_NONE:
2603                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2604                 break;
2605         case SCALE_UP:
2606                 switch (win->yrgb_vsu_mode) {
2607                 case SCALE_UP_BIL:
2608                         yrgb_yscl_factor =
2609                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2610                         break;
2611                 case SCALE_UP_BIC:
2612                         if (yrgb_srcH < 3) {
2613                                 pr_err("yrgb_srcH should be");
2614                                 pr_err(" greater than 3 !!!\n");
2615                         }
2616                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2617                                                                 yrgb_dstH);
2618                         break;
2619                 default:
2620                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2621                                 __func__, win->yrgb_vsu_mode);
2622                         break;
2623                 }
2624                 break;
2625         case SCALE_DOWN:
2626                 switch (win->yrgb_vsd_mode) {
2627                 case SCALE_DOWN_BIL:
2628                         yrgb_vscalednmult =
2629                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2630                                                             yrgb_dstH);
2631                         yrgb_yscl_factor =
2632                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2633                                                            yrgb_vscalednmult);
2634                         if (yrgb_yscl_factor >= 0x2000) {
2635                                 pr_err("yrgb_yscl_factor should be ");
2636                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2637                                        yrgb_yscl_factor);
2638                         }
2639                         if (yrgb_vscalednmult == 4) {
2640                                 yrgb_vsd_bil_gt4 = 1;
2641                                 yrgb_vsd_bil_gt2 = 0;
2642                         } else if (yrgb_vscalednmult == 2) {
2643                                 yrgb_vsd_bil_gt4 = 0;
2644                                 yrgb_vsd_bil_gt2 = 1;
2645                         } else {
2646                                 yrgb_vsd_bil_gt4 = 0;
2647                                 yrgb_vsd_bil_gt2 = 0;
2648                         }
2649                         break;
2650                 case SCALE_DOWN_AVG:
2651                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2652                                                                  yrgb_dstH);
2653                         break;
2654                 default:
2655                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2656                                 __func__, win->yrgb_vsd_mode);
2657                         break;
2658                 }               /*win->yrgb_vsd_mode */
2659                 break;
2660         default:
2661                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2662                         __func__, win->yrgb_ver_scl_mode);
2663                 break;
2664         }
2665         win->scale_yrgb_x = yrgb_xscl_factor;
2666         win->scale_yrgb_y = yrgb_yscl_factor;
2667         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2668         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2669         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2670             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2671
2672         /*(2.1)CBCR HOR SCALE FACTOR */
2673         switch (win->cbr_hor_scl_mode) {
2674         case SCALE_NONE:
2675                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2676                 break;
2677         case SCALE_UP:
2678                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2679                 break;
2680         case SCALE_DOWN:
2681                 switch (win->cbr_hsd_mode) {
2682                 case SCALE_DOWN_BIL:
2683                         cbcr_xscl_factor =
2684                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2685                         break;
2686                 case SCALE_DOWN_AVG:
2687                         cbcr_xscl_factor =
2688                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2689                         break;
2690                 default:
2691                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2692                                 __func__, win->cbr_hsd_mode);
2693                         break;
2694                 }
2695                 break;
2696         default:
2697                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2698                         __func__, win->cbr_hor_scl_mode);
2699                 break;
2700         }                       /*win->cbr_hor_scl_mode */
2701
2702         /*(2.2)CBCR VER SCALE FACTOR */
2703         switch (win->cbr_ver_scl_mode) {
2704         case SCALE_NONE:
2705                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2706                 break;
2707         case SCALE_UP:
2708                 switch (win->cbr_vsu_mode) {
2709                 case SCALE_UP_BIL:
2710                         cbcr_yscl_factor =
2711                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2712                         break;
2713                 case SCALE_UP_BIC:
2714                         if (cbcr_srcH < 3) {
2715                                 pr_err("cbcr_srcH should be ");
2716                                 pr_err("greater than 3 !!!\n");
2717                         }
2718                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2719                                                                 cbcr_dstH);
2720                         break;
2721                 default:
2722                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2723                                 __func__, win->cbr_vsu_mode);
2724                         break;
2725                 }
2726                 break;
2727         case SCALE_DOWN:
2728                 switch (win->cbr_vsd_mode) {
2729                 case SCALE_DOWN_BIL:
2730                         cbcr_vscalednmult =
2731                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2732                                                             cbcr_dstH);
2733                         cbcr_yscl_factor =
2734                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2735                                                            cbcr_vscalednmult);
2736                         if (cbcr_yscl_factor >= 0x2000) {
2737                                 pr_err("cbcr_yscl_factor should be less ");
2738                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2739                                        cbcr_yscl_factor);
2740                         }
2741
2742                         if (cbcr_vscalednmult == 4) {
2743                                 cbcr_vsd_bil_gt4 = 1;
2744                                 cbcr_vsd_bil_gt2 = 0;
2745                         } else if (cbcr_vscalednmult == 2) {
2746                                 cbcr_vsd_bil_gt4 = 0;
2747                                 cbcr_vsd_bil_gt2 = 1;
2748                         } else {
2749                                 cbcr_vsd_bil_gt4 = 0;
2750                                 cbcr_vsd_bil_gt2 = 0;
2751                         }
2752                         break;
2753                 case SCALE_DOWN_AVG:
2754                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2755                                                                  cbcr_dstH);
2756                         break;
2757                 default:
2758                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2759                                 __func__, win->cbr_vsd_mode);
2760                         break;
2761                 }
2762                 break;
2763         default:
2764                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2765                         __func__, win->cbr_ver_scl_mode);
2766                 break;
2767         }
2768         win->scale_cbcr_x = cbcr_xscl_factor;
2769         win->scale_cbcr_y = cbcr_yscl_factor;
2770         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2771         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2772
2773         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2774             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2775         return 0;
2776 }
2777
2778 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2779                      struct rk_lcdc_win_area *area)
2780 {
2781         int pos;
2782
2783         if (screen->x_mirror && mirror_en)
2784                 pr_err("not support both win and global mirror\n");
2785
2786         if ((!mirror_en) && (!screen->x_mirror))
2787                 pos = area->xpos + screen->mode.left_margin +
2788                         screen->mode.hsync_len;
2789         else
2790                 pos = screen->mode.xres - area->xpos -
2791                         area->xsize + screen->mode.left_margin +
2792                         screen->mode.hsync_len;
2793
2794         return pos;
2795 }
2796
2797 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2798                      struct rk_lcdc_win_area *area)
2799 {
2800         int pos;
2801
2802         if (screen->y_mirror && mirror_en)
2803                 pr_err("not support both win and global mirror\n");
2804         if (screen->mode.vmode == FB_VMODE_NONINTERLACED) {
2805                 if ((!mirror_en) && (!screen->y_mirror))
2806                         pos = area->ypos + screen->mode.upper_margin +
2807                                 screen->mode.vsync_len;
2808                 else
2809                         pos = screen->mode.yres - area->ypos -
2810                                 area->ysize + screen->mode.upper_margin +
2811                                 screen->mode.vsync_len;
2812         } else if (screen->mode.vmode == FB_VMODE_INTERLACED) {
2813                 pos = area->ypos / 2 + screen->mode.upper_margin +
2814                         screen->mode.vsync_len;
2815                 area->ysize /= 2;
2816         }
2817
2818         return pos;
2819 }
2820
2821 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2822                            struct rk_screen *screen, struct rk_lcdc_win *win)
2823 {
2824         u32 xact, yact, xvir, yvir, xpos, ypos;
2825         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2826         char fmt[9] = "NULL";
2827
2828         xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2829         ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2830
2831         spin_lock(&lcdc_dev->reg_lock);
2832         if (likely(lcdc_dev->clk_on)) {
2833                 rk3368_lcdc_cal_scl_fac(win);   /*fac,lb,gt2,gt4 */
2834                 switch (win->area[0].format) {
2835                 case FBDC_RGB_565:
2836                         fmt_cfg = 2;
2837                         swap_rb = 0;
2838                         win->fmt_10 = 0;
2839                         win->area[0].fbdc_fmt_cfg = 0x05;
2840                         break;
2841                 case FBDC_ARGB_888:
2842                         fmt_cfg = 0;
2843                         swap_rb = 0;
2844                         win->fmt_10 = 0;
2845                         win->area[0].fbdc_fmt_cfg = 0x0c;
2846                         break;
2847                 case FBDC_ABGR_888:
2848                         fmt_cfg = 0;
2849                         swap_rb = 1;
2850                         win->fmt_10 = 0;
2851                         win->area[0].fbdc_fmt_cfg = 0x0c;
2852                         break;
2853                 case FBDC_RGBX_888:
2854                         fmt_cfg = 0;
2855                         swap_rb = 0;
2856                         win->fmt_10 = 0;
2857                         win->area[0].fbdc_fmt_cfg = 0x3a;
2858                         break;
2859                 case ARGB888:
2860                         fmt_cfg = 0;
2861                         swap_rb = 0;
2862                         win->fmt_10 = 0;
2863                         break;
2864                 case XBGR888:
2865                 case ABGR888:
2866                         fmt_cfg = 0;
2867                         swap_rb = 1;
2868                         win->fmt_10 = 0;
2869                         break;
2870                 case RGB888:
2871                         fmt_cfg = 1;
2872                         swap_rb = 0;
2873                         win->fmt_10 = 0;
2874                         break;
2875                 case RGB565:
2876                         fmt_cfg = 2;
2877                         swap_rb = 0;
2878                         win->fmt_10 = 0;
2879                         break;
2880                 case YUV422:
2881                         fmt_cfg = 5;
2882                         swap_rb = 0;
2883                         win->fmt_10 = 0;
2884                         break;
2885                 case YUV420:
2886                         fmt_cfg = 4;
2887                         swap_rb = 0;
2888                         win->fmt_10 = 0;
2889                         break;
2890                 case YUV420_NV21:
2891                         fmt_cfg = 4;
2892                         swap_rb = 0;
2893                         swap_uv = 1;
2894                         win->fmt_10 = 0;
2895                         break;
2896                 case YUV444:
2897                         fmt_cfg = 6;
2898                         swap_rb = 0;
2899                         win->fmt_10 = 0;
2900                         break;
2901                 case YUV422_A:
2902                         fmt_cfg = 5;
2903                         swap_rb = 0;
2904                         win->fmt_10 = 1;
2905                         break;
2906                 case YUV420_A:
2907                         fmt_cfg = 4;
2908                         swap_rb = 0;
2909                         win->fmt_10 = 1;
2910                         break;
2911                 case YUV444_A:
2912                         fmt_cfg = 6;
2913                         swap_rb = 0;
2914                         win->fmt_10 = 1;
2915                         break;
2916                 default:
2917                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2918                                 __func__);
2919                         break;
2920                 }
2921                 win->area[0].fmt_cfg = fmt_cfg;
2922                 win->area[0].swap_rb = swap_rb;
2923                 win->area[0].swap_uv = swap_uv;
2924                 win->area[0].dsp_stx = xpos;
2925                 win->area[0].dsp_sty = ypos;
2926                 xact = win->area[0].xact;
2927                 yact = win->area[0].yact;
2928                 xvir = win->area[0].xvir;
2929                 yvir = win->area[0].yvir;
2930         }
2931         if (win->area[0].fbdc_en)
2932                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2933         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2934         spin_unlock(&lcdc_dev->reg_lock);
2935
2936         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2937             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2938             xact, yact, win->area[0].xsize);
2939         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2940             win->area[0].ysize, xvir, yvir, xpos, ypos);
2941
2942         return 0;
2943 }
2944
2945
2946 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2947                            struct rk_screen *screen, struct rk_lcdc_win *win)
2948 {
2949         int i;
2950         u8 fmt_cfg, swap_rb;
2951         char fmt[9] = "NULL";
2952
2953         if (win->mirror_en)
2954                 pr_err("win[%d] not support y mirror\n", win->id);
2955         spin_lock(&lcdc_dev->reg_lock);
2956         if (likely(lcdc_dev->clk_on)) {
2957                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2958                 for (i = 0; i < win->area_num; i++) {
2959                         switch (win->area[i].format) {
2960                         case FBDC_RGB_565:
2961                                 fmt_cfg = 2;
2962                                 swap_rb = 0;
2963                                 win->fmt_10 = 0;
2964                                 win->area[0].fbdc_fmt_cfg = 0x05;
2965                                 break;
2966                         case FBDC_ARGB_888:
2967                                 fmt_cfg = 0;
2968                                 swap_rb = 0;
2969                                 win->fmt_10 = 0;
2970                                 win->area[0].fbdc_fmt_cfg = 0x0c;
2971                                 break;
2972                         case FBDC_RGBX_888:
2973                                 fmt_cfg = 0;
2974                                 swap_rb = 0;
2975                                 win->fmt_10 = 0;
2976                                 win->area[0].fbdc_fmt_cfg = 0x3a;
2977                                 break;
2978                         case ARGB888:
2979                                 fmt_cfg = 0;
2980                                 swap_rb = 0;
2981                                 break;
2982                         case XBGR888:
2983                         case ABGR888:
2984                                 fmt_cfg = 0;
2985                                 swap_rb = 1;
2986                                 break;
2987                         case RGB888:
2988                                 fmt_cfg = 1;
2989                                 swap_rb = 0;
2990                                 break;
2991                         case RGB565:
2992                                 fmt_cfg = 2;
2993                                 swap_rb = 0;
2994                                 break;
2995                         default:
2996                                 dev_err(lcdc_dev->driver.dev,
2997                                         "%s:un supported format!\n", __func__);
2998                                 break;
2999                         }
3000                         win->area[i].fmt_cfg = fmt_cfg;
3001                         win->area[i].swap_rb = swap_rb;
3002                         win->area[i].dsp_stx =
3003                                         dsp_x_pos(win->mirror_en, screen,
3004                                                   &win->area[i]);
3005                         win->area[i].dsp_sty =
3006                                         dsp_y_pos(win->mirror_en, screen,
3007                                                   &win->area[i]);
3008                         if ((win->area[i].xact != win->area[i].xsize) ||
3009                             (win->area[i].yact != win->area[i].ysize)) {
3010                                 pr_err("win[%d]->area[%d],not support scale\n",
3011                                         win->id, i);
3012                                 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
3013                                         win->area[i].xact,win->area[i].yact,
3014                                         win->area[i].xsize,win->area[i].ysize);
3015                                 win->area[i].xsize = win->area[i].xact;
3016                                 win->area[i].ysize = win->area[i].yact;
3017                         }
3018                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
3019                             get_format_string(win->area[i].format, fmt),
3020                             win->area[i].xsize, win->area[i].ysize,
3021                             win->area[i].xpos, win->area[i].ypos);
3022                 }
3023         }
3024         if (win->area[0].fbdc_en)
3025                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
3026         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
3027         spin_unlock(&lcdc_dev->reg_lock);
3028         return 0;
3029 }
3030
3031 static int hwc_set_par(struct lcdc_device *lcdc_dev,
3032                        struct rk_screen *screen, struct rk_lcdc_win *win)
3033 {
3034         u32 xact, yact, xvir, yvir, xpos, ypos;
3035         u8 fmt_cfg = 0, swap_rb;
3036         char fmt[9] = "NULL";
3037
3038         xpos = win->area[0].xpos + screen->mode.left_margin +
3039             screen->mode.hsync_len;
3040         ypos = win->area[0].ypos + screen->mode.upper_margin +
3041             screen->mode.vsync_len;
3042
3043         spin_lock(&lcdc_dev->reg_lock);
3044         if (likely(lcdc_dev->clk_on)) {
3045                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
3046                 switch (win->area[0].format) {
3047                 case ARGB888:
3048                         fmt_cfg = 0;
3049                         swap_rb = 0;
3050                         break;
3051                 case XBGR888:
3052                 case ABGR888:
3053                         fmt_cfg = 0;
3054                         swap_rb = 1;
3055                         break;
3056                 case RGB888:
3057                         fmt_cfg = 1;
3058                         swap_rb = 0;
3059                         break;
3060                 case RGB565:
3061                         fmt_cfg = 2;
3062                         swap_rb = 0;
3063                         break;
3064                 default:
3065                         dev_err(lcdc_dev->driver.dev,
3066                                 "%s:un supported format!\n", __func__);
3067                         break;
3068                 }
3069                 win->area[0].fmt_cfg = fmt_cfg;
3070                 win->area[0].swap_rb = swap_rb;
3071                 win->area[0].dsp_stx = xpos;
3072                 win->area[0].dsp_sty = ypos;
3073                 xact = win->area[0].xact;
3074                 yact = win->area[0].yact;
3075                 xvir = win->area[0].xvir;
3076                 yvir = win->area[0].yvir;
3077         }
3078         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
3079         spin_unlock(&lcdc_dev->reg_lock);
3080
3081         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
3082             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
3083             xact, yact, win->area[0].xsize);
3084         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
3085             win->area[0].ysize, xvir, yvir, xpos, ypos);
3086         return 0;
3087 }
3088
3089 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
3090 {
3091         struct lcdc_device *lcdc_dev =
3092             container_of(dev_drv, struct lcdc_device, driver);
3093         struct rk_lcdc_win *win = NULL;
3094         struct rk_screen *screen = dev_drv->cur_screen;
3095
3096         win = dev_drv->win[win_id];
3097         switch (win_id) {
3098         case 0:
3099                 win_0_1_set_par(lcdc_dev, screen, win);
3100                 break;
3101         case 1:
3102                 win_0_1_set_par(lcdc_dev, screen, win);
3103                 break;
3104         case 2:
3105                 win_2_3_set_par(lcdc_dev, screen, win);
3106                 break;
3107         case 3:
3108                 win_2_3_set_par(lcdc_dev, screen, win);
3109                 break;
3110         case 4:
3111                 hwc_set_par(lcdc_dev, screen, win);
3112                 break;
3113         default:
3114                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
3115                 break;
3116         }
3117         return 0;
3118 }
3119
3120 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
3121                              unsigned long arg, int win_id)
3122 {
3123         struct lcdc_device *lcdc_dev =
3124             container_of(dev_drv, struct lcdc_device, driver);
3125         u32 panel_size[2];
3126         void __user *argp = (void __user *)arg;
3127         struct color_key_cfg clr_key_cfg;
3128
3129         switch (cmd) {
3130         case RK_FBIOGET_PANEL_SIZE:
3131                 panel_size[0] = lcdc_dev->screen->mode.xres;
3132                 panel_size[1] = lcdc_dev->screen->mode.yres;
3133                 if (copy_to_user(argp, panel_size, 8))
3134                         return -EFAULT;
3135                 break;
3136         case RK_FBIOPUT_COLOR_KEY_CFG:
3137                 if (copy_from_user(&clr_key_cfg, argp,
3138                                    sizeof(struct color_key_cfg)))
3139                         return -EFAULT;
3140                 rk3368_lcdc_clr_key_cfg(dev_drv);
3141                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
3142                             clr_key_cfg.win0_color_key_cfg);
3143                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
3144                             clr_key_cfg.win1_color_key_cfg);
3145                 break;
3146
3147         default:
3148                 break;
3149         }
3150         return 0;
3151 }
3152
3153 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
3154 {
3155         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3156                                                     struct lcdc_device, driver);
3157         struct device_node *backlight;
3158         struct property *prop;
3159         u32 brightness_levels[256];
3160         u32 length, max, last;
3161
3162         if (lcdc_dev->backlight)
3163                 return 0;
3164         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
3165         if (backlight) {
3166                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
3167                 if (!lcdc_dev->backlight)
3168                         dev_info(lcdc_dev->dev, "No find backlight device\n");
3169         } else {
3170                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
3171         }
3172         prop = of_find_property(backlight, "brightness-levels", &length);
3173         if (!prop)
3174                 return -EINVAL;
3175         max = length / sizeof(u32);
3176         last = max - 1;
3177         if (!of_property_read_u32_array(backlight, "brightness-levels", brightness_levels, max)) {
3178                 if (brightness_levels[0] > brightness_levels[last])
3179                         dev_drv->cabc_pwm_pol = 1;/*negative*/
3180                 else
3181                         dev_drv->cabc_pwm_pol = 0;/*positive*/
3182         } else {
3183                 dev_info(lcdc_dev->dev, "Can not read brightness-levels value\n");
3184         }
3185         return 0;
3186 }
3187
3188 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
3189 {
3190         struct lcdc_device *lcdc_dev =
3191             container_of(dev_drv, struct lcdc_device, driver);
3192         if (dev_drv->suspend_flag)
3193                 return 0;
3194         /* close the backlight */
3195         /*rk3368_lcdc_get_backlight_device(dev_drv);
3196         if (lcdc_dev->backlight) {
3197                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
3198                 backlight_update_status(lcdc_dev->backlight);
3199         }*/
3200
3201         dev_drv->suspend_flag = 1;
3202         flush_kthread_worker(&dev_drv->update_regs_worker);
3203
3204         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3205                 dev_drv->trsm_ops->disable();
3206
3207         spin_lock(&lcdc_dev->reg_lock);
3208         if (likely(lcdc_dev->clk_on)) {
3209                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3210                              v_DSP_BLANK_EN(1));
3211                 lcdc_msk_reg(lcdc_dev,
3212                              INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
3213                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
3214                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3215                              v_DSP_OUT_ZERO(1));
3216                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
3217                 lcdc_cfg_done(lcdc_dev);
3218
3219                 if (dev_drv->iommu_enabled) {
3220                         if (dev_drv->mmu_dev)
3221                                 rockchip_iovmm_deactivate(dev_drv->dev);
3222                 }
3223
3224                 spin_unlock(&lcdc_dev->reg_lock);
3225         } else {
3226                 spin_unlock(&lcdc_dev->reg_lock);
3227                 return 0;
3228         }
3229         rk3368_lcdc_clk_disable(lcdc_dev);
3230         rk_disp_pwr_disable(dev_drv);
3231         return 0;
3232 }
3233
3234 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
3235 {
3236         struct lcdc_device *lcdc_dev =
3237             container_of(dev_drv, struct lcdc_device, driver);
3238
3239         if (!dev_drv->suspend_flag)
3240                 return 0;
3241         rk_disp_pwr_enable(dev_drv);
3242
3243         if (1/*lcdc_dev->atv_layer_cnt*/) {
3244                 rk3368_lcdc_clk_enable(lcdc_dev);
3245                 rk3368_lcdc_reg_restore(lcdc_dev);
3246
3247                 spin_lock(&lcdc_dev->reg_lock);
3248                 if (dev_drv->cur_screen->dsp_lut)
3249                         rk3368_lcdc_set_lut(dev_drv,
3250                                             dev_drv->cur_screen->dsp_lut);
3251                 if (dev_drv->cur_screen->cabc_lut)
3252                         rk3368_set_cabc_lut(dev_drv,
3253                                             dev_drv->cur_screen->cabc_lut);
3254
3255                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3256                              v_DSP_OUT_ZERO(0));
3257                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
3258                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3259                              v_DSP_BLANK_EN(0));
3260                 lcdc_cfg_done(lcdc_dev);
3261
3262                 if (dev_drv->iommu_enabled) {
3263                         if (dev_drv->mmu_dev)
3264                                 rockchip_iovmm_activate(dev_drv->dev);
3265                 }
3266
3267                 spin_unlock(&lcdc_dev->reg_lock);
3268         }
3269         dev_drv->suspend_flag = 0;
3270
3271         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3272                 dev_drv->trsm_ops->enable();
3273         mdelay(100);
3274         return 0;
3275 }
3276
3277 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
3278                              int win_id, int blank_mode)
3279 {
3280         switch (blank_mode) {
3281         case FB_BLANK_UNBLANK:
3282                 rk3368_lcdc_early_resume(dev_drv);
3283                 break;
3284         case FB_BLANK_NORMAL:
3285                 rk3368_lcdc_early_suspend(dev_drv);
3286                 break;
3287         default:
3288                 rk3368_lcdc_early_suspend(dev_drv);
3289                 break;
3290         }
3291
3292         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3293
3294         return 0;
3295 }
3296
3297 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
3298                                            int win_id, int area_id)
3299 {
3300         struct lcdc_device *lcdc_dev =
3301             container_of(dev_drv, struct lcdc_device, driver);
3302         u32 win_ctrl = 0;
3303         u32 area_status = 0;
3304
3305         switch (win_id) {
3306         case 0:
3307                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3308                 area_status = win_ctrl & m_WIN0_EN;
3309                 break;
3310         case 1:
3311                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3312                 area_status = win_ctrl & m_WIN1_EN;
3313                 break;
3314         case 2:
3315                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3316                 if (area_id == 0)
3317                         area_status = win_ctrl & m_WIN2_MST0_EN;
3318                 if (area_id == 1)
3319                         area_status = win_ctrl & m_WIN2_MST1_EN;
3320                 if (area_id == 2)
3321                         area_status = win_ctrl & m_WIN2_MST2_EN;
3322                 if (area_id == 3)
3323                         area_status = win_ctrl & m_WIN2_MST3_EN;
3324                 break;
3325         case 3:
3326                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3327                 if (area_id == 0)
3328                         area_status = win_ctrl & m_WIN3_MST0_EN;
3329                 if (area_id == 1)
3330                         area_status = win_ctrl & m_WIN3_MST1_EN;
3331                 if (area_id == 2)
3332                         area_status = win_ctrl & m_WIN3_MST2_EN;
3333                 if (area_id == 3)
3334                         area_status = win_ctrl & m_WIN3_MST3_EN;
3335                 break;
3336         case 4:
3337                 win_ctrl = lcdc_readl(lcdc_dev, HWC_CTRL0);
3338                 area_status = win_ctrl & m_HWC_EN;
3339                 break;
3340         default:
3341                 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",__func__,win_id,area_id);
3342                 break;
3343         }
3344         return area_status;
3345 }
3346
3347 static int rk3368_lcdc_get_area_num(struct rk_lcdc_driver *dev_drv,
3348                                            unsigned int *area_support)
3349 {
3350         area_support[0] = 1;
3351         area_support[1] = 1;
3352         area_support[2] = 4;
3353         area_support[3] = 4;
3354
3355         return 0;
3356 }
3357
3358 /*overlay will be do at regupdate*/
3359 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
3360                                bool set)
3361 {
3362         struct lcdc_device *lcdc_dev =
3363             container_of(dev_drv, struct lcdc_device, driver);
3364         struct rk_lcdc_win *win = NULL;
3365         int i, ovl;
3366         unsigned int mask, val;
3367         int z_order_num = 0;
3368         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3369
3370         if (swap == 0) {
3371                 for (i = 0; i < 4; i++) {
3372                         win = dev_drv->win[i];
3373                         if (win->state == 1)
3374                                 z_order_num++;
3375                 }
3376                 for (i = 0; i < 4; i++) {
3377                         win = dev_drv->win[i];
3378                         if (win->state == 0)
3379                                 win->z_order = z_order_num++;
3380                         switch (win->z_order) {
3381                         case 0:
3382                                 layer0_sel = win->id;
3383                                 break;
3384                         case 1:
3385                                 layer1_sel = win->id;
3386                                 break;
3387                         case 2:
3388                                 layer2_sel = win->id;
3389                                 break;
3390                         case 3:
3391                                 layer3_sel = win->id;
3392                                 break;
3393                         default:
3394                                 break;
3395                         }
3396                 }
3397         } else {
3398                 layer0_sel = swap % 10;
3399                 layer1_sel = swap / 10 % 10;
3400                 layer2_sel = swap / 100 % 10;
3401                 layer3_sel = swap / 1000;
3402         }
3403
3404         spin_lock(&lcdc_dev->reg_lock);
3405         if (lcdc_dev->clk_on) {
3406                 if (set) {
3407                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3408                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3409                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3410                             v_DSP_LAYER1_SEL(layer1_sel) |
3411                             v_DSP_LAYER2_SEL(layer2_sel) |
3412                             v_DSP_LAYER3_SEL(layer3_sel);
3413                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3414                 } else {
3415                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3416                                                    m_DSP_LAYER0_SEL);
3417                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3418                                                    m_DSP_LAYER1_SEL);
3419                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3420                                                    m_DSP_LAYER2_SEL);
3421                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3422                                                    m_DSP_LAYER3_SEL);
3423                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3424                             layer1_sel * 10 + layer0_sel;
3425                 }
3426         } else {
3427                 ovl = -EPERM;
3428         }
3429         spin_unlock(&lcdc_dev->reg_lock);
3430
3431         return ovl;
3432 }
3433
3434 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3435 {
3436         if (!fmt)
3437                 return NULL;
3438
3439         switch (format) {
3440         case 0:
3441                 strcpy(fmt, "ARGB888");
3442                 break;
3443         case 1:
3444                 strcpy(fmt, "RGB888");
3445                 break;
3446         case 2:
3447                 strcpy(fmt, "RGB565");
3448                 break;
3449         case 4:
3450                 strcpy(fmt, "YCbCr420");
3451                 break;
3452         case 5:
3453                 strcpy(fmt, "YCbCr422");
3454                 break;
3455         case 6:
3456                 strcpy(fmt, "YCbCr444");
3457                 break;
3458         default:
3459                 strcpy(fmt, "invalid\n");
3460                 break;
3461         }
3462         return fmt;
3463 }
3464 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3465                                          char *buf, int win_id)
3466 {
3467         struct lcdc_device *lcdc_dev =
3468             container_of(dev_drv, struct lcdc_device, driver);
3469         struct rk_screen *screen = dev_drv->cur_screen;
3470         u16 hsync_len = screen->mode.hsync_len;
3471         u16 left_margin = screen->mode.left_margin;
3472         u16 vsync_len = screen->mode.vsync_len;
3473         u16 upper_margin = screen->mode.upper_margin;
3474         u32 h_pw_bp = hsync_len + left_margin;
3475         u32 v_pw_bp = vsync_len + upper_margin;
3476         u32 fmt_id;
3477         char format_w0[9] = "NULL";
3478         char format_w1[9] = "NULL";
3479         char format_w2_0[9] = "NULL";
3480         char format_w2_1[9] = "NULL";
3481         char format_w2_2[9] = "NULL";
3482         char format_w2_3[9] = "NULL";
3483         char format_w3_0[9] = "NULL";
3484         char format_w3_1[9] = "NULL";
3485         char format_w3_2[9] = "NULL";
3486         char format_w3_3[9] = "NULL";
3487         char dsp_buf[100];
3488         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3489         u32 y_factor, uv_factor;
3490         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3491         u8 w0_state, w1_state, w2_state, w3_state;
3492         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3493         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3494
3495         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3496         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3497         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3498         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3499         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3500         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3501
3502         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3503         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3504         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3505         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3506         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3507         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3508         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3509
3510         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3511         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3512         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3513         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3514         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3515         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3516         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3517         u32 dclk_freq;
3518         int size = 0;
3519
3520         dclk_freq = screen->mode.pixclock;
3521         /*rk3368_lcdc_reg_dump(dev_drv); */
3522
3523         spin_lock(&lcdc_dev->reg_lock);
3524         if (lcdc_dev->clk_on) {
3525                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3526                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3527                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3528                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3529                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3530                 /*WIN0 */
3531                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3532                 w0_state = win_ctrl & m_WIN0_EN;
3533                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3534                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3535                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3536                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3537                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3538                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3539                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3540                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3541                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3542                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3543                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3544                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3545                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3546                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3547                 if (w0_state) {
3548                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3549                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3550                 }
3551                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3552                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3553                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3554                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3555
3556                 /*WIN1 */
3557                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3558                 w1_state = win_ctrl & m_WIN1_EN;
3559                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3560                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3561                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3562                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3563                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3564                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3565                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3566                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3567                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3568                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3569                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3570                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3571                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3572                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3573                 if (w1_state) {
3574                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3575                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3576                 }
3577                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3578                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3579                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3580                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3581                 /*WIN2 */
3582                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3583                 w2_state = win_ctrl & m_WIN2_EN;
3584                 w2_0_state = (win_ctrl & 0x10) >> 4;
3585                 w2_1_state = (win_ctrl & 0x100) >> 8;
3586                 w2_2_state = (win_ctrl & 0x1000) >> 12;
3587                 w2_3_state = (win_ctrl & 0x10000) >> 16;
3588                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3589                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3590                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3591                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3592                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3593                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3594
3595                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3596                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3597                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3598                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3599                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3600                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3601                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3602                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3603
3604                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3605                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3606                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3607                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3608                 if (w2_0_state) {
3609                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3610                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3611                 }
3612                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3613                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3614                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3615                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3616                 if (w2_1_state) {
3617                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3618                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3619                 }
3620                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3621                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3622                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3623                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3624                 if (w2_2_state) {
3625                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3626                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3627                 }
3628                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3629                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3630                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3631                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3632                 if (w2_3_state) {
3633                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3634                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3635                 }
3636
3637                 /*WIN3 */
3638                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3639                 w3_state = win_ctrl & m_WIN3_EN;
3640                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3641                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 8;
3642                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 12;
3643                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 16;
3644                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3645                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3646                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3647                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3648                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3649                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3650                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3651                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3652                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3653                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3654                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3655                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3656                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3657                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3658                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3659                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3660                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3661                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3662                 if (w3_0_state) {
3663                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3664                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3665                 }
3666
3667                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3668                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3669                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3670                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3671                 if (w3_1_state) {
3672                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3673                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3674                 }
3675
3676                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3677                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3678                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3679                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3680                 if (w3_2_state) {
3681                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3682                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3683                 }
3684
3685                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3686                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3687                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3688                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3689                 if (w3_3_state) {
3690                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3691                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3692                 }
3693
3694         } else {
3695                 spin_unlock(&lcdc_dev->reg_lock);
3696                 return -EPERM;
3697         }
3698         spin_unlock(&lcdc_dev->reg_lock);
3699         size += snprintf(dsp_buf, 80,
3700                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3701                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3702         strcat(buf, dsp_buf);
3703         memset(dsp_buf, 0, sizeof(dsp_buf));
3704         /*win0*/
3705         size += snprintf(dsp_buf, 80,
3706                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3707                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3708         strcat(buf, dsp_buf);
3709         memset(dsp_buf, 0, sizeof(dsp_buf));
3710
3711         size += snprintf(dsp_buf, 80,
3712                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3713                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3714         strcat(buf, dsp_buf);
3715         memset(dsp_buf, 0, sizeof(dsp_buf));
3716
3717         size += snprintf(dsp_buf, 80,
3718                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3719                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3720         strcat(buf, dsp_buf);
3721         memset(dsp_buf, 0, sizeof(dsp_buf));
3722
3723         size += snprintf(dsp_buf, 80,
3724                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3725                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3726                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3727         strcat(buf, dsp_buf);
3728         memset(dsp_buf, 0, sizeof(dsp_buf));
3729
3730         /*win1*/
3731         size += snprintf(dsp_buf, 80,
3732                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3733                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3734         strcat(buf, dsp_buf);
3735         memset(dsp_buf, 0, sizeof(dsp_buf));
3736
3737         size += snprintf(dsp_buf, 80,
3738                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3739                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3740         strcat(buf, dsp_buf);
3741         memset(dsp_buf, 0, sizeof(dsp_buf));
3742
3743         size += snprintf(dsp_buf, 80,
3744                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3745                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3746         strcat(buf, dsp_buf);
3747         memset(dsp_buf, 0, sizeof(dsp_buf));
3748
3749         size += snprintf(dsp_buf, 80,
3750                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3751                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3752                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3753         strcat(buf, dsp_buf);
3754         memset(dsp_buf, 0, sizeof(dsp_buf));
3755
3756         /*win2*/
3757         size += snprintf(dsp_buf, 80,
3758                  "win2:\n  state:%d\n",
3759                  w2_state);
3760         strcat(buf, dsp_buf);
3761         memset(dsp_buf, 0, sizeof(dsp_buf));
3762         /*area 0*/
3763         size += snprintf(dsp_buf, 80,
3764                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3765                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3766         strcat(buf, dsp_buf);
3767         memset(dsp_buf, 0, sizeof(dsp_buf));
3768         size += snprintf(dsp_buf, 80,
3769                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3770                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3771                  lcdc_readl(lcdc_dev, WIN2_MST0));
3772         strcat(buf, dsp_buf);
3773         memset(dsp_buf, 0, sizeof(dsp_buf));
3774
3775         /*area 1*/
3776         size += snprintf(dsp_buf, 80,
3777                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3778                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3779         strcat(buf, dsp_buf);
3780         memset(dsp_buf, 0, sizeof(dsp_buf));
3781         size += snprintf(dsp_buf, 80,
3782                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3783                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3784                  lcdc_readl(lcdc_dev, WIN2_MST1));
3785         strcat(buf, dsp_buf);
3786         memset(dsp_buf, 0, sizeof(dsp_buf));
3787
3788         /*area 2*/
3789         size += snprintf(dsp_buf, 80,
3790                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3791                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3792         strcat(buf, dsp_buf);
3793         memset(dsp_buf, 0, sizeof(dsp_buf));
3794         size += snprintf(dsp_buf, 80,
3795                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3796                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3797                  lcdc_readl(lcdc_dev, WIN2_MST2));
3798         strcat(buf, dsp_buf);
3799         memset(dsp_buf, 0, sizeof(dsp_buf));
3800
3801         /*area 3*/
3802         size += snprintf(dsp_buf, 80,
3803                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3804                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3805         strcat(buf, dsp_buf);
3806         memset(dsp_buf, 0, sizeof(dsp_buf));
3807         size += snprintf(dsp_buf, 80,
3808                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3809                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3810                  lcdc_readl(lcdc_dev, WIN2_MST3));
3811         strcat(buf, dsp_buf);
3812         memset(dsp_buf, 0, sizeof(dsp_buf));
3813
3814         /*win3*/
3815         size += snprintf(dsp_buf, 80,
3816                  "win3:\n  state:%d\n",
3817                  w3_state);
3818         strcat(buf, dsp_buf);
3819         memset(dsp_buf, 0, sizeof(dsp_buf));
3820         /*area 0*/
3821         size += snprintf(dsp_buf, 80,
3822                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3823                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3824         strcat(buf, dsp_buf);
3825         memset(dsp_buf, 0, sizeof(dsp_buf));
3826         size += snprintf(dsp_buf, 80,
3827                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3828                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3829                  lcdc_readl(lcdc_dev, WIN3_MST0));
3830         strcat(buf, dsp_buf);
3831         memset(dsp_buf, 0, sizeof(dsp_buf));
3832
3833         /*area 1*/
3834         size += snprintf(dsp_buf, 80,
3835                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3836                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3837         strcat(buf, dsp_buf);
3838         memset(dsp_buf, 0, sizeof(dsp_buf));
3839         size += snprintf(dsp_buf, 80,
3840                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3841                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3842                  lcdc_readl(lcdc_dev, WIN3_MST1));
3843         strcat(buf, dsp_buf);
3844         memset(dsp_buf, 0, sizeof(dsp_buf));
3845
3846         /*area 2*/
3847         size += snprintf(dsp_buf, 80,
3848                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3849                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3850         strcat(buf, dsp_buf);
3851         memset(dsp_buf, 0, sizeof(dsp_buf));
3852         size += snprintf(dsp_buf, 80,
3853                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3854                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3855                  lcdc_readl(lcdc_dev, WIN3_MST2));
3856         strcat(buf, dsp_buf);
3857         memset(dsp_buf, 0, sizeof(dsp_buf));
3858
3859         /*area 3*/
3860         size += snprintf(dsp_buf, 80,
3861                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3862                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3863         strcat(buf, dsp_buf);
3864         memset(dsp_buf, 0, sizeof(dsp_buf));
3865         size += snprintf(dsp_buf, 80,
3866                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3867                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3868                  lcdc_readl(lcdc_dev, WIN3_MST3));
3869         strcat(buf, dsp_buf);
3870         memset(dsp_buf, 0, sizeof(dsp_buf));
3871
3872         return size;
3873 }
3874
3875 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3876                                bool set)
3877 {
3878         struct lcdc_device *lcdc_dev =
3879             container_of(dev_drv, struct lcdc_device, driver);
3880         struct rk_screen *screen = dev_drv->cur_screen;
3881         u64 ft = 0;
3882         u32 dotclk;
3883         int ret;
3884         u32 pixclock;
3885         u32 x_total, y_total;
3886
3887         if (set) {
3888                 if (fps == 0) {
3889                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3890                         return 0;
3891                 }
3892                 ft = div_u64(1000000000000llu, fps);
3893                 x_total =
3894                     screen->mode.upper_margin + screen->mode.lower_margin +
3895                     screen->mode.yres + screen->mode.vsync_len;
3896                 y_total =
3897                     screen->mode.left_margin + screen->mode.right_margin +
3898                     screen->mode.xres + screen->mode.hsync_len;
3899                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3900                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3901                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3902         }
3903
3904         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3905         lcdc_dev->pixclock = pixclock;
3906         dev_drv->pixclock = lcdc_dev->pixclock;
3907         fps = rk_fb_calc_fps(screen, pixclock);
3908         screen->ft = 1000 / fps;        /*one frame time in ms */
3909
3910         if (set)
3911                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3912                          clk_get_rate(lcdc_dev->dclk), fps);
3913
3914         return fps;
3915 }
3916
3917 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3918 {
3919         mutex_lock(&dev_drv->fb_win_id_mutex);
3920         if (order == FB_DEFAULT_ORDER)
3921                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3922         dev_drv->fb4_win_id = order / 10000;
3923         dev_drv->fb3_win_id = (order / 1000) % 10;
3924         dev_drv->fb2_win_id = (order / 100) % 10;
3925         dev_drv->fb1_win_id = (order / 10) % 10;
3926         dev_drv->fb0_win_id = order % 10;
3927         mutex_unlock(&dev_drv->fb_win_id_mutex);
3928
3929         return 0;
3930 }
3931
3932 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3933                                   const char *id)
3934 {
3935         int win_id = 0;
3936
3937         mutex_lock(&dev_drv->fb_win_id_mutex);
3938         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3939                 win_id = dev_drv->fb0_win_id;
3940         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3941                 win_id = dev_drv->fb1_win_id;
3942         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3943                 win_id = dev_drv->fb2_win_id;
3944         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3945                 win_id = dev_drv->fb3_win_id;
3946         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3947                 win_id = dev_drv->fb4_win_id;
3948         mutex_unlock(&dev_drv->fb_win_id_mutex);
3949
3950         return win_id;
3951 }
3952
3953 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3954 {
3955         struct lcdc_device *lcdc_dev =
3956             container_of(dev_drv, struct lcdc_device, driver);
3957         int i;
3958         unsigned int mask, val;
3959         struct rk_lcdc_win *win = NULL;
3960
3961         spin_lock(&lcdc_dev->reg_lock);
3962         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3963                      v_STANDBY_EN(lcdc_dev->standby));
3964         for (i = 0; i < 4; i++) {
3965                 win = dev_drv->win[i];
3966                 if ((win->state == 0) && (win->last_state == 1)) {
3967                         switch (win->id) {
3968                         case 0:
3969                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3970                                    for rk3288 to fix hw bug? */
3971                                 mask = m_WIN0_EN;
3972                                 val = v_WIN0_EN(0);
3973                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3974                                 break;
3975                         case 1:
3976                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3977                                    for rk3288 to fix hw bug? */
3978                                 mask = m_WIN1_EN;
3979                                 val = v_WIN1_EN(0);
3980                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3981                                 break;
3982                         case 2:
3983                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3984                                     m_WIN2_MST1_EN |
3985                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3986                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3987                                     v_WIN2_MST1_EN(0) |
3988                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3989                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3990                                 break;
3991                         case 3:
3992                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3993                                     m_WIN3_MST1_EN |
3994                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3995                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3996                                     v_WIN3_MST1_EN(0) |
3997                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3998                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3999                                 break;
4000                         case 4:
4001                                 mask = m_HWC_EN;
4002                                 val = v_HWC_EN(0);
4003                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
4004                                 break;
4005                         default:
4006                                 break;
4007                         }
4008                 }
4009                 win->last_state = win->state;
4010         }
4011         lcdc_cfg_done(lcdc_dev);
4012         spin_unlock(&lcdc_dev->reg_lock);
4013         return 0;
4014 }
4015
4016 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
4017 {
4018         struct lcdc_device *lcdc_dev =
4019             container_of(dev_drv, struct lcdc_device, driver);
4020         spin_lock(&lcdc_dev->reg_lock);
4021         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
4022                      v_DIRECT_PATH_EN(open));
4023         lcdc_cfg_done(lcdc_dev);
4024         spin_unlock(&lcdc_dev->reg_lock);
4025         return 0;
4026 }
4027
4028 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
4029 {
4030         struct lcdc_device *lcdc_dev = container_of(dev_drv,
4031                                                     struct lcdc_device, driver);
4032         spin_lock(&lcdc_dev->reg_lock);
4033         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
4034                      v_DIRECT_PATCH_SEL(win_id));
4035         lcdc_cfg_done(lcdc_dev);
4036         spin_unlock(&lcdc_dev->reg_lock);
4037         return 0;
4038 }
4039
4040 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
4041 {
4042         struct lcdc_device *lcdc_dev =
4043             container_of(dev_drv, struct lcdc_device, driver);
4044         int ovl;
4045
4046         spin_lock(&lcdc_dev->reg_lock);
4047         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
4048         spin_unlock(&lcdc_dev->reg_lock);
4049         return ovl;
4050 }
4051
4052 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
4053                                       int enable)
4054 {
4055         struct lcdc_device *lcdc_dev =
4056             container_of(dev_drv, struct lcdc_device, driver);
4057         if (enable)
4058                 enable_irq(lcdc_dev->irq);
4059         else
4060                 disable_irq(lcdc_dev->irq);
4061         return 0;
4062 }
4063
4064 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
4065 {
4066         struct lcdc_device *lcdc_dev =
4067             container_of(dev_drv, struct lcdc_device, driver);
4068         u32 int_reg;
4069         int ret;
4070
4071         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
4072                 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
4073                 if (int_reg & m_LINE_FLAG0_INTR_STS) {
4074                         lcdc_dev->driver.frame_time.last_framedone_t =
4075                             lcdc_dev->driver.frame_time.framedone_t;
4076                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4077                         lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
4078                                      m_LINE_FLAG0_INTR_CLR,
4079                                      v_LINE_FLAG0_INTR_CLR(1));
4080                         ret = RK_LF_STATUS_FC;
4081                 } else {
4082                         ret = RK_LF_STATUS_FR;
4083                 }
4084         } else {
4085                 ret = RK_LF_STATUS_NC;
4086         }
4087
4088         return ret;
4089 }
4090
4091 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
4092                                     unsigned int dsp_addr[][4])
4093 {
4094         struct lcdc_device *lcdc_dev =
4095             container_of(dev_drv, struct lcdc_device, driver);
4096         spin_lock(&lcdc_dev->reg_lock);
4097         if (lcdc_dev->clk_on) {
4098                 dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
4099                 dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
4100                 dsp_addr[2][0] = lcdc_readl(lcdc_dev, WIN2_MST0);
4101                 dsp_addr[2][1] = lcdc_readl(lcdc_dev, WIN2_MST1);
4102                 dsp_addr[2][2] = lcdc_readl(lcdc_dev, WIN2_MST2);
4103                 dsp_addr[2][3] = lcdc_readl(lcdc_dev, WIN2_MST3);
4104                 dsp_addr[3][0] = lcdc_readl(lcdc_dev, WIN3_MST0);
4105                 dsp_addr[3][1] = lcdc_readl(lcdc_dev, WIN3_MST1);
4106                 dsp_addr[3][2] = lcdc_readl(lcdc_dev, WIN3_MST2);
4107                 dsp_addr[3][3] = lcdc_readl(lcdc_dev, WIN3_MST3);
4108         }
4109         spin_unlock(&lcdc_dev->reg_lock);
4110         return 0;
4111 }
4112 static u32 pwm_period_hpr, pwm_duty_lpr;
4113 static u32 cabc_status = 0;
4114
4115 int rk3368_lcdc_update_pwm(int bl_pwm_period, int bl_pwm_duty)
4116 {
4117         pwm_period_hpr = bl_pwm_period;
4118         pwm_duty_lpr = bl_pwm_duty;
4119         /*pr_info("bl_pwm_period_hpr = 0x%x, bl_pwm_duty_lpr = 0x%x\n",
4120         bl_pwm_period, bl_pwm_duty);*/
4121         return 0;
4122 }
4123
4124 int rk3368_lcdc_cabc_status(void)
4125 {
4126         return cabc_status;
4127 }
4128
4129 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv,
4130                                     int mode, int calc, int up,
4131                                     int down, int global)
4132 {
4133         struct lcdc_device *lcdc_dev =
4134             container_of(dev_drv, struct lcdc_device, driver);
4135         struct rk_screen *screen = dev_drv->cur_screen;
4136         u32 total_pixel, calc_pixel, stage_up, stage_down;
4137         u32 pixel_num, global_su;
4138         u32 stage_up_rec, stage_down_rec, global_su_rec, gamma_global_su_rec;
4139         u32 mask = 0, val = 0, cabc_en = 0;
4140         int *cabc_lut = NULL;
4141
4142         if (!screen->cabc_lut) {
4143                 pr_err("screen cabc lut not config, so not open cabc\n");
4144                 return 0;
4145         } else {
4146                 cabc_lut = screen->cabc_lut;
4147         }
4148
4149         if (!screen->cabc_gamma_base) {
4150                 pr_err("screen cabc_gamma_base no config, so not open cabc\n");
4151                 return 0;
4152         }
4153         dev_drv->cabc_mode = mode;
4154         cabc_en = (mode > 0) ? 1 : 0;
4155         rk3368_lcdc_get_backlight_device(dev_drv);
4156         if (cabc_en == 0) {
4157                 spin_lock(&lcdc_dev->reg_lock);
4158                 if (lcdc_dev->clk_on) {
4159                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
4160                                      m_CABC_EN, v_CABC_EN(0));
4161                         lcdc_cfg_done(lcdc_dev);
4162                 }
4163                 pr_info("mode = 0, close cabc\n");
4164                 rk_pwm_set(pwm_period_hpr, pwm_duty_lpr);
4165                 cabc_status = 0;
4166                 spin_unlock(&lcdc_dev->reg_lock);
4167                 return 0;
4168         }
4169         if (cabc_status == 0) { /*get from pwm*/
4170                 rk_pwm_get(&pwm_period_hpr, &pwm_duty_lpr);
4171                 pr_info("pwm_period_hpr=0x%x, pwm_duty_lpr=0x%x\n",
4172                         pwm_period_hpr, pwm_duty_lpr);
4173         }
4174
4175         total_pixel = screen->mode.xres * screen->mode.yres;
4176         pixel_num = 1000 - calc;
4177         calc_pixel = (total_pixel * pixel_num) / 1000;
4178         stage_up = up;
4179         stage_down = down;
4180         global_su = global;
4181         pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n",
4182                 mode, calc, stage_up, stage_down, global_su);
4183
4184         stage_up_rec = 256 * 256 / stage_up;
4185         stage_down_rec = 256 * 256 / stage_down;
4186         global_su_rec = (256 * 256 / global_su);
4187         gamma_global_su_rec = cabc_lut[global_su_rec];
4188
4189         spin_lock(&lcdc_dev->reg_lock);
4190         if (lcdc_dev->clk_on) {
4191                 mask = m_CABC_CALC_PIXEL_NUM | m_CABC_EN;
4192                 val = v_CABC_CALC_PIXEL_NUM(calc_pixel) |
4193                         v_CABC_EN(cabc_en);
4194                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
4195
4196                 mask = m_CABC_TOTAL_PIXEL_NUM | m_CABC_LUT_EN;
4197                 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel) | v_CABC_LUT_EN(1);
4198                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
4199
4200                 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
4201                     m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
4202                 val = v_CABC_STAGE_UP(stage_up) |
4203                     v_CABC_STAGE_UP_REC(stage_up_rec) |
4204                     v_CABC_GLOBAL_SU_LIMIT_EN(1) |
4205                     v_CABC_GLOBAL_SU_REC(gamma_global_su_rec);
4206                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
4207
4208                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
4209                     m_CABC_GLOBAL_SU;
4210                 val = v_CABC_STAGE_DOWN(stage_down) |
4211                     v_CABC_STAGE_DOWN_REC(stage_down_rec) |
4212                     v_CABC_GLOBAL_SU(global_su);
4213                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
4214                 lcdc_cfg_done(lcdc_dev);
4215         }
4216         cabc_status = 1;
4217         spin_unlock(&lcdc_dev->reg_lock);
4218
4219         return 0;
4220 }
4221
4222 /*
4223         a:[-30~0]:
4224             sin_hue = sin(a)*256 +0x100;
4225             cos_hue = cos(a)*256;
4226         a:[0~30]
4227             sin_hue = sin(a)*256;
4228             cos_hue = cos(a)*256;
4229 */
4230 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4231                                     bcsh_hue_mode mode)
4232 {
4233         struct lcdc_device *lcdc_dev =
4234             container_of(dev_drv, struct lcdc_device, driver);
4235         u32 val;
4236
4237         spin_lock(&lcdc_dev->reg_lock);
4238         if (lcdc_dev->clk_on) {
4239                 val = lcdc_readl(lcdc_dev, BCSH_H);
4240                 switch (mode) {
4241                 case H_SIN:
4242                         val &= m_BCSH_SIN_HUE;
4243                         break;
4244                 case H_COS:
4245                         val &= m_BCSH_COS_HUE;
4246                         val >>= 16;
4247                         break;
4248                 default:
4249                         break;
4250                 }
4251         }
4252         spin_unlock(&lcdc_dev->reg_lock);
4253
4254         return val;
4255 }
4256
4257 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4258                                     int sin_hue, int cos_hue)
4259 {
4260         struct lcdc_device *lcdc_dev =
4261             container_of(dev_drv, struct lcdc_device, driver);
4262         u32 mask, val;
4263
4264         spin_lock(&lcdc_dev->reg_lock);
4265         if (lcdc_dev->clk_on) {
4266                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
4267                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
4268                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
4269                 lcdc_cfg_done(lcdc_dev);
4270         }
4271         spin_unlock(&lcdc_dev->reg_lock);
4272
4273         return 0;
4274 }
4275
4276 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4277                                     bcsh_bcs_mode mode, int value)
4278 {
4279         struct lcdc_device *lcdc_dev =
4280             container_of(dev_drv, struct lcdc_device, driver);
4281         u32 mask, val;
4282
4283         spin_lock(&lcdc_dev->reg_lock);
4284         if (lcdc_dev->clk_on) {
4285                 switch (mode) {
4286                 case BRIGHTNESS:
4287                         /*from 0 to 255,typical is 128 */
4288                         if (value < 0x80)
4289                                 value += 0x80;
4290                         else if (value >= 0x80)
4291                                 value = value - 0x80;
4292                         mask = m_BCSH_BRIGHTNESS;
4293                         val = v_BCSH_BRIGHTNESS(value);
4294                         break;
4295                 case CONTRAST:
4296                         /*from 0 to 510,typical is 256 */
4297                         mask = m_BCSH_CONTRAST;
4298                         val = v_BCSH_CONTRAST(value);
4299                         break;
4300                 case SAT_CON:
4301                         /*from 0 to 1015,typical is 256 */
4302                         mask = m_BCSH_SAT_CON;
4303                         val = v_BCSH_SAT_CON(value);
4304                         break;
4305                 default:
4306                         break;
4307                 }
4308                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
4309                 lcdc_cfg_done(lcdc_dev);
4310         }
4311         spin_unlock(&lcdc_dev->reg_lock);
4312         return val;
4313 }
4314
4315 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4316                                     bcsh_bcs_mode mode)
4317 {
4318         struct lcdc_device *lcdc_dev =
4319             container_of(dev_drv, struct lcdc_device, driver);
4320         u32 val;
4321
4322         spin_lock(&lcdc_dev->reg_lock);
4323         if (lcdc_dev->clk_on) {
4324                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
4325                 switch (mode) {
4326                 case BRIGHTNESS:
4327                         val &= m_BCSH_BRIGHTNESS;
4328                         if (val > 0x80)
4329                                 val -= 0x80;
4330                         else
4331                                 val += 0x80;
4332                         break;
4333                 case CONTRAST:
4334                         val &= m_BCSH_CONTRAST;
4335                         val >>= 8;
4336                         break;
4337                 case SAT_CON:
4338                         val &= m_BCSH_SAT_CON;
4339                         val >>= 20;
4340                         break;
4341                 default:
4342                         break;
4343                 }
4344         }
4345         spin_unlock(&lcdc_dev->reg_lock);
4346         return val;
4347 }
4348
4349 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4350 {
4351         struct lcdc_device *lcdc_dev =
4352             container_of(dev_drv, struct lcdc_device, driver);
4353         u32 mask, val;
4354
4355         spin_lock(&lcdc_dev->reg_lock);
4356         if (lcdc_dev->clk_on) {
4357                 if (open) {
4358                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
4359                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4360                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4361                         dev_drv->bcsh.enable = 1;
4362                 } else {
4363                         mask = m_BCSH_EN;
4364                         val = v_BCSH_EN(0);
4365                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4366                         dev_drv->bcsh.enable = 0;
4367                 }
4368                 rk3368_lcdc_bcsh_path_sel(dev_drv);
4369                 lcdc_cfg_done(lcdc_dev);
4370         }
4371         spin_unlock(&lcdc_dev->reg_lock);
4372         return 0;
4373 }
4374
4375 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4376 {
4377         if (!enable || !dev_drv->bcsh.enable) {
4378                 rk3368_lcdc_open_bcsh(dev_drv, false);
4379                 return 0;
4380         }
4381
4382         if (dev_drv->bcsh.brightness <= 255 ||
4383             dev_drv->bcsh.contrast <= 510 ||
4384             dev_drv->bcsh.sat_con <= 1015 ||
4385             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4386                 rk3368_lcdc_open_bcsh(dev_drv, true);
4387                 if (dev_drv->bcsh.brightness <= 255)
4388                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4389                                                  dev_drv->bcsh.brightness);
4390                 if (dev_drv->bcsh.contrast <= 510)
4391                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4392                                                  dev_drv->bcsh.contrast);
4393                 if (dev_drv->bcsh.sat_con <= 1015)
4394                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4395                                                  dev_drv->bcsh.sat_con);
4396                 if (dev_drv->bcsh.sin_hue <= 511 &&
4397                     dev_drv->bcsh.cos_hue <= 511)
4398                         rk3368_lcdc_set_bcsh_hue(dev_drv,
4399                                                  dev_drv->bcsh.sin_hue,
4400                                                  dev_drv->bcsh.cos_hue);
4401         }
4402         return 0;
4403 }
4404
4405 static int __maybe_unused
4406 rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4407 {
4408         struct lcdc_device *lcdc_dev =
4409             container_of(dev_drv, struct lcdc_device, driver);
4410
4411         if (enable) {
4412                 spin_lock(&lcdc_dev->reg_lock);
4413                 if (likely(lcdc_dev->clk_on)) {
4414                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4415                                      v_DSP_BLACK_EN(1));
4416                         lcdc_cfg_done(lcdc_dev);
4417                 }
4418                 spin_unlock(&lcdc_dev->reg_lock);
4419         } else {
4420                 spin_lock(&lcdc_dev->reg_lock);
4421                 if (likely(lcdc_dev->clk_on)) {
4422                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4423                                      v_DSP_BLACK_EN(0));
4424
4425                         lcdc_cfg_done(lcdc_dev);
4426                 }
4427                 spin_unlock(&lcdc_dev->reg_lock);
4428         }
4429
4430         return 0;
4431 }
4432
4433
4434 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4435                                        int enable)
4436 {
4437         struct lcdc_device *lcdc_dev =
4438             container_of(dev_drv, struct lcdc_device, driver);
4439
4440         rk3368_lcdc_get_backlight_device(dev_drv);
4441
4442         if (enable) {
4443                 /* close the backlight */
4444                 if (lcdc_dev->backlight) {
4445                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4446                         backlight_update_status(lcdc_dev->backlight);
4447                 }
4448                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4449                         dev_drv->trsm_ops->disable();
4450         } else {
4451                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4452                         dev_drv->trsm_ops->enable();
4453                 msleep(100);
4454                 /* open the backlight */
4455                 if (lcdc_dev->backlight) {
4456                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4457                         backlight_update_status(lcdc_dev->backlight);
4458                 }
4459         }
4460
4461         return 0;
4462 }
4463
4464 static int rk3368_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
4465                                     struct overscan *overscan)
4466 {
4467         rk3368_lcdc_post_cfg(dev_drv);
4468
4469         return 0;
4470 }
4471
4472 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4473         .open = rk3368_lcdc_open,
4474         .win_direct_en = rk3368_lcdc_win_direct_en,
4475         .load_screen = rk3368_load_screen,
4476         .get_dspbuf_info = rk3368_get_dspbuf_info,
4477         .post_dspbuf = rk3368_post_dspbuf,
4478         .set_par = rk3368_lcdc_set_par,
4479         .pan_display = rk3368_lcdc_pan_display,
4480         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4481         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4482         .blank = rk3368_lcdc_blank,
4483         .ioctl = rk3368_lcdc_ioctl,
4484         .suspend = rk3368_lcdc_early_suspend,
4485         .resume = rk3368_lcdc_early_resume,
4486         .get_win_state = rk3368_lcdc_get_win_state,
4487         .area_support_num = rk3368_lcdc_get_area_num,
4488         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4489         .get_disp_info = rk3368_lcdc_get_disp_info,
4490         .fps_mgr = rk3368_lcdc_fps_mgr,
4491         .fb_get_win_id = rk3368_lcdc_get_win_id,
4492         .fb_win_remap = rk3368_fb_win_remap,
4493         .set_dsp_lut = rk3368_lcdc_set_lut,
4494         .set_cabc_lut = rk3368_set_cabc_lut,
4495         .poll_vblank = rk3368_lcdc_poll_vblank,
4496         .dpi_open = rk3368_lcdc_dpi_open,
4497         .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4498         .dpi_status = rk3368_lcdc_dpi_status,
4499         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4500         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4501         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4502         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4503         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4504         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4505         .open_bcsh = rk3368_lcdc_open_bcsh,
4506         .dump_reg = rk3368_lcdc_reg_dump,
4507         .cfg_done = rk3368_lcdc_config_done,
4508         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4509         /*.dsp_black = rk3368_lcdc_dsp_black,*/
4510         .backlight_close = rk3368_lcdc_backlight_close,
4511         .mmu_en    = rk3368_lcdc_mmu_en,
4512         .set_overscan   = rk3368_lcdc_set_overscan,
4513 };
4514
4515 #ifdef LCDC_IRQ_EMPTY_DEBUG
4516 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4517                                  unsigned int intr_status)
4518 {
4519         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4520                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4521                              v_WIN0_EMPTY_INTR_CLR(1));
4522                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4523         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4524                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4525                              v_WIN1_EMPTY_INTR_CLR(1));
4526                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4527         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4528                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4529                              v_WIN2_EMPTY_INTR_CLR(1));
4530                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4531         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4532                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4533                              v_WIN3_EMPTY_INTR_CLR(1));
4534                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4535         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4536                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4537                              v_HWC_EMPTY_INTR_CLR(1));
4538                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4539         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4540                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4541                              v_POST_BUF_EMPTY_INTR_CLR(1));
4542                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4543         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4544                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4545                              v_PWM_GEN_INTR_CLR(1));
4546                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4547         }
4548         return 0;
4549 }
4550 #endif
4551
4552 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4553 {
4554         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4555         ktime_t timestamp = ktime_get();
4556         u32 intr_status;
4557         u32 scale_global_limit, scale_global_limit_reg;
4558         u32 cabc_pwm_lut_value;
4559         int pwm_plus;
4560         int *cabc_gamma_base = NULL;
4561         intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4562
4563         if (intr_status & m_FS_INTR_STS) {
4564                 timestamp = ktime_get();
4565                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4566                              v_FS_INTR_CLR(1));
4567                 /*if(lcdc_dev->driver.wait_fs){ */
4568                 if (0) {
4569                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4570                         complete(&(lcdc_dev->driver.frame_done));
4571                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4572                 }
4573 #ifdef CONFIG_DRM_ROCKCHIP
4574                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4575 #endif
4576                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4577                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4578         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4579                 lcdc_dev->driver.frame_time.last_framedone_t =
4580                         lcdc_dev->driver.frame_time.framedone_t;
4581                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4582                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4583                              v_LINE_FLAG0_INTR_CLR(1));
4584
4585                 if (cabc_status == 1) {
4586                         cabc_gamma_base =
4587                                 lcdc_dev->driver.cur_screen->cabc_gamma_base;
4588                         scale_global_limit  = lcdc_readl(lcdc_dev, CABC_DEBUG2);
4589                         scale_global_limit_reg = scale_global_limit;
4590                         scale_global_limit >>= 16;
4591                         scale_global_limit &= 0xff;
4592
4593                         if (lcdc_dev->driver.cabc_pwm_pol == 1) {/*negative*/
4594                                 pwm_plus = pwm_period_hpr - pwm_duty_lpr;
4595                                 cabc_pwm_lut_value =
4596                                         pwm_period_hpr -
4597                                         ((cabc_gamma_base[scale_global_limit] * pwm_plus) >> 16);
4598                         } else {/*positive*/
4599                                 pwm_plus = pwm_duty_lpr;
4600                                 cabc_pwm_lut_value =
4601                                         cabc_gamma_base[scale_global_limit] *
4602                                         pwm_plus >> 16;
4603                         }
4604                         rk_pwm_set(pwm_period_hpr, cabc_pwm_lut_value);
4605                 }
4606         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4607                 /*line flag1 */
4608                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4609                              v_LINE_FLAG1_INTR_CLR(1));
4610         } else if (intr_status & m_FS_NEW_INTR_STS) {
4611                 /*new frame start */
4612                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4613                              v_FS_NEW_INTR_CLR(1));
4614         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4615                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4616                              v_BUS_ERROR_INTR_CLR(1));
4617                 dev_warn(lcdc_dev->dev, "bus error!");
4618         }
4619
4620         /* for win empty debug */
4621 #ifdef LCDC_IRQ_EMPTY_DEBUG
4622         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4623 #endif
4624         return IRQ_HANDLED;
4625 }
4626
4627 #if defined(CONFIG_PM)
4628 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4629 {
4630         return 0;
4631 }
4632
4633 static int rk3368_lcdc_resume(struct platform_device *pdev)
4634 {
4635         return 0;
4636 }
4637 #else
4638 #define rk3368_lcdc_suspend NULL
4639 #define rk3368_lcdc_resume  NULL
4640 #endif
4641
4642 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4643 {
4644         struct device_node *np = lcdc_dev->dev->of_node;
4645         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4646         int val;
4647
4648         if (of_property_read_u32(np, "rockchip,prop", &val))
4649                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4650         else
4651                 lcdc_dev->prop = val;
4652
4653         if (of_property_read_u32(np, "rockchip,mirror", &val))
4654                 dev_drv->rotate_mode = NO_MIRROR;
4655         else
4656                 dev_drv->rotate_mode = val;
4657
4658         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4659                 dev_drv->cabc_mode = 0; /* default set close cabc */
4660         else
4661                 dev_drv->cabc_mode = val;
4662
4663         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4664                 /*default set it as 3.xv power supply */
4665                 lcdc_dev->pwr18 = false;
4666         else
4667                 lcdc_dev->pwr18 = (val ? true : false);
4668
4669         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4670                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4671         else
4672                 dev_drv->fb_win_map = val;
4673
4674         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4675                 dev_drv->bcsh.enable = false;
4676         else
4677                 dev_drv->bcsh.enable = (val ? true : false);
4678
4679         if (of_property_read_u32(np, "rockchip,brightness", &val))
4680                 dev_drv->bcsh.brightness = 0xffff;
4681         else
4682                 dev_drv->bcsh.brightness = val;
4683
4684         if (of_property_read_u32(np, "rockchip,contrast", &val))
4685                 dev_drv->bcsh.contrast = 0xffff;
4686         else
4687                 dev_drv->bcsh.contrast = val;
4688
4689         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4690                 dev_drv->bcsh.sat_con = 0xffff;
4691         else
4692                 dev_drv->bcsh.sat_con = val;
4693
4694         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4695                 dev_drv->bcsh.sin_hue = 0xffff;
4696                 dev_drv->bcsh.cos_hue = 0xffff;
4697         } else {
4698                 dev_drv->bcsh.sin_hue = val & 0xff;
4699                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4700         }
4701
4702 #if defined(CONFIG_ROCKCHIP_IOMMU)
4703         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4704                 dev_drv->iommu_enabled = 0;
4705         else
4706                 dev_drv->iommu_enabled = val;
4707 #else
4708         dev_drv->iommu_enabled = 0;
4709 #endif
4710         return 0;
4711 }
4712
4713 static int rk3368_lcdc_probe(struct platform_device *pdev)
4714 {
4715         struct lcdc_device *lcdc_dev = NULL;
4716         struct rk_lcdc_driver *dev_drv;
4717         struct device *dev = &pdev->dev;
4718         struct resource *res;
4719         struct device_node *np = pdev->dev.of_node;
4720         int prop;
4721         int ret = 0;
4722
4723         /*if the primary lcdc has not registered ,the extend
4724            lcdc register later */
4725         of_property_read_u32(np, "rockchip,prop", &prop);
4726         if (prop == EXTEND) {
4727                 if (!is_prmry_rk_lcdc_registered())
4728                         return -EPROBE_DEFER;
4729         }
4730         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4731         if (!lcdc_dev) {
4732                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4733                 return -ENOMEM;
4734         }
4735         platform_set_drvdata(pdev, lcdc_dev);
4736         lcdc_dev->dev = dev;
4737         rk3368_lcdc_parse_dt(lcdc_dev);
4738         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4739         lcdc_dev->reg_phy_base = res->start;
4740         lcdc_dev->len = resource_size(res);
4741         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4742         if (IS_ERR(lcdc_dev->regs))
4743                 return PTR_ERR(lcdc_dev->regs);
4744         else
4745                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4746
4747         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4748         if (IS_ERR(lcdc_dev->regsbak))
4749                 return PTR_ERR(lcdc_dev->regsbak);
4750         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4751         lcdc_dev->cabc_lut_addr_base = (lcdc_dev->regs + CABC_GAMMA_LUT_ADDR);
4752         lcdc_dev->grf_base =
4753                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4754         if (IS_ERR(lcdc_dev->grf_base)) {
4755                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4756                 return PTR_ERR(lcdc_dev->grf_base);
4757         }
4758         lcdc_dev->pmugrf_base =
4759                 syscon_regmap_lookup_by_phandle(np, "rockchip,pmugrf");
4760         if (IS_ERR(lcdc_dev->pmugrf_base)) {
4761                 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
4762                 return PTR_ERR(lcdc_dev->pmugrf_base);
4763         }
4764
4765         lcdc_dev->cru_base =
4766                 syscon_regmap_lookup_by_phandle(np, "rockchip,cru");
4767         if (IS_ERR(lcdc_dev->cru_base)) {
4768                 dev_err(&pdev->dev, "can't find lcdc cru_base property\n");
4769                 return PTR_ERR(lcdc_dev->cru_base);
4770         }
4771
4772         lcdc_dev->id = 0;
4773         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4774         dev_drv = &lcdc_dev->driver;
4775         dev_drv->dev = dev;
4776         dev_drv->prop = prop;
4777         dev_drv->id = lcdc_dev->id;
4778         dev_drv->ops = &lcdc_drv_ops;
4779         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4780         dev_drv->reserved_fb = 1;/*only need reserved 1 buffer*/
4781         spin_lock_init(&lcdc_dev->reg_lock);
4782
4783         lcdc_dev->irq = platform_get_irq(pdev, 0);
4784         if (lcdc_dev->irq < 0) {
4785                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4786                         lcdc_dev->id);
4787                 return -ENXIO;
4788         }
4789
4790         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4791                                IRQF_DISABLED | IRQF_SHARED,
4792                                dev_name(dev), lcdc_dev);
4793         if (ret) {
4794                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4795                         lcdc_dev->irq, ret);
4796                 return ret;
4797         }
4798
4799         if (dev_drv->iommu_enabled) {
4800                 if (lcdc_dev->id == 0) {
4801                         strcpy(dev_drv->mmu_dts_name,
4802                                VOPB_IOMMU_COMPATIBLE_NAME);
4803                 } else {
4804                         strcpy(dev_drv->mmu_dts_name,
4805                                VOPL_IOMMU_COMPATIBLE_NAME);
4806                 }
4807         }
4808
4809         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4810         if (ret < 0) {
4811                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4812                 return ret;
4813         }
4814         lcdc_dev->screen = dev_drv->screen0;
4815         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4816                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4817
4818         return 0;
4819 }
4820
4821 static int rk3368_lcdc_remove(struct platform_device *pdev)
4822 {
4823         return 0;
4824 }
4825
4826 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4827 {
4828         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4829         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4830 #if 1
4831         dev_drv->suspend_flag = 1;
4832         mdelay(100);
4833         flush_kthread_worker(&dev_drv->update_regs_worker);
4834         kthread_stop(dev_drv->update_regs_thread);
4835         rk3368_lcdc_deint(lcdc_dev);
4836         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4837                 dev_drv->trsm_ops->disable();
4838
4839         rk3368_lcdc_clk_disable(lcdc_dev);
4840         rk_disp_pwr_disable(dev_drv);
4841 #else
4842         rk3368_lcdc_early_suspend(&lcdc_dev->driver);
4843         rk3368_lcdc_deint(lcdc_dev);
4844 #endif
4845
4846 }
4847
4848 #if defined(CONFIG_OF)
4849 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4850         {.compatible = "rockchip,rk3368-lcdc",},
4851         {}
4852 };
4853 #endif
4854
4855 static struct platform_driver rk3368_lcdc_driver = {
4856         .probe = rk3368_lcdc_probe,
4857         .remove = rk3368_lcdc_remove,
4858         .driver = {
4859                    .name = "rk3368-lcdc",
4860                    .owner = THIS_MODULE,
4861                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4862                    },
4863         .suspend = rk3368_lcdc_suspend,
4864         .resume = rk3368_lcdc_resume,
4865         .shutdown = rk3368_lcdc_shutdown,
4866 };
4867
4868 static int __init rk3368_lcdc_module_init(void)
4869 {
4870         return platform_driver_register(&rk3368_lcdc_driver);
4871 }
4872
4873 static void __exit rk3368_lcdc_module_exit(void)
4874 {
4875         platform_driver_unregister(&rk3368_lcdc_driver);
4876 }
4877
4878 fs_initcall(rk3368_lcdc_module_init);
4879 module_exit(rk3368_lcdc_module_exit);