drivers/video/rockchip/hdmi/rockchip-hdmiv2/rockchip_hdmiv2_hw.c

   1 #include <linux/clk.h>
   2 #include <linux/delay.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/rockchip/cru.h>
   5 #include <linux/rockchip/grf.h>
   6 #include <linux/rockchip/iomap.h>
   7 #include "rockchip_hdmiv2.h"
   8 #include "rockchip_hdmiv2_hw.h"
   9 #include <linux/rockchip/grf.h>
  10
  11 #define HDMI_SEL_LCDC(x, bit)   ((((x) & 1) << bit) | (1 << (16 + bit)))
  12 #define grf_writel(v, offset)   writel_relaxed(v, RK_GRF_VIRT + offset)
  13 #define RK3399_GRF_SOC_CON20 0x6250
  14
  15 static const struct phy_mpll_config_tab PHY_MPLL_TABLE[] = {
  16 /*      tmdsclk = (pixclk / ref_cntrl ) * (fbdiv2 * fbdiv1) / nctrl / tmdsmhl
  17  *      opmode: 0:HDMI1.4       1:HDMI2.0
  18  *
  19  *      |pixclock|      tmdsclock|pixrepet|colordepth|prepdiv|tmdsmhl|opmode|
  20  *              fbdiv2|fbdiv1|ref_cntrl|nctrl|propctrl|intctrl|gmpctrl|
  21  */
  22         {27000000,      27000000,       0,      8,      0,      0,      0,
  23                 2,      3,      0,      3,      3,      0,      0},
  24         {27000000,      27000000,       1,      8,      0,      0,      0,
  25                 2,      3,      0,      3,      3,      0,      0},
  26         {27000000,      33750000,       0,      10,     1,      0,      0,
  27                 5,      1,      0,      3,      3,      0,      0},
  28         {27000000,      33750000,       1,      10,     1,      0,      0,
  29                 5,      1,      0,      3,      3,      0,      0},
  30         {27000000,      40500000,       0,      12,     2,      0,      0,
  31                 3,      3,      0,      3,      3,      0,      0},
  32         {27000000,      54000000,       0,      16,     3,      0,      0,
  33                 2,      3,      0,      2,      5,      0,      1},
  34         {59400000,      59400000,       0,      8,      0,      0,      0,
  35                 1,      3,      0,      2,      5,      0,      1},
  36         {59400000,      74250000,       0,      10,     1,      0,      0,
  37                 5,      0,      0,      2,      5,      0,      1},
  38         {59400000,      89100000,       0,      12,     2,      0,      0,
  39                 2,      2,      0,      2,      5,      0,      1},
  40         {59400000,      118800000,      0,      16,     3,      0,      0,
  41                 1,      3,      0,      1,      7,      0,      2},
  42         {65000000,      65000000,       0,      8,      0,      0,      0,
  43                 1,      3,      0,      2,      5,      0,      1},
  44         {74250000,      74250000,       0,      8,      0,      0,      0,
  45                 4,      3,      3,      2,      7,      0,      3},
  46         {74250000,      92812500,       0,      10,     1,      0,      0,
  47                 5,      0,      1,      1,      7,      0,      2},
  48         {74250000,      111375000,      0,      12,     2,      0,      0,
  49                 1,      2,      0,      1,      7,      0,      2},
  50         {74250000,      148500000,      0,      16,     3,      0,      0,
  51                 1,      3,      0,      1,      7,      0,      2},
  52         {83500000,      83500000,       0,      8,      0,      0,      0,
  53                 1,      3,      0,      2,      5,      0,      1},
  54         {85500000,      85500000,       0,      8,      0,      0,      0,
  55                 1,      3,      0,      2,      5,      0,      1},
  56         {106500000,     106500000,      0,      8,      0,      0,      0,
  57                 1,      1,      0,      1,      7,      0,      2},
  58         {108000000,     108000000,      0,      8,      0,      0,      0,
  59                 1,      1,      0,      1,      7,      0,      2},
  60         {146250000,     146250000,      0,      8,      0,      0,      0,
  61                 1,      1,      0,      1,      7,      0,      2},
  62         {148500000,     74250000,       0,      8,      0,      0,      0,
  63                 1,      1,      1,      1,      0,      0,      3},
  64         {148500000,     148500000,      0,      8,      0,      0,      0,
  65                 1,      1,      0,      1,      0,      0,      3},
  66         {148500000,     185625000,      0,      10,     1,      0,      0,
  67                 5,      0,      3,      0,      7,      0,      3},
  68         {148500000,     222750000,      0,      12,     2,      0,      0,
  69                 1,      2,      1,      0,      7,      0,      3},
  70         {148500000,     297000000,      0,      16,     3,      0,      0,
  71                 1,      1,      0,      0,      7,      0,      3},
  72         {148500000,     297000000,      0,      8,      0,      0,      0,
  73                 1,      1,      0,      0,      0,      0,      3},
  74         {148500000,     594000000,      0,      8,      0,      3,      1,
  75                 1,      3,      0,      0,      0,      0,      3},
  76         {269390000,     269390000,      0,      8,      0,      0,      0,
  77                 1,      0,      0,      0,      0,      0,      3},
  78         {285000000,     285000000,      0,      8,      0,      0,      0,
  79                 1,      0,      0,      0,      0,      0,      3},
  80         {297000000,     148500000,      0,      8,      0,      0,      0,
  81                 1,      0,      1,      0,      0,      0,      3},
  82         {297000000,     297000000,      0,      8,      0,      0,      0,
  83                 1,      0,      0,      0,      0,      0,      3},
  84         {297000000,     371250000,      0,      10,     1,      3,      1,
  85                 5,      1,      3,      1,      7,      0,      3},
  86         {297000000,     445500000,      0,      12,     2,      3,      1,
  87                 1,      2,      0,      1,      7,      0,      3},
  88         {297000000,     594000000,      0,      16,     3,      3,      1,
  89                 1,      3,      1,      0,      0,      0,      3},
  90         {340000000,     340000000,      0,      8,      0,      0,      0,
  91                 1,      0,      0,      0,      0,      0,      3},
  92         {403000000,     403000000,      0,      8,      0,      3,      1,
  93                 1,      3,      3,      0,      0,      0,      3},
  94         {594000000,     297000000,      0,      8,      0,      0,      0,
  95                 1,      0,      1,      0,      0,      0,      3},
  96         {594000000,     371250000,      0,      10,     1,      3,      1,
  97                 5,      0,      3,      1,      7,      0,      3},
  98         {594000000,     445500000,      0,      12,     2,      3,      1,
  99                 1,      2,      1,      1,      7,      0,      3},
 100         {594000000,     594000000,      0,      16,     3,      3,      1,
 101                 1,      3,      3,      0,      0,      0,      3},
 102         {594000000,     594000000,      0,      8,      0,      3,      1,
 103                 1,      3,      3,      0,      0,      0,      3},
 104 };
 105
 106 static const struct ext_pll_config_tab EXT_PLL_TABLE[] = {
 107         {27000000,      27000000,       8,      1,      90,     3,      2,
 108                 2,      10,     3,      3,      4,      0,      1,      40,
 109                 8},
 110         {27000000,      33750000,       10,     1,      90,     1,      3,
 111                 3,      10,     3,      3,      4,      0,      1,      40,
 112                 8},
 113         {59400000,      59400000,       8,      1,      99,     3,      2,
 114                 2,      1,      3,      3,      4,      0,      1,      40,
 115                 8},
 116         {59400000,      74250000,       10,     1,      99,     1,      2,
 117                 2,      1,      3,      3,      4,      0,      1,      40,
 118                 8},
 119         {74250000,      74250000,       8,      1,      99,     1,      2,
 120                 2,      1,      2,      3,      4,      0,      1,      40,
 121                 8},
 122         {74250000,      92812500,       10,     4,      495,    1,      2,
 123                 2,      1,      3,      3,      4,      0,      2,      40,
 124                 4},
 125         {148500000,     148500000,      8,      1,      99,     1,      1,
 126                 1,      1,      2,      2,      2,      0,      2,      40,
 127                 4},
 128         {148500000,     185625000,      10,     4,      495,    0,      2,
 129                 2,      1,      3,      2,      2,      0,      4,      40,
 130                 2},
 131         {297000000,     297000000,      8,      1,      99,     0,      1,
 132                 1,      1,      0,      2,      2,      0,      4,      40,
 133                 2},
 134         {297000000,     371250000,      10,     4,      495,    1,      2,
 135                 0,      1,      3,      1,      1,      0,      8,      40,
 136                 1},
 137         {594000000,     297000000,      8,      1,      99,     0,      1,
 138                 1,      1,      0,      2,      1,      0,      4,      40,
 139                 2},
 140         {594000000,     371250000,      10,     4,      495,    1,      2,
 141                 0,      1,      3,      1,      1,      1,      8,      40,
 142                 1},
 143         {594000000,     594000000,      8,      1,      99,     0,      2,
 144                 0,      1,      0,      1,      1,      0,      8,      40,
 145                 1},
 146 };
 147
 148 /* ddc i2c master reset */
 149 static void rockchip_hdmiv2_i2cm_reset(struct hdmi_dev *hdmi_dev)
 150 {
 151         hdmi_msk_reg(hdmi_dev, I2CM_SOFTRSTZ,
 152                      m_I2CM_SOFTRST, v_I2CM_SOFTRST(0));
 153         usleep_range(90, 100);
 154 }
 155
 156 /*set read/write offset,set read/write mode*/
 157 static void rockchip_hdmiv2_i2cm_write_request(struct hdmi_dev *hdmi_dev,
 158                                                u8 offset, u8 data)
 159 {
 160         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
 161         hdmi_writel(hdmi_dev, I2CM_DATAO, data);
 162         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_WR, v_I2CM_WR(1));
 163 }
 164
 165 static void rockchip_hdmiv2_i2cm_read_request(struct hdmi_dev *hdmi_dev,
 166                                               u8 offset)
 167 {
 168         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
 169         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_RD, v_I2CM_RD(1));
 170 }
 171
 172 static void rockchip_hdmiv2_i2cm_write_data(struct hdmi_dev *hdmi_dev,
 173                                             u8 data, u8 offset)
 174 {
 175         u8 interrupt = 0;
 176         int trytime = 2;
 177         int i = 20;
 178
 179         while (trytime-- > 0) {
 180                 rockchip_hdmiv2_i2cm_write_request(hdmi_dev, offset, data);
 181                 while (i--) {
 182                         usleep_range(900, 1000);
 183                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 184                         if (interrupt)
 185                                 hdmi_writel(hdmi_dev,
 186                                             IH_I2CM_STAT0, interrupt);
 187
 188                         if (interrupt & (m_SCDC_READREQ |
 189                                          m_I2CM_DONE | m_I2CM_ERROR))
 190                                 break;
 191                 }
 192
 193                 if (interrupt & m_I2CM_DONE) {
 194                         dev_dbg(hdmi_dev->hdmi->dev,
 195                                 "[%s] write offset %02x data %02x success\n",
 196                                 __func__, offset, data);
 197                         trytime = 0;
 198                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 199                         dev_err(hdmi_dev->hdmi->dev,
 200                                 "[%s] write data error\n", __func__);
 201                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 202                 }
 203         }
 204 }
 205
 206 static int rockchip_hdmiv2_i2cm_read_data(struct hdmi_dev *hdmi_dev, u8 offset)
 207 {
 208         u8 interrupt = 0, val;
 209         int trytime = 2;
 210         int i = 20;
 211
 212         while (trytime-- > 0) {
 213                 rockchip_hdmiv2_i2cm_read_request(hdmi_dev, offset);
 214                 while (i--) {
 215                         usleep_range(900, 1000);
 216                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 217                         if (interrupt)
 218                                 hdmi_writel(hdmi_dev, IH_I2CM_STAT0, interrupt);
 219
 220                         if (interrupt & (m_SCDC_READREQ |
 221                                 m_I2CM_DONE | m_I2CM_ERROR))
 222                                 break;
 223                 }
 224
 225                 if (interrupt & m_I2CM_DONE) {
 226                         val = hdmi_readl(hdmi_dev, I2CM_DATAI);
 227                         trytime = 0;
 228                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 229                         pr_err("[%s] read data error\n", __func__);
 230                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 231                 }
 232         }
 233         return val;
 234 }
 235
 236 static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
 237 {
 238         if (!mask) {
 239                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 240                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(0));
 241                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 242                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 243                              v_I2CM_NACK_MASK(0) | v_I2CM_ARB_MASK(0));
 244         } else {
 245                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 246                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(1));
 247                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 248                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 249                              v_I2CM_NACK_MASK(1) | v_I2CM_ARB_MASK(1));
 250         }
 251 }
 252
 253 #define I2C_DIV_FACTOR 1000000
 254 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
 255 {
 256         unsigned long tmp_scl_period = 0;
 257
 258         if (((sfrclock * sclmintime) % I2C_DIV_FACTOR) != 0)
 259                 tmp_scl_period = (unsigned long)((sfrclock * sclmintime) +
 260                                 (I2C_DIV_FACTOR - ((sfrclock * sclmintime) %
 261                                 I2C_DIV_FACTOR))) / I2C_DIV_FACTOR;
 262         else
 263                 tmp_scl_period = (unsigned long)(sfrclock * sclmintime) /
 264                                 I2C_DIV_FACTOR;
 265
 266         return (u16)(tmp_scl_period);
 267 }
 268
 269 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME   9625
 270 #define EDID_I2C_MIN_SS_SCL_LOW_TIME    10000
 271
 272 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
 273 {
 274         int value;
 275
 276         /* Set DDC I2C CLK which divided from DDC_CLK. */
 277         value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME);
 278         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
 279                     value & 0xff);
 280         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_1_ADDR,
 281                     (value >> 8) & 0xff);
 282         value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME);
 283         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
 284                     value & 0xff);
 285         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_1_ADDR,
 286                     (value >> 8) & 0xff);
 287         hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
 288                      v_I2CM_FAST_STD_MODE(STANDARD_MODE));
 289 }
 290
 291 static int rockchip_hdmiv2_scdc_get_sink_version(struct hdmi_dev *hdmi_dev)
 292 {
 293         return rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SINK_VER);
 294 }
 295
 296 static void rockchip_hdmiv2_scdc_set_source_version(struct hdmi_dev *hdmi_dev,
 297                                                     u8 version)
 298 {
 299         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, version, SCDC_SOURCE_VER);
 300 }
 301
 302 static void rockchip_hdmiv2_scdc_read_request(struct hdmi_dev *hdmi_dev,
 303                                               int enable)
 304 {
 305         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 306                      m_I2CM_READ_REQ_EN, v_I2CM_READ_REQ_EN(enable));
 307         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, enable, SCDC_CONFIG_0);
 308 }
 309
 310 #ifdef HDMI_20_SCDC
 311 static void rockchip_hdmiv2_scdc_update_read(struct hdmi_dev *hdmi_dev)
 312 {
 313         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 314                      m_I2CM_READ_UPDATE, v_I2CM_READ_UPDATE(1));
 315 }
 316
 317 static int rockchip_hdmiv2_scdc_get_scambling_status(struct hdmi_dev *hdmi_dev)
 318 {
 319         int val;
 320
 321         val = rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SCRAMBLER_STAT);
 322         return val;
 323 }
 324
 325 static void rockchip_hdmiv2_scdc_enable_polling(struct hdmi_dev *hdmi_dev,
 326                                                 int enable)
 327 {
 328         rockchip_hdmiv2_scdc_read_request(hdmi_dev, enable);
 329         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 330                      m_I2CM_UPRD_VSYNC_EN, v_I2CM_UPRD_VSYNC_EN(enable));
 331 }
 332
 333 static int rockchip_hdmiv2_scdc_get_status_reg0(struct hdmi_dev *hdmi_dev)
 334 {
 335         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 336         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 337         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE0);
 338 }
 339
 340 static int rockchip_hdmiv2_scdc_get_status_reg1(struct hdmi_dev *hdmi_dev)
 341 {
 342         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 343         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 344         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE1);
 345 }
 346 #endif
 347
 348 static void rockchip_hdmiv2_scdc_init(struct hdmi_dev *hdmi_dev)
 349 {
 350         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 351         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
 352         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
 353         /* set scdc i2c addr */
 354         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_SCDC_ADDR);
 355         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);/*enable interrupt*/
 356 }
 357
 358 static void rockchip_hdmiv2_scdc_set_tmds_rate(struct hdmi_dev *hdmi_dev)
 359 {
 360         int stat;
 361
 362         mutex_lock(&hdmi_dev->ddc_lock);
 363         rockchip_hdmiv2_scdc_init(hdmi_dev);
 364         stat = rockchip_hdmiv2_i2cm_read_data(hdmi_dev,
 365                                               SCDC_TMDS_CONFIG);
 366         if (hdmi_dev->tmdsclk > 340000000)
 367                 stat |= 2;
 368         else
 369                 stat &= 0x1;
 370         rockchip_hdmiv2_i2cm_write_data(hdmi_dev,
 371                                         stat, SCDC_TMDS_CONFIG);
 372         mutex_unlock(&hdmi_dev->ddc_lock);
 373 }
 374
 375 static int rockchip_hdmiv2_scrambling_enable(struct hdmi_dev *hdmi_dev,
 376                                              int enable)
 377 {
 378         HDMIDBG(2, "%s enable %d\n", __func__, enable);
 379         if (enable == 1) {
 380                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 381                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 1, SCDC_TMDS_CONFIG);
 382                 /* TMDS software reset request */
 383                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 384                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 385                 /* Enable/Disable Scrambling */
 386                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 387                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
 388         } else {
 389                 /* Enable/Disable Scrambling */
 390                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 391                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 392                 /* TMDS software reset request */
 393                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 394                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 395                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 396                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 0, SCDC_TMDS_CONFIG);
 397         }
 398         return 0;
 399 }
 400
 401 static const struct ext_pll_config_tab *get_phy_ext_tab(
 402                 unsigned int pixclock, unsigned int tmdsclk,
 403                 char colordepth)
 404 {
 405         int i;
 406
 407         if (pixclock == 0)
 408                 return NULL;
 409         HDMIDBG(2, "%s pixClock %u tmdsclk %u colorDepth %d\n",
 410                 __func__, pixclock, tmdsclk, colordepth);
 411         for (i = 0; i < ARRAY_SIZE(EXT_PLL_TABLE); i++) {
 412                 if ((EXT_PLL_TABLE[i].pix_clock == pixclock) &&
 413                     (EXT_PLL_TABLE[i].tmdsclock == tmdsclk) &&
 414                     (EXT_PLL_TABLE[i].color_depth == colordepth))
 415                         return &EXT_PLL_TABLE[i];
 416         }
 417         return NULL;
 418 }
 419
 420 static const struct phy_mpll_config_tab *get_phy_mpll_tab(
 421                 unsigned int pixclock, unsigned int tmdsclk,
 422                 char pixrepet, char colordepth)
 423 {
 424         int i;
 425
 426         if (pixclock == 0)
 427                 return NULL;
 428         HDMIDBG(2, "%s pixClock %u tmdsclk %u pixRepet %d colorDepth %d\n",
 429                 __func__, pixclock, tmdsclk, pixrepet, colordepth);
 430         for (i = 0; i < ARRAY_SIZE(PHY_MPLL_TABLE); i++) {
 431                 if ((PHY_MPLL_TABLE[i].pix_clock == pixclock) &&
 432                     (PHY_MPLL_TABLE[i].tmdsclock == tmdsclk) &&
 433                     (PHY_MPLL_TABLE[i].pix_repet == pixrepet) &&
 434                     (PHY_MPLL_TABLE[i].color_depth == colordepth))
 435                         return &PHY_MPLL_TABLE[i];
 436         }
 437         return NULL;
 438 }
 439
 440 static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
 441 {
 442         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
 443
 444         if (hdmi_dev->soctype != HDMI_SOC_RK322X) {
 445                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 446                              m_PDDQ_SIG | m_TXPWRON_SIG |
 447                              m_ENHPD_RXSENSE_SIG | m_SVSRET_SIG,
 448                              v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) |
 449                              v_ENHPD_RXSENSE_SIG(1)) | v_SVSRET_SIG(0);
 450         } else {
 451                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 452                              m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
 453                              v_TXPWRON_SIG(0) | v_ENHPD_RXSENSE_SIG(0));
 454                 regmap_write(hdmi_dev->grf_base,
 455                              RK322X_GRF_SOC_CON2,
 456                              RK322X_PLL_PDATA_DEN);
 457         }
 458         hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
 459 }
 460
 461 int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
 462                               int reg_addr, int val)
 463 {
 464         int trytime = 2, i = 0, op_status = 0;
 465
 466         if (hdmi_dev->phybase) {
 467                 writel_relaxed(val, hdmi_dev->phybase + (reg_addr) * 0x04);
 468                 return 0;
 469         }
 470         while (trytime--) {
 471                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 472                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_1, (val >> 8) & 0xff);
 473                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
 474                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
 475
 476                 i = 20;
 477                 while (i--) {
 478                         usleep_range(900, 1000);
 479                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 480                         if (op_status)
 481                                 hdmi_writel(hdmi_dev,
 482                                             IH_I2CMPHY_STAT0,
 483                                             op_status);
 484
 485                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 486                                 break;
 487                 }
 488
 489                 if (!(op_status & m_I2CMPHY_DONE))
 490                         dev_err(hdmi_dev->hdmi->dev,
 491                                 "[%s] operation error,trytime=%d\n",
 492                                 __func__, trytime);
 493                 else
 494                         return 0;
 495                 msleep(100);
 496         }
 497
 498         return -1;
 499 }
 500
 501 int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
 502                              int reg_addr)
 503 {
 504         int trytime = 2, i = 0, op_status = 0;
 505         int val = 0;
 506
 507         if (hdmi_dev->phybase)
 508                 return readl_relaxed(hdmi_dev->phybase + (reg_addr) * 0x04);
 509
 510         while (trytime--) {
 511                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 512                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_1, 0x00);
 513                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_0, 0x00);
 514                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_READ);
 515
 516                 i = 20;
 517                 while (i--) {
 518                         usleep_range(900, 1000);
 519                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 520                         if (op_status)
 521                                 hdmi_writel(hdmi_dev, IH_I2CMPHY_STAT0,
 522                                             op_status);
 523
 524                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 525                                 break;
 526                 }
 527
 528                 if (!(op_status & m_I2CMPHY_DONE)) {
 529                         pr_err("[%s] operation error,trytime=%d\n",
 530                                __func__, trytime);
 531                 } else {
 532                         val = hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_1);
 533                         val = (val & 0xff) << 8;
 534                         val += (hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_0) & 0xff);
 535                         pr_debug("phy_reg0x%02x: 0x%04x",
 536                                  reg_addr, val);
 537                         return val;
 538                 }
 539                 msleep(100);
 540         }
 541
 542         return -1;
 543 }
 544
 545 #define PHY_TIMEOUT     10000
 546
 547 static int ext_phy_config(struct hdmi_dev *hdmi_dev)
 548 {
 549         int stat = 0, i = 0, temp;
 550         const struct ext_pll_config_tab *phy_ext = NULL;
 551
 552         if (hdmi_dev->grf_base)
 553                 regmap_write(hdmi_dev->grf_base,
 554                              RK322X_GRF_SOC_CON2,
 555                              RK322X_PLL_POWER_DOWN |
 556                              RK322X_PLL_PDATA_DEN);
 557         if (hdmi_dev->tmdsclk_ratio_change &&
 558             hdmi_dev->hdmi->edid.scdc_present == 1)
 559                 rockchip_hdmiv2_scdc_set_tmds_rate(hdmi_dev);
 560
 561         /* config the required PHY I2C register */
 562         phy_ext = get_phy_ext_tab(hdmi_dev->pixelclk,
 563                                   hdmi_dev->tmdsclk,
 564                                   hdmi_dev->colordepth);
 565         if (phy_ext) {
 566                 stat = ((phy_ext->pll_nf >> 1) & EXT_PHY_PLL_FB_BIT8_MASK) |
 567                        ((phy_ext->vco_div_5 & 1) << 5) |
 568                        (phy_ext->pll_nd & EXT_PHY_PLL_PRE_DIVIDER_MASK);
 569                 rockchip_hdmiv2_write_phy(hdmi_dev,
 570                                           EXT_PHY_PLL_PRE_DIVIDER, stat);
 571                 stat = phy_ext->pll_nf & 0xff;
 572                 rockchip_hdmiv2_write_phy(hdmi_dev,
 573                                           EXT_PHY_PLL_FB_DIVIDER, stat);
 574                 stat = (phy_ext->pclk_divider_a & EXT_PHY_PCLK_DIVIDERA_MASK) |
 575                        ((phy_ext->pclk_divider_b & 3) << 5);
 576                 rockchip_hdmiv2_write_phy(hdmi_dev,
 577                                           EXT_PHY_PCLK_DIVIDER1, stat);
 578                 stat = (phy_ext->pclk_divider_d & EXT_PHY_PCLK_DIVIDERD_MASK) |
 579                        ((phy_ext->pclk_divider_c & 3) << 5);
 580                 rockchip_hdmiv2_write_phy(hdmi_dev,
 581                                           EXT_PHY_PCLK_DIVIDER2, stat);
 582                 stat = ((phy_ext->tmsd_divider_c & 3) << 4) |
 583                        ((phy_ext->tmsd_divider_a & 3) << 2) |
 584                        (phy_ext->tmsd_divider_b & 3);
 585                 rockchip_hdmiv2_write_phy(hdmi_dev,
 586                                           EXT_PHY_TMDSCLK_DIVIDER, stat);
 587                 rockchip_hdmiv2_write_phy(hdmi_dev,
 588                                           EXT_PHY_PPLL_FB_DIVIDER,
 589                                           phy_ext->ppll_nf);
 590
 591                 if (phy_ext->ppll_no == 1) {
 592                         rockchip_hdmiv2_write_phy(hdmi_dev,
 593                                                   EXT_PHY_PPLL_POST_DIVIDER,
 594                                                   0);
 595                         stat = 0x20 | phy_ext->ppll_nd;
 596                         rockchip_hdmiv2_write_phy(hdmi_dev,
 597                                                   EXT_PHY_PPLL_PRE_DIVIDER,
 598                                                   stat);
 599                 } else {
 600                         stat = ((phy_ext->ppll_no / 2) - 1) << 4;
 601                         rockchip_hdmiv2_write_phy(hdmi_dev,
 602                                                   EXT_PHY_PPLL_POST_DIVIDER,
 603                                                   stat);
 604                         stat = 0xe0 | phy_ext->ppll_nd;
 605                         rockchip_hdmiv2_write_phy(hdmi_dev,
 606                                                   EXT_PHY_PPLL_PRE_DIVIDER,
 607                                                   stat);
 608                 }
 609         } else {
 610                 pr_err("%s no supported phy configuration.\n", __func__);
 611                 return -1;
 612         }
 613
 614         if (hdmi_dev->phy_table) {
 615                 for (i = 0; i < hdmi_dev->phy_table_size; i++) {
 616                         temp = hdmi_dev->phy_table[i].maxfreq;
 617                         if (hdmi_dev->tmdsclk <= temp)
 618                                 break;
 619                 }
 620         }
 621
 622         if (i != hdmi_dev->phy_table_size && hdmi_dev->phy_table) {
 623                 if (hdmi_dev->phy_table[i].slopeboost) {
 624                         rockchip_hdmiv2_write_phy(hdmi_dev,
 625                                                   EXT_PHY_SIGNAL_CTRL, 0xff);
 626                         temp = hdmi_dev->phy_table[i].slopeboost - 1;
 627                         stat = ((temp & 3) << 6) | ((temp & 3) << 4) |
 628                                ((temp & 3) << 2) | (temp & 3);
 629                         rockchip_hdmiv2_write_phy(hdmi_dev,
 630                                                   EXT_PHY_SLOPEBOOST, stat);
 631                 } else {
 632                         rockchip_hdmiv2_write_phy(hdmi_dev,
 633                                                   EXT_PHY_SIGNAL_CTRL, 0x0f);
 634                 }
 635                 stat = ((hdmi_dev->phy_table[i].pre_emphasis & 3) << 4) |
 636                        ((hdmi_dev->phy_table[i].pre_emphasis & 3) << 2) |
 637                        (hdmi_dev->phy_table[i].pre_emphasis & 3);
 638                 rockchip_hdmiv2_write_phy(hdmi_dev,
 639                                           EXT_PHY_PREEMPHASIS, stat);
 640                 stat = ((hdmi_dev->phy_table[i].clk_level & 0xf) << 4) |
 641                        (hdmi_dev->phy_table[i].data2_level & 0xf);
 642                 rockchip_hdmiv2_write_phy(hdmi_dev,
 643                                           EXT_PHY_LEVEL1, stat);
 644                 stat = ((hdmi_dev->phy_table[i].data1_level & 0xf) << 4) |
 645                        (hdmi_dev->phy_table[i].data0_level & 0xf);
 646                 rockchip_hdmiv2_write_phy(hdmi_dev,
 647                                           EXT_PHY_LEVEL2, stat);
 648         } else {
 649                 rockchip_hdmiv2_write_phy(hdmi_dev,
 650                                           EXT_PHY_SIGNAL_CTRL, 0x0f);
 651         }
 652         rockchip_hdmiv2_write_phy(hdmi_dev, 0xf3, 0x22);
 653
 654         stat = clk_get_rate(hdmi_dev->pclk_phy) / 100000;
 655         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL,
 656                                   ((stat >> 8) & 0xff) | 0x80);
 657         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL_DIV_L,
 658                                   stat & 0xff);
 659         if (hdmi_dev->tmdsclk > 340000000)
 660                 stat = EXT_PHY_AUTO_R100_OHMS;
 661         else if (hdmi_dev->tmdsclk > 200000000)
 662                 stat = EXT_PHY_AUTO_R50_OHMS;
 663         else
 664                 stat = EXT_PHY_AUTO_ROPEN_CIRCUIT;
 665         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_RESIS_AUTO,
 666                                   stat | 0x20);
 667         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL,
 668                                   (stat >> 8) & 0xff);
 669         if (hdmi_dev->tmdsclk > 200000000)
 670                 stat = 0;
 671         else
 672                 stat = 0x11;
 673         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_PLL_BW, stat);
 674         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_PPLL_BW, 0x27);
 675         if (hdmi_dev->grf_base)
 676                 regmap_write(hdmi_dev->grf_base,
 677                              RK322X_GRF_SOC_CON2,
 678                              RK322X_PLL_POWER_UP);
 679         if (hdmi_dev->tmdsclk_ratio_change)
 680                 msleep(100);
 681         else
 682                 usleep_range(900, 1000);
 683         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 684                      m_TXPWRON_SIG, v_TXPWRON_SIG(1));
 685         i = 0;
 686         while (i++ < PHY_TIMEOUT) {
 687                 if ((i % 10) == 0) {
 688                         temp = EXT_PHY_PPLL_POST_DIVIDER;
 689                         stat = rockchip_hdmiv2_read_phy(hdmi_dev, temp);
 690                         if (stat & EXT_PHY_PPLL_LOCK_STATUS_MASK)
 691                                 break;
 692                         usleep_range(1000, 2000);
 693                 }
 694         }
 695         if ((stat & EXT_PHY_PPLL_LOCK_STATUS_MASK) == 0) {
 696                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 697                 dev_err(hdmi_dev->hdmi->dev,
 698                         "PHY PLL not locked: PCLK_ON=%ld,TMDSCLK_ON=%ld\n",
 699                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 700                 return -1;
 701         }
 702
 703         if (hdmi_dev->grf_base)
 704                 regmap_write(hdmi_dev->grf_base,
 705                              RK322X_GRF_SOC_CON2,
 706                              RK322X_PLL_PDATA_EN);
 707
 708         return 0;
 709 }
 710
 711 static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
 712 {
 713         int stat = 0, i = 0;
 714         const struct phy_mpll_config_tab *phy_mpll = NULL;
 715
 716         if (hdmi_dev->soctype == HDMI_SOC_RK322X) {
 717                 return ext_phy_config(hdmi_dev);
 718         } else if (hdmi_dev->soctype == HDMI_SOC_RK3366) {
 719                 if (hdmi_dev->pixelclk > 148500000)
 720                         clk_set_rate(hdmi_dev->pclk_phy, 148500000);
 721                 else
 722                         clk_set_rate(hdmi_dev->pclk_phy, hdmi_dev->pixelclk);
 723         } else if (hdmi_dev->soctype == HDMI_SOC_RK3399) {
 724                 clk_set_rate(hdmi_dev->pclk_phy, hdmi_dev->pixelclk);
 725         }
 726
 727         hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
 728                      m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
 729         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
 730         /* power off PHY */
 731         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 732                      m_PDDQ_SIG | m_TXPWRON_SIG | m_SVSRET_SIG,
 733                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) | v_SVSRET_SIG(1));
 734
 735         if (hdmi_dev->tmdsclk_ratio_change &&
 736             hdmi_dev->hdmi->edid.scdc_present == 1)
 737                 rockchip_hdmiv2_scdc_set_tmds_rate(hdmi_dev);
 738
 739         /* reset PHY */
 740         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
 741         usleep_range(1000, 2000);
 742         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
 743
 744         /* Set slave address as PHY GEN2 address */
 745         hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR);
 746
 747         /* config the required PHY I2C register */
 748         if (hdmi_dev->soctype == HDMI_SOC_RK3366 &&
 749             hdmi_dev->pixelclk > 148500000)
 750                 phy_mpll = get_phy_mpll_tab(148500000,
 751                                             hdmi_dev->tmdsclk,
 752                                             hdmi_dev->pixelrepeat - 1,
 753                                             hdmi_dev->colordepth);
 754         else
 755                 phy_mpll = get_phy_mpll_tab(hdmi_dev->pixelclk,
 756                                             hdmi_dev->tmdsclk,
 757                                             hdmi_dev->pixelrepeat - 1,
 758                                             hdmi_dev->colordepth);
 759         if (phy_mpll) {
 760                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_OPMODE_PLLCFG,
 761                                           v_PREP_DIV(phy_mpll->prep_div) |
 762                                           v_TMDS_CNTRL(
 763                                           phy_mpll->tmdsmhl_cntrl) |
 764                                           v_OPMODE(phy_mpll->opmode) |
 765                                           v_FBDIV2_CNTRL(
 766                                           phy_mpll->fbdiv2_cntrl) |
 767                                           v_FBDIV1_CNTRL(
 768                                           phy_mpll->fbdiv1_cntrl) |
 769                                           v_REF_CNTRL(phy_mpll->ref_cntrl) |
 770                                           v_MPLL_N_CNTRL(phy_mpll->n_cntrl));
 771                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLCURRCTRL,
 772                                           v_MPLL_PROP_CNTRL(
 773                                           phy_mpll->prop_cntrl) |
 774                                           v_MPLL_INT_CNTRL(
 775                                           phy_mpll->int_cntrl));
 776                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLGMPCTRL,
 777                                           v_MPLL_GMP_CNTRL(
 778                                           phy_mpll->gmp_cntrl));
 779         }
 780
 781         if (hdmi_dev->phy_table) {
 782                 for (i = 0; i < hdmi_dev->phy_table_size; i++)
 783                         if (hdmi_dev->tmdsclk <= hdmi_dev->phy_table[i].maxfreq)
 784                                 break;
 785         }
 786         if (i != hdmi_dev->phy_table_size && hdmi_dev->phy_table) {
 787                 stat = v_OVERRIDE(1) | v_TX_SYMON(1) | v_CLK_SYMON(1) |
 788                        v_PREEMPHASIS(hdmi_dev->phy_table[i].pre_emphasis) |
 789                        v_SLOPEBOOST(hdmi_dev->phy_table[i].slopeboost);
 790                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL, stat);
 791
 792                 stat = v_SUP_CLKLVL(hdmi_dev->phy_table[i].clk_level) |
 793                        v_SUP_TXLVL(hdmi_dev->phy_table[i].data0_level);
 794                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL, stat);
 795         } else {
 796                 pr_info("%s use default phy settings\n", __func__);
 797                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
 798                                           v_OVERRIDE(1) | v_SLOPEBOOST(0) |
 799                                           v_TX_SYMON(1) | v_CLK_SYMON(1) |
 800                                           v_PREEMPHASIS(0));
 801                 if (hdmi_dev->tmdsclk > 340000000)
 802                         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 803                                                   v_SUP_TXLVL(9) |
 804                                                   v_SUP_CLKLVL(17));
 805                 else if (hdmi_dev->tmdsclk > 165000000)
 806                         rockchip_hdmiv2_write_phy(hdmi_dev,
 807                                                   PHYTX_VLEVCTRL,
 808                                                   v_SUP_TXLVL(14) |
 809                                                   v_SUP_CLKLVL(17));
 810                 else
 811                         rockchip_hdmiv2_write_phy(hdmi_dev,
 812                                                   PHYTX_VLEVCTRL,
 813                                                   v_SUP_TXLVL(18) |
 814                                                   v_SUP_CLKLVL(17));
 815         }
 816
 817         if (hdmi_dev->tmdsclk > 340000000)
 818                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 819                                           v_TX_TERM(R50_OHMS));
 820         else
 821                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 822                                           v_TX_TERM(R100_OHMS));
 823         /* rockchip_hdmiv2_write_phy(hdmi_dev, 0x05, 0x8000); */
 824         if (hdmi_dev->tmdsclk_ratio_change)
 825                 msleep(100);
 826         /* power on PHY */
 827         hdmi_writel(hdmi_dev, PHY_CONF0, 0x2e);
 828
 829         /* check if the PHY PLL is locked */
 830
 831         i = 0;
 832         while (i++ < PHY_TIMEOUT) {
 833                 if ((i % 10) == 0) {
 834                         stat = hdmi_readl(hdmi_dev, PHY_STAT0);
 835                         if (stat & m_PHY_LOCK)
 836                                 break;
 837                         usleep_range(1000, 2000);
 838                 }
 839         }
 840         if ((stat & m_PHY_LOCK) == 0) {
 841                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 842                 dev_err(hdmi_dev->hdmi->dev,
 843                         "PHY PLL not locked: PCLK_ON=%ld,TMDSCLK_ON=%ld\n",
 844                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 845                 return -1;
 846         }
 847         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
 848         return 0;
 849 }
 850
 851 static int rockchip_hdmiv2_video_framecomposer(struct hdmi *hdmi_drv,
 852                                                struct hdmi_video *vpara)
 853 {
 854         struct hdmi_dev *hdmi_dev = hdmi_drv->property->priv;
 855         int value, vsync_pol, hsync_pol, de_pol;
 856         struct hdmi_video_timing *timing = NULL;
 857         struct fb_videomode *mode = NULL;
 858         u32 sink_version, tmdsclk;
 859
 860         vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
 861         hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
 862         de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
 863
 864         hdmi_msk_reg(hdmi_dev, A_VIDPOLCFG,
 865                      m_DATAEN_POL | m_VSYNC_POL | m_HSYNC_POL,
 866                      v_DATAEN_POL(de_pol) |
 867                      v_VSYNC_POL(vsync_pol) |
 868                      v_HSYNC_POL(hsync_pol));
 869
 870         timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
 871         if (!timing) {
 872                 dev_err(hdmi_drv->dev,
 873                         "[%s] not found vic %d\n", __func__, vpara->vic);
 874                 return -ENOENT;
 875         }
 876         mode = &timing->mode;
 877         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 878                 tmdsclk = mode->pixclock / 2;
 879         else if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 880                 tmdsclk = 2 * mode->pixclock;
 881         else
 882                 tmdsclk = mode->pixclock;
 883         if (vpara->color_output != HDMI_COLOR_YCBCR422) {
 884                 switch (vpara->color_output_depth) {
 885                 case 10:
 886                         tmdsclk += tmdsclk / 4;
 887                         break;
 888                 case 12:
 889                         tmdsclk += tmdsclk / 2;
 890                         break;
 891                 case 16:
 892                         tmdsclk += tmdsclk;
 893                         break;
 894                 case 8:
 895                 default:
 896                         break;
 897                 }
 898         } else if (vpara->color_output_depth > 12) {
 899                 /* YCbCr422 mode only support up to 12bit */
 900                 vpara->color_output_depth = 12;
 901         }
 902         if ((tmdsclk > 594000000) ||
 903             (tmdsclk > 340000000 &&
 904              tmdsclk > hdmi_drv->edid.maxtmdsclock)) {
 905                 if (vpara->format_3d == HDMI_3D_FRAME_PACKING) {
 906                         pr_err("3d frame packing mode out of max tmdsclk\n");
 907                         return -1;
 908                 } else if (vpara->color_output == HDMI_COLOR_YCBCR444 &&
 909                            hdmi_drv->edid.ycbcr422) {
 910                         pr_warn("out of max tmdsclk, down to YCbCr422");
 911                         vpara->color_output = HDMI_COLOR_YCBCR422;
 912                         tmdsclk = mode->pixclock;
 913                 } else {
 914                         pr_warn("out of max tmds clock, limit to 8bit\n");
 915                         vpara->color_output_depth = 8;
 916                         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 917                                 tmdsclk = mode->pixclock / 2;
 918                         else
 919                                 tmdsclk = mode->pixclock;
 920                 }
 921         }
 922
 923         if ((tmdsclk > 340000000) ||
 924             (tmdsclk < 340000000 && hdmi_dev->tmdsclk > 340000000))
 925                 hdmi_dev->tmdsclk_ratio_change = true;
 926         else
 927                 hdmi_dev->tmdsclk_ratio_change = false;
 928
 929         hdmi_dev->tmdsclk = tmdsclk;
 930         if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 931                 hdmi_dev->pixelclk = 2 * mode->pixclock;
 932         else
 933                 hdmi_dev->pixelclk = mode->pixclock;
 934         hdmi_dev->pixelrepeat = timing->pixelrepeat;
 935         /* hdmi_dev->colordepth is used for find pll config.
 936          * For YCbCr422, tmdsclk is same on all color depth.
 937          */
 938         if (vpara->color_output == HDMI_COLOR_YCBCR422)
 939                 hdmi_dev->colordepth = 8;
 940         else
 941                 hdmi_dev->colordepth = vpara->color_output_depth;
 942         pr_info("pixel clk is %lu tmds clk is %u\n",
 943                 hdmi_dev->pixelclk, hdmi_dev->tmdsclk);
 944         /* Start/stop HDCP keepout window generation */
 945         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 946                      m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
 947         if (hdmi_drv->edid.scdc_present == 1 && !hdmi_drv->uboot) {
 948                 if (tmdsclk > 340000000 ||
 949                     hdmi_drv->edid.lte_340mcsc_scramble) {
 950                         /* used for HDMI 2.0 TX */
 951                         mutex_lock(&hdmi_dev->ddc_lock);
 952                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 953                         sink_version =
 954                         rockchip_hdmiv2_scdc_get_sink_version(hdmi_dev);
 955                         pr_info("sink scdc version is %d\n", sink_version);
 956                         sink_version = hdmi_drv->edid.hf_vsdb_version;
 957                         rockchip_hdmiv2_scdc_set_source_version(hdmi_dev,
 958                                                                 sink_version);
 959                         if (hdmi_drv->edid.rr_capable == 1)
 960                                 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 961                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 1);
 962                         mutex_unlock(&hdmi_dev->ddc_lock);
 963                 } else {
 964                         mutex_lock(&hdmi_dev->ddc_lock);
 965                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 966                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 0);
 967                         mutex_unlock(&hdmi_dev->ddc_lock);
 968                 }
 969         } else {
 970                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 971                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 972         }
 973
 974         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 975                      m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL |
 976                      m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
 977                      v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) |
 978                      v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->sink_hdmi) |
 979                      v_FC_INTERLACE_MODE(mode->vmode));
 980         if ((mode->vmode & FB_VMODE_INTERLACED) &&
 981             vpara->format_3d != HDMI_3D_FRAME_PACKING)
 982                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 983                              m_FC_VBLANK, v_FC_VBLANK(1));
 984         else
 985                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 986                              m_FC_VBLANK, v_FC_VBLANK(0));
 987
 988         value = mode->xres;
 989         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 990                 value = value / 2;
 991         hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(value >> 8));
 992         hdmi_writel(hdmi_dev, FC_INHACTIV0, (value & 0xff));
 993
 994         if (vpara->format_3d == HDMI_3D_FRAME_PACKING) {
 995                 if (mode->vmode == 0)
 996                         value = 2 * mode->yres +
 997                                 mode->upper_margin +
 998                                 mode->lower_margin +
 999                                 mode->vsync_len;
1000                 else
1001                         value = 2 * mode->yres +
1002                                 3 * (mode->upper_margin +
1003                                      mode->lower_margin +
1004                                      mode->vsync_len) + 2;
1005         } else {
1006                 value = mode->yres;
1007         }
1008         hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(value >> 8));
1009         hdmi_writel(hdmi_dev, FC_INVACTIV0, (value & 0xff));
1010
1011         value = mode->hsync_len + mode->left_margin + mode->right_margin;
1012         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1013                 value = value / 2;
1014         hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(value >> 8));
1015         hdmi_writel(hdmi_dev, FC_INHBLANK0, (value & 0xff));
1016
1017         value = mode->vsync_len + mode->upper_margin + mode->lower_margin;
1018         hdmi_writel(hdmi_dev, FC_INVBLANK, (value & 0xff));
1019
1020         value = mode->right_margin;
1021         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1022                 value = value / 2;
1023         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(value >> 8));
1024         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (value & 0xff));
1025
1026         value = mode->lower_margin;
1027         hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (value & 0xff));
1028
1029         value = mode->hsync_len;
1030         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1031                 value = value / 2;
1032         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(value >> 8));
1033         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (value & 0xff));
1034
1035         value = mode->vsync_len;
1036         hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (value & 0xff));
1037
1038         /* Set the control period minimum duration (min. of 12 pixel
1039          * clock cycles, refer to HDMI 1.4b specification)
1040          */
1041         hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
1042         hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
1043
1044         /* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
1045          * worst case: tmdsClock == 25MHz => config <= 19
1046          */
1047         hdmi_writel(hdmi_dev, FC_EXCTRLSPAC,
1048                     (hdmi_dev->tmdsclk / 1000) * 50 / (256 * 512));
1049
1050         hdmi_writel(hdmi_dev, FC_PRCONF,
1051                     v_FC_PR_FACTOR(timing->pixelrepeat) |
1052                     v_FC_PR_FACTOR_OUT(timing->pixelrepeat - 1));
1053
1054         return 0;
1055 }
1056
1057 static int rockchip_hdmiv2_video_packetizer(struct hdmi_dev *hdmi_dev,
1058                                             struct hdmi_video *vpara)
1059 {
1060         unsigned char color_depth = COLOR_DEPTH_24BIT_DEFAULT;
1061         unsigned char output_select = 0;
1062         unsigned char remap_size = 0;
1063
1064         if (vpara->color_output == HDMI_COLOR_YCBCR422) {
1065                 switch (vpara->color_output_depth) {
1066                 case 8:
1067                         remap_size = YCC422_16BIT;
1068                         break;
1069                 case 10:
1070                         remap_size = YCC422_20BIT;
1071                         break;
1072                 case 12:
1073                         remap_size = YCC422_24BIT;
1074                         break;
1075                 default:
1076                         remap_size = YCC422_16BIT;
1077                         break;
1078                 }
1079
1080                 output_select = OUT_FROM_YCC422_REMAP;
1081                 /*Config remap size for the different color Depth*/
1082                 hdmi_msk_reg(hdmi_dev, VP_REMAP,
1083                              m_YCC422_SIZE, v_YCC422_SIZE(remap_size));
1084         } else {
1085                 switch (vpara->color_output_depth) {
1086                 case 10:
1087                         color_depth = COLOR_DEPTH_30BIT;
1088                         output_select = OUT_FROM_PIXEL_PACKING;
1089                         break;
1090                 case 12:
1091                         color_depth = COLOR_DEPTH_36BIT;
1092                         output_select = OUT_FROM_PIXEL_PACKING;
1093                         break;
1094                 case 16:
1095                         color_depth = COLOR_DEPTH_48BIT;
1096                         output_select = OUT_FROM_PIXEL_PACKING;
1097                         break;
1098                 case 8:
1099                 default:
1100                         color_depth = COLOR_DEPTH_24BIT_DEFAULT;
1101                         output_select = OUT_FROM_8BIT_BYPASS;
1102                         break;
1103                 }
1104         }
1105         /*Config Color Depth*/
1106         hdmi_msk_reg(hdmi_dev, VP_PR_CD,
1107                      m_COLOR_DEPTH, v_COLOR_DEPTH(color_depth));
1108         /*Config pixel repettion*/
1109         hdmi_msk_reg(hdmi_dev, VP_PR_CD, m_DESIRED_PR_FACTOR,
1110                      v_DESIRED_PR_FACTOR(hdmi_dev->pixelrepeat - 1));
1111         if (hdmi_dev->pixelrepeat > 1)
1112                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1113                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
1114                              v_PIXEL_REPET_EN(1) | v_BYPASS_SEL(0));
1115         else
1116                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1117                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
1118                              v_PIXEL_REPET_EN(0) | v_BYPASS_SEL(1));
1119
1120         /*config output select*/
1121         if (output_select == OUT_FROM_PIXEL_PACKING) { /* pixel packing */
1122                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1123                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1124                              m_YCC422_EN | m_OUTPUT_SEL,
1125                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(1) |
1126                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
1127         } else if (output_select == OUT_FROM_YCC422_REMAP) { /* YCC422 */
1128                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1129                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1130                              m_YCC422_EN | m_OUTPUT_SEL,
1131                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(0) |
1132                              v_YCC422_EN(1) | v_OUTPUT_SEL(output_select));
1133         } else if (output_select == OUT_FROM_8BIT_BYPASS ||
1134                    output_select == 3) { /* bypass */
1135                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1136                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1137                              m_YCC422_EN | m_OUTPUT_SEL,
1138                              v_BYPASS_EN(1) | v_PIXEL_PACK_EN(0) |
1139                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
1140         }
1141
1142 #if defined(HDMI_VIDEO_STUFFING)
1143         /* YCC422 and pixel packing stuffing*/
1144         hdmi_msk_reg(hdmi_dev, VP_STUFF, m_PR_STUFFING, v_PR_STUFFING(1));
1145         hdmi_msk_reg(hdmi_dev, VP_STUFF,
1146                      m_YCC422_STUFFING | m_PP_STUFFING,
1147                      v_YCC422_STUFFING(1) | v_PP_STUFFING(1));
1148 #endif
1149         return 0;
1150 }
1151
1152 static int rockchip_hdmiv2_video_sampler(struct hdmi_dev *hdmi_dev,
1153                                          struct hdmi_video *vpara)
1154 {
1155         int map_code = 0;
1156
1157         if (vpara->color_input == HDMI_COLOR_YCBCR422) {
1158                 /* YCC422 mapping is discontinued - only map 1 is supported */
1159                 switch (vpara->color_output_depth) {
1160                 case 8:
1161                         map_code = VIDEO_YCBCR422_8BIT;
1162                         break;
1163                 case 10:
1164                         map_code = VIDEO_YCBCR422_10BIT;
1165                         break;
1166                 case 12:
1167                         map_code = VIDEO_YCBCR422_12BIT;
1168                         break;
1169                 default:
1170                         map_code = VIDEO_YCBCR422_8BIT;
1171                         break;
1172                 }
1173         } else if (vpara->color_input == HDMI_COLOR_YCBCR420 ||
1174                    vpara->color_input == HDMI_COLOR_YCBCR444) {
1175                 switch (vpara->color_output_depth) {
1176                 case 10:
1177                         map_code = VIDEO_YCBCR444_10BIT;
1178                         break;
1179                 case 12:
1180                         map_code = VIDEO_YCBCR444_12BIT;
1181                         break;
1182                 case 16:
1183                         map_code = VIDEO_YCBCR444_16BIT;
1184                         break;
1185                 case 8:
1186                 default:
1187                         map_code = VIDEO_YCBCR444_8BIT;
1188                         break;
1189                 }
1190         } else {
1191                 switch (vpara->color_output_depth) {
1192                 case 10:
1193                         map_code = VIDEO_RGB444_10BIT;
1194                         break;
1195                 case 12:
1196                         map_code = VIDEO_RGB444_12BIT;
1197                         break;
1198                 case 16:
1199                         map_code = VIDEO_RGB444_16BIT;
1200                         break;
1201                 case 8:
1202                 default:
1203                         map_code = VIDEO_RGB444_8BIT;
1204                         break;
1205                 }
1206         }
1207
1208         /* Set Data enable signal from external
1209          * and set video sample input mapping
1210          */
1211         hdmi_msk_reg(hdmi_dev, TX_INVID0,
1212                      m_INTERNAL_DE_GEN | m_VIDEO_MAPPING,
1213                      v_INTERNAL_DE_GEN(0) | v_VIDEO_MAPPING(map_code));
1214
1215 #if defined(HDMI_VIDEO_STUFFING)
1216         hdmi_writel(hdmi_dev, TX_GYDATA0, 0x00);
1217         hdmi_writel(hdmi_dev, TX_GYDATA1, 0x00);
1218         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1219                      m_GYDATA_STUFF, v_GYDATA_STUFF(1));
1220         hdmi_writel(hdmi_dev, TX_RCRDATA0, 0x00);
1221         hdmi_writel(hdmi_dev, TX_RCRDATA1, 0x00);
1222         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1223                      m_RCRDATA_STUFF, v_RCRDATA_STUFF(1));
1224         hdmi_writel(hdmi_dev, TX_BCBDATA0, 0x00);
1225         hdmi_writel(hdmi_dev, TX_BCBDATA1, 0x00);
1226         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1227                      m_BCBDATA_STUFF, v_BCBDATA_STUFF(1));
1228 #endif
1229         return 0;
1230 }
1231
1232 static const char coeff_csc[][24] = {
1233                 /*   G          R           B           Bias
1234                  *   A1    |    A2     |    A3     |    A4    |
1235                  *   B1    |    B2     |    B3     |    B4    |
1236                  *   C1    |    C2     |    C3     |    C4    |
1237                  */
1238         {       /* CSC_BYPASS */
1239                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1240                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1241                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1242         },
1243         {       /* CSC_RGB_0_255_TO_RGB_16_235_8BIT */
1244                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,         /*G*/
1245                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x00, 0x40,         /*R*/
1246                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x00, 0x40,         /*B*/
1247         },
1248         {       /* CSC_RGB_0_255_TO_RGB_16_235_10BIT */
1249                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,         /*G*/
1250                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x01, 0x00,         /*R*/
1251                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x01, 0x00,         /*B*/
1252         },
1253         {       /* CSC_RGB_0_255_TO_ITU601_16_235_8BIT */
1254                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x00, 0x40,         /*Y*/
1255                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x02, 0x00,         /*Cr*/
1256                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
1257         },
1258         {       /* CSC_RGB_0_255_TO_ITU601_16_235_10BIT */
1259                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x01, 0x00,         /*Y*/
1260                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x08, 0x00,         /*Cr*/
1261                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
1262         },
1263         {       /* CSC_RGB_0_255_TO_ITU709_16_235_8BIT */
1264                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x00, 0x40,         /*Y*/
1265                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x02, 0x00,         /*Cr*/
1266                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
1267         },
1268         {       /* CSC_RGB_0_255_TO_ITU709_16_235_10BIT */
1269                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x01, 0x00,         /*Y*/
1270                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x08, 0x00,         /*Cr*/
1271                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
1272         },
1273                 /* Y            Cr          Cb          Bias */
1274         {       /* CSC_ITU601_16_235_TO_RGB_0_255_8BIT */
1275                 0x20, 0x00, 0x69, 0x26, 0x74, 0xfd, 0x01, 0x0e,         /*G*/
1276                 0x20, 0x00, 0x2c, 0xdd, 0x00, 0x00, 0x7e, 0x9a,         /*R*/
1277                 0x20, 0x00, 0x00, 0x00, 0x38, 0xb4, 0x7e, 0x3b,         /*B*/
1278         },
1279         {       /* CSC_ITU709_16_235_TO_RGB_0_255_8BIT */
1280                 0x20, 0x00, 0x71, 0x06, 0x7a, 0x02, 0x00, 0xa7,         /*G*/
1281                 0x20, 0x00, 0x32, 0x64, 0x00, 0x00, 0x7e, 0x6d,         /*R*/
1282                 0x20, 0x00, 0x00, 0x00, 0x3b, 0x61, 0x7e, 0x25,         /*B*/
1283         },
1284 };
1285
1286 static int rockchip_hdmiv2_video_csc(struct hdmi_dev *hdmi_dev,
1287                                      struct hdmi_video *vpara)
1288 {
1289         int i, mode, interpolation, decimation, csc_scale = 0;
1290         const char *coeff = NULL;
1291         unsigned char color_depth = 0;
1292
1293         if (vpara->color_input == vpara->color_output) {
1294                 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1295                              m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
1296                 return 0;
1297         }
1298
1299         if (vpara->color_input == HDMI_COLOR_YCBCR422 &&
1300             vpara->color_output != HDMI_COLOR_YCBCR422 &&
1301             vpara->color_output != HDMI_COLOR_YCBCR420) {
1302                 interpolation = 1;
1303                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
1304                              m_CSC_INTPMODE, v_CSC_INTPMODE(interpolation));
1305         }
1306
1307         if ((vpara->color_input == HDMI_COLOR_RGB_0_255 ||
1308              vpara->color_input == HDMI_COLOR_YCBCR444) &&
1309              vpara->color_output == HDMI_COLOR_YCBCR422) {
1310                 decimation = 1;
1311                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
1312                              m_CSC_DECIMODE, v_CSC_DECIMODE(decimation));
1313         }
1314
1315         mode = CSC_BYPASS;
1316         csc_scale = 0;
1317
1318         switch (vpara->vic) {
1319         case HDMI_720X480I_60HZ_4_3:
1320         case HDMI_720X576I_50HZ_4_3:
1321         case HDMI_720X480P_60HZ_4_3:
1322         case HDMI_720X576P_50HZ_4_3:
1323         case HDMI_720X480I_60HZ_16_9:
1324         case HDMI_720X576I_50HZ_16_9:
1325         case HDMI_720X480P_60HZ_16_9:
1326         case HDMI_720X576P_50HZ_16_9:
1327                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
1328                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
1329                         mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
1330                         csc_scale = 0;
1331                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
1332                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
1333                         mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
1334                         csc_scale = 1;
1335                 }
1336                 break;
1337         default:
1338                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
1339                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
1340                         mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
1341                         csc_scale = 0;
1342                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
1343                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
1344                         mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
1345                         csc_scale = 1;
1346                 }
1347                 break;
1348         }
1349
1350         if ((vpara->color_input == HDMI_COLOR_RGB_0_255) &&
1351             (vpara->color_output == HDMI_COLOR_RGB_16_235)) {
1352                 mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
1353                 csc_scale = 0;
1354         }
1355         if (mode != CSC_BYPASS) {
1356                 switch (vpara->color_output_depth) {
1357                 case 10:
1358                         color_depth = COLOR_DEPTH_30BIT;
1359                         mode += 1;
1360                         break;
1361                 case 12:
1362                         color_depth = COLOR_DEPTH_36BIT;
1363                         mode += 2;
1364                         break;
1365                 case 16:
1366                         color_depth = COLOR_DEPTH_48BIT;
1367                         mode += 3;
1368                         break;
1369                 case 8:
1370                 default:
1371                         color_depth = COLOR_DEPTH_24BIT;
1372                         break;
1373                 }
1374         }
1375         coeff = coeff_csc[mode];
1376         for (i = 0; i < 24; i++)
1377                 hdmi_writel(hdmi_dev, CSC_COEF_A1_MSB + i, coeff[i]);
1378
1379         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1380                      m_CSC_SCALE, v_CSC_SCALE(csc_scale));
1381         /*config CSC_COLOR_DEPTH*/
1382         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1383                      m_CSC_COLOR_DEPTH, v_CSC_COLOR_DEPTH(color_depth));
1384
1385         /* enable CSC */
1386         if (mode == CSC_BYPASS)
1387                 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1388                              m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
1389         else
1390                 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1391                              m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(1));
1392         return 0;
1393 }
1394
1395 static int hdmi_dev_detect_hotplug(struct hdmi *hdmi)
1396 {
1397         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1398         u32 value;
1399
1400         value = hdmi_readl(hdmi_dev, PHY_STAT0);
1401         HDMIDBG(2, "[%s] reg%x value %02x\n", __func__, PHY_STAT0, value);
1402         if (value & m_PHY_HPD)
1403                 return HDMI_HPD_ACTIVATED;
1404
1405         return HDMI_HPD_REMOVED;
1406 }
1407
1408 static int hdmi_dev_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
1409 {
1410         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1411         int i = 0, n = 0, index = 0, ret = -1, trytime = 5;
1412         int offset = (block % 2) * 0x80;
1413         int interrupt = 0;
1414
1415         HDMIDBG(2, "[%s] block %d\n", __func__, block);
1416
1417         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
1418
1419         /* Set DDC I2C CLK which divided from DDC_CLK to 100KHz. */
1420         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
1421
1422         /* Enable I2C interrupt for reading edid */
1423         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);
1424
1425         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_EDID_ADDR);
1426         hdmi_writel(hdmi_dev, I2CM_SEGADDR, DDC_I2C_SEG_ADDR);
1427         hdmi_writel(hdmi_dev, I2CM_SEGPTR, block / 2);
1428         for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
1429                 for (trytime = 0; trytime < 5; trytime++) {
1430                         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset + 8 * n);
1431                         /* enable extend sequential read operation */
1432                         if (block == 0)
1433                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1434                                              m_I2CM_RD8, v_I2CM_RD8(1));
1435                         else
1436                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1437                                              m_I2CM_RD8_EXT,
1438                                              v_I2CM_RD8_EXT(1));
1439
1440                         i = 20;
1441                         while (i--) {
1442                                 usleep_range(900, 1000);
1443                                 interrupt = hdmi_readl(hdmi_dev,
1444                                                        IH_I2CM_STAT0);
1445                                 if (interrupt)
1446                                         hdmi_writel(hdmi_dev,
1447                                                     IH_I2CM_STAT0, interrupt);
1448
1449                                 if (interrupt &
1450                                     (m_SCDC_READREQ | m_I2CM_DONE |
1451                                      m_I2CM_ERROR))
1452                                         break;
1453                         }
1454
1455                         if (interrupt & m_I2CM_DONE) {
1456                                 for (index = 0; index < 8; index++)
1457                                         buff[8 * n + index] =
1458                                                 hdmi_readl(hdmi_dev,
1459                                                            I2CM_READ_BUFF0 +
1460                                                            index);
1461
1462                                 if (n == HDMI_EDID_BLOCK_SIZE / 8 - 1) {
1463                                         ret = 0;
1464                                         goto exit;
1465                                 }
1466                                 break;
1467                         } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
1468                                 dev_err(hdmi->dev,
1469                                         "[%s] edid read %d error\n",
1470                                         __func__, offset + 8 * n);
1471                         }
1472                 }
1473                 if (trytime == 5) {
1474                         dev_err(hdmi->dev,
1475                                 "[%s] edid read error\n", __func__);
1476                         break;
1477                 }
1478         }
1479
1480 exit:
1481         /* Disable I2C interrupt */
1482         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
1483         return ret;
1484 }
1485
1486 static void hdmi_dev_config_avi(struct hdmi *hdmi,
1487                                 struct hdmi_video *vpara)
1488 {
1489         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1490         unsigned char colorimetry, ext_colorimetry = 0, aspect_ratio, y1y0;
1491         unsigned char rgb_quan_range = AVI_QUANTIZATION_RANGE_DEFAULT;
1492
1493         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(0));
1494         hdmi_msk_reg(hdmi_dev, IH_FC_STAT1,
1495                      m_AVI_INFOFRAME, v_AVI_INFOFRAME(1));
1496         /* Set AVI infoFrame Data byte1 */
1497         if (vpara->color_output == HDMI_COLOR_YCBCR444)
1498                 y1y0 = AVI_COLOR_MODE_YCBCR444;
1499         else if (vpara->color_output == HDMI_COLOR_YCBCR422)
1500                 y1y0 = AVI_COLOR_MODE_YCBCR422;
1501         else if (vpara->color_output == HDMI_COLOR_YCBCR420)
1502                 y1y0 = AVI_COLOR_MODE_YCBCR420;
1503         else
1504                 y1y0 = AVI_COLOR_MODE_RGB;
1505
1506         hdmi_msk_reg(hdmi_dev, FC_AVICONF0,
1507                      m_FC_ACTIV_FORMAT | m_FC_RGC_YCC,
1508                      v_FC_RGC_YCC(y1y0) | v_FC_ACTIV_FORMAT(1));
1509
1510         /* Set AVI infoFrame Data byte2 */
1511         switch (vpara->vic) {
1512         case HDMI_720X480I_60HZ_4_3:
1513         case HDMI_720X576I_50HZ_4_3:
1514         case HDMI_720X480P_60HZ_4_3:
1515         case HDMI_720X576P_50HZ_4_3:
1516                 aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3;
1517                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1518                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1519                 break;
1520         case HDMI_720X480I_60HZ_16_9:
1521         case HDMI_720X576I_50HZ_16_9:
1522         case HDMI_720X480P_60HZ_16_9:
1523         case HDMI_720X576P_50HZ_16_9:
1524                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1525                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1526                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1527                 break;
1528         default:
1529                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1530                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1531                         colorimetry = AVI_COLORIMETRY_ITU709;
1532         }
1533
1534         if (vpara->colorimetry > HDMI_COLORIMETRY_ITU709) {
1535                 colorimetry = AVI_COLORIMETRY_EXTENDED;
1536                 ext_colorimetry = vpara->colorimetry -
1537                                 HDMI_COLORIMETRY_EXTEND_XVYCC_601;
1538         } else if (vpara->color_output == HDMI_COLOR_RGB_16_235 ||
1539                  vpara->color_output == HDMI_COLOR_RGB_0_255) {
1540                 colorimetry = AVI_COLORIMETRY_NO_DATA;
1541         } else if (vpara->colorimetry != HDMI_COLORIMETRY_NO_DATA) {
1542                 colorimetry = vpara->colorimetry;
1543         }
1544
1545         hdmi_writel(hdmi_dev, FC_AVICONF1,
1546                     v_FC_COLORIMETRY(colorimetry) |
1547                     v_FC_PIC_ASPEC_RATIO(aspect_ratio) |
1548                     v_FC_ACT_ASPEC_RATIO(ACTIVE_ASPECT_RATE_DEFAULT));
1549
1550         /* Set AVI infoFrame Data byte3 */
1551         hdmi_msk_reg(hdmi_dev, FC_AVICONF2,
1552                      m_FC_EXT_COLORIMETRY | m_FC_QUAN_RANGE,
1553                      v_FC_EXT_COLORIMETRY(ext_colorimetry) |
1554                      v_FC_QUAN_RANGE(rgb_quan_range));
1555
1556         /* Set AVI infoFrame Data byte4 */
1557         if ((vpara->vic > 92 && vpara->vic < 96) ||
1558             (vpara->vic == 98) ||
1559             (vpara->vic & HDMI_VIDEO_DMT) ||
1560             (vpara->vic & HDMI_VIDEO_DISCRETE_VR))
1561                 hdmi_writel(hdmi_dev, FC_AVIVID, 0);
1562         else
1563                 hdmi_writel(hdmi_dev, FC_AVIVID, vpara->vic & 0xff);
1564         /* Set AVI infoFrame Data byte5 */
1565         hdmi_msk_reg(hdmi_dev, FC_AVICONF3, m_FC_YQ | m_FC_CN,
1566                      v_FC_YQ(YQ_LIMITED_RANGE) | v_FC_CN(CN_GRAPHICS));
1567         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(1));
1568 }
1569
1570 static int hdmi_dev_config_vsi(struct hdmi *hdmi,
1571                                unsigned char vic_3d, unsigned char format)
1572 {
1573         int i = 0, id = 0x000c03;
1574         unsigned char data[3] = {0};
1575
1576         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1577
1578         HDMIDBG(2, "[%s] vic %d format %d.\n", __func__, vic_3d, format);
1579
1580         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(0));
1581         hdmi_writel(hdmi_dev, FC_VSDIEEEID2, id & 0xff);
1582         hdmi_writel(hdmi_dev, FC_VSDIEEEID1, (id >> 8) & 0xff);
1583         hdmi_writel(hdmi_dev, FC_VSDIEEEID0, (id >> 16) & 0xff);
1584
1585         data[0] = format << 5;  /* PB4 --HDMI_Video_Format */
1586         switch (format) {
1587         case HDMI_VIDEO_FORMAT_4KX2K:
1588                 data[1] = vic_3d;       /* PB5--HDMI_VIC */
1589                 data[2] = 0;
1590                 break;
1591         case HDMI_VIDEO_FORMAT_3D:
1592                 data[1] = vic_3d << 4;  /* PB5--3D_Structure field */
1593                 data[2] = 0;            /* PB6--3D_Ext_Data field */
1594                 break;
1595         default:
1596                 data[1] = 0;
1597                 data[2] = 0;
1598                 break;
1599         }
1600
1601         for (i = 0; i < 3; i++)
1602                 hdmi_writel(hdmi_dev, FC_VSDPAYLOAD0 + i, data[i]);
1603         hdmi_writel(hdmi_dev, FC_VSDSIZE, 0x6);
1604
1605         hdmi_writel(hdmi_dev, FC_DATAUTO1, 0);
1606         hdmi_writel(hdmi_dev, FC_DATAUTO2, 0x11);
1607         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(1));
1608         return 0;
1609 }
1610
1611 #define HDR_LSB(n) ((n) & 0xff)
1612 #define HDR_MSB(n) (((n) & 0xff00) >> 8)
1613
1614 static void hdmi_dev_config_hdr(struct hdmi *hdmi,
1615                                 int eotf,
1616                                 struct hdmi_hdr_metadata *hdr)
1617 {
1618         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1619
1620         /* hdr is supportted after disignid = 0x21 */
1621         if (!hdmi_dev || hdmi_readl(hdmi_dev, DESIGN_ID) < 0x21)
1622                 return;
1623
1624         hdmi_writel(hdmi_dev, FC_DRM_HB, 1);/*verion = 0x1*/
1625         hdmi_writel(hdmi_dev, (FC_DRM_HB + 1), 26);/*length of following data*/
1626         hdmi_writel(hdmi_dev, FC_DRM_PB, eotf / 2);
1627         hdmi_writel(hdmi_dev, FC_DRM_PB + 1, 0);
1628
1629         if (hdr) {
1630                 hdmi_writel(hdmi_dev, FC_DRM_PB + 2, HDR_LSB(hdr->prim_x0));
1631                 hdmi_writel(hdmi_dev, FC_DRM_PB + 3, HDR_MSB(hdr->prim_x0));
1632                 hdmi_writel(hdmi_dev, FC_DRM_PB + 4, HDR_LSB(hdr->prim_y0));
1633                 hdmi_writel(hdmi_dev, FC_DRM_PB + 5, HDR_MSB(hdr->prim_y0));
1634                 hdmi_writel(hdmi_dev, FC_DRM_PB + 6, HDR_LSB(hdr->prim_x1));
1635                 hdmi_writel(hdmi_dev, FC_DRM_PB + 7, HDR_MSB(hdr->prim_x1));
1636                 hdmi_writel(hdmi_dev, FC_DRM_PB + 8, HDR_LSB(hdr->prim_y1));
1637                 hdmi_writel(hdmi_dev, FC_DRM_PB + 9, HDR_MSB(hdr->prim_y1));
1638                 hdmi_writel(hdmi_dev, FC_DRM_PB + 10, HDR_LSB(hdr->prim_x2));
1639                 hdmi_writel(hdmi_dev, FC_DRM_PB + 11, HDR_MSB(hdr->prim_x2));
1640                 hdmi_writel(hdmi_dev, FC_DRM_PB + 12, HDR_LSB(hdr->prim_y2));
1641                 hdmi_writel(hdmi_dev, FC_DRM_PB + 13, HDR_MSB(hdr->prim_y2));
1642                 hdmi_writel(hdmi_dev, FC_DRM_PB + 14, HDR_LSB(hdr->white_px));
1643                 hdmi_writel(hdmi_dev, FC_DRM_PB + 15, HDR_MSB(hdr->white_px));
1644                 hdmi_writel(hdmi_dev, FC_DRM_PB + 16, HDR_LSB(hdr->white_py));
1645                 hdmi_writel(hdmi_dev, FC_DRM_PB + 17, HDR_MSB(hdr->white_py));
1646                 hdmi_writel(hdmi_dev, FC_DRM_PB + 18, HDR_LSB(hdr->max_dml));
1647                 hdmi_writel(hdmi_dev, FC_DRM_PB + 19, HDR_MSB(hdr->max_dml));
1648                 hdmi_writel(hdmi_dev, FC_DRM_PB + 20, HDR_LSB(hdr->min_dml));
1649                 hdmi_writel(hdmi_dev, FC_DRM_PB + 21, HDR_MSB(hdr->min_dml));
1650                 hdmi_writel(hdmi_dev, FC_DRM_PB + 22, HDR_LSB(hdr->max_cll));
1651                 hdmi_writel(hdmi_dev, FC_DRM_PB + 23, HDR_MSB(hdr->max_cll));
1652                 hdmi_writel(hdmi_dev, FC_DRM_PB + 24, HDR_LSB(hdr->max_fall));
1653                 hdmi_writel(hdmi_dev, FC_DRM_PB + 25, HDR_MSB(hdr->max_fall));
1654         } else {
1655                 hdmi_writel(hdmi_dev, FC_DRM_PB + 1, 0);
1656                 hdmi_writel(hdmi_dev, FC_DRM_PB + 2, 0);
1657                 hdmi_writel(hdmi_dev, FC_DRM_PB + 3, 0);
1658                 hdmi_writel(hdmi_dev, FC_DRM_PB + 4, 0);
1659                 hdmi_writel(hdmi_dev, FC_DRM_PB + 5, 0);
1660                 hdmi_writel(hdmi_dev, FC_DRM_PB + 6, 0);
1661                 hdmi_writel(hdmi_dev, FC_DRM_PB + 7, 0);
1662                 hdmi_writel(hdmi_dev, FC_DRM_PB + 8, 0);
1663                 hdmi_writel(hdmi_dev, FC_DRM_PB + 9, 0);
1664                 hdmi_writel(hdmi_dev, FC_DRM_PB + 10, 0);
1665                 hdmi_writel(hdmi_dev, FC_DRM_PB + 11, 0);
1666                 hdmi_writel(hdmi_dev, FC_DRM_PB + 12, 0);
1667                 hdmi_writel(hdmi_dev, FC_DRM_PB + 13, 0);
1668                 hdmi_writel(hdmi_dev, FC_DRM_PB + 14, 0);
1669                 hdmi_writel(hdmi_dev, FC_DRM_PB + 15, 0);
1670                 hdmi_writel(hdmi_dev, FC_DRM_PB + 16, 0);
1671                 hdmi_writel(hdmi_dev, FC_DRM_PB + 17, 0);
1672                 hdmi_writel(hdmi_dev, FC_DRM_PB + 18, 0);
1673                 hdmi_writel(hdmi_dev, FC_DRM_PB + 19, 0);
1674                 hdmi_writel(hdmi_dev, FC_DRM_PB + 20, 0);
1675                 hdmi_writel(hdmi_dev, FC_DRM_PB + 21, 0);
1676                 hdmi_writel(hdmi_dev, FC_DRM_PB + 22, 0);
1677                 hdmi_writel(hdmi_dev, FC_DRM_PB + 23, 0);
1678                 hdmi_writel(hdmi_dev, FC_DRM_PB + 24, 0);
1679                 hdmi_writel(hdmi_dev, FC_DRM_PB + 25, 0);
1680         }
1681         if (eotf) {
1682                 hdmi_msk_reg(hdmi_dev, FC_PACK_TXE, m_DRM_TXEN, v_DRM_TXEN(1));
1683                 hdmi_msk_reg(hdmi_dev, FC_MASK2, m_DRM_MASK, v_DRM_MASK(0));
1684                 hdmi_msk_reg(hdmi_dev, FC_DRM_UP, m_DRM_PUPD, v_DRM_PUPD(1));
1685         } else {
1686                 hdmi_msk_reg(hdmi_dev, FC_PACK_TXE, m_DRM_TXEN, v_DRM_TXEN(0));
1687                 hdmi_msk_reg(hdmi_dev, FC_MASK2, m_DRM_MASK, v_DRM_MASK(1));
1688                 hdmi_msk_reg(hdmi_dev, FC_DRM_UP, m_DRM_PUPD, v_DRM_PUPD(1));
1689         }
1690 }
1691
1692 static int hdmi_dev_config_spd(struct hdmi *hdmi, const char *vendor,
1693                                const char *product, char deviceinfo)
1694 {
1695         struct hdmi_dev *hdmi_dev;
1696         int i, len;
1697
1698         if (!hdmi || !vendor || !product)
1699                 return -1;
1700         hdmi_dev = hdmi->property->priv;
1701
1702         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_SPD_AUTO, v_SPD_AUTO(0));
1703         len = strlen(vendor);
1704         for (i = 0; i < 8; i++) {
1705                 if (i < len)
1706                         hdmi_writel(hdmi_dev, FC_SPDVENDORNAME0 + i,
1707                                     vendor[i]);
1708                 else
1709                         hdmi_writel(hdmi_dev, FC_SPDVENDORNAME0 + i,
1710                                     0);
1711         }
1712         len = strlen(product);
1713         for (i = 0; i < 16; i++) {
1714                 if (i < len)
1715                         hdmi_writel(hdmi_dev, FC_SPDPRODUCTNAME0 + i,
1716                                     product[i]);
1717                 else
1718                         hdmi_writel(hdmi_dev, FC_SPDPRODUCTNAME0 + i,
1719                                     0);
1720         }
1721         hdmi_writel(hdmi_dev, FC_SPDDEVICEINF, deviceinfo);
1722         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_SPD_AUTO, v_SPD_AUTO(1));
1723         return 0;
1724 }
1725
1726 static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
1727 {
1728         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1729
1730         HDMIDBG(2, "%s vic %d 3dformat %d color mode %d color depth %d\n",
1731                 __func__, vpara->vic, vpara->format_3d,
1732                 vpara->color_output, vpara->color_output_depth);
1733
1734         if (hdmi_dev->soctype == HDMI_SOC_RK3288)
1735                 vpara->color_input = HDMI_COLOR_RGB_0_255;
1736
1737         if (!hdmi->uboot) {
1738                 /* before configure video, we power off phy */
1739                 if (hdmi_dev->soctype != HDMI_SOC_RK322X) {
1740                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1741                                      m_PDDQ_SIG | m_TXPWRON_SIG,
1742                                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1743                 } else {
1744                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1745                                      m_ENHPD_RXSENSE_SIG,
1746                                      v_ENHPD_RXSENSE_SIG(1));
1747                         regmap_write(hdmi_dev->grf_base,
1748                                      RK322X_GRF_SOC_CON2,
1749                                      RK322X_PLL_POWER_DOWN);
1750                 }
1751                 /* force output blue */
1752                 if (vpara->color_output == HDMI_COLOR_RGB_0_255) {
1753                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x00);       /*R*/
1754                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x00);       /*G*/
1755                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x00);       /*B*/
1756                 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235) {
1757                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x10);       /*R*/
1758                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*G*/
1759                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x10);       /*B*/
1760                 } else {
1761                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x80);       /*Cr*/
1762                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*Y*/
1763                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x80);       /*Cb*/
1764                 }
1765                 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1766                              m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1767                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1768         }
1769
1770         if (rockchip_hdmiv2_video_framecomposer(hdmi, vpara) < 0)
1771                 return -1;
1772
1773         if (rockchip_hdmiv2_video_packetizer(hdmi_dev, vpara) < 0)
1774                 return -1;
1775         /* Color space convert */
1776         if (rockchip_hdmiv2_video_csc(hdmi_dev, vpara) < 0)
1777                 return -1;
1778         if (rockchip_hdmiv2_video_sampler(hdmi_dev, vpara) < 0)
1779                 return -1;
1780
1781         if (vpara->sink_hdmi == OUTPUT_HDMI) {
1782                 hdmi_dev_config_avi(hdmi, vpara);
1783                 hdmi_dev_config_spd(hdmi, hdmi_dev->vendor_name,
1784                                     hdmi_dev->product_name,
1785                                     hdmi_dev->deviceinfo);
1786                 if (vpara->format_3d != HDMI_3D_NONE) {
1787                         hdmi_dev_config_vsi(hdmi,
1788                                             vpara->format_3d,
1789                                             HDMI_VIDEO_FORMAT_3D);
1790                 } else if ((vpara->vic > 92 && vpara->vic < 96) ||
1791                          (vpara->vic == 98)) {
1792                         vpara->vic = (vpara->vic == 98) ?
1793                                      4 : (96 - vpara->vic);
1794                         hdmi_dev_config_vsi(hdmi,
1795                                             vpara->vic,
1796                                             HDMI_VIDEO_FORMAT_4KX2K);
1797                 } else {
1798                         hdmi_dev_config_vsi(hdmi,
1799                                             vpara->vic,
1800                                             HDMI_VIDEO_FORMAT_NORMAL);
1801                 }
1802                 hdmi_dev_config_hdr(hdmi, vpara->eotf, &hdmi->hdr);
1803                 dev_info(hdmi->dev, "[%s] success output HDMI.\n", __func__);
1804         } else {
1805                 dev_info(hdmi->dev, "[%s] success output DVI.\n", __func__);
1806         }
1807
1808         if (!hdmi->uboot)
1809                 rockchip_hdmiv2_config_phy(hdmi_dev);
1810         else
1811                 hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
1812         return 0;
1813 }
1814
1815 static void hdmi_dev_config_aai(struct hdmi_dev *hdmi_dev,
1816                                 struct hdmi_audio *audio)
1817 {
1818         /* Refer to CEA861-E Audio infoFrame
1819          * Set both Audio Channel Count and Audio Coding
1820          * Type Refer to Stream Head for HDMI
1821          */
1822         hdmi_msk_reg(hdmi_dev, FC_AUDICONF0,
1823                      m_FC_CHN_CNT | m_FC_CODING_TYPE,
1824                      v_FC_CHN_CNT(audio->channel - 1) | v_FC_CODING_TYPE(0));
1825
1826         /* Set both Audio Sample Size and Sample Frequency
1827          * Refer to Stream Head for HDMI
1828          */
1829         hdmi_msk_reg(hdmi_dev, FC_AUDICONF1,
1830                      m_FC_SAMPLE_SIZE | m_FC_SAMPLE_FREQ,
1831                      v_FC_SAMPLE_SIZE(0) | v_FC_SAMPLE_FREQ(0));
1832
1833         /* Set Channel Allocation */
1834         hdmi_writel(hdmi_dev, FC_AUDICONF2, 0x00);
1835
1836         /* Set LFEPBLDOWN-MIX INH and LSV */
1837         hdmi_writel(hdmi_dev, FC_AUDICONF3, 0x00);
1838 }
1839
1840 static int hdmi_dev_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
1841 {
1842         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1843         int word_length = 0, channel = 0, mclk_fs;
1844         unsigned int N = 0, CTS = 0;
1845         int rate = 0;
1846         char design_id;
1847
1848         HDMIDBG(2, "%s\n", __func__);
1849
1850         if (audio->channel < 3)
1851                 channel = I2S_CHANNEL_1_2;
1852         else if (audio->channel < 5)
1853                 channel = I2S_CHANNEL_3_4;
1854         else if (audio->channel < 7)
1855                 channel = I2S_CHANNEL_5_6;
1856         else
1857                 channel = I2S_CHANNEL_7_8;
1858
1859         switch (audio->rate) {
1860         case HDMI_AUDIO_FS_32000:
1861                 mclk_fs = FS_128;
1862                 rate = AUDIO_32K;
1863                 if (hdmi_dev->tmdsclk >= 594000000)
1864                         N = N_32K_HIGHCLK;
1865                 else if (hdmi_dev->tmdsclk >= 297000000)
1866                         N = N_32K_MIDCLK;
1867                 else
1868                         N = N_32K_LOWCLK;
1869                 /*div a num to avoid the value is exceed 2^32(int)*/
1870                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 32);
1871                 break;
1872         case HDMI_AUDIO_FS_44100:
1873                 mclk_fs = FS_128;
1874                 rate = AUDIO_441K;
1875                 if (hdmi_dev->tmdsclk >= 594000000)
1876                         N = N_441K_HIGHCLK;
1877                 else if (hdmi_dev->tmdsclk >= 297000000)
1878                         N = N_441K_MIDCLK;
1879                 else
1880                         N = N_441K_LOWCLK;
1881
1882                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 441);
1883                 break;
1884         case HDMI_AUDIO_FS_48000:
1885                 mclk_fs = FS_128;
1886                 rate = AUDIO_48K;
1887                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1888                         N = N_48K_HIGHCLK;
1889                 else if (hdmi_dev->tmdsclk >= 297000000)
1890                         N = N_48K_MIDCLK;
1891                 else
1892                         N = N_48K_LOWCLK;
1893
1894                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 48);
1895                 break;
1896         case HDMI_AUDIO_FS_88200:
1897                 mclk_fs = FS_128;
1898                 rate = AUDIO_882K;
1899                 if (hdmi_dev->tmdsclk >= 594000000)
1900                         N = N_882K_HIGHCLK;
1901                 else if (hdmi_dev->tmdsclk >= 297000000)
1902                         N = N_882K_MIDCLK;
1903                 else
1904                         N = N_882K_LOWCLK;
1905
1906                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 882);
1907                 break;
1908         case HDMI_AUDIO_FS_96000:
1909                 mclk_fs = FS_128;
1910                 rate = AUDIO_96K;
1911                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1912                         N = N_96K_HIGHCLK;
1913                 else if (hdmi_dev->tmdsclk >= 297000000)
1914                         N = N_96K_MIDCLK;
1915                 else
1916                         N = N_96K_LOWCLK;
1917
1918                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 96);
1919                 break;
1920         case HDMI_AUDIO_FS_176400:
1921                 mclk_fs = FS_128;
1922                 rate = AUDIO_1764K;
1923                 if (hdmi_dev->tmdsclk >= 594000000)
1924                         N = N_1764K_HIGHCLK;
1925                 else if (hdmi_dev->tmdsclk >= 297000000)
1926                         N = N_1764K_MIDCLK;
1927                 else
1928                         N = N_1764K_LOWCLK;
1929
1930                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 1764);
1931                 break;
1932         case HDMI_AUDIO_FS_192000:
1933                 mclk_fs = FS_128;
1934                 rate = AUDIO_192K;
1935                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1936                         N = N_192K_HIGHCLK;
1937                 else if (hdmi_dev->tmdsclk >= 297000000)
1938                         N = N_192K_MIDCLK;
1939                 else
1940                         N = N_192K_LOWCLK;
1941
1942                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 192);
1943                 break;
1944         default:
1945                 dev_err(hdmi_dev->hdmi->dev,
1946                         "[%s] not support such sample rate %d\n",
1947                         __func__, audio->rate);
1948                 return -ENOENT;
1949         }
1950
1951         switch (audio->word_length) {
1952         case HDMI_AUDIO_WORD_LENGTH_16bit:
1953                 word_length = I2S_16BIT_SAMPLE;
1954                 break;
1955         case HDMI_AUDIO_WORD_LENGTH_20bit:
1956                 word_length = I2S_20BIT_SAMPLE;
1957                 break;
1958         case HDMI_AUDIO_WORD_LENGTH_24bit:
1959                 word_length = I2S_24BIT_SAMPLE;
1960                 break;
1961         default:
1962                 word_length = I2S_16BIT_SAMPLE;
1963         }
1964
1965         HDMIDBG(2, "rate = %d, tmdsclk = %u, N = %d, CTS = %d\n",
1966                 audio->rate, hdmi_dev->tmdsclk, N, CTS);
1967         /* more than 2 channels => layout 1 else layout 0 */
1968         hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1969                      m_AUD_PACK_LAYOUT,
1970                      v_AUD_PACK_LAYOUT((audio->channel > 2) ? 1 : 0));
1971
1972         if (hdmi_dev->audiosrc == HDMI_AUDIO_SRC_SPDIF) {
1973                 mclk_fs = FS_128;
1974                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1975                              m_I2S_SEL, v_I2S_SEL(AUDIO_SPDIF_GPA));
1976                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF1,
1977                              m_SET_NLPCM | m_SPDIF_WIDTH,
1978                              v_SET_NLPCM(PCM_LINEAR) |
1979                              v_SPDIF_WIDTH(word_length));
1980                 /*Mask fifo empty and full int and reset fifo*/
1981                 hdmi_msk_reg(hdmi_dev, AUD_SPDIFINT,
1982                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1983                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1984                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF0,
1985                              m_SW_SAUD_FIFO_RST, v_SW_SAUD_FIFO_RST(1));
1986         } else {
1987                 /*Mask fifo empty and full int and reset fifo*/
1988                 hdmi_msk_reg(hdmi_dev, AUD_INT,
1989                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1990                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1991                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1992                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1993                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1994                 design_id = hdmi_readl(hdmi_dev, DESIGN_ID);
1995                 if (design_id >= 0x21)
1996                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x4);
1997                 else
1998                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1999                 usleep_range(90, 100);
2000                 /*
2001                  * when we try to use hdmi nlpcm mode
2002                  * we should use set AUD_CONF2 to open this route and set
2003                  * word_length to 24bit for b.p.c.u.v with 16bit raw data
2004                  * when the bitstream data  up to 8 channel, we should use
2005                  * the hdmi hbr mode
2006                  * HBR Mode : Dolby TrueHD
2007                  *            Dolby Atmos
2008                  *            DTS-HDMA
2009                  * NLPCM Mode :
2010                  * FS_32000 FS_44100 FS_48000 : Dolby Digital &  DTS
2011                  * FS_176400 FS_192000        : Dolby Digital Plus
2012                  */
2013                 if (audio->type == HDMI_AUDIO_NLPCM) {
2014                         if (channel == I2S_CHANNEL_7_8) {
2015                                 HDMIDBG(2, "hbr mode.\n");
2016                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
2017                                 word_length = I2S_24BIT_SAMPLE;
2018                         } else if ((audio->rate == HDMI_AUDIO_FS_32000) ||
2019                                    (audio->rate == HDMI_AUDIO_FS_44100) ||
2020                                    (audio->rate == HDMI_AUDIO_FS_48000) ||
2021                                    (audio->rate == HDMI_AUDIO_FS_176400) ||
2022                                    (audio->rate == HDMI_AUDIO_FS_192000)) {
2023                                 HDMIDBG(2, "nlpcm mode.\n");
2024                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
2025                                 word_length = I2S_24BIT_SAMPLE;
2026                         } else {
2027                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
2028                         }
2029                 } else {
2030                         if (design_id >= 0x21)
2031                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x4);
2032                         else
2033                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
2034                 }
2035                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
2036                              m_I2S_SEL | m_I2S_IN_EN,
2037                              v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
2038                 hdmi_writel(hdmi_dev, AUD_CONF1,
2039                             v_I2S_MODE(I2S_STANDARD_MODE) |
2040                             v_I2S_WIDTH(word_length));
2041         }
2042
2043         hdmi_msk_reg(hdmi_dev, AUD_INPUTCLKFS,
2044                      m_LFS_FACTOR, v_LFS_FACTOR(mclk_fs));
2045
2046         /*Set N value*/
2047         hdmi_msk_reg(hdmi_dev, AUD_N3, m_NCTS_ATOMIC_WR, v_NCTS_ATOMIC_WR(1));
2048         /*Set CTS by manual*/
2049         hdmi_msk_reg(hdmi_dev, AUD_CTS3,
2050                      m_N_SHIFT | m_CTS_MANUAL | m_AUD_CTS3,
2051                      v_N_SHIFT(N_SHIFT_1) |
2052                      v_CTS_MANUAL(1) |
2053                      v_AUD_CTS3(CTS >> 16));
2054         hdmi_writel(hdmi_dev, AUD_CTS2, (CTS >> 8) & 0xff);
2055         hdmi_writel(hdmi_dev, AUD_CTS1, CTS & 0xff);
2056
2057         hdmi_msk_reg(hdmi_dev, AUD_N3, m_AUD_N3, v_AUD_N3(N >> 16));
2058         hdmi_writel(hdmi_dev, AUD_N2, (N >> 8) & 0xff);
2059         hdmi_writel(hdmi_dev, AUD_N1, N & 0xff);
2060
2061         /* set channel status register */
2062         hdmi_msk_reg(hdmi_dev, FC_AUDSCHNLS7,
2063                      m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate));
2064         hdmi_writel(hdmi_dev, FC_AUDSCHNLS8, ((~rate) << 4) | 0x2);
2065
2066         hdmi_msk_reg(hdmi_dev, AUD_CONF0,
2067                      m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
2068
2069         hdmi_dev_config_aai(hdmi_dev, audio);
2070
2071         return 0;
2072 }
2073
2074 static int hdmi_dev_control_output(struct hdmi *hdmi, int enable)
2075 {
2076         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2077         struct hdmi_video vpara;
2078
2079         HDMIDBG(2, "[%s] %d\n", __func__, enable);
2080         if (enable == HDMI_AV_UNMUTE) {
2081                 hdmi_writel(hdmi_dev, FC_DBGFORCE, 0x00);
2082                 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI)
2083                         hdmi_msk_reg(hdmi_dev, FC_GCP,
2084                                      m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
2085                                      v_FC_SET_AVMUTE(0) | v_FC_CLR_AVMUTE(1));
2086         } else {
2087                 if (enable & HDMI_VIDEO_MUTE) {
2088                         hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
2089                                      m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
2090                         if (hdmi->edid.sink_hdmi == OUTPUT_HDMI) {
2091                                 hdmi_msk_reg(hdmi_dev, FC_GCP,
2092                                              m_FC_SET_AVMUTE |
2093                                              m_FC_CLR_AVMUTE,
2094                                              v_FC_SET_AVMUTE(1) |
2095                                              v_FC_CLR_AVMUTE(0));
2096                                 vpara.vic = hdmi->vic;
2097                                 vpara.color_output = HDMI_COLOR_RGB_0_255;
2098                                 hdmi_dev_config_avi(hdmi, &vpara);
2099                                 while ((!hdmi_readl(hdmi_dev, IH_FC_STAT1)) &
2100                                        m_AVI_INFOFRAME) {
2101                                         usleep_range(900, 1000);
2102                                 }
2103                         }
2104                 }
2105 /*              if (enable & HDMI_AUDIO_MUTE) {
2106  *                      hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
2107  *                                   m_AUD_PACK_SAMPFIT,
2108  *                                   v_AUD_PACK_SAMPFIT(0x0F));
2109  *              }
2110  */
2111                 if (enable == (HDMI_VIDEO_MUTE | HDMI_AUDIO_MUTE)) {
2112                         if (hdmi->ops->hdcp_power_off_cb)
2113                                 hdmi->ops->hdcp_power_off_cb(hdmi);
2114                         rockchip_hdmiv2_powerdown(hdmi_dev);
2115                 }
2116         }
2117         return 0;
2118 }
2119
2120 static int hdmi_dev_insert(struct hdmi *hdmi)
2121 {
2122         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2123
2124         HDMIDBG(2, "%s\n", __func__);
2125         if (!hdmi->uboot)
2126                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
2127
2128         return HDMI_ERROR_SUCCESS;
2129 }
2130
2131 static int hdmi_dev_remove(struct hdmi *hdmi)
2132 {
2133         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2134
2135         HDMIDBG(2, "%s\n", __func__);
2136         if (hdmi->ops->hdcp_power_off_cb)
2137                 hdmi->ops->hdcp_power_off_cb(hdmi);
2138         rockchip_hdmiv2_powerdown(hdmi_dev);
2139         hdmi_dev->tmdsclk = 0;
2140         return HDMI_ERROR_SUCCESS;
2141 }
2142
2143 static int hdmi_dev_enable(struct hdmi *hdmi)
2144 {
2145         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2146
2147         HDMIDBG(2, "%s\n", __func__);
2148         if (!hdmi_dev->enable) {
2149                 hdmi_writel(hdmi_dev, IH_MUTE, 0x00);
2150                 hdmi_dev->enable = 1;
2151         }
2152         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 10, 0);
2153         return 0;
2154 }
2155
2156 static int hdmi_dev_disable(struct hdmi *hdmi)
2157 {
2158         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2159
2160         HDMIDBG(2, "%s\n", __func__);
2161         if (hdmi_dev->enable) {
2162                 hdmi_dev->enable = 0;
2163                 hdmi_writel(hdmi_dev, IH_MUTE, 0x1);
2164         }
2165         return 0;
2166 }
2167
2168 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops)
2169 {
2170         if (ops) {
2171                 ops->enable     = hdmi_dev_enable;
2172                 ops->disable    = hdmi_dev_disable;
2173                 ops->getstatus  = hdmi_dev_detect_hotplug;
2174                 ops->insert     = hdmi_dev_insert;
2175                 ops->remove     = hdmi_dev_remove;
2176                 ops->getedid    = hdmi_dev_read_edid;
2177                 ops->setvideo   = hdmi_dev_config_video;
2178                 ops->setaudio   = hdmi_dev_config_audio;
2179                 ops->setmute    = hdmi_dev_control_output;
2180                 ops->setavi     = hdmi_dev_config_avi;
2181                 ops->setvsi     = hdmi_dev_config_vsi;
2182                 ops->sethdr     = hdmi_dev_config_hdr;
2183         }
2184 }
2185
2186 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
2187 {
2188         struct hdmi *hdmi = hdmi_dev->hdmi;
2189
2190         /*lcdc source select*/
2191         if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
2192                 grf_writel(HDMI_SEL_LCDC(hdmi->property->videosrc, 4),
2193                            RK3288_GRF_SOC_CON6);
2194                 /* select GPIO7_C0 as cec pin */
2195                 grf_writel(((1 << 12) | (1 << 28)), RK3288_GRF_SOC_CON8);
2196         } else if (hdmi_dev->soctype == HDMI_SOC_RK3399) {
2197                 regmap_write(hdmi_dev->grf_base,
2198                              RK3399_GRF_SOC_CON20,
2199                              HDMI_SEL_LCDC(hdmi->property->videosrc, 6));
2200         }
2201
2202         if (!hdmi->uboot) {
2203                 pr_info("reset hdmi\n");
2204                 if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
2205                         rk3288_cru_set_soft_reset(RK3288_SOFT_RST_HDMI, true);
2206                         usleep_range(10, 20);
2207                         rk3288_cru_set_soft_reset(RK3288_SOFT_RST_HDMI, false);
2208                 } else {
2209                         if (hdmi_dev->soctype == HDMI_SOC_RK322X) {
2210                                 regmap_write(hdmi_dev->grf_base,
2211                                              RK322X_GRF_SOC_CON2,
2212                                              RK322X_DDC_MASK_EN);
2213                                 regmap_write(hdmi_dev->grf_base,
2214                                              RK322X_GRF_SOC_CON6,
2215                                              RK322X_IO_3V_DOMAIN);
2216                         }
2217                         reset_control_assert(hdmi_dev->reset);
2218                         usleep_range(10, 20);
2219                         reset_control_deassert(hdmi_dev->reset);
2220                 }
2221                 rockchip_hdmiv2_powerdown(hdmi_dev);
2222         } else {
2223                 hdmi->hotplug = hdmi_dev_detect_hotplug(hdmi);
2224                 if (hdmi->hotplug != HDMI_HPD_ACTIVATED)
2225                         hdmi->uboot = 0;
2226         }
2227         /*mute unnecessary interrupt, only enable hpd*/
2228         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT0, 0xff);
2229         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
2230         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
2231         hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
2232         hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfc);
2233         hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
2234         hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
2235         hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
2236         hdmi_writel(hdmi_dev, IH_MUTE_I2CMPHY_STAT0, 0xff);
2237         hdmi_writel(hdmi_dev, IH_MUTE_AHBDMAAUD_STAT0, 0xff);
2238
2239         /* disable hdcp interrupt */
2240         hdmi_writel(hdmi_dev, A_APIINTMSK, 0xff);
2241         hdmi_writel(hdmi_dev, PHY_MASK, 0xf1);
2242
2243         if (hdmi->property->feature & SUPPORT_CEC)
2244                 rockchip_hdmiv2_cec_init(hdmi);
2245         if (hdmi->property->feature & SUPPORT_HDCP)
2246                 rockchip_hdmiv2_hdcp_init(hdmi);
2247 }
2248
2249 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
2250 {
2251         struct hdmi_dev *hdmi_dev = priv;
2252         struct hdmi *hdmi = hdmi_dev->hdmi;
2253         char phy_pol = hdmi_readl(hdmi_dev, PHY_POL0);
2254         char phy_status = hdmi_readl(hdmi_dev, PHY_STAT0);
2255         char phy_int0 = hdmi_readl(hdmi_dev, PHY_INI0);
2256         /*read interrupt*/
2257         char fc_stat0 = hdmi_readl(hdmi_dev, IH_FC_STAT0);
2258         char fc_stat1 = hdmi_readl(hdmi_dev, IH_FC_STAT1);
2259         char fc_stat2 = hdmi_readl(hdmi_dev, IH_FC_STAT2);
2260         char aud_int = hdmi_readl(hdmi_dev, IH_AS_SATA0);
2261         char phy_int = hdmi_readl(hdmi_dev, IH_PHY_STAT0);
2262         char vp_stat0 = hdmi_readl(hdmi_dev, IH_VP_STAT0);
2263         char cec_int = hdmi_readl(hdmi_dev, IH_CEC_STAT0);
2264         char hdcp_int = hdmi_readl(hdmi_dev, A_APIINTSTAT);
2265         u8 hdcp2_int = hdmi_readl(hdmi_dev, HDCP2REG_STAT);
2266
2267         /*clear interrupt*/
2268         hdmi_writel(hdmi_dev, IH_FC_STAT0, fc_stat0);
2269         hdmi_writel(hdmi_dev, IH_FC_STAT1, fc_stat1);
2270         hdmi_writel(hdmi_dev, IH_FC_STAT2, fc_stat2);
2271         hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
2272
2273         if (phy_int0 || phy_int) {
2274                 if ((phy_int0 & m_PHY_LOCK) &&
2275                     (phy_pol & m_PHY_LOCK) == 0) {
2276                         pr_info("hdmi phy pll unlock\n");
2277                         hdmi_submit_work(hdmi, HDMI_SET_VIDEO, 0, 0);
2278                 }
2279                 phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
2280                 hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
2281                 hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
2282                 if ((phy_int & m_HPD) || ((phy_int & 0x3c) == 0x3c))
2283                         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 20, 0);
2284         }
2285
2286         /* Audio error */
2287         if (aud_int) {
2288                 hdmi_writel(hdmi_dev, IH_AS_SATA0, aud_int);
2289                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
2290                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
2291                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
2292         }
2293         /* CEC */
2294         if (cec_int) {
2295                 hdmi_writel(hdmi_dev, IH_CEC_STAT0, cec_int);
2296                 if (hdmi_dev->hdmi->property->feature & SUPPORT_CEC)
2297                         rockchip_hdmiv2_cec_isr(hdmi_dev, cec_int);
2298         }
2299         /* HDCP */
2300         if (hdcp_int) {
2301                 hdmi_writel(hdmi_dev, A_APIINTCLR, hdcp_int);
2302                 rockchip_hdmiv2_hdcp_isr(hdmi_dev, hdcp_int);
2303         }
2304
2305         /* HDCP2 */
2306         if (hdcp2_int) {
2307                 hdmi_writel(hdmi_dev, HDCP2REG_STAT, hdcp2_int);
2308                 pr_info("hdcp2_int is 0x%02x\n", hdcp2_int);
2309                 if ((hdcp2_int & m_HDCP2_AUTH_FAIL ||
2310                      hdcp2_int & m_HDCP2_AUTH_LOST) &&
2311                     hdmi_dev->hdcp2_start) {
2312                         pr_info("hdcp2 failed or lost\n");
2313                         hdmi_dev->hdcp2_start();
2314                 }
2315         }
2316         return IRQ_HANDLED;
2317 }