drivers/video/fbdev/sh_mobile_hdmi.c

   1 /*
   2  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
   3  * for SLISHDMI13T and SLIPHDMIT IP cores
   4  *
   5  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28
  29 #include <video/sh_mobile_hdmi.h>
  30 #include <video/sh_mobile_lcdc.h>
  31
  32 #include "sh_mobile_lcdcfb.h"
  33
  34 /* HDMI Core Control Register (HTOP0) */
  35 #define HDMI_SYSTEM_CTRL                        0x00 /* System control */
  36 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT            0x01 /* L/R data swap control,
  37                                                         bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  38 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8       0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  39 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0        0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  40 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS          0x04 /* SPDIF audio sampling frequency,
  41                                                         bits 19..16 of Internal CTS */
  42 #define HDMI_INTERNAL_CTS_15_8                  0x05 /* bits 15..8 of Internal CTS */
  43 #define HDMI_INTERNAL_CTS_7_0                   0x06 /* bits 7..0 of Internal CTS */
  44 #define HDMI_EXTERNAL_CTS_19_16                 0x07 /* External CTS */
  45 #define HDMI_EXTERNAL_CTS_15_8                  0x08 /* External CTS */
  46 #define HDMI_EXTERNAL_CTS_7_0                   0x09 /* External CTS */
  47 #define HDMI_AUDIO_SETTING_1                    0x0A /* Audio setting.1 */
  48 #define HDMI_AUDIO_SETTING_2                    0x0B /* Audio setting.2 */
  49 #define HDMI_I2S_AUDIO_SET                      0x0C /* I2S audio setting */
  50 #define HDMI_DSD_AUDIO_SET                      0x0D /* DSD audio setting */
  51 #define HDMI_DEBUG_MONITOR_1                    0x0E /* Debug monitor.1 */
  52 #define HDMI_DEBUG_MONITOR_2                    0x0F /* Debug monitor.2 */
  53 #define HDMI_I2S_INPUT_PIN_SWAP                 0x10 /* I2S input pin swap */
  54 #define HDMI_AUDIO_STATUS_BITS_SETTING_1        0x11 /* Audio status bits setting.1 */
  55 #define HDMI_AUDIO_STATUS_BITS_SETTING_2        0x12 /* Audio status bits setting.2 */
  56 #define HDMI_CATEGORY_CODE                      0x13 /* Category code */
  57 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN          0x14 /* Source number/Audio word length */
  58 #define HDMI_AUDIO_VIDEO_SETTING_1              0x15 /* Audio/Video setting.1 */
  59 #define HDMI_VIDEO_SETTING_1                    0x16 /* Video setting.1 */
  60 #define HDMI_DEEP_COLOR_MODES                   0x17 /* Deep Color Modes */
  61
  62 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  63 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS  0x18
  64
  65 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS      0x30 /* External video parameter settings */
  66 #define HDMI_EXTERNAL_H_TOTAL_7_0               0x31 /* External horizontal total (LSB) */
  67 #define HDMI_EXTERNAL_H_TOTAL_11_8              0x32 /* External horizontal total (MSB) */
  68 #define HDMI_EXTERNAL_H_BLANK_7_0               0x33 /* External horizontal blank (LSB) */
  69 #define HDMI_EXTERNAL_H_BLANK_9_8               0x34 /* External horizontal blank (MSB) */
  70 #define HDMI_EXTERNAL_H_DELAY_7_0               0x35 /* External horizontal delay (LSB) */
  71 #define HDMI_EXTERNAL_H_DELAY_9_8               0x36 /* External horizontal delay (MSB) */
  72 #define HDMI_EXTERNAL_H_DURATION_7_0            0x37 /* External horizontal duration (LSB) */
  73 #define HDMI_EXTERNAL_H_DURATION_9_8            0x38 /* External horizontal duration (MSB) */
  74 #define HDMI_EXTERNAL_V_TOTAL_7_0               0x39 /* External vertical total (LSB) */
  75 #define HDMI_EXTERNAL_V_TOTAL_9_8               0x3A /* External vertical total (MSB) */
  76 #define HDMI_AUDIO_VIDEO_SETTING_2              0x3B /* Audio/Video setting.2 */
  77 #define HDMI_EXTERNAL_V_BLANK                   0x3D /* External vertical blank */
  78 #define HDMI_EXTERNAL_V_DELAY                   0x3E /* External vertical delay */
  79 #define HDMI_EXTERNAL_V_DURATION                0x3F /* External vertical duration */
  80 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL       0x40 /* Control packet manual send control */
  81 #define HDMI_CTRL_PKT_AUTO_SEND                 0x41 /* Control packet auto send with VSYNC control */
  82 #define HDMI_AUTO_CHECKSUM_OPTION               0x42 /* Auto checksum option */
  83 #define HDMI_VIDEO_SETTING_2                    0x45 /* Video setting.2 */
  84 #define HDMI_OUTPUT_OPTION                      0x46 /* Output option */
  85 #define HDMI_SLIPHDMIT_PARAM_OPTION             0x51 /* SLIPHDMIT parameter option */
  86 #define HDMI_HSYNC_PMENT_AT_EMB_7_0             0x52 /* HSYNC placement at embedded sync (LSB) */
  87 #define HDMI_HSYNC_PMENT_AT_EMB_15_8            0x53 /* HSYNC placement at embedded sync (MSB) */
  88 #define HDMI_VSYNC_PMENT_AT_EMB_7_0             0x54 /* VSYNC placement at embedded sync (LSB) */
  89 #define HDMI_VSYNC_PMENT_AT_EMB_14_8            0x55 /* VSYNC placement at embedded sync (MSB) */
  90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1         0x56 /* SLIPHDMIT parameter settings.1 */
  91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2         0x57 /* SLIPHDMIT parameter settings.2 */
  92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3         0x58 /* SLIPHDMIT parameter settings.3 */
  93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5         0x59 /* SLIPHDMIT parameter settings.5 */
  94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6         0x5A /* SLIPHDMIT parameter settings.6 */
  95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7         0x5B /* SLIPHDMIT parameter settings.7 */
  96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8         0x5C /* SLIPHDMIT parameter settings.8 */
  97 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9         0x5D /* SLIPHDMIT parameter settings.9 */
  98 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10        0x5E /* SLIPHDMIT parameter settings.10 */
  99 #define HDMI_CTRL_PKT_BUF_INDEX                 0x5F /* Control packet buffer index */
 100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0            0x60 /* Control packet data buffer access window - HB0 */
 101 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1            0x61 /* Control packet data buffer access window - HB1 */
 102 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2            0x62 /* Control packet data buffer access window - HB2 */
 103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0            0x63 /* Control packet data buffer access window - PB0 */
 104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1            0x64 /* Control packet data buffer access window - PB1 */
 105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2            0x65 /* Control packet data buffer access window - PB2 */
 106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3            0x66 /* Control packet data buffer access window - PB3 */
 107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4            0x67 /* Control packet data buffer access window - PB4 */
 108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5            0x68 /* Control packet data buffer access window - PB5 */
 109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6            0x69 /* Control packet data buffer access window - PB6 */
 110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7            0x6A /* Control packet data buffer access window - PB7 */
 111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8            0x6B /* Control packet data buffer access window - PB8 */
 112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9            0x6C /* Control packet data buffer access window - PB9 */
 113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10           0x6D /* Control packet data buffer access window - PB10 */
 114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11           0x6E /* Control packet data buffer access window - PB11 */
 115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12           0x6F /* Control packet data buffer access window - PB12 */
 116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13           0x70 /* Control packet data buffer access window - PB13 */
 117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14           0x71 /* Control packet data buffer access window - PB14 */
 118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15           0x72 /* Control packet data buffer access window - PB15 */
 119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16           0x73 /* Control packet data buffer access window - PB16 */
 120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17           0x74 /* Control packet data buffer access window - PB17 */
 121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18           0x75 /* Control packet data buffer access window - PB18 */
 122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19           0x76 /* Control packet data buffer access window - PB19 */
 123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20           0x77 /* Control packet data buffer access window - PB20 */
 124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21           0x78 /* Control packet data buffer access window - PB21 */
 125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22           0x79 /* Control packet data buffer access window - PB22 */
 126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23           0x7A /* Control packet data buffer access window - PB23 */
 127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24           0x7B /* Control packet data buffer access window - PB24 */
 128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25           0x7C /* Control packet data buffer access window - PB25 */
 129 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26           0x7D /* Control packet data buffer access window - PB26 */
 130 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27           0x7E /* Control packet data buffer access window - PB27 */
 131 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW        0x80 /* EDID/KSV FIFO access window */
 132 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0       0x81 /* DDC bus access frequency control (LSB) */
 133 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8      0x82 /* DDC bus access frequency control (MSB) */
 134 #define HDMI_INTERRUPT_MASK_1                   0x92 /* Interrupt mask.1 */
 135 #define HDMI_INTERRUPT_MASK_2                   0x93 /* Interrupt mask.2 */
 136 #define HDMI_INTERRUPT_STATUS_1                 0x94 /* Interrupt status.1 */
 137 #define HDMI_INTERRUPT_STATUS_2                 0x95 /* Interrupt status.2 */
 138 #define HDMI_INTERRUPT_MASK_3                   0x96 /* Interrupt mask.3 */
 139 #define HDMI_INTERRUPT_MASK_4                   0x97 /* Interrupt mask.4 */
 140 #define HDMI_INTERRUPT_STATUS_3                 0x98 /* Interrupt status.3 */
 141 #define HDMI_INTERRUPT_STATUS_4                 0x99 /* Interrupt status.4 */
 142 #define HDMI_SOFTWARE_HDCP_CONTROL_1            0x9A /* Software HDCP control.1 */
 143 #define HDMI_FRAME_COUNTER                      0x9C /* Frame counter */
 144 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK         0x9D /* Frame counter for Ri check */
 145 #define HDMI_HDCP_CONTROL                       0xAF /* HDCP control */
 146 #define HDMI_RI_FRAME_COUNT_REGISTER            0xB2 /* Ri frame count register */
 147 #define HDMI_DDC_BUS_CONTROL                    0xB7 /* DDC bus control */
 148 #define HDMI_HDCP_STATUS                        0xB8 /* HDCP status */
 149 #define HDMI_SHA0                               0xB9 /* sha0 */
 150 #define HDMI_SHA1                               0xBA /* sha1 */
 151 #define HDMI_SHA2                               0xBB /* sha2 */
 152 #define HDMI_SHA3                               0xBC /* sha3 */
 153 #define HDMI_SHA4                               0xBD /* sha4 */
 154 #define HDMI_BCAPS_READ                         0xBE /* BCAPS read / debug */
 155 #define HDMI_AKSV_BKSV_7_0_MONITOR              0xBF /* AKSV/BKSV[7:0] monitor */
 156 #define HDMI_AKSV_BKSV_15_8_MONITOR             0xC0 /* AKSV/BKSV[15:8] monitor */
 157 #define HDMI_AKSV_BKSV_23_16_MONITOR            0xC1 /* AKSV/BKSV[23:16] monitor */
 158 #define HDMI_AKSV_BKSV_31_24_MONITOR            0xC2 /* AKSV/BKSV[31:24] monitor */
 159 #define HDMI_AKSV_BKSV_39_32_MONITOR            0xC3 /* AKSV/BKSV[39:32] monitor */
 160 #define HDMI_EDID_SEGMENT_POINTER               0xC4 /* EDID segment pointer */
 161 #define HDMI_EDID_WORD_ADDRESS                  0xC5 /* EDID word address */
 162 #define HDMI_EDID_DATA_FIFO_ADDRESS             0xC6 /* EDID data FIFO address */
 163 #define HDMI_NUM_OF_HDMI_DEVICES                0xC7 /* Number of HDMI devices */
 164 #define HDMI_HDCP_ERROR_CODE                    0xC8 /* HDCP error code */
 165 #define HDMI_100MS_TIMER_SET                    0xC9 /* 100ms timer setting */
 166 #define HDMI_5SEC_TIMER_SET                     0xCA /* 5sec timer setting */
 167 #define HDMI_RI_READ_COUNT                      0xCB /* Ri read count */
 168 #define HDMI_AN_SEED                            0xCC /* An seed */
 169 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED          0xCD /* Maximum number of receivers allowed */
 170 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1       0xCE /* HDCP memory access control.1 */
 171 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2       0xCF /* HDCP memory access control.2 */
 172 #define HDMI_HDCP_CONTROL_2                     0xD0 /* HDCP Control 2 */
 173 #define HDMI_HDCP_KEY_MEMORY_CONTROL            0xD2 /* HDCP Key Memory Control */
 174 #define HDMI_COLOR_SPACE_CONV_CONFIG_1          0xD3 /* Color space conversion configuration.1 */
 175 #define HDMI_VIDEO_SETTING_3                    0xD4 /* Video setting.3 */
 176 #define HDMI_RI_7_0                             0xD5 /* Ri[7:0] */
 177 #define HDMI_RI_15_8                            0xD6 /* Ri[15:8] */
 178 #define HDMI_PJ                                 0xD7 /* Pj */
 179 #define HDMI_SHA_RD                             0xD8 /* sha_rd */
 180 #define HDMI_RI_7_0_SAVED                       0xD9 /* Ri[7:0] saved */
 181 #define HDMI_RI_15_8_SAVED                      0xDA /* Ri[15:8] saved */
 182 #define HDMI_PJ_SAVED                           0xDB /* Pj saved */
 183 #define HDMI_NUM_OF_DEVICES                     0xDC /* Number of devices */
 184 #define HDMI_HOT_PLUG_MSENS_STATUS              0xDF /* Hot plug/MSENS status */
 185 #define HDMI_BCAPS_WRITE                        0xE0 /* bcaps */
 186 #define HDMI_BSTAT_7_0                          0xE1 /* bstat[7:0] */
 187 #define HDMI_BSTAT_15_8                         0xE2 /* bstat[15:8] */
 188 #define HDMI_BKSV_7_0                           0xE3 /* bksv[7:0] */
 189 #define HDMI_BKSV_15_8                          0xE4 /* bksv[15:8] */
 190 #define HDMI_BKSV_23_16                         0xE5 /* bksv[23:16] */
 191 #define HDMI_BKSV_31_24                         0xE6 /* bksv[31:24] */
 192 #define HDMI_BKSV_39_32                         0xE7 /* bksv[39:32] */
 193 #define HDMI_AN_7_0                             0xE8 /* An[7:0] */
 194 #define HDMI_AN_15_8                            0xE9 /* An [15:8] */
 195 #define HDMI_AN_23_16                           0xEA /* An [23:16] */
 196 #define HDMI_AN_31_24                           0xEB /* An [31:24] */
 197 #define HDMI_AN_39_32                           0xEC /* An [39:32] */
 198 #define HDMI_AN_47_40                           0xED /* An [47:40] */
 199 #define HDMI_AN_55_48                           0xEE /* An [55:48] */
 200 #define HDMI_AN_63_56                           0xEF /* An [63:56] */
 201 #define HDMI_PRODUCT_ID                         0xF0 /* Product ID */
 202 #define HDMI_REVISION_ID                        0xF1 /* Revision ID */
 203 #define HDMI_TEST_MODE                          0xFE /* Test mode */
 204
 205 /* HDMI Control Register (HTOP1) */
 206 #define HDMI_HTOP1_TEST_MODE                    0x0000 /* Test mode */
 207 #define HDMI_HTOP1_VIDEO_INPUT                  0x0008 /* VideoInput */
 208 #define HDMI_HTOP1_CORE_RSTN                    0x000C /* CoreResetn */
 209 #define HDMI_HTOP1_PLLBW                        0x0018 /* PLLBW */
 210 #define HDMI_HTOP1_CLK_TO_PHY                   0x001C /* Clk to Phy */
 211 #define HDMI_HTOP1_VIDEO_INPUT2                 0x0020 /* VideoInput2 */
 212 #define HDMI_HTOP1_TISEMP0_1                    0x0024 /* tisemp0-1 */
 213 #define HDMI_HTOP1_TISEMP2_C                    0x0028 /* tisemp2-c */
 214 #define HDMI_HTOP1_TISIDRV                      0x002C /* tisidrv */
 215 #define HDMI_HTOP1_TISEN                        0x0034 /* tisen */
 216 #define HDMI_HTOP1_TISDREN                      0x0038 /* tisdren  */
 217 #define HDMI_HTOP1_CISRANGE                     0x003C /* cisrange  */
 218 #define HDMI_HTOP1_ENABLE_SELECTOR              0x0040 /* Enable Selector */
 219 #define HDMI_HTOP1_MACRO_RESET                  0x0044 /* Macro reset */
 220 #define HDMI_HTOP1_PLL_CALIBRATION              0x0048 /* PLL calibration */
 221 #define HDMI_HTOP1_RE_CALIBRATION               0x004C /* Re-calibration */
 222 #define HDMI_HTOP1_CURRENT                      0x0050 /* Current */
 223 #define HDMI_HTOP1_PLL_LOCK_DETECT              0x0054 /* PLL lock detect */
 224 #define HDMI_HTOP1_PHY_TEST_MODE                0x0058 /* PHY Test Mode */
 225 #define HDMI_HTOP1_CLK_SET                      0x0080 /* Clock Set */
 226 #define HDMI_HTOP1_DDC_FAIL_SAFE                0x0084 /* DDC fail safe */
 227 #define HDMI_HTOP1_PRBS                         0x0088 /* PRBS */
 228 #define HDMI_HTOP1_EDID_AINC_CONTROL            0x008C /* EDID ainc Control */
 229 #define HDMI_HTOP1_HTOP_DCL_MODE                0x00FC /* Deep Coloer Mode */
 230 #define HDMI_HTOP1_HTOP_DCL_FRC_COEF0           0x0100 /* Deep Color:FRC COEF0 */
 231 #define HDMI_HTOP1_HTOP_DCL_FRC_COEF1           0x0104 /* Deep Color:FRC COEF1 */
 232 #define HDMI_HTOP1_HTOP_DCL_FRC_COEF2           0x0108 /* Deep Color:FRC COEF2 */
 233 #define HDMI_HTOP1_HTOP_DCL_FRC_COEF3           0x010C /* Deep Color:FRC COEF3 */
 234 #define HDMI_HTOP1_HTOP_DCL_FRC_COEF0_C         0x0110 /* Deep Color:FRC COEF0C */
 235 #define HDMI_HTOP1_HTOP_DCL_FRC_COEF1_C         0x0114 /* Deep Color:FRC COEF1C */
 236 #define HDMI_HTOP1_HTOP_DCL_FRC_COEF2_C         0x0118 /* Deep Color:FRC COEF2C */
 237 #define HDMI_HTOP1_HTOP_DCL_FRC_COEF3_C         0x011C /* Deep Color:FRC COEF3C */
 238 #define HDMI_HTOP1_HTOP_DCL_FRC_MODE            0x0120 /* Deep Color:FRC Mode */
 239 #define HDMI_HTOP1_HTOP_DCL_RECT_START1         0x0124 /* Deep Color:Rect Start1 */
 240 #define HDMI_HTOP1_HTOP_DCL_RECT_SIZE1          0x0128 /* Deep Color:Rect Size1 */
 241 #define HDMI_HTOP1_HTOP_DCL_RECT_START2         0x012C /* Deep Color:Rect Start2 */
 242 #define HDMI_HTOP1_HTOP_DCL_RECT_SIZE2          0x0130 /* Deep Color:Rect Size2 */
 243 #define HDMI_HTOP1_HTOP_DCL_RECT_START3         0x0134 /* Deep Color:Rect Start3 */
 244 #define HDMI_HTOP1_HTOP_DCL_RECT_SIZE3          0x0138 /* Deep Color:Rect Size3 */
 245 #define HDMI_HTOP1_HTOP_DCL_RECT_START4         0x013C /* Deep Color:Rect Start4 */
 246 #define HDMI_HTOP1_HTOP_DCL_RECT_SIZE4          0x0140 /* Deep Color:Rect Size4 */
 247 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y1_1       0x0144 /* Deep Color:Fil Para Y1_1 */
 248 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y1_2       0x0148 /* Deep Color:Fil Para Y1_2 */
 249 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB1_1      0x014C /* Deep Color:Fil Para CB1_1 */
 250 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB1_2      0x0150 /* Deep Color:Fil Para CB1_2 */
 251 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR1_1      0x0154 /* Deep Color:Fil Para CR1_1 */
 252 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR1_2      0x0158 /* Deep Color:Fil Para CR1_2 */
 253 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y2_1       0x015C /* Deep Color:Fil Para Y2_1 */
 254 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y2_2       0x0160 /* Deep Color:Fil Para Y2_2 */
 255 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB2_1      0x0164 /* Deep Color:Fil Para CB2_1 */
 256 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB2_2      0x0168 /* Deep Color:Fil Para CB2_2 */
 257 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR2_1      0x016C /* Deep Color:Fil Para CR2_1 */
 258 #define HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR2_2      0x0170 /* Deep Color:Fil Para CR2_2 */
 259 #define HDMI_HTOP1_HTOP_DCL_COR_PARA_Y1         0x0174 /* Deep Color:Cor Para Y1 */
 260 #define HDMI_HTOP1_HTOP_DCL_COR_PARA_CB1        0x0178 /* Deep Color:Cor Para CB1 */
 261 #define HDMI_HTOP1_HTOP_DCL_COR_PARA_CR1        0x017C /* Deep Color:Cor Para CR1 */
 262 #define HDMI_HTOP1_HTOP_DCL_COR_PARA_Y2         0x0180 /* Deep Color:Cor Para Y2 */
 263 #define HDMI_HTOP1_HTOP_DCL_COR_PARA_CB2        0x0184 /* Deep Color:Cor Para CB2 */
 264 #define HDMI_HTOP1_HTOP_DCL_COR_PARA_CR2        0x0188 /* Deep Color:Cor Para CR2 */
 265 #define HDMI_HTOP1_EDID_DATA_READ               0x0200 /* EDID Data Read 128Byte:0x03FC */
 266
 267 enum hotplug_state {
 268         HDMI_HOTPLUG_DISCONNECTED,
 269         HDMI_HOTPLUG_CONNECTED,
 270         HDMI_HOTPLUG_EDID_DONE,
 271 };
 272
 273 struct sh_hdmi {
 274         struct sh_mobile_lcdc_entity entity;
 275
 276         void __iomem *base;
 277         void __iomem *htop1;
 278         enum hotplug_state hp_state;    /* hot-plug status */
 279         u8 preprogrammed_vic;           /* use a pre-programmed VIC or
 280                                            the external mode */
 281         u8 edid_block_addr;
 282         u8 edid_segment_nr;
 283         u8 edid_blocks;
 284         int irq;
 285         struct clk *hdmi_clk;
 286         struct device *dev;
 287         struct delayed_work edid_work;
 288         struct fb_videomode mode;
 289         struct fb_monspecs monspec;
 290
 291         /* register access functions */
 292         void (*write)(struct sh_hdmi *hdmi, u8 data, u8 reg);
 293         u8 (*read)(struct sh_hdmi *hdmi, u8 reg);
 294 };
 295
 296 #define entity_to_sh_hdmi(e)    container_of(e, struct sh_hdmi, entity)
 297
 298 static void __hdmi_write8(struct sh_hdmi *hdmi, u8 data, u8 reg)
 299 {
 300         iowrite8(data, hdmi->base + reg);
 301 }
 302
 303 static u8 __hdmi_read8(struct sh_hdmi *hdmi, u8 reg)
 304 {
 305         return ioread8(hdmi->base + reg);
 306 }
 307
 308 static void __hdmi_write32(struct sh_hdmi *hdmi, u8 data, u8 reg)
 309 {
 310         iowrite32((u32)data, hdmi->base + (reg * 4));
 311         udelay(100);
 312 }
 313
 314 static u8 __hdmi_read32(struct sh_hdmi *hdmi, u8 reg)
 315 {
 316         return (u8)ioread32(hdmi->base + (reg * 4));
 317 }
 318
 319 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
 320 {
 321         hdmi->write(hdmi, data, reg);
 322 }
 323
 324 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
 325 {
 326         return hdmi->read(hdmi, reg);
 327 }
 328
 329 static void hdmi_bit_set(struct sh_hdmi *hdmi, u8 mask, u8 data, u8 reg)
 330 {
 331         u8 val = hdmi_read(hdmi, reg);
 332
 333         val &= ~mask;
 334         val |= (data & mask);
 335
 336         hdmi_write(hdmi, val, reg);
 337 }
 338
 339 static void hdmi_htop1_write(struct sh_hdmi *hdmi, u32 data, u32 reg)
 340 {
 341         iowrite32(data, hdmi->htop1 + reg);
 342         udelay(100);
 343 }
 344
 345 static u32 hdmi_htop1_read(struct sh_hdmi *hdmi, u32 reg)
 346 {
 347         return ioread32(hdmi->htop1 + reg);
 348 }
 349
 350 /*
 351  *      HDMI sound
 352  */
 353 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
 354                                      unsigned int reg)
 355 {
 356         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 357
 358         return hdmi_read(hdmi, reg);
 359 }
 360
 361 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
 362                              unsigned int reg,
 363                              unsigned int value)
 364 {
 365         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 366
 367         hdmi_write(hdmi, value, reg);
 368         return 0;
 369 }
 370
 371 static struct snd_soc_dai_driver sh_hdmi_dai = {
 372         .name = "sh_mobile_hdmi-hifi",
 373         .playback = {
 374                 .stream_name = "Playback",
 375                 .channels_min = 2,
 376                 .channels_max = 8,
 377                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100  |
 378                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200  |
 379                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 380                          SNDRV_PCM_RATE_192000,
 381                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 382         },
 383 };
 384
 385 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
 386 {
 387         dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
 388
 389         return 0;
 390 }
 391
 392 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
 393         .probe          = sh_hdmi_snd_probe,
 394         .read           = sh_hdmi_snd_read,
 395         .write          = sh_hdmi_snd_write,
 396 };
 397
 398 /*
 399  *      HDMI video
 400  */
 401
 402 /* External video parameter settings */
 403 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
 404 {
 405         struct fb_videomode *mode = &hdmi->mode;
 406         u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
 407         u8 sync = 0;
 408
 409         htotal = mode->xres + mode->right_margin + mode->left_margin
 410                + mode->hsync_len;
 411         hdelay = mode->hsync_len + mode->left_margin;
 412         hblank = mode->right_margin + hdelay;
 413
 414         /*
 415          * Vertical timing looks a bit different in Figure 18,
 416          * but let's try the same first by setting offset = 0
 417          */
 418         vtotal = mode->yres + mode->upper_margin + mode->lower_margin
 419                + mode->vsync_len;
 420         vdelay = mode->vsync_len + mode->upper_margin;
 421         vblank = mode->lower_margin + vdelay;
 422         voffset = min(mode->upper_margin / 2, 6U);
 423
 424         /*
 425          * [3]: VSYNC polarity: Positive
 426          * [2]: HSYNC polarity: Positive
 427          * [1]: Interlace/Progressive: Progressive
 428          * [0]: External video settings enable: used.
 429          */
 430         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 431                 sync |= 4;
 432         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 433                 sync |= 8;
 434
 435         dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
 436                 htotal, hblank, hdelay, mode->hsync_len,
 437                 vtotal, vblank, vdelay, mode->vsync_len, sync);
 438
 439         hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 440
 441         hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
 442         hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
 443
 444         hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
 445         hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
 446
 447         hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
 448         hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
 449
 450         hdmi_write(hdmi, mode->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
 451         hdmi_write(hdmi, mode->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
 452
 453         hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
 454         hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
 455
 456         hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
 457
 458         hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
 459
 460         hdmi_write(hdmi, mode->vsync_len, HDMI_EXTERNAL_V_DURATION);
 461
 462         /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
 463         if (!hdmi->preprogrammed_vic)
 464                 hdmi_write(hdmi, sync | 1 | (voffset << 4),
 465                            HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 466 }
 467
 468 /**
 469  * sh_hdmi_video_config()
 470  */
 471 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
 472 {
 473         /*
 474          * [7:4]: Audio sampling frequency: 48kHz
 475          * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
 476          * [0]: Internal/External DE select: internal
 477          */
 478         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 479
 480         /*
 481          * [7:6]: Video output format: RGB 4:4:4
 482          * [5:4]: Input video data width: 8 bit
 483          * [3:1]: EAV/SAV location: channel 1
 484          * [0]: Video input color space: RGB
 485          */
 486         hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
 487
 488         /*
 489          * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
 490          * left at 0 by default, this configures 24bpp and sets the Color Depth
 491          * (CD) field in the General Control Packet
 492          */
 493         hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
 494 }
 495
 496 /**
 497  * sh_hdmi_audio_config()
 498  */
 499 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
 500 {
 501         u8 data;
 502         struct sh_mobile_hdmi_info *pdata = dev_get_platdata(hdmi->dev);
 503
 504         /*
 505          * [7:4] L/R data swap control
 506          * [3:0] appropriate N[19:16]
 507          */
 508         hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
 509         /* appropriate N[15:8] */
 510         hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
 511         /* appropriate N[7:0] */
 512         hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
 513
 514         /* [7:4] 48 kHz SPDIF not used */
 515         hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
 516
 517         /*
 518          * [6:5] set required down sampling rate if required
 519          * [4:3] set required audio source
 520          */
 521         switch (pdata->flags & HDMI_SND_SRC_MASK) {
 522         default:
 523                 /* fall through */
 524         case HDMI_SND_SRC_I2S:
 525                 data = 0x0 << 3;
 526                 break;
 527         case HDMI_SND_SRC_SPDIF:
 528                 data = 0x1 << 3;
 529                 break;
 530         case HDMI_SND_SRC_DSD:
 531                 data = 0x2 << 3;
 532                 break;
 533         case HDMI_SND_SRC_HBR:
 534                 data = 0x3 << 3;
 535                 break;
 536         }
 537         hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
 538
 539         /* [3:0] set sending channel number for channel status */
 540         hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
 541
 542         /*
 543          * [5:2] set valid I2S source input pin
 544          * [1:0] set input I2S source mode
 545          */
 546         hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
 547
 548         /* [7:4] set valid DSD source input pin */
 549         hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
 550
 551         /* [7:0] set appropriate I2S input pin swap settings if required */
 552         hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
 553
 554         /*
 555          * [7] set validity bit for channel status
 556          * [3:0] set original sample frequency for channel status
 557          */
 558         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
 559
 560         /*
 561          * [7] set value for channel status
 562          * [6] set value for channel status
 563          * [5] set copyright bit for channel status
 564          * [4:2] set additional information for channel status
 565          * [1:0] set clock accuracy for channel status
 566          */
 567         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
 568
 569         /* [7:0] set category code for channel status */
 570         hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
 571
 572         /*
 573          * [7:4] set source number for channel status
 574          * [3:0] set word length for channel status
 575          */
 576         hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
 577
 578         /* [7:4] set sample frequency for channel status */
 579         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 580 }
 581
 582 /**
 583  * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
 584  */
 585 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
 586 {
 587         if (hdmi->mode.pixclock < 10000) {
 588                 /* for 1080p8bit 148MHz */
 589                 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 590                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 591                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 592                 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 593                 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 594                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 595                 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 596                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 597                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 598         } else if (hdmi->mode.pixclock < 30000) {
 599                 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
 600                 /*
 601                  * [1:0]        Speed_A
 602                  * [3:2]        Speed_B
 603                  * [4]          PLLA_Bypass
 604                  * [6]          DRV_TEST_EN
 605                  * [7]          DRV_TEST_IN
 606                  */
 607                 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 608                 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
 609                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 610                 /*
 611                  * [2:0]        BGR_I_OFFSET
 612                  * [6:4]        BGR_V_OFFSET
 613                  */
 614                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 615                 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
 616                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 617                 /*
 618                  * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
 619                  * LPF capacitance, LPF resistance[1]
 620                  */
 621                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 622                 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
 623                 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 624                 /*
 625                  * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
 626                  * LPF capacitance, LPF resistance[1]
 627                  */
 628                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 629                 /* DRV_CONFIG, PE_CONFIG */
 630                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 631                 /*
 632                  * [2:0]        AMON_SEL (4 == LPF voltage)
 633                  * [4]          PLLA_CONFIG[16]
 634                  * [5]          PLLB_CONFIG[16]
 635                  */
 636                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 637         } else {
 638                 /* for 480p8bit 27MHz */
 639                 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 640                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 641                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 642                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 643                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 644                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 645                 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 646                 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 647                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 648         }
 649 }
 650
 651 /**
 652  * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
 653  */
 654 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
 655 {
 656         u8 vic;
 657
 658         /* AVI InfoFrame */
 659         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
 660
 661         /* Packet Type = 0x82 */
 662         hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 663
 664         /* Version = 0x02 */
 665         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 666
 667         /* Length = 13 (0x0D) */
 668         hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 669
 670         /* N. A. Checksum */
 671         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 672
 673         /*
 674          * Y = RGB
 675          * A0 = No Data
 676          * B = Bar Data not valid
 677          * S = No Data
 678          */
 679         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 680
 681         /*
 682          * [7:6] C = Colorimetry: no data
 683          * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
 684          * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
 685          */
 686         hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 687
 688         /*
 689          * ITC = No Data
 690          * EC = xvYCC601
 691          * Q = Default (depends on video format)
 692          * SC = No Known non_uniform Scaling
 693          */
 694         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 695
 696         /*
 697          * VIC should be ignored if external config is used, so, we could just use 0,
 698          * but play safe and use a valid value in any case just in case
 699          */
 700         if (hdmi->preprogrammed_vic)
 701                 vic = hdmi->preprogrammed_vic;
 702         else
 703                 vic = 4;
 704         hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 705
 706         /* PR = No Repetition */
 707         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 708
 709         /* Line Number of End of Top Bar (lower 8 bits) */
 710         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 711
 712         /* Line Number of End of Top Bar (upper 8 bits) */
 713         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 714
 715         /* Line Number of Start of Bottom Bar (lower 8 bits) */
 716         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 717
 718         /* Line Number of Start of Bottom Bar (upper 8 bits) */
 719         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 720
 721         /* Pixel Number of End of Left Bar (lower 8 bits) */
 722         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 723
 724         /* Pixel Number of End of Left Bar (upper 8 bits) */
 725         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
 726
 727         /* Pixel Number of Start of Right Bar (lower 8 bits) */
 728         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
 729
 730         /* Pixel Number of Start of Right Bar (upper 8 bits) */
 731         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
 732 }
 733
 734 /**
 735  * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
 736  */
 737 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
 738 {
 739         /* Audio InfoFrame */
 740         hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
 741
 742         /* Packet Type = 0x84 */
 743         hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 744
 745         /* Version Number = 0x01 */
 746         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 747
 748         /* 0 Length = 10 (0x0A) */
 749         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 750
 751         /* n. a. Checksum */
 752         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 753
 754         /* Audio Channel Count = Refer to Stream Header */
 755         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 756
 757         /* Refer to Stream Header */
 758         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 759
 760         /* Format depends on coding type (i.e. CT0...CT3) */
 761         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 762
 763         /* Speaker Channel Allocation = Front Right + Front Left */
 764         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 765
 766         /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
 767         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 768
 769         /* Reserved (0) */
 770         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 771         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 772         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 773         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 774         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 775 }
 776
 777 /**
 778  * sh_hdmi_configure() - Initialise HDMI for output
 779  */
 780 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
 781 {
 782         /* Configure video format */
 783         sh_hdmi_video_config(hdmi);
 784
 785         /* Configure audio format */
 786         sh_hdmi_audio_config(hdmi);
 787
 788         /* Configure PHY */
 789         sh_hdmi_phy_config(hdmi);
 790
 791         /* Auxiliary Video Information (AVI) InfoFrame */
 792         sh_hdmi_avi_infoframe_setup(hdmi);
 793
 794         /* Audio InfoFrame */
 795         sh_hdmi_audio_infoframe_setup(hdmi);
 796
 797         /*
 798          * Control packet auto send with VSYNC control: auto send
 799          * General control, Gamut metadata, ISRC, and ACP packets
 800          */
 801         hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
 802
 803         /* FIXME */
 804         msleep(10);
 805
 806         /* PS mode b->d, reset PLLA and PLLB */
 807         hdmi_bit_set(hdmi, 0xFC, 0x4C, HDMI_SYSTEM_CTRL);
 808
 809         udelay(10);
 810
 811         hdmi_bit_set(hdmi, 0xFC, 0x40, HDMI_SYSTEM_CTRL);
 812 }
 813
 814 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
 815                 const struct fb_videomode *mode,
 816                 unsigned long *hdmi_rate, unsigned long *parent_rate)
 817 {
 818         unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
 819         struct sh_mobile_hdmi_info *pdata = dev_get_platdata(hdmi->dev);
 820
 821         *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
 822         if ((long)*hdmi_rate < 0)
 823                 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
 824
 825         rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
 826         if (rate_error && pdata->clk_optimize_parent)
 827                 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
 828         else if (clk_get_parent(hdmi->hdmi_clk))
 829                 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
 830
 831         dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
 832                 mode->left_margin, mode->xres,
 833                 mode->right_margin, mode->hsync_len,
 834                 mode->upper_margin, mode->yres,
 835                 mode->lower_margin, mode->vsync_len);
 836
 837         dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
 838                 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
 839                 mode->refresh, *parent_rate);
 840
 841         return rate_error;
 842 }
 843
 844 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
 845                              unsigned long *parent_rate)
 846 {
 847         struct sh_mobile_lcdc_chan *ch = hdmi->entity.lcdc;
 848         const struct fb_videomode *mode, *found = NULL;
 849         unsigned int f_width = 0, f_height = 0, f_refresh = 0;
 850         unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
 851         bool scanning = false, preferred_bad = false;
 852         bool use_edid_mode = false;
 853         u8 edid[128];
 854         char *forced;
 855         int i;
 856
 857         /* Read EDID */
 858         dev_dbg(hdmi->dev, "Read back EDID code:");
 859         for (i = 0; i < 128; i++) {
 860                 edid[i] = (hdmi->htop1) ?
 861                         (u8)hdmi_htop1_read(hdmi, HDMI_HTOP1_EDID_DATA_READ + (i * 4)) :
 862                         hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
 863 #ifdef DEBUG
 864                 if ((i % 16) == 0) {
 865                         printk(KERN_CONT "\n");
 866                         printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
 867                 } else {
 868                         printk(KERN_CONT " %02X", edid[i]);
 869                 }
 870 #endif
 871         }
 872 #ifdef DEBUG
 873         printk(KERN_CONT "\n");
 874 #endif
 875
 876         if (!hdmi->edid_blocks) {
 877                 fb_edid_to_monspecs(edid, &hdmi->monspec);
 878                 hdmi->edid_blocks = edid[126] + 1;
 879
 880                 dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
 881                         hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
 882         } else {
 883                 dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
 884                         edid[0], edid[2]);
 885                 fb_edid_add_monspecs(edid, &hdmi->monspec);
 886         }
 887
 888         if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
 889             (hdmi->edid_block_addr >> 7) + 1) {
 890                 /* More blocks to read */
 891                 if (hdmi->edid_block_addr) {
 892                         hdmi->edid_block_addr = 0;
 893                         hdmi->edid_segment_nr++;
 894                 } else {
 895                         hdmi->edid_block_addr = 0x80;
 896                 }
 897                 /* Set EDID word address  */
 898                 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
 899                 /* Enable EDID interrupt */
 900                 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 901                 /* Set EDID segment pointer - starts reading EDID */
 902                 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
 903                 return -EAGAIN;
 904         }
 905
 906         /* All E-EDID blocks ready */
 907         dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
 908
 909         fb_get_options("sh_mobile_lcdc", &forced);
 910         if (forced && *forced) {
 911                 /* Only primitive parsing so far */
 912                 i = sscanf(forced, "%ux%u@%u",
 913                            &f_width, &f_height, &f_refresh);
 914                 if (i < 2) {
 915                         f_width = 0;
 916                         f_height = 0;
 917                 } else {
 918                         /* The user wants us to use the EDID data */
 919                         scanning = true;
 920                 }
 921                 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
 922                         f_width, f_height, f_refresh);
 923         }
 924
 925         /* Walk monitor modes to find the best or the exact match */
 926         for (i = 0, mode = hdmi->monspec.modedb;
 927              i < hdmi->monspec.modedb_len && scanning;
 928              i++, mode++) {
 929                 unsigned long rate_error;
 930
 931                 if (!f_width && !f_height) {
 932                         /*
 933                          * A parameter string "video=sh_mobile_lcdc:0x0" means
 934                          * use the preferred EDID mode. If it is rejected by
 935                          * .fb_check_var(), keep looking, until an acceptable
 936                          * one is found.
 937                          */
 938                         if ((mode->flag & FB_MODE_IS_FIRST) || preferred_bad)
 939                                 scanning = false;
 940                         else
 941                                 continue;
 942                 } else if (f_width != mode->xres || f_height != mode->yres) {
 943                         /* No interest in unmatching modes */
 944                         continue;
 945                 }
 946
 947                 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
 948
 949                 if (scanning) {
 950                         if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
 951                                 /*
 952                                  * Exact match if either the refresh rate
 953                                  * matches or it hasn't been specified and we've
 954                                  * found a mode, for which we can configure the
 955                                  * clock precisely
 956                                  */
 957                                 scanning = false;
 958                         else if (found && found_rate_error <= rate_error)
 959                                 /*
 960                                  * We otherwise search for the closest matching
 961                                  * clock rate - either if no refresh rate has
 962                                  * been specified or we cannot find an exactly
 963                                  * matching one
 964                                  */
 965                                 continue;
 966                 }
 967
 968                 /* Check if supported: sufficient fb memory, supported clock-rate */
 969                 if (ch && ch->notify &&
 970                     ch->notify(ch, SH_MOBILE_LCDC_EVENT_DISPLAY_MODE, mode,
 971                                NULL)) {
 972                         scanning = true;
 973                         preferred_bad = true;
 974                         continue;
 975                 }
 976
 977                 found = mode;
 978                 found_rate_error = rate_error;
 979                 use_edid_mode = true;
 980         }
 981
 982         /*
 983          * TODO 1: if no default mode is present, postpone running the config
 984          * until after the LCDC channel is initialized.
 985          * TODO 2: consider registering the HDMI platform device from the LCDC
 986          * driver.
 987          */
 988         if (!found && hdmi->entity.def_mode.xres != 0) {
 989                 found = &hdmi->entity.def_mode;
 990                 found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate,
 991                                                       parent_rate);
 992         }
 993
 994         /* No cookie today */
 995         if (!found)
 996                 return -ENXIO;
 997
 998         if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
 999                 hdmi->preprogrammed_vic = 1;
1000         else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
1001                 hdmi->preprogrammed_vic = 2;
1002         else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
1003                 hdmi->preprogrammed_vic = 17;
1004         else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
1005                 hdmi->preprogrammed_vic = 4;
1006         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
1007                 hdmi->preprogrammed_vic = 32;
1008         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
1009                 hdmi->preprogrammed_vic = 31;
1010         else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
1011                 hdmi->preprogrammed_vic = 16;
1012         else
1013                 hdmi->preprogrammed_vic = 0;
1014
1015         dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), "
1016                 "clock error %luHz\n", use_edid_mode ? "EDID" : "default",
1017                 hdmi->preprogrammed_vic ? "VIC" : "external", found->xres,
1018                 found->yres, found->refresh, PICOS2KHZ(found->pixclock) * 1000,
1019                 found_rate_error);
1020
1021         hdmi->mode = *found;
1022         sh_hdmi_external_video_param(hdmi);
1023
1024         return 0;
1025 }
1026
1027 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
1028 {
1029         struct sh_hdmi *hdmi = dev_id;
1030         u8 status1, status2, mask1, mask2;
1031
1032         /* mode_b and PLLA and PLLB reset */
1033         hdmi_bit_set(hdmi, 0xFC, 0x2C, HDMI_SYSTEM_CTRL);
1034
1035         /* How long shall reset be held? */
1036         udelay(10);
1037
1038         /* mode_b and PLLA and PLLB reset release */
1039         hdmi_bit_set(hdmi, 0xFC, 0x20, HDMI_SYSTEM_CTRL);
1040
1041         status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
1042         status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
1043
1044         mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
1045         mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
1046
1047         /* Correct would be to ack only set bits, but the datasheet requires 0xff */
1048         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
1049         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
1050
1051         if (printk_ratelimit())
1052                 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
1053                         irq, status1, mask1, status2, mask2);
1054
1055         if (!((status1 & mask1) | (status2 & mask2))) {
1056                 return IRQ_NONE;
1057         } else if (status1 & 0xc0) {
1058                 u8 msens;
1059
1060                 /* Datasheet specifies 10ms... */
1061                 udelay(500);
1062
1063                 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
1064                 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
1065                 /* Check, if hot plug & MSENS pin status are both high */
1066                 if ((msens & 0xC0) == 0xC0) {
1067                         /* Display plug in */
1068                         hdmi->edid_segment_nr = 0;
1069                         hdmi->edid_block_addr = 0;
1070                         hdmi->edid_blocks = 0;
1071                         hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
1072
1073                         /* Set EDID word address  */
1074                         hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
1075                         /* Enable EDID interrupt */
1076                         hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
1077                         /* Set EDID segment pointer - starts reading EDID */
1078                         hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
1079                 } else if (!(status1 & 0x80)) {
1080                         /* Display unplug, beware multiple interrupts */
1081                         if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
1082                                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1083                                 schedule_delayed_work(&hdmi->edid_work, 0);
1084                         }
1085                         /* display_off will switch back to mode_a */
1086                 }
1087         } else if (status1 & 2) {
1088                 /* EDID error interrupt: retry */
1089                 /* Set EDID word address  */
1090                 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
1091                 /* Set EDID segment pointer */
1092                 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
1093         } else if (status1 & 4) {
1094                 /* Disable EDID interrupt */
1095                 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
1096                 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
1097         }
1098
1099         return IRQ_HANDLED;
1100 }
1101
1102 static int sh_hdmi_display_on(struct sh_mobile_lcdc_entity *entity)
1103 {
1104         struct sh_hdmi *hdmi = entity_to_sh_hdmi(entity);
1105
1106         dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__, hdmi,
1107                 hdmi->hp_state);
1108
1109         /*
1110          * hp_state can be set to
1111          * HDMI_HOTPLUG_DISCONNECTED:   on monitor unplug
1112          * HDMI_HOTPLUG_CONNECTED:      on monitor plug-in
1113          * HDMI_HOTPLUG_EDID_DONE:      on EDID read completion
1114          */
1115         if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
1116                 /* PS mode d->e. All functions are active */
1117                 hdmi_bit_set(hdmi, 0xFC, 0x80, HDMI_SYSTEM_CTRL);
1118                 dev_dbg(hdmi->dev, "HDMI running\n");
1119         }
1120
1121         return hdmi->hp_state == HDMI_HOTPLUG_DISCONNECTED
1122                 ? SH_MOBILE_LCDC_DISPLAY_DISCONNECTED
1123                 : SH_MOBILE_LCDC_DISPLAY_CONNECTED;
1124 }
1125
1126 static void sh_hdmi_display_off(struct sh_mobile_lcdc_entity *entity)
1127 {
1128         struct sh_hdmi *hdmi = entity_to_sh_hdmi(entity);
1129
1130         dev_dbg(hdmi->dev, "%s(%p)\n", __func__, hdmi);
1131         /* PS mode e->a */
1132         hdmi_bit_set(hdmi, 0xFC, 0x10, HDMI_SYSTEM_CTRL);
1133 }
1134
1135 static const struct sh_mobile_lcdc_entity_ops sh_hdmi_ops = {
1136         .display_on = sh_hdmi_display_on,
1137         .display_off = sh_hdmi_display_off,
1138 };
1139
1140 /**
1141  * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
1142  * @hdmi:               driver context
1143  * @hdmi_rate:          HDMI clock frequency in Hz
1144  * @parent_rate:        if != 0 - set parent clock rate for optimal precision
1145  * return:              configured positive rate if successful
1146  *                      0 if couldn't set the rate, but managed to enable the
1147  *                      clock, negative error, if couldn't enable the clock
1148  */
1149 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1150                                   unsigned long parent_rate)
1151 {
1152         int ret;
1153
1154         if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1155                 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
1156                 if (ret < 0) {
1157                         dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1158                         hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
1159                 } else {
1160                         dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
1161                 }
1162         }
1163
1164         ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
1165         if (ret < 0) {
1166                 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1167                 hdmi_rate = 0;
1168         } else {
1169                 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
1170         }
1171
1172         return hdmi_rate;
1173 }
1174
1175 /* Hotplug interrupt occurred, read EDID */
1176 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1177 {
1178         struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1179         struct sh_mobile_lcdc_chan *ch = hdmi->entity.lcdc;
1180         int ret;
1181
1182         dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__, hdmi,
1183                 hdmi->hp_state);
1184
1185         if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
1186                 unsigned long parent_rate = 0, hdmi_rate;
1187
1188                 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
1189                 if (ret < 0)
1190                         goto out;
1191
1192                 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
1193
1194                 /* Reconfigure the clock */
1195                 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
1196                 if (ret < 0)
1197                         goto out;
1198
1199                 msleep(10);
1200                 sh_hdmi_configure(hdmi);
1201                 /* Switched to another (d) power-save mode */
1202                 msleep(10);
1203
1204                 if (ch && ch->notify)
1205                         ch->notify(ch, SH_MOBILE_LCDC_EVENT_DISPLAY_CONNECT,
1206                                    &hdmi->mode, &hdmi->monspec);
1207         } else {
1208                 hdmi->monspec.modedb_len = 0;
1209                 fb_destroy_modedb(hdmi->monspec.modedb);
1210                 hdmi->monspec.modedb = NULL;
1211
1212                 if (ch && ch->notify)
1213                         ch->notify(ch, SH_MOBILE_LCDC_EVENT_DISPLAY_DISCONNECT,
1214                                    NULL, NULL);
1215
1216                 ret = 0;
1217         }
1218
1219 out:
1220         if (ret < 0 && ret != -EAGAIN)
1221                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1222
1223         dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, hdmi);
1224 }
1225
1226 static void sh_hdmi_htop1_init(struct sh_hdmi *hdmi)
1227 {
1228         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_MODE);
1229         hdmi_htop1_write(hdmi, 0x0000000b, 0x0010);
1230         hdmi_htop1_write(hdmi, 0x00006710, HDMI_HTOP1_HTOP_DCL_FRC_MODE);
1231         hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y1_1);
1232         hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y1_2);
1233         hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB1_1);
1234         hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB1_2);
1235         hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR1_1);
1236         hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR1_2);
1237         hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y2_1);
1238         hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_Y2_2);
1239         hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB2_1);
1240         hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CB2_2);
1241         hdmi_htop1_write(hdmi, 0x01020406, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR2_1);
1242         hdmi_htop1_write(hdmi, 0x07080806, HDMI_HTOP1_HTOP_DCL_FIL_PARA_CR2_2);
1243         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_Y1);
1244         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_CB1);
1245         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_CR1);
1246         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_Y2);
1247         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_CB2);
1248         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_HTOP_DCL_COR_PARA_CR2);
1249         hdmi_htop1_write(hdmi, 0x00000008, HDMI_HTOP1_CURRENT);
1250         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_TISEMP0_1);
1251         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_TISEMP2_C);
1252         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_PHY_TEST_MODE);
1253         hdmi_htop1_write(hdmi, 0x00000081, HDMI_HTOP1_TISIDRV);
1254         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_PLLBW);
1255         hdmi_htop1_write(hdmi, 0x0000000f, HDMI_HTOP1_TISEN);
1256         hdmi_htop1_write(hdmi, 0x0000000f, HDMI_HTOP1_TISDREN);
1257         hdmi_htop1_write(hdmi, 0x00000003, HDMI_HTOP1_ENABLE_SELECTOR);
1258         hdmi_htop1_write(hdmi, 0x00000001, HDMI_HTOP1_MACRO_RESET);
1259         hdmi_htop1_write(hdmi, 0x00000016, HDMI_HTOP1_CISRANGE);
1260         msleep(100);
1261         hdmi_htop1_write(hdmi, 0x00000001, HDMI_HTOP1_ENABLE_SELECTOR);
1262         msleep(100);
1263         hdmi_htop1_write(hdmi, 0x00000003, HDMI_HTOP1_ENABLE_SELECTOR);
1264         hdmi_htop1_write(hdmi, 0x00000001, HDMI_HTOP1_MACRO_RESET);
1265         hdmi_htop1_write(hdmi, 0x0000000f, HDMI_HTOP1_TISEN);
1266         hdmi_htop1_write(hdmi, 0x0000000f, HDMI_HTOP1_TISDREN);
1267         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_VIDEO_INPUT);
1268         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_CLK_TO_PHY);
1269         hdmi_htop1_write(hdmi, 0x00000000, HDMI_HTOP1_VIDEO_INPUT2);
1270         hdmi_htop1_write(hdmi, 0x0000000a, HDMI_HTOP1_CLK_SET);
1271 }
1272
1273 static int __init sh_hdmi_probe(struct platform_device *pdev)
1274 {
1275         struct sh_mobile_hdmi_info *pdata = dev_get_platdata(&pdev->dev);
1276         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1277         struct resource *htop1_res;
1278         int irq = platform_get_irq(pdev, 0), ret;
1279         struct sh_hdmi *hdmi;
1280         long rate;
1281
1282         if (!res || !pdata || irq < 0)
1283                 return -ENODEV;
1284
1285         htop1_res = NULL;
1286         if (pdata->flags & HDMI_HAS_HTOP1) {
1287                 htop1_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1288                 if (!htop1_res) {
1289                         dev_err(&pdev->dev, "htop1 needs register base\n");
1290                         return -EINVAL;
1291                 }
1292         }
1293
1294         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1295         if (!hdmi) {
1296                 dev_err(&pdev->dev, "Cannot allocate device data\n");
1297                 return -ENOMEM;
1298         }
1299
1300         hdmi->dev = &pdev->dev;
1301         hdmi->entity.owner = THIS_MODULE;
1302         hdmi->entity.ops = &sh_hdmi_ops;
1303         hdmi->irq = irq;
1304
1305         hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1306         if (IS_ERR(hdmi->hdmi_clk)) {
1307                 ret = PTR_ERR(hdmi->hdmi_clk);
1308                 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1309                 return ret;
1310         }
1311
1312         /* select register access functions */
1313         if (pdata->flags & HDMI_32BIT_REG) {
1314                 hdmi->write     = __hdmi_write32;
1315                 hdmi->read      = __hdmi_read32;
1316         } else {
1317                 hdmi->write     = __hdmi_write8;
1318                 hdmi->read      = __hdmi_read8;
1319         }
1320
1321         /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1322         rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1323         if (rate > 0)
1324                 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1325
1326         if (rate < 0) {
1327                 ret = rate;
1328                 goto erate;
1329         }
1330
1331         ret = clk_prepare_enable(hdmi->hdmi_clk);
1332         if (ret < 0) {
1333                 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1334                 goto erate;
1335         }
1336
1337         dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1338
1339         if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1340                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1341                 ret = -EBUSY;
1342                 goto ereqreg;
1343         }
1344
1345         hdmi->base = ioremap(res->start, resource_size(res));
1346         if (!hdmi->base) {
1347                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1348                 ret = -ENOMEM;
1349                 goto emap;
1350         }
1351
1352         platform_set_drvdata(pdev, &hdmi->entity);
1353
1354         INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1355
1356         pm_runtime_enable(&pdev->dev);
1357         pm_runtime_get_sync(&pdev->dev);
1358
1359         /* init interrupt polarity */
1360         if (pdata->flags & HDMI_OUTPUT_PUSH_PULL)
1361                 hdmi_bit_set(hdmi, 0x02, 0x02, HDMI_SYSTEM_CTRL);
1362
1363         if (pdata->flags & HDMI_OUTPUT_POLARITY_HI)
1364                 hdmi_bit_set(hdmi, 0x01, 0x01, HDMI_SYSTEM_CTRL);
1365
1366         /* enable htop1 register if needed */
1367         if (htop1_res) {
1368                 hdmi->htop1 = ioremap(htop1_res->start, resource_size(htop1_res));
1369                 if (!hdmi->htop1) {
1370                         dev_err(&pdev->dev, "control register region already claimed\n");
1371                         ret = -ENOMEM;
1372                         goto emap_htop1;
1373                 }
1374                 sh_hdmi_htop1_init(hdmi);
1375         }
1376
1377         /* Product and revision IDs are 0 in sh-mobile version */
1378         dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1379                  hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1380
1381         ret = request_irq(irq, sh_hdmi_hotplug, 0,
1382                           dev_name(&pdev->dev), hdmi);
1383         if (ret < 0) {
1384                 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1385                 goto ereqirq;
1386         }
1387
1388         ret = snd_soc_register_codec(&pdev->dev,
1389                         &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1390         if (ret < 0) {
1391                 dev_err(&pdev->dev, "codec registration failed\n");
1392                 goto ecodec;
1393         }
1394
1395         return 0;
1396
1397 ecodec:
1398         free_irq(irq, hdmi);
1399 ereqirq:
1400         if (hdmi->htop1)
1401                 iounmap(hdmi->htop1);
1402 emap_htop1:
1403         pm_runtime_put(&pdev->dev);
1404         pm_runtime_disable(&pdev->dev);
1405         iounmap(hdmi->base);
1406 emap:
1407         release_mem_region(res->start, resource_size(res));
1408 ereqreg:
1409         clk_disable_unprepare(hdmi->hdmi_clk);
1410 erate:
1411         clk_put(hdmi->hdmi_clk);
1412
1413         return ret;
1414 }
1415
1416 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1417 {
1418         struct sh_hdmi *hdmi = entity_to_sh_hdmi(platform_get_drvdata(pdev));
1419         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1420
1421         snd_soc_unregister_codec(&pdev->dev);
1422
1423         /* No new work will be scheduled, wait for running ISR */
1424         free_irq(hdmi->irq, hdmi);
1425         /* Wait for already scheduled work */
1426         cancel_delayed_work_sync(&hdmi->edid_work);
1427         pm_runtime_put(&pdev->dev);
1428         pm_runtime_disable(&pdev->dev);
1429         clk_disable_unprepare(hdmi->hdmi_clk);
1430         clk_put(hdmi->hdmi_clk);
1431         if (hdmi->htop1)
1432                 iounmap(hdmi->htop1);
1433         iounmap(hdmi->base);
1434         release_mem_region(res->start, resource_size(res));
1435
1436         return 0;
1437 }
1438
1439 static int sh_hdmi_suspend(struct device *dev)
1440 {
1441         struct platform_device *pdev = to_platform_device(dev);
1442         struct sh_hdmi *hdmi = entity_to_sh_hdmi(platform_get_drvdata(pdev));
1443
1444         disable_irq(hdmi->irq);
1445         /* Wait for already scheduled work */
1446         cancel_delayed_work_sync(&hdmi->edid_work);
1447         return 0;
1448 }
1449
1450 static int sh_hdmi_resume(struct device *dev)
1451 {
1452         struct platform_device *pdev = to_platform_device(dev);
1453         struct sh_mobile_hdmi_info *pdata = dev_get_platdata(dev);
1454         struct sh_hdmi *hdmi = entity_to_sh_hdmi(platform_get_drvdata(pdev));
1455
1456         /* Re-init interrupt polarity */
1457         if (pdata->flags & HDMI_OUTPUT_PUSH_PULL)
1458                 hdmi_bit_set(hdmi, 0x02, 0x02, HDMI_SYSTEM_CTRL);
1459
1460         if (pdata->flags & HDMI_OUTPUT_POLARITY_HI)
1461                 hdmi_bit_set(hdmi, 0x01, 0x01, HDMI_SYSTEM_CTRL);
1462
1463         /* Re-init htop1 */
1464         if (hdmi->htop1)
1465                 sh_hdmi_htop1_init(hdmi);
1466
1467         /* Now it's safe to enable interrupts again */
1468         enable_irq(hdmi->irq);
1469         return 0;
1470 }
1471
1472 static const struct dev_pm_ops sh_hdmi_pm_ops = {
1473         .suspend        = sh_hdmi_suspend,
1474         .resume         = sh_hdmi_resume,
1475 };
1476
1477 static struct platform_driver sh_hdmi_driver = {
1478         .remove         = __exit_p(sh_hdmi_remove),
1479         .driver = {
1480                 .name   = "sh-mobile-hdmi",
1481                 .pm     = &sh_hdmi_pm_ops,
1482         },
1483 };
1484
1485 module_platform_driver_probe(sh_hdmi_driver, sh_hdmi_probe);
1486
1487 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1488 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1489 MODULE_LICENSE("GPL v2");