drivers/usb/phy/phy-tegra-usb.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  * Copyright (C) 2013 NVIDIA Corporation
   4  *
   5  * Author:
   6  *      Erik Gilling <konkers@google.com>
   7  *      Benoit Goby <benoit@android.com>
   8  *      Venu Byravarasu <vbyravarasu@nvidia.com>
   9  *
  10  * This software is licensed under the terms of the GNU General Public
  11  * License version 2, as published by the Free Software Foundation, and
  12  * may be copied, distributed, and modified under those terms.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  */
  20
  21 #include <linux/resource.h>
  22 #include <linux/delay.h>
  23 #include <linux/slab.h>
  24 #include <linux/err.h>
  25 #include <linux/export.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/gpio.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/usb/otg.h>
  34 #include <linux/usb/ulpi.h>
  35 #include <linux/usb/of.h>
  36 #include <linux/usb/ehci_def.h>
  37 #include <linux/usb/tegra_usb_phy.h>
  38 #include <linux/regulator/consumer.h>
  39
  40 #define ULPI_VIEWPORT           0x170
  41
  42 /* PORTSC PTS/PHCD bits, Tegra20 only */
  43 #define TEGRA_USB_PORTSC1                               0x184
  44 #define TEGRA_USB_PORTSC1_PTS(x)                        (((x) & 0x3) << 30)
  45 #define TEGRA_USB_PORTSC1_PHCD                          (1 << 23)
  46
  47 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
  48 #define TEGRA_USB_HOSTPC1_DEVLC         0x1b4
  49 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)  (((x) & 0x7) << 29)
  50 #define TEGRA_USB_HOSTPC1_DEVLC_PHCD    (1 << 22)
  51
  52 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
  53 #define TEGRA_PORTSC1_RWC_BITS  (PORT_CSC | PORT_PEC | PORT_OCC)
  54
  55 #define USB_SUSP_CTRL           0x400
  56 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
  57 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
  58 #define   USB_SUSP_CLR          (1 << 5)
  59 #define   USB_PHY_CLK_VALID     (1 << 7)
  60 #define   UTMIP_RESET                   (1 << 11)
  61 #define   UHSIC_RESET                   (1 << 11)
  62 #define   UTMIP_PHY_ENABLE              (1 << 12)
  63 #define   ULPI_PHY_ENABLE       (1 << 13)
  64 #define   USB_SUSP_SET          (1 << 14)
  65 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
  66
  67 #define USB1_LEGACY_CTRL        0x410
  68 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
  69 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
  70 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
  71 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
  72                                                 (1 << 1)
  73 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
  74 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
  75
  76 #define ULPI_TIMING_CTRL_0      0x424
  77 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
  78 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
  79
  80 #define ULPI_TIMING_CTRL_1      0x428
  81 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
  82 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
  83 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
  84 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
  85 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
  86 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
  87
  88 #define UTMIP_PLL_CFG1          0x804
  89 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
  90 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
  91
  92 #define UTMIP_XCVR_CFG0         0x808
  93 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
  94 #define   UTMIP_XCVR_SETUP_MSB(x)               ((((x) & 0x70) >> 4) << 22)
  95 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
  96 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
  97 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
  98 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
  99 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
 100 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
 101 #define   UTMIP_XCVR_HSSLEW(x)                  (((x) & 0x3) << 4)
 102 #define   UTMIP_XCVR_HSSLEW_MSB(x)              ((((x) & 0x1fc) >> 2) << 25)
 103
 104 #define UTMIP_BIAS_CFG0         0x80c
 105 #define   UTMIP_OTGPD                   (1 << 11)
 106 #define   UTMIP_BIASPD                  (1 << 10)
 107 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
 108 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
 109 #define   UTMIP_HSDISCON_LEVEL_MSB(x)   ((((x) & 0x4) >> 2) << 24)
 110
 111 #define UTMIP_HSRX_CFG0         0x810
 112 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
 113 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
 114
 115 #define UTMIP_HSRX_CFG1         0x814
 116 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
 117
 118 #define UTMIP_TX_CFG0           0x820
 119 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
 120 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
 121
 122 #define UTMIP_MISC_CFG0         0x824
 123 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
 124 #define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
 125 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
 126 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
 127 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
 128 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
 129 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
 130
 131 #define UTMIP_MISC_CFG1         0x828
 132 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
 133 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
 134
 135 #define UTMIP_DEBOUNCE_CFG0     0x82c
 136 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
 137
 138 #define UTMIP_BAT_CHRG_CFG0     0x830
 139 #define   UTMIP_PD_CHRG                 (1 << 0)
 140
 141 #define UTMIP_SPARE_CFG0        0x834
 142 #define   FUSE_SETUP_SEL                (1 << 3)
 143
 144 #define UTMIP_XCVR_CFG1         0x838
 145 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
 146 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
 147 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
 148 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
 149
 150 #define UTMIP_BIAS_CFG1         0x83c
 151 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
 152
 153 /* For Tegra30 and above only, the address is different in Tegra20 */
 154 #define USB_USBMODE             0x1f8
 155 #define   USB_USBMODE_MASK              (3 << 0)
 156 #define   USB_USBMODE_HOST              (3 << 0)
 157 #define   USB_USBMODE_DEVICE            (2 << 0)
 158
 159 static DEFINE_SPINLOCK(utmip_pad_lock);
 160 static int utmip_pad_count;
 161
 162 struct tegra_xtal_freq {
 163         int freq;
 164         u8 enable_delay;
 165         u8 stable_count;
 166         u8 active_delay;
 167         u8 xtal_freq_count;
 168         u16 debounce;
 169 };
 170
 171 static const struct tegra_xtal_freq tegra_freq_table[] = {
 172         {
 173                 .freq = 12000000,
 174                 .enable_delay = 0x02,
 175                 .stable_count = 0x2F,
 176                 .active_delay = 0x04,
 177                 .xtal_freq_count = 0x76,
 178                 .debounce = 0x7530,
 179         },
 180         {
 181                 .freq = 13000000,
 182                 .enable_delay = 0x02,
 183                 .stable_count = 0x33,
 184                 .active_delay = 0x05,
 185                 .xtal_freq_count = 0x7F,
 186                 .debounce = 0x7EF4,
 187         },
 188         {
 189                 .freq = 19200000,
 190                 .enable_delay = 0x03,
 191                 .stable_count = 0x4B,
 192                 .active_delay = 0x06,
 193                 .xtal_freq_count = 0xBB,
 194                 .debounce = 0xBB80,
 195         },
 196         {
 197                 .freq = 26000000,
 198                 .enable_delay = 0x04,
 199                 .stable_count = 0x66,
 200                 .active_delay = 0x09,
 201                 .xtal_freq_count = 0xFE,
 202                 .debounce = 0xFDE8,
 203         },
 204 };
 205
 206 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
 207 {
 208         void __iomem *base = phy->regs;
 209         unsigned long val;
 210
 211         if (phy->soc_config->has_hostpc) {
 212                 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
 213                 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
 214                 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
 215                 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 216         } else {
 217                 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
 218                 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
 219                 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
 220                 writel(val, base + TEGRA_USB_PORTSC1);
 221         }
 222 }
 223
 224 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
 225 {
 226         void __iomem *base = phy->regs;
 227         unsigned long val;
 228
 229         if (phy->soc_config->has_hostpc) {
 230                 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
 231                 if (enable)
 232                         val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 233                 else
 234                         val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 235                 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 236         } else {
 237                 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
 238                 if (enable)
 239                         val |= TEGRA_USB_PORTSC1_PHCD;
 240                 else
 241                         val &= ~TEGRA_USB_PORTSC1_PHCD;
 242                 writel(val, base + TEGRA_USB_PORTSC1);
 243         }
 244 }
 245
 246 static int utmip_pad_open(struct tegra_usb_phy *phy)
 247 {
 248         phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
 249         if (IS_ERR(phy->pad_clk)) {
 250                 pr_err("%s: can't get utmip pad clock\n", __func__);
 251                 return PTR_ERR(phy->pad_clk);
 252         }
 253
 254         return 0;
 255 }
 256
 257 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
 258 {
 259         unsigned long val, flags;
 260         void __iomem *base = phy->pad_regs;
 261         struct tegra_utmip_config *config = phy->config;
 262
 263         clk_prepare_enable(phy->pad_clk);
 264
 265         spin_lock_irqsave(&utmip_pad_lock, flags);
 266
 267         if (utmip_pad_count++ == 0) {
 268                 val = readl(base + UTMIP_BIAS_CFG0);
 269                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 270
 271                 if (phy->soc_config->requires_extra_tuning_parameters) {
 272                         val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
 273                                 UTMIP_HSDISCON_LEVEL(~0) |
 274                                 UTMIP_HSDISCON_LEVEL_MSB(~0));
 275
 276                         val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
 277                         val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
 278                         val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
 279                 }
 280                 writel(val, base + UTMIP_BIAS_CFG0);
 281         }
 282
 283         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 284
 285         clk_disable_unprepare(phy->pad_clk);
 286 }
 287
 288 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 289 {
 290         unsigned long val, flags;
 291         void __iomem *base = phy->pad_regs;
 292
 293         if (!utmip_pad_count) {
 294                 pr_err("%s: utmip pad already powered off\n", __func__);
 295                 return -EINVAL;
 296         }
 297
 298         clk_prepare_enable(phy->pad_clk);
 299
 300         spin_lock_irqsave(&utmip_pad_lock, flags);
 301
 302         if (--utmip_pad_count == 0) {
 303                 val = readl(base + UTMIP_BIAS_CFG0);
 304                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
 305                 writel(val, base + UTMIP_BIAS_CFG0);
 306         }
 307
 308         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 309
 310         clk_disable_unprepare(phy->pad_clk);
 311
 312         return 0;
 313 }
 314
 315 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 316 {
 317         unsigned long timeout = 2000;
 318         do {
 319                 if ((readl(reg) & mask) == result)
 320                         return 0;
 321                 udelay(1);
 322                 timeout--;
 323         } while (timeout);
 324         return -1;
 325 }
 326
 327 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 328 {
 329         unsigned long val;
 330         void __iomem *base = phy->regs;
 331
 332         if (phy->is_legacy_phy) {
 333                 val = readl(base + USB_SUSP_CTRL);
 334                 val |= USB_SUSP_SET;
 335                 writel(val, base + USB_SUSP_CTRL);
 336
 337                 udelay(10);
 338
 339                 val = readl(base + USB_SUSP_CTRL);
 340                 val &= ~USB_SUSP_SET;
 341                 writel(val, base + USB_SUSP_CTRL);
 342         } else
 343                 set_phcd(phy, true);
 344
 345         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
 346                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 347 }
 348
 349 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 350 {
 351         unsigned long val;
 352         void __iomem *base = phy->regs;
 353
 354         if (phy->is_legacy_phy) {
 355                 val = readl(base + USB_SUSP_CTRL);
 356                 val |= USB_SUSP_CLR;
 357                 writel(val, base + USB_SUSP_CTRL);
 358
 359                 udelay(10);
 360
 361                 val = readl(base + USB_SUSP_CTRL);
 362                 val &= ~USB_SUSP_CLR;
 363                 writel(val, base + USB_SUSP_CTRL);
 364         } else
 365                 set_phcd(phy, false);
 366
 367         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 368                                                      USB_PHY_CLK_VALID))
 369                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 370 }
 371
 372 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 373 {
 374         unsigned long val;
 375         void __iomem *base = phy->regs;
 376         struct tegra_utmip_config *config = phy->config;
 377
 378         val = readl(base + USB_SUSP_CTRL);
 379         val |= UTMIP_RESET;
 380         writel(val, base + USB_SUSP_CTRL);
 381
 382         if (phy->is_legacy_phy) {
 383                 val = readl(base + USB1_LEGACY_CTRL);
 384                 val |= USB1_NO_LEGACY_MODE;
 385                 writel(val, base + USB1_LEGACY_CTRL);
 386         }
 387
 388         val = readl(base + UTMIP_TX_CFG0);
 389         val |= UTMIP_FS_PREABMLE_J;
 390         writel(val, base + UTMIP_TX_CFG0);
 391
 392         val = readl(base + UTMIP_HSRX_CFG0);
 393         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 394         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 395         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 396         writel(val, base + UTMIP_HSRX_CFG0);
 397
 398         val = readl(base + UTMIP_HSRX_CFG1);
 399         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 400         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 401         writel(val, base + UTMIP_HSRX_CFG1);
 402
 403         val = readl(base + UTMIP_DEBOUNCE_CFG0);
 404         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 405         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
 406         writel(val, base + UTMIP_DEBOUNCE_CFG0);
 407
 408         val = readl(base + UTMIP_MISC_CFG0);
 409         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 410         writel(val, base + UTMIP_MISC_CFG0);
 411
 412         if (!phy->soc_config->utmi_pll_config_in_car_module) {
 413                 val = readl(base + UTMIP_MISC_CFG1);
 414                 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
 415                         UTMIP_PLLU_STABLE_COUNT(~0));
 416                 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
 417                         UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
 418                 writel(val, base + UTMIP_MISC_CFG1);
 419
 420                 val = readl(base + UTMIP_PLL_CFG1);
 421                 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
 422                         UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 423                 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
 424                         UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
 425                 writel(val, base + UTMIP_PLL_CFG1);
 426         }
 427
 428         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 429                 val = readl(base + USB_SUSP_CTRL);
 430                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 431                 writel(val, base + USB_SUSP_CTRL);
 432
 433                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
 434                 val &= ~UTMIP_PD_CHRG;
 435                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
 436         } else {
 437                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
 438                 val |= UTMIP_PD_CHRG;
 439                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
 440         }
 441
 442         utmip_pad_power_on(phy);
 443
 444         val = readl(base + UTMIP_XCVR_CFG0);
 445         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 446                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
 447                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
 448                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
 449
 450         if (!config->xcvr_setup_use_fuses) {
 451                 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 452                 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
 453         }
 454         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 455         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 456
 457         if (phy->soc_config->requires_extra_tuning_parameters) {
 458                 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
 459                 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
 460                 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
 461         }
 462         writel(val, base + UTMIP_XCVR_CFG0);
 463
 464         val = readl(base + UTMIP_XCVR_CFG1);
 465         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 466                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 467         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 468         writel(val, base + UTMIP_XCVR_CFG1);
 469
 470         val = readl(base + UTMIP_BIAS_CFG1);
 471         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 472         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 473         writel(val, base + UTMIP_BIAS_CFG1);
 474
 475         val = readl(base + UTMIP_SPARE_CFG0);
 476         if (config->xcvr_setup_use_fuses)
 477                 val |= FUSE_SETUP_SEL;
 478         else
 479                 val &= ~FUSE_SETUP_SEL;
 480         writel(val, base + UTMIP_SPARE_CFG0);
 481
 482         if (!phy->is_legacy_phy) {
 483                 val = readl(base + USB_SUSP_CTRL);
 484                 val |= UTMIP_PHY_ENABLE;
 485                 writel(val, base + USB_SUSP_CTRL);
 486         }
 487
 488         val = readl(base + USB_SUSP_CTRL);
 489         val &= ~UTMIP_RESET;
 490         writel(val, base + USB_SUSP_CTRL);
 491
 492         if (phy->is_legacy_phy) {
 493                 val = readl(base + USB1_LEGACY_CTRL);
 494                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
 495                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 496                 writel(val, base + USB1_LEGACY_CTRL);
 497
 498                 val = readl(base + USB_SUSP_CTRL);
 499                 val &= ~USB_SUSP_SET;
 500                 writel(val, base + USB_SUSP_CTRL);
 501         }
 502
 503         utmi_phy_clk_enable(phy);
 504
 505         if (phy->soc_config->requires_usbmode_setup) {
 506                 val = readl(base + USB_USBMODE);
 507                 val &= ~USB_USBMODE_MASK;
 508                 if (phy->mode == USB_DR_MODE_HOST)
 509                         val |= USB_USBMODE_HOST;
 510                 else
 511                         val |= USB_USBMODE_DEVICE;
 512                 writel(val, base + USB_USBMODE);
 513         }
 514
 515         if (!phy->is_legacy_phy)
 516                 set_pts(phy, 0);
 517
 518         return 0;
 519 }
 520
 521 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 522 {
 523         unsigned long val;
 524         void __iomem *base = phy->regs;
 525
 526         utmi_phy_clk_disable(phy);
 527
 528         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 529                 val = readl(base + USB_SUSP_CTRL);
 530                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 531                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
 532                 writel(val, base + USB_SUSP_CTRL);
 533         }
 534
 535         val = readl(base + USB_SUSP_CTRL);
 536         val |= UTMIP_RESET;
 537         writel(val, base + USB_SUSP_CTRL);
 538
 539         val = readl(base + UTMIP_BAT_CHRG_CFG0);
 540         val |= UTMIP_PD_CHRG;
 541         writel(val, base + UTMIP_BAT_CHRG_CFG0);
 542
 543         val = readl(base + UTMIP_XCVR_CFG0);
 544         val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 545                UTMIP_FORCE_PDZI_POWERDOWN;
 546         writel(val, base + UTMIP_XCVR_CFG0);
 547
 548         val = readl(base + UTMIP_XCVR_CFG1);
 549         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 550                UTMIP_FORCE_PDDR_POWERDOWN;
 551         writel(val, base + UTMIP_XCVR_CFG1);
 552
 553         return utmip_pad_power_off(phy);
 554 }
 555
 556 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 557 {
 558         unsigned long val;
 559         void __iomem *base = phy->regs;
 560
 561         val = readl(base + UTMIP_TX_CFG0);
 562         val |= UTMIP_HS_DISCON_DISABLE;
 563         writel(val, base + UTMIP_TX_CFG0);
 564 }
 565
 566 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 567 {
 568         unsigned long val;
 569         void __iomem *base = phy->regs;
 570
 571         val = readl(base + UTMIP_TX_CFG0);
 572         val &= ~UTMIP_HS_DISCON_DISABLE;
 573         writel(val, base + UTMIP_TX_CFG0);
 574 }
 575
 576 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
 577                                    enum tegra_usb_phy_port_speed port_speed)
 578 {
 579         unsigned long val;
 580         void __iomem *base = phy->regs;
 581
 582         val = readl(base + UTMIP_MISC_CFG0);
 583         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
 584         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 585                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
 586         else
 587                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
 588         writel(val, base + UTMIP_MISC_CFG0);
 589         udelay(1);
 590
 591         val = readl(base + UTMIP_MISC_CFG0);
 592         val |= UTMIP_DPDM_OBSERVE;
 593         writel(val, base + UTMIP_MISC_CFG0);
 594         udelay(10);
 595 }
 596
 597 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
 598 {
 599         unsigned long val;
 600         void __iomem *base = phy->regs;
 601
 602         val = readl(base + UTMIP_MISC_CFG0);
 603         val &= ~UTMIP_DPDM_OBSERVE;
 604         writel(val, base + UTMIP_MISC_CFG0);
 605         udelay(10);
 606 }
 607
 608 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 609 {
 610         int ret;
 611         unsigned long val;
 612         void __iomem *base = phy->regs;
 613
 614         ret = gpio_direction_output(phy->reset_gpio, 0);
 615         if (ret < 0) {
 616                 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n",
 617                         phy->reset_gpio);
 618                 return ret;
 619         }
 620         msleep(5);
 621         ret = gpio_direction_output(phy->reset_gpio, 1);
 622         if (ret < 0) {
 623                 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n",
 624                         phy->reset_gpio);
 625                 return ret;
 626         }
 627
 628         clk_prepare_enable(phy->clk);
 629         msleep(1);
 630
 631         val = readl(base + USB_SUSP_CTRL);
 632         val |= UHSIC_RESET;
 633         writel(val, base + USB_SUSP_CTRL);
 634
 635         val = readl(base + ULPI_TIMING_CTRL_0);
 636         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 637         writel(val, base + ULPI_TIMING_CTRL_0);
 638
 639         val = readl(base + USB_SUSP_CTRL);
 640         val |= ULPI_PHY_ENABLE;
 641         writel(val, base + USB_SUSP_CTRL);
 642
 643         val = 0;
 644         writel(val, base + ULPI_TIMING_CTRL_1);
 645
 646         val |= ULPI_DATA_TRIMMER_SEL(4);
 647         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 648         val |= ULPI_DIR_TRIMMER_SEL(4);
 649         writel(val, base + ULPI_TIMING_CTRL_1);
 650         udelay(10);
 651
 652         val |= ULPI_DATA_TRIMMER_LOAD;
 653         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 654         val |= ULPI_DIR_TRIMMER_LOAD;
 655         writel(val, base + ULPI_TIMING_CTRL_1);
 656
 657         /* Fix VbusInvalid due to floating VBUS */
 658         ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
 659         if (ret) {
 660                 pr_err("%s: ulpi write failed\n", __func__);
 661                 return ret;
 662         }
 663
 664         ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
 665         if (ret) {
 666                 pr_err("%s: ulpi write failed\n", __func__);
 667                 return ret;
 668         }
 669
 670         val = readl(base + USB_SUSP_CTRL);
 671         val |= USB_SUSP_CLR;
 672         writel(val, base + USB_SUSP_CTRL);
 673         udelay(100);
 674
 675         val = readl(base + USB_SUSP_CTRL);
 676         val &= ~USB_SUSP_CLR;
 677         writel(val, base + USB_SUSP_CTRL);
 678
 679         return 0;
 680 }
 681
 682 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 683 {
 684         clk_disable(phy->clk);
 685         return gpio_direction_output(phy->reset_gpio, 0);
 686 }
 687
 688 static void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 689 {
 690         if (!IS_ERR(phy->vbus))
 691                 regulator_disable(phy->vbus);
 692
 693         clk_disable_unprepare(phy->pll_u);
 694 }
 695
 696 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 697 {
 698         if (phy->is_ulpi_phy)
 699                 return ulpi_phy_power_on(phy);
 700         else
 701                 return utmi_phy_power_on(phy);
 702 }
 703
 704 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 705 {
 706         if (phy->is_ulpi_phy)
 707                 return ulpi_phy_power_off(phy);
 708         else
 709                 return utmi_phy_power_off(phy);
 710 }
 711
 712 static int      tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
 713 {
 714         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 715         if (suspend)
 716                 return tegra_usb_phy_power_off(phy);
 717         else
 718                 return tegra_usb_phy_power_on(phy);
 719 }
 720
 721 static int ulpi_open(struct tegra_usb_phy *phy)
 722 {
 723         int err;
 724
 725         phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
 726         if (IS_ERR(phy->clk)) {
 727                 pr_err("%s: can't get ulpi clock\n", __func__);
 728                 return PTR_ERR(phy->clk);
 729         }
 730
 731         err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
 732                 "ulpi_phy_reset_b");
 733         if (err < 0) {
 734                 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n",
 735                        phy->reset_gpio);
 736                 return err;
 737         }
 738
 739         err = gpio_direction_output(phy->reset_gpio, 0);
 740         if (err < 0) {
 741                 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n",
 742                        phy->reset_gpio);
 743                 return err;
 744         }
 745
 746         phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
 747         if (!phy->ulpi) {
 748                 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n");
 749                 err = -ENOMEM;
 750                 return err;
 751         }
 752
 753         phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
 754         return 0;
 755 }
 756
 757 static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
 758 {
 759         unsigned long parent_rate;
 760         int i;
 761         int err;
 762
 763         phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
 764         if (IS_ERR(phy->pll_u)) {
 765                 pr_err("Can't get pll_u clock\n");
 766                 return PTR_ERR(phy->pll_u);
 767         }
 768
 769         err = clk_prepare_enable(phy->pll_u);
 770         if (err)
 771                 return err;
 772
 773         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 774         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
 775                 if (tegra_freq_table[i].freq == parent_rate) {
 776                         phy->freq = &tegra_freq_table[i];
 777                         break;
 778                 }
 779         }
 780         if (!phy->freq) {
 781                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
 782                 err = -EINVAL;
 783                 goto fail;
 784         }
 785
 786         if (!IS_ERR(phy->vbus)) {
 787                 err = regulator_enable(phy->vbus);
 788                 if (err) {
 789                         dev_err(phy->u_phy.dev,
 790                                 "failed to enable usb vbus regulator: %d\n",
 791                                 err);
 792                         goto fail;
 793                 }
 794         }
 795
 796         if (phy->is_ulpi_phy)
 797                 err = ulpi_open(phy);
 798         else
 799                 err = utmip_pad_open(phy);
 800         if (err < 0)
 801                 goto fail;
 802
 803         return 0;
 804
 805 fail:
 806         clk_disable_unprepare(phy->pll_u);
 807         return err;
 808 }
 809
 810 void tegra_usb_phy_preresume(struct usb_phy *x)
 811 {
 812         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 813
 814         if (!phy->is_ulpi_phy)
 815                 utmi_phy_preresume(phy);
 816 }
 817 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 818
 819 void tegra_usb_phy_postresume(struct usb_phy *x)
 820 {
 821         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 822
 823         if (!phy->is_ulpi_phy)
 824                 utmi_phy_postresume(phy);
 825 }
 826 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 827
 828 void tegra_ehci_phy_restore_start(struct usb_phy *x,
 829                                  enum tegra_usb_phy_port_speed port_speed)
 830 {
 831         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 832
 833         if (!phy->is_ulpi_phy)
 834                 utmi_phy_restore_start(phy, port_speed);
 835 }
 836 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 837
 838 void tegra_ehci_phy_restore_end(struct usb_phy *x)
 839 {
 840         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 841
 842         if (!phy->is_ulpi_phy)
 843                 utmi_phy_restore_end(phy);
 844 }
 845 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 846
 847 static int read_utmi_param(struct platform_device *pdev, const char *param,
 848                            u8 *dest)
 849 {
 850         u32 value;
 851         int err = of_property_read_u32(pdev->dev.of_node, param, &value);
 852         *dest = (u8)value;
 853         if (err < 0)
 854                 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n",
 855                         param, err);
 856         return err;
 857 }
 858
 859 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
 860                           struct platform_device *pdev)
 861 {
 862         struct resource *res;
 863         int err;
 864         struct tegra_utmip_config *config;
 865
 866         tegra_phy->is_ulpi_phy = false;
 867
 868         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 869         if (!res) {
 870                 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
 871                 return  -ENXIO;
 872         }
 873
 874         tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
 875                 resource_size(res));
 876         if (!tegra_phy->pad_regs) {
 877                 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
 878                 return -ENOMEM;
 879         }
 880
 881         tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
 882                                          GFP_KERNEL);
 883         if (!tegra_phy->config)
 884                 return -ENOMEM;
 885
 886         config = tegra_phy->config;
 887
 888         err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
 889                 &config->hssync_start_delay);
 890         if (err < 0)
 891                 return err;
 892
 893         err = read_utmi_param(pdev, "nvidia,elastic-limit",
 894                 &config->elastic_limit);
 895         if (err < 0)
 896                 return err;
 897
 898         err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
 899                 &config->idle_wait_delay);
 900         if (err < 0)
 901                 return err;
 902
 903         err = read_utmi_param(pdev, "nvidia,term-range-adj",
 904                 &config->term_range_adj);
 905         if (err < 0)
 906                 return err;
 907
 908         err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
 909                 &config->xcvr_lsfslew);
 910         if (err < 0)
 911                 return err;
 912
 913         err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
 914                 &config->xcvr_lsrslew);
 915         if (err < 0)
 916                 return err;
 917
 918         if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
 919                 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
 920                         &config->xcvr_hsslew);
 921                 if (err < 0)
 922                         return err;
 923
 924                 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
 925                         &config->hssquelch_level);
 926                 if (err < 0)
 927                         return err;
 928
 929                 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
 930                         &config->hsdiscon_level);
 931                 if (err < 0)
 932                         return err;
 933         }
 934
 935         config->xcvr_setup_use_fuses = of_property_read_bool(
 936                 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
 937
 938         if (!config->xcvr_setup_use_fuses) {
 939                 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
 940                         &config->xcvr_setup);
 941                 if (err < 0)
 942                         return err;
 943         }
 944
 945         return 0;
 946 }
 947
 948 static const struct tegra_phy_soc_config tegra20_soc_config = {
 949         .utmi_pll_config_in_car_module = false,
 950         .has_hostpc = false,
 951         .requires_usbmode_setup = false,
 952         .requires_extra_tuning_parameters = false,
 953 };
 954
 955 static const struct tegra_phy_soc_config tegra30_soc_config = {
 956         .utmi_pll_config_in_car_module = true,
 957         .has_hostpc = true,
 958         .requires_usbmode_setup = true,
 959         .requires_extra_tuning_parameters = true,
 960 };
 961
 962 static const struct of_device_id tegra_usb_phy_id_table[] = {
 963         { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
 964         { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
 965         { },
 966 };
 967 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
 968
 969 static int tegra_usb_phy_probe(struct platform_device *pdev)
 970 {
 971         const struct of_device_id *match;
 972         struct resource *res;
 973         struct tegra_usb_phy *tegra_phy = NULL;
 974         struct device_node *np = pdev->dev.of_node;
 975         enum usb_phy_interface phy_type;
 976         int err;
 977
 978         tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
 979         if (!tegra_phy)
 980                 return -ENOMEM;
 981
 982         match = of_match_device(tegra_usb_phy_id_table, &pdev->dev);
 983         if (!match) {
 984                 dev_err(&pdev->dev, "Error: No device match found\n");
 985                 return -ENODEV;
 986         }
 987         tegra_phy->soc_config = match->data;
 988
 989         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 990         if (!res) {
 991                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
 992                 return  -ENXIO;
 993         }
 994
 995         tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
 996                 resource_size(res));
 997         if (!tegra_phy->regs) {
 998                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
 999                 return -ENOMEM;
1000         }
1001
1002         tegra_phy->is_legacy_phy =
1003                 of_property_read_bool(np, "nvidia,has-legacy-mode");
1004
1005         phy_type = of_usb_get_phy_mode(np);
1006         switch (phy_type) {
1007         case USBPHY_INTERFACE_MODE_UTMI:
1008                 err = utmi_phy_probe(tegra_phy, pdev);
1009                 if (err < 0)
1010                         return err;
1011                 break;
1012
1013         case USBPHY_INTERFACE_MODE_ULPI:
1014                 tegra_phy->is_ulpi_phy = true;
1015
1016                 tegra_phy->reset_gpio =
1017                         of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
1018                 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
1019                         dev_err(&pdev->dev, "invalid gpio: %d\n",
1020                                 tegra_phy->reset_gpio);
1021                         return tegra_phy->reset_gpio;
1022                 }
1023                 tegra_phy->config = NULL;
1024                 break;
1025
1026         default:
1027                 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n");
1028                 return -EINVAL;
1029         }
1030
1031         if (of_find_property(np, "dr_mode", NULL))
1032                 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1033         else
1034                 tegra_phy->mode = USB_DR_MODE_HOST;
1035
1036         if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1037                 dev_err(&pdev->dev, "dr_mode is invalid\n");
1038                 return -EINVAL;
1039         }
1040
1041         /* On some boards, the VBUS regulator doesn't need to be controlled */
1042         if (of_find_property(np, "vbus-supply", NULL)) {
1043                 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1044                 if (IS_ERR(tegra_phy->vbus))
1045                         return PTR_ERR(tegra_phy->vbus);
1046         } else {
1047                 dev_notice(&pdev->dev, "no vbus regulator");
1048                 tegra_phy->vbus = ERR_PTR(-ENODEV);
1049         }
1050
1051         tegra_phy->u_phy.dev = &pdev->dev;
1052         err = tegra_usb_phy_init(tegra_phy);
1053         if (err < 0)
1054                 return err;
1055
1056         tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
1057
1058         platform_set_drvdata(pdev, tegra_phy);
1059
1060         err = usb_add_phy_dev(&tegra_phy->u_phy);
1061         if (err < 0) {
1062                 tegra_usb_phy_close(tegra_phy);
1063                 return err;
1064         }
1065
1066         return 0;
1067 }
1068
1069 static int tegra_usb_phy_remove(struct platform_device *pdev)
1070 {
1071         struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1072
1073         usb_remove_phy(&tegra_phy->u_phy);
1074         tegra_usb_phy_close(tegra_phy);
1075
1076         return 0;
1077 }
1078
1079 static struct platform_driver tegra_usb_phy_driver = {
1080         .probe          = tegra_usb_phy_probe,
1081         .remove         = tegra_usb_phy_remove,
1082         .driver         = {
1083                 .name   = "tegra-phy",
1084                 .of_match_table = tegra_usb_phy_id_table,
1085         },
1086 };
1087 module_platform_driver(tegra_usb_phy_driver);
1088
1089 MODULE_DESCRIPTION("Tegra USB PHY driver");
1090 MODULE_LICENSE("GPL v2");