2 * MUSB OTG driver host support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/list.h>
43 #include <linux/dma-mapping.h>
45 #include "musb_core.h"
46 #include "musb_host.h"
48 /* MUSB HOST status 22-mar-2006
50 * - There's still lots of partial code duplication for fault paths, so
51 * they aren't handled as consistently as they need to be.
53 * - PIO mostly behaved when last tested.
54 * + including ep0, with all usbtest cases 9, 10
55 * + usbtest 14 (ep0out) doesn't seem to run at all
56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
57 * configurations, but otherwise double buffering passes basic tests.
58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
60 * - DMA (CPPI) ... partially behaves, not currently recommended
61 * + about 1/15 the speed of typical EHCI implementations (PCI)
62 * + RX, all too often reqpkt seems to misbehave after tx
63 * + TX, no known issues (other than evident silicon issue)
65 * - DMA (Mentor/OMAP) ...has at least toggle update problems
67 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
68 * starvation ... nothing yet for TX, interrupt, or bulk.
70 * - Not tested with HNP, but some SRP paths seem to behave.
72 * NOTE 24-August-2006:
74 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
75 * extra endpoint for periodic use enabling hub + keybd + mouse. That
76 * mostly works, except that with "usbnet" it's easy to trigger cases
77 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
78 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
79 * although ARP RX wins. (That test was done with a full speed link.)
84 * NOTE on endpoint usage:
86 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
87 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
88 * (Yes, bulk _could_ use more of the endpoints than that, and would even
91 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
92 * So far that scheduling is both dumb and optimistic: the endpoint will be
93 * "claimed" until its software queue is no longer refilled. No multiplexing
94 * of transfers between endpoints, or anything clever.
97 struct musb *hcd_to_musb(struct usb_hcd *hcd)
99 return *(struct musb **) hcd->hcd_priv;
103 static void musb_ep_program(struct musb *musb, u8 epnum,
104 struct urb *urb, int is_out,
105 u8 *buf, u32 offset, u32 len);
108 * Clear TX fifo. Needed to avoid BABBLE errors.
110 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
112 struct musb *musb = ep->musb;
113 void __iomem *epio = ep->regs;
118 csr = musb_readw(epio, MUSB_TXCSR);
119 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
121 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
123 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY;
124 musb_writew(epio, MUSB_TXCSR, csr);
125 csr = musb_readw(epio, MUSB_TXCSR);
126 if (WARN(retries-- < 1,
127 "Could not flush host TX%d fifo: csr: %04x\n",
134 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
136 void __iomem *epio = ep->regs;
140 /* scrub any data left in the fifo */
142 csr = musb_readw(epio, MUSB_TXCSR);
143 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
145 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
146 csr = musb_readw(epio, MUSB_TXCSR);
150 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
153 /* and reset for the next transfer */
154 musb_writew(epio, MUSB_TXCSR, 0);
158 * Start transmit. Caller is responsible for locking shared resources.
159 * musb must be locked.
161 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
165 /* NOTE: no locks here; caller should lock and select EP */
167 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
168 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
169 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
171 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
172 musb_writew(ep->regs, MUSB_CSR0, txcsr);
177 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
181 /* NOTE: no locks here; caller should lock and select EP */
182 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
183 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
184 if (is_cppi_enabled(ep->musb))
185 txcsr |= MUSB_TXCSR_DMAMODE;
186 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
189 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
191 if (is_in != 0 || ep->is_shared_fifo)
193 if (is_in == 0 || ep->is_shared_fifo)
197 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
199 return is_in ? ep->in_qh : ep->out_qh;
203 * Start the URB at the front of an endpoint's queue
204 * end must be claimed from the caller.
206 * Context: controller locked, irqs blocked
209 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
213 void __iomem *mbase = musb->mregs;
214 struct urb *urb = next_urb(qh);
215 void *buf = urb->transfer_buffer;
217 struct musb_hw_ep *hw_ep = qh->hw_ep;
218 unsigned pipe = urb->pipe;
219 u8 address = usb_pipedevice(pipe);
220 int epnum = hw_ep->epnum;
222 /* initialize software qh state */
226 /* gather right source of data */
228 case USB_ENDPOINT_XFER_CONTROL:
229 /* control transfers always start with SETUP */
231 musb->ep0_stage = MUSB_EP0_START;
232 buf = urb->setup_packet;
235 case USB_ENDPOINT_XFER_ISOC:
238 offset = urb->iso_frame_desc[0].offset;
239 len = urb->iso_frame_desc[0].length;
241 default: /* bulk, interrupt */
242 /* actual_length may be nonzero on retry paths */
243 buf = urb->transfer_buffer + urb->actual_length;
244 len = urb->transfer_buffer_length - urb->actual_length;
247 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
248 qh, urb, address, qh->epnum,
249 is_in ? "in" : "out",
250 ({char *s; switch (qh->type) {
251 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
252 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
253 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
254 default: s = "-intr"; break;
256 epnum, buf + offset, len);
258 /* Configure endpoint */
259 musb_ep_set_qh(hw_ep, is_in, qh);
260 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
262 /* transmit may have more work: start it when it is time */
266 /* determine if the time is right for a periodic transfer */
268 case USB_ENDPOINT_XFER_ISOC:
269 case USB_ENDPOINT_XFER_INT:
270 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
271 frame = musb_readw(mbase, MUSB_FRAME);
272 /* FIXME this doesn't implement that scheduling policy ...
273 * or handle framecounter wrapping
275 if (1) { /* Always assume URB_ISO_ASAP */
276 /* REVISIT the SOF irq handler shouldn't duplicate
277 * this code; and we don't init urb->start_frame...
282 qh->frame = urb->start_frame;
283 /* enable SOF interrupt so we can count down */
284 dev_dbg(musb->controller, "SOF for %d\n", epnum);
285 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
286 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
292 dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
293 hw_ep->tx_channel ? "dma" : "pio");
295 if (!hw_ep->tx_channel)
296 musb_h_tx_start(hw_ep);
297 else if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
298 musb_h_tx_dma_start(hw_ep);
302 /* Context: caller owns controller lock, IRQs are blocked */
303 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
304 __releases(musb->lock)
305 __acquires(musb->lock)
307 dev_dbg(musb->controller,
308 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
309 urb, urb->complete, status,
310 usb_pipedevice(urb->pipe),
311 usb_pipeendpoint(urb->pipe),
312 usb_pipein(urb->pipe) ? "in" : "out",
313 urb->actual_length, urb->transfer_buffer_length
316 usb_hcd_unlink_urb_from_ep(musb->hcd, urb);
317 spin_unlock(&musb->lock);
318 usb_hcd_giveback_urb(musb->hcd, urb, status);
319 spin_lock(&musb->lock);
322 /* For bulk/interrupt endpoints only */
323 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
326 void __iomem *epio = qh->hw_ep->regs;
330 * FIXME: the current Mentor DMA code seems to have
331 * problems getting toggle correct.
335 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
337 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
339 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
343 * Advance this hardware endpoint's queue, completing the specified URB and
344 * advancing to either the next URB queued to that qh, or else invalidating
345 * that qh and advancing to the next qh scheduled after the current one.
347 * Context: caller owns controller lock, IRQs are blocked
349 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
350 struct musb_hw_ep *hw_ep, int is_in)
352 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
353 struct musb_hw_ep *ep = qh->hw_ep;
354 int ready = qh->is_ready;
357 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
359 /* save toggle eagerly, for paranoia */
361 case USB_ENDPOINT_XFER_BULK:
362 case USB_ENDPOINT_XFER_INT:
363 musb_save_toggle(qh, is_in, urb);
365 case USB_ENDPOINT_XFER_ISOC:
366 if (status == 0 && urb->error_count)
372 musb_giveback(musb, urb, status);
373 qh->is_ready = ready;
375 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
376 * invalidate qh as soon as list_empty(&hep->urb_list)
378 if (list_empty(&qh->hep->urb_list)) {
379 struct list_head *head;
380 struct dma_controller *dma = musb->dma_controller;
384 if (ep->rx_channel) {
385 dma->channel_release(ep->rx_channel);
386 ep->rx_channel = NULL;
390 if (ep->tx_channel) {
391 dma->channel_release(ep->tx_channel);
392 ep->tx_channel = NULL;
396 /* Clobber old pointers to this qh */
397 musb_ep_set_qh(ep, is_in, NULL);
398 qh->hep->hcpriv = NULL;
402 case USB_ENDPOINT_XFER_CONTROL:
403 case USB_ENDPOINT_XFER_BULK:
404 /* fifo policy for these lists, except that NAKing
405 * should rotate a qh to the end (for fairness).
408 head = qh->ring.prev;
415 case USB_ENDPOINT_XFER_ISOC:
416 case USB_ENDPOINT_XFER_INT:
417 /* this is where periodic bandwidth should be
418 * de-allocated if it's tracked and allocated;
419 * and where we'd update the schedule tree...
427 if (qh != NULL && qh->is_ready) {
428 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
429 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
430 musb_start_urb(musb, is_in, qh);
434 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
436 /* we don't want fifo to fill itself again;
437 * ignore dma (various models),
438 * leave toggle alone (may not have been saved yet)
440 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
441 csr &= ~(MUSB_RXCSR_H_REQPKT
442 | MUSB_RXCSR_H_AUTOREQ
443 | MUSB_RXCSR_AUTOCLEAR);
445 /* write 2x to allow double buffering */
446 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
449 /* flush writebuffer */
450 return musb_readw(hw_ep->regs, MUSB_RXCSR);
454 * PIO RX for a packet (or part of it).
457 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
465 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
466 void __iomem *epio = hw_ep->regs;
467 struct musb_qh *qh = hw_ep->in_qh;
468 int pipe = urb->pipe;
469 void *buffer = urb->transfer_buffer;
471 /* musb_ep_select(mbase, epnum); */
472 rx_count = musb_readw(epio, MUSB_RXCOUNT);
473 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
474 urb->transfer_buffer, qh->offset,
475 urb->transfer_buffer_length);
478 if (usb_pipeisoc(pipe)) {
480 struct usb_iso_packet_descriptor *d;
487 d = urb->iso_frame_desc + qh->iso_idx;
488 buf = buffer + d->offset;
490 if (rx_count > length) {
495 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
499 urb->actual_length += length;
500 d->actual_length = length;
504 /* see if we are done */
505 done = (++qh->iso_idx >= urb->number_of_packets);
508 buf = buffer + qh->offset;
509 length = urb->transfer_buffer_length - qh->offset;
510 if (rx_count > length) {
511 if (urb->status == -EINPROGRESS)
512 urb->status = -EOVERFLOW;
513 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
517 urb->actual_length += length;
518 qh->offset += length;
520 /* see if we are done */
521 done = (urb->actual_length == urb->transfer_buffer_length)
522 || (rx_count < qh->maxpacket)
523 || (urb->status != -EINPROGRESS);
525 && (urb->status == -EINPROGRESS)
526 && (urb->transfer_flags & URB_SHORT_NOT_OK)
527 && (urb->actual_length
528 < urb->transfer_buffer_length))
529 urb->status = -EREMOTEIO;
532 musb_read_fifo(hw_ep, length, buf);
534 csr = musb_readw(epio, MUSB_RXCSR);
535 csr |= MUSB_RXCSR_H_WZC_BITS;
536 if (unlikely(do_flush))
537 musb_h_flush_rxfifo(hw_ep, csr);
539 /* REVISIT this assumes AUTOCLEAR is never set */
540 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
542 csr |= MUSB_RXCSR_H_REQPKT;
543 musb_writew(epio, MUSB_RXCSR, csr);
549 /* we don't always need to reinit a given side of an endpoint...
550 * when we do, use tx/rx reinit routine and then construct a new CSR
551 * to address data toggle, NYET, and DMA or PIO.
553 * it's possible that driver bugs (especially for DMA) or aborting a
554 * transfer might have left the endpoint busier than it should be.
555 * the busy/not-empty tests are basically paranoia.
558 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
562 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
563 * That always uses tx_reinit since ep0 repurposes TX register
564 * offsets; the initial SETUP packet is also a kind of OUT.
567 /* if programmed for Tx, put it in RX mode */
568 if (ep->is_shared_fifo) {
569 csr = musb_readw(ep->regs, MUSB_TXCSR);
570 if (csr & MUSB_TXCSR_MODE) {
571 musb_h_tx_flush_fifo(ep);
572 csr = musb_readw(ep->regs, MUSB_TXCSR);
573 musb_writew(ep->regs, MUSB_TXCSR,
574 csr | MUSB_TXCSR_FRCDATATOG);
578 * Clear the MODE bit (and everything else) to enable Rx.
579 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
581 if (csr & MUSB_TXCSR_DMAMODE)
582 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
583 musb_writew(ep->regs, MUSB_TXCSR, 0);
585 /* scrub all previous state, clearing toggle */
587 csr = musb_readw(ep->regs, MUSB_RXCSR);
588 if (csr & MUSB_RXCSR_RXPKTRDY)
589 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
590 musb_readw(ep->regs, MUSB_RXCOUNT));
592 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
595 /* target addr and (for multipoint) hub addr/port */
596 if (musb->is_multipoint) {
597 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
598 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
599 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
602 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
604 /* protocol/endpoint, interval/NAKlimit, i/o size */
605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
607 /* NOTE: bulk combining rewrites high bits of maxpacket */
608 /* Set RXMAXP with the FIFO size of the endpoint
609 * to disable double buffer mode.
611 if (musb->double_buffer_not_ok)
612 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
614 musb_writew(ep->regs, MUSB_RXMAXP,
615 qh->maxpacket | ((qh->hb_mult - 1) << 11));
620 static int musb_tx_dma_set_mode_mentor(struct dma_controller *dma,
621 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
622 struct urb *urb, u32 offset,
623 u32 *length, u8 *mode)
625 struct dma_channel *channel = hw_ep->tx_channel;
626 void __iomem *epio = hw_ep->regs;
627 u16 pkt_size = qh->maxpacket;
630 if (*length > channel->max_len)
631 *length = channel->max_len;
633 csr = musb_readw(epio, MUSB_TXCSR);
634 if (*length > pkt_size) {
636 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
637 /* autoset shouldn't be set in high bandwidth */
639 * Enable Autoset according to table
641 * bulk_split hb_mult Autoset_Enable
643 * 0 >1 No(High BW ISO)
647 if (qh->hb_mult == 1 || (qh->hb_mult > 1 &&
648 can_bulk_split(hw_ep->musb, qh->type)))
649 csr |= MUSB_TXCSR_AUTOSET;
652 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
653 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
655 channel->desired_mode = mode;
656 musb_writew(epio, MUSB_TXCSR, csr);
661 static int musb_tx_dma_set_mode_cppi_tusb(struct dma_controller *dma,
662 struct musb_hw_ep *hw_ep,
669 struct dma_channel *channel = hw_ep->tx_channel;
671 if (!is_cppi_enabled(hw_ep->musb) && !tusb_dma_omap(hw_ep->musb))
674 channel->actual_len = 0;
677 * TX uses "RNDIS" mode automatically but needs help
678 * to identify the zero-length-final-packet case.
680 *mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
685 static bool musb_tx_dma_program(struct dma_controller *dma,
686 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
687 struct urb *urb, u32 offset, u32 length)
689 struct dma_channel *channel = hw_ep->tx_channel;
690 u16 pkt_size = qh->maxpacket;
694 if (musb_dma_inventra(hw_ep->musb) || musb_dma_ux500(hw_ep->musb))
695 res = musb_tx_dma_set_mode_mentor(dma, hw_ep, qh, urb,
696 offset, &length, &mode);
698 res = musb_tx_dma_set_mode_cppi_tusb(dma, hw_ep, qh, urb,
699 offset, &length, &mode);
703 qh->segsize = length;
706 * Ensure the data reaches to main memory before starting
711 if (!dma->channel_program(channel, pkt_size, mode,
712 urb->transfer_dma + offset, length)) {
713 void __iomem *epio = hw_ep->regs;
716 dma->channel_release(channel);
717 hw_ep->tx_channel = NULL;
719 csr = musb_readw(epio, MUSB_TXCSR);
720 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
721 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
728 * Program an HDRC endpoint as per the given URB
729 * Context: irqs blocked, controller lock held
731 static void musb_ep_program(struct musb *musb, u8 epnum,
732 struct urb *urb, int is_out,
733 u8 *buf, u32 offset, u32 len)
735 struct dma_controller *dma_controller;
736 struct dma_channel *dma_channel;
738 void __iomem *mbase = musb->mregs;
739 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
740 void __iomem *epio = hw_ep->regs;
741 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
742 u16 packet_sz = qh->maxpacket;
746 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
747 "h_addr%02x h_port%02x bytes %d\n",
748 is_out ? "-->" : "<--",
749 epnum, urb, urb->dev->speed,
750 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
751 qh->h_addr_reg, qh->h_port_reg,
754 musb_ep_select(mbase, epnum);
756 if (is_out && !len) {
758 csr = musb_readw(epio, MUSB_TXCSR);
759 csr &= ~MUSB_TXCSR_DMAENAB;
760 musb_writew(epio, MUSB_TXCSR, csr);
761 hw_ep->tx_channel = NULL;
764 /* candidate for DMA? */
765 dma_controller = musb->dma_controller;
766 if (use_dma && is_dma_capable() && epnum && dma_controller) {
767 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
769 dma_channel = dma_controller->channel_alloc(
770 dma_controller, hw_ep, is_out);
772 hw_ep->tx_channel = dma_channel;
774 hw_ep->rx_channel = dma_channel;
779 /* make sure we clear DMAEnab, autoSet bits from previous run */
781 /* OUT/transmit/EP0 or IN/receive? */
787 csr = musb_readw(epio, MUSB_TXCSR);
789 /* disable interrupt in case we flush */
790 int_txe = musb->intrtxe;
791 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
793 /* general endpoint setup */
795 /* flush all old state, set default */
797 * We could be flushing valid
798 * packets in double buffering
801 if (!hw_ep->tx_double_buffered)
802 musb_h_tx_flush_fifo(hw_ep);
805 * We must not clear the DMAMODE bit before or in
806 * the same cycle with the DMAENAB bit, so we clear
807 * the latter first...
809 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
812 | MUSB_TXCSR_FRCDATATOG
813 | MUSB_TXCSR_H_RXSTALL
815 | MUSB_TXCSR_TXPKTRDY
817 csr |= MUSB_TXCSR_MODE;
819 if (!hw_ep->tx_double_buffered) {
820 if (usb_gettoggle(urb->dev, qh->epnum, 1))
821 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
822 | MUSB_TXCSR_H_DATATOGGLE;
824 csr |= MUSB_TXCSR_CLRDATATOG;
827 musb_writew(epio, MUSB_TXCSR, csr);
828 /* REVISIT may need to clear FLUSHFIFO ... */
829 csr &= ~MUSB_TXCSR_DMAMODE;
830 musb_writew(epio, MUSB_TXCSR, csr);
831 csr = musb_readw(epio, MUSB_TXCSR);
833 /* endpoint 0: just flush */
834 musb_h_ep0_flush_fifo(hw_ep);
837 /* target addr and (for multipoint) hub addr/port */
838 if (musb->is_multipoint) {
839 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
840 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
841 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
842 /* FIXME if !epnum, do the same for RX ... */
844 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
846 /* protocol/endpoint/interval/NAKlimit */
848 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
849 if (musb->double_buffer_not_ok) {
850 musb_writew(epio, MUSB_TXMAXP,
851 hw_ep->max_packet_sz_tx);
852 } else if (can_bulk_split(musb, qh->type)) {
853 qh->hb_mult = hw_ep->max_packet_sz_tx
855 musb_writew(epio, MUSB_TXMAXP, packet_sz
856 | ((qh->hb_mult) - 1) << 11);
858 musb_writew(epio, MUSB_TXMAXP,
860 ((qh->hb_mult - 1) << 11));
862 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
864 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
865 if (musb->is_multipoint)
866 musb_writeb(epio, MUSB_TYPE0,
870 if (can_bulk_split(musb, qh->type))
871 load_count = min((u32) hw_ep->max_packet_sz_tx,
874 load_count = min((u32) packet_sz, len);
876 if (dma_channel && musb_tx_dma_program(dma_controller,
877 hw_ep, qh, urb, offset, len))
881 /* PIO to load FIFO */
882 qh->segsize = load_count;
884 sg_miter_start(&qh->sg_miter, urb->sg, 1,
887 if (!sg_miter_next(&qh->sg_miter)) {
888 dev_err(musb->controller,
891 sg_miter_stop(&qh->sg_miter);
894 buf = qh->sg_miter.addr + urb->sg->offset +
896 load_count = min_t(u32, load_count,
897 qh->sg_miter.length);
898 musb_write_fifo(hw_ep, load_count, buf);
899 qh->sg_miter.consumed = load_count;
900 sg_miter_stop(&qh->sg_miter);
902 musb_write_fifo(hw_ep, load_count, buf);
905 /* re-enable interrupt */
906 musb_writew(mbase, MUSB_INTRTXE, int_txe);
912 if (hw_ep->rx_reinit) {
913 musb_rx_reinit(musb, qh, hw_ep);
915 /* init new state: toggle and NYET, maybe DMA later */
916 if (usb_gettoggle(urb->dev, qh->epnum, 0))
917 csr = MUSB_RXCSR_H_WR_DATATOGGLE
918 | MUSB_RXCSR_H_DATATOGGLE;
921 if (qh->type == USB_ENDPOINT_XFER_INT)
922 csr |= MUSB_RXCSR_DISNYET;
925 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
927 if (csr & (MUSB_RXCSR_RXPKTRDY
929 | MUSB_RXCSR_H_REQPKT))
930 ERR("broken !rx_reinit, ep%d csr %04x\n",
933 /* scrub any stale state, leaving toggle alone */
934 csr &= MUSB_RXCSR_DISNYET;
937 /* kick things off */
939 if ((is_cppi_enabled(musb) || tusb_dma_omap(musb)) && dma_channel) {
940 /* Candidate for DMA */
941 dma_channel->actual_len = 0L;
944 /* AUTOREQ is in a DMA register */
945 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
946 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
949 * Unless caller treats short RX transfers as
950 * errors, we dare not queue multiple transfers.
952 dma_ok = dma_controller->channel_program(dma_channel,
953 packet_sz, !(urb->transfer_flags &
955 urb->transfer_dma + offset,
958 dma_controller->channel_release(dma_channel);
959 hw_ep->rx_channel = dma_channel = NULL;
961 csr |= MUSB_RXCSR_DMAENAB;
964 csr |= MUSB_RXCSR_H_REQPKT;
965 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
966 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
967 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
971 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
972 * the end; avoids starvation for other endpoints.
974 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
977 struct dma_channel *dma;
979 void __iomem *mbase = musb->mregs;
980 void __iomem *epio = ep->regs;
981 struct musb_qh *cur_qh, *next_qh;
984 musb_ep_select(mbase, ep->epnum);
986 dma = is_dma_capable() ? ep->rx_channel : NULL;
988 /* clear nak timeout bit */
989 rx_csr = musb_readw(epio, MUSB_RXCSR);
990 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
991 rx_csr &= ~MUSB_RXCSR_DATAERROR;
992 musb_writew(epio, MUSB_RXCSR, rx_csr);
994 cur_qh = first_qh(&musb->in_bulk);
996 dma = is_dma_capable() ? ep->tx_channel : NULL;
998 /* clear nak timeout bit */
999 tx_csr = musb_readw(epio, MUSB_TXCSR);
1000 tx_csr |= MUSB_TXCSR_H_WZC_BITS;
1001 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
1002 musb_writew(epio, MUSB_TXCSR, tx_csr);
1004 cur_qh = first_qh(&musb->out_bulk);
1007 urb = next_urb(cur_qh);
1008 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1009 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1010 musb->dma_controller->channel_abort(dma);
1011 urb->actual_length += dma->actual_len;
1012 dma->actual_len = 0L;
1014 musb_save_toggle(cur_qh, is_in, urb);
1017 /* move cur_qh to end of queue */
1018 list_move_tail(&cur_qh->ring, &musb->in_bulk);
1020 /* get the next qh from musb->in_bulk */
1021 next_qh = first_qh(&musb->in_bulk);
1023 /* set rx_reinit and schedule the next qh */
1026 /* move cur_qh to end of queue */
1027 list_move_tail(&cur_qh->ring, &musb->out_bulk);
1029 /* get the next qh from musb->out_bulk */
1030 next_qh = first_qh(&musb->out_bulk);
1032 /* set tx_reinit and schedule the next qh */
1035 musb_start_urb(musb, is_in, next_qh);
1040 * Service the default endpoint (ep0) as host.
1041 * Return true until it's time to start the status stage.
1043 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
1046 u8 *fifo_dest = NULL;
1048 struct musb_hw_ep *hw_ep = musb->control_ep;
1049 struct musb_qh *qh = hw_ep->in_qh;
1050 struct usb_ctrlrequest *request;
1052 switch (musb->ep0_stage) {
1054 fifo_dest = urb->transfer_buffer + urb->actual_length;
1055 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
1056 urb->actual_length);
1057 if (fifo_count < len)
1058 urb->status = -EOVERFLOW;
1060 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
1062 urb->actual_length += fifo_count;
1063 if (len < qh->maxpacket) {
1064 /* always terminate on short read; it's
1065 * rarely reported as an error.
1067 } else if (urb->actual_length <
1068 urb->transfer_buffer_length)
1071 case MUSB_EP0_START:
1072 request = (struct usb_ctrlrequest *) urb->setup_packet;
1074 if (!request->wLength) {
1075 dev_dbg(musb->controller, "start no-DATA\n");
1077 } else if (request->bRequestType & USB_DIR_IN) {
1078 dev_dbg(musb->controller, "start IN-DATA\n");
1079 musb->ep0_stage = MUSB_EP0_IN;
1083 dev_dbg(musb->controller, "start OUT-DATA\n");
1084 musb->ep0_stage = MUSB_EP0_OUT;
1089 fifo_count = min_t(size_t, qh->maxpacket,
1090 urb->transfer_buffer_length -
1091 urb->actual_length);
1093 fifo_dest = (u8 *) (urb->transfer_buffer
1094 + urb->actual_length);
1095 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
1097 (fifo_count == 1) ? "" : "s",
1099 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
1101 urb->actual_length += fifo_count;
1106 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
1114 * Handle default endpoint interrupt as host. Only called in IRQ time
1115 * from musb_interrupt().
1117 * called with controller irqlocked
1119 irqreturn_t musb_h_ep0_irq(struct musb *musb)
1124 void __iomem *mbase = musb->mregs;
1125 struct musb_hw_ep *hw_ep = musb->control_ep;
1126 void __iomem *epio = hw_ep->regs;
1127 struct musb_qh *qh = hw_ep->in_qh;
1128 bool complete = false;
1129 irqreturn_t retval = IRQ_NONE;
1131 /* ep0 only has one queue, "in" */
1134 musb_ep_select(mbase, 0);
1135 csr = musb_readw(epio, MUSB_CSR0);
1136 len = (csr & MUSB_CSR0_RXPKTRDY)
1137 ? musb_readb(epio, MUSB_COUNT0)
1140 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1141 csr, qh, len, urb, musb->ep0_stage);
1143 /* if we just did status stage, we are done */
1144 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1145 retval = IRQ_HANDLED;
1149 /* prepare status */
1150 if (csr & MUSB_CSR0_H_RXSTALL) {
1151 dev_dbg(musb->controller, "STALLING ENDPOINT\n");
1154 } else if (csr & MUSB_CSR0_H_ERROR) {
1155 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
1158 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1159 dev_dbg(musb->controller, "control NAK timeout\n");
1161 /* NOTE: this code path would be a good place to PAUSE a
1162 * control transfer, if another one is queued, so that
1163 * ep0 is more likely to stay busy. That's already done
1164 * for bulk RX transfers.
1166 * if (qh->ring.next != &musb->control), then
1167 * we have a candidate... NAKing is *NOT* an error
1169 musb_writew(epio, MUSB_CSR0, 0);
1170 retval = IRQ_HANDLED;
1174 dev_dbg(musb->controller, "aborting\n");
1175 retval = IRQ_HANDLED;
1177 urb->status = status;
1180 /* use the proper sequence to abort the transfer */
1181 if (csr & MUSB_CSR0_H_REQPKT) {
1182 csr &= ~MUSB_CSR0_H_REQPKT;
1183 musb_writew(epio, MUSB_CSR0, csr);
1184 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1185 musb_writew(epio, MUSB_CSR0, csr);
1187 musb_h_ep0_flush_fifo(hw_ep);
1190 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1193 musb_writew(epio, MUSB_CSR0, 0);
1196 if (unlikely(!urb)) {
1197 /* stop endpoint since we have no place for its data, this
1198 * SHOULD NEVER HAPPEN! */
1199 ERR("no URB for end 0\n");
1201 musb_h_ep0_flush_fifo(hw_ep);
1206 /* call common logic and prepare response */
1207 if (musb_h_ep0_continue(musb, len, urb)) {
1208 /* more packets required */
1209 csr = (MUSB_EP0_IN == musb->ep0_stage)
1210 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1212 /* data transfer complete; perform status phase */
1213 if (usb_pipeout(urb->pipe)
1214 || !urb->transfer_buffer_length)
1215 csr = MUSB_CSR0_H_STATUSPKT
1216 | MUSB_CSR0_H_REQPKT;
1218 csr = MUSB_CSR0_H_STATUSPKT
1219 | MUSB_CSR0_TXPKTRDY;
1221 /* disable ping token in status phase */
1222 csr |= MUSB_CSR0_H_DIS_PING;
1224 /* flag status stage */
1225 musb->ep0_stage = MUSB_EP0_STATUS;
1227 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
1230 musb_writew(epio, MUSB_CSR0, csr);
1231 retval = IRQ_HANDLED;
1233 musb->ep0_stage = MUSB_EP0_IDLE;
1235 /* call completion handler if done */
1237 musb_advance_schedule(musb, urb, hw_ep, 1);
1243 #ifdef CONFIG_USB_INVENTRA_DMA
1245 /* Host side TX (OUT) using Mentor DMA works as follows:
1247 - if queue was empty, Program Endpoint
1248 - ... which starts DMA to fifo in mode 1 or 0
1250 DMA Isr (transfer complete) -> TxAvail()
1251 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1252 only in musb_cleanup_urb)
1253 - TxPktRdy has to be set in mode 0 or for
1254 short packets in mode 1.
1259 /* Service a Tx-Available or dma completion irq for the endpoint */
1260 void musb_host_tx(struct musb *musb, u8 epnum)
1267 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1268 void __iomem *epio = hw_ep->regs;
1269 struct musb_qh *qh = hw_ep->out_qh;
1270 struct urb *urb = next_urb(qh);
1272 void __iomem *mbase = musb->mregs;
1273 struct dma_channel *dma;
1274 bool transfer_pending = false;
1276 musb_ep_select(mbase, epnum);
1277 tx_csr = musb_readw(epio, MUSB_TXCSR);
1279 /* with CPPI, DMA sometimes triggers "extra" irqs */
1281 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1286 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1287 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1288 dma ? ", dma" : "");
1290 /* check for errors */
1291 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1292 /* dma was disabled, fifo flushed */
1293 dev_dbg(musb->controller, "TX end %d stall\n", epnum);
1295 /* stall; record URB status */
1298 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1299 /* (NON-ISO) dma was disabled, fifo flushed */
1300 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
1302 status = -ETIMEDOUT;
1304 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1305 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
1306 && !list_is_singular(&musb->out_bulk)) {
1307 dev_dbg(musb->controller,
1308 "NAK timeout on TX%d ep\n", epnum);
1309 musb_bulk_nak_timeout(musb, hw_ep, 0);
1311 dev_dbg(musb->controller,
1312 "TX end=%d device not responding\n", epnum);
1313 /* NOTE: this code path would be a good place to PAUSE a
1314 * transfer, if there's some other (nonperiodic) tx urb
1315 * that could use this fifo. (dma complicates it...)
1316 * That's already done for bulk RX transfers.
1318 * if (bulk && qh->ring.next != &musb->out_bulk), then
1319 * we have a candidate... NAKing is *NOT* an error
1321 musb_ep_select(mbase, epnum);
1322 musb_writew(epio, MUSB_TXCSR,
1323 MUSB_TXCSR_H_WZC_BITS
1324 | MUSB_TXCSR_TXPKTRDY);
1331 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1332 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1333 musb->dma_controller->channel_abort(dma);
1336 /* do the proper sequence to abort the transfer in the
1337 * usb core; the dma engine should already be stopped.
1339 musb_h_tx_flush_fifo(hw_ep);
1340 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1341 | MUSB_TXCSR_DMAENAB
1342 | MUSB_TXCSR_H_ERROR
1343 | MUSB_TXCSR_H_RXSTALL
1344 | MUSB_TXCSR_H_NAKTIMEOUT
1347 musb_ep_select(mbase, epnum);
1348 musb_writew(epio, MUSB_TXCSR, tx_csr);
1349 /* REVISIT may need to clear FLUSHFIFO ... */
1350 musb_writew(epio, MUSB_TXCSR, tx_csr);
1351 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1356 /* second cppi case */
1357 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1358 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1362 if (is_dma_capable() && dma && !status) {
1364 * DMA has completed. But if we're using DMA mode 1 (multi
1365 * packet DMA), we need a terminal TXPKTRDY interrupt before
1366 * we can consider this transfer completed, lest we trash
1367 * its last packet when writing the next URB's data. So we
1368 * switch back to mode 0 to get that interrupt; we'll come
1369 * back here once it happens.
1371 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1373 * We shouldn't clear DMAMODE with DMAENAB set; so
1374 * clear them in a safe order. That should be OK
1375 * once TXPKTRDY has been set (and I've never seen
1376 * it being 0 at this moment -- DMA interrupt latency
1377 * is significant) but if it hasn't been then we have
1378 * no choice but to stop being polite and ignore the
1379 * programmer's guide... :-)
1381 * Note that we must write TXCSR with TXPKTRDY cleared
1382 * in order not to re-trigger the packet send (this bit
1383 * can't be cleared by CPU), and there's another caveat:
1384 * TXPKTRDY may be set shortly and then cleared in the
1385 * double-buffered FIFO mode, so we do an extra TXCSR
1386 * read for debouncing...
1388 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1389 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1390 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1391 MUSB_TXCSR_TXPKTRDY);
1392 musb_writew(epio, MUSB_TXCSR,
1393 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1395 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1396 MUSB_TXCSR_TXPKTRDY);
1397 musb_writew(epio, MUSB_TXCSR,
1398 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1401 * There is no guarantee that we'll get an interrupt
1402 * after clearing DMAMODE as we might have done this
1403 * too late (after TXPKTRDY was cleared by controller).
1404 * Re-read TXCSR as we have spoiled its previous value.
1406 tx_csr = musb_readw(epio, MUSB_TXCSR);
1410 * We may get here from a DMA completion or TXPKTRDY interrupt.
1411 * In any case, we must check the FIFO status here and bail out
1412 * only if the FIFO still has data -- that should prevent the
1413 * "missed" TXPKTRDY interrupts and deal with double-buffered
1416 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1417 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
1418 "CSR %04x\n", tx_csr);
1423 if (!status || dma || usb_pipeisoc(pipe)) {
1425 length = dma->actual_len;
1427 length = qh->segsize;
1428 qh->offset += length;
1430 if (usb_pipeisoc(pipe)) {
1431 struct usb_iso_packet_descriptor *d;
1433 d = urb->iso_frame_desc + qh->iso_idx;
1434 d->actual_length = length;
1436 if (++qh->iso_idx >= urb->number_of_packets) {
1443 } else if (dma && urb->transfer_buffer_length == qh->offset) {
1446 /* see if we need to send more data, or ZLP */
1447 if (qh->segsize < qh->maxpacket)
1449 else if (qh->offset == urb->transfer_buffer_length
1450 && !(urb->transfer_flags
1454 offset = qh->offset;
1455 length = urb->transfer_buffer_length - offset;
1456 transfer_pending = true;
1461 /* urb->status != -EINPROGRESS means request has been faulted,
1462 * so we must abort this transfer after cleanup
1464 if (urb->status != -EINPROGRESS) {
1467 status = urb->status;
1472 urb->status = status;
1473 urb->actual_length = qh->offset;
1474 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1476 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1477 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1479 if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
1480 musb_h_tx_dma_start(hw_ep);
1483 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1484 dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
1489 * PIO: start next packet in this URB.
1491 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1492 * (and presumably, FIFO is not half-full) we should write *two*
1493 * packets before updating TXCSR; other docs disagree...
1495 if (length > qh->maxpacket)
1496 length = qh->maxpacket;
1497 /* Unmap the buffer so that CPU can use it */
1498 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1501 * We need to map sg if the transfer_buffer is
1504 if (!urb->transfer_buffer)
1508 /* sg_miter_start is already done in musb_ep_program */
1509 if (!sg_miter_next(&qh->sg_miter)) {
1510 dev_err(musb->controller, "error: sg list empty\n");
1511 sg_miter_stop(&qh->sg_miter);
1515 urb->transfer_buffer = qh->sg_miter.addr;
1516 length = min_t(u32, length, qh->sg_miter.length);
1517 musb_write_fifo(hw_ep, length, urb->transfer_buffer);
1518 qh->sg_miter.consumed = length;
1519 sg_miter_stop(&qh->sg_miter);
1521 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1524 qh->segsize = length;
1527 if (offset + length >= urb->transfer_buffer_length)
1531 musb_ep_select(mbase, epnum);
1532 musb_writew(epio, MUSB_TXCSR,
1533 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1536 #ifdef CONFIG_USB_TI_CPPI41_DMA
1537 /* Seems to set up ISO for cppi41 and not advance len. See commit c57c41d */
1538 static int musb_rx_dma_iso_cppi41(struct dma_controller *dma,
1539 struct musb_hw_ep *hw_ep,
1544 struct dma_channel *channel = hw_ep->tx_channel;
1545 void __iomem *epio = hw_ep->regs;
1550 buf = (void *)urb->iso_frame_desc[qh->iso_idx].offset +
1551 (u32)urb->transfer_dma;
1553 length = urb->iso_frame_desc[qh->iso_idx].length;
1555 val = musb_readw(epio, MUSB_RXCSR);
1556 val |= MUSB_RXCSR_DMAENAB;
1557 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1559 res = dma->channel_program(channel, qh->maxpacket, 0,
1565 static inline int musb_rx_dma_iso_cppi41(struct dma_controller *dma,
1566 struct musb_hw_ep *hw_ep,
1575 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \
1576 defined(CONFIG_USB_TI_CPPI41_DMA)
1577 /* Host side RX (IN) using Mentor DMA works as follows:
1579 - if queue was empty, ProgramEndpoint
1580 - first IN token is sent out (by setting ReqPkt)
1581 LinuxIsr -> RxReady()
1582 /\ => first packet is received
1583 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1584 | -> DMA Isr (transfer complete) -> RxReady()
1585 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1586 | - if urb not complete, send next IN token (ReqPkt)
1587 | | else complete urb.
1589 ---------------------------
1591 * Nuances of mode 1:
1592 * For short packets, no ack (+RxPktRdy) is sent automatically
1593 * (even if AutoClear is ON)
1594 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1595 * automatically => major problem, as collecting the next packet becomes
1596 * difficult. Hence mode 1 is not used.
1599 * All we care about at this driver level is that
1600 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1601 * (b) termination conditions are: short RX, or buffer full;
1602 * (c) fault modes include
1603 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1604 * (and that endpoint's dma queue stops immediately)
1605 * - overflow (full, PLUS more bytes in the terminal packet)
1607 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1608 * thus be a great candidate for using mode 1 ... for all but the
1609 * last packet of one URB's transfer.
1611 static int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
1612 struct musb_hw_ep *hw_ep,
1617 struct dma_channel *channel = hw_ep->rx_channel;
1618 void __iomem *epio = hw_ep->regs;
1625 if (usb_pipeisoc(pipe)) {
1626 struct usb_iso_packet_descriptor *d;
1628 d = urb->iso_frame_desc + qh->iso_idx;
1629 d->actual_length = len;
1631 /* even if there was an error, we did the dma
1632 * for iso_frame_desc->length
1634 if (d->status != -EILSEQ && d->status != -EOVERFLOW)
1637 if (++qh->iso_idx >= urb->number_of_packets) {
1640 /* REVISIT: Why ignore return value here? */
1641 if (musb_dma_cppi41(hw_ep->musb))
1642 done = musb_rx_dma_iso_cppi41(dma, hw_ep, qh,
1648 /* done if urb buffer is full or short packet is recd */
1649 done = (urb->actual_length + len >=
1650 urb->transfer_buffer_length
1651 || channel->actual_len < qh->maxpacket
1652 || channel->rx_packet_done);
1655 /* send IN token for next packet, without AUTOREQ */
1657 val = musb_readw(epio, MUSB_RXCSR);
1658 val |= MUSB_RXCSR_H_REQPKT;
1659 musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
1665 static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
1666 struct musb_hw_ep *hw_ep,
1676 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1677 * and high-bandwidth IN transfer cases.
1679 void musb_host_rx(struct musb *musb, u8 epnum)
1682 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1683 struct dma_controller *c = musb->dma_controller;
1684 void __iomem *epio = hw_ep->regs;
1685 struct musb_qh *qh = hw_ep->in_qh;
1687 void __iomem *mbase = musb->mregs;
1690 bool iso_err = false;
1693 struct dma_channel *dma;
1694 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
1696 musb_ep_select(mbase, epnum);
1699 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1703 rx_csr = musb_readw(epio, MUSB_RXCSR);
1706 if (unlikely(!urb)) {
1707 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1708 * usbtest #11 (unlinks) triggers it regularly, sometimes
1709 * with fifo full. (Only with DMA??)
1711 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1712 musb_readw(epio, MUSB_RXCOUNT));
1713 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1719 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1720 epnum, rx_csr, urb->actual_length,
1721 dma ? dma->actual_len : 0);
1723 /* check for errors, concurrent stall & unlink is not really
1725 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1726 dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
1728 /* stall; record URB status */
1731 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1732 dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
1735 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1737 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1739 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1740 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
1742 /* NOTE: NAKing is *NOT* an error, so we want to
1743 * continue. Except ... if there's a request for
1744 * another QH, use that instead of starving it.
1746 * Devices like Ethernet and serial adapters keep
1747 * reads posted at all times, which will starve
1748 * other devices without this logic.
1750 if (usb_pipebulk(urb->pipe)
1752 && !list_is_singular(&musb->in_bulk)) {
1753 musb_bulk_nak_timeout(musb, hw_ep, 1);
1756 musb_ep_select(mbase, epnum);
1757 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1758 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1759 musb_writew(epio, MUSB_RXCSR, rx_csr);
1763 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
1764 /* packet error reported later */
1767 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1768 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
1773 /* faults abort the transfer */
1775 /* clean up dma and collect transfer count */
1776 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1777 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1778 musb->dma_controller->channel_abort(dma);
1779 xfer_len = dma->actual_len;
1781 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1782 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1787 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1788 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1789 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1793 /* thorough shutdown for now ... given more precise fault handling
1794 * and better queueing support, we might keep a DMA pipeline going
1795 * while processing this irq for earlier completions.
1798 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1799 if (!musb_dma_inventra(musb) && !musb_dma_ux500(musb) &&
1800 (rx_csr & MUSB_RXCSR_H_REQPKT)) {
1801 /* REVISIT this happened for a while on some short reads...
1802 * the cleanup still needs investigation... looks bad...
1803 * and also duplicates dma cleanup code above ... plus,
1804 * shouldn't this be the "half full" double buffer case?
1806 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1807 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1808 musb->dma_controller->channel_abort(dma);
1809 xfer_len = dma->actual_len;
1813 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1814 xfer_len, dma ? ", dma" : "");
1815 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1817 musb_ep_select(mbase, epnum);
1818 musb_writew(epio, MUSB_RXCSR,
1819 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1822 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1823 xfer_len = dma->actual_len;
1825 val &= ~(MUSB_RXCSR_DMAENAB
1826 | MUSB_RXCSR_H_AUTOREQ
1827 | MUSB_RXCSR_AUTOCLEAR
1828 | MUSB_RXCSR_RXPKTRDY);
1829 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1831 if (musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
1832 musb_dma_cppi41(musb)) {
1833 done = musb_rx_dma_inventra_cppi41(c, hw_ep, qh, urb, xfer_len);
1834 dev_dbg(hw_ep->musb->controller,
1835 "ep %d dma %s, rxcsr %04x, rxcount %d\n",
1836 epnum, done ? "off" : "reset",
1837 musb_readw(epio, MUSB_RXCSR),
1838 musb_readw(epio, MUSB_RXCOUNT));
1843 } else if (urb->status == -EINPROGRESS) {
1844 /* if no errors, be sure a packet is ready for unloading */
1845 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1847 ERR("Rx interrupt with no errors or packet!\n");
1849 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1852 /* do the proper sequence to abort the transfer */
1853 musb_ep_select(mbase, epnum);
1854 val &= ~MUSB_RXCSR_H_REQPKT;
1855 musb_writew(epio, MUSB_RXCSR, val);
1859 /* we are expecting IN packets */
1860 if ((musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
1861 musb_dma_cppi41(musb)) && dma) {
1862 struct dma_controller *c;
1867 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1869 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%llx len %d/%d\n",
1871 (unsigned long long) urb->transfer_dma
1872 + urb->actual_length,
1874 urb->transfer_buffer_length);
1876 c = musb->dma_controller;
1878 if (usb_pipeisoc(pipe)) {
1880 struct usb_iso_packet_descriptor *d;
1882 d = urb->iso_frame_desc + qh->iso_idx;
1888 if (rx_count > d->length) {
1889 if (d_status == 0) {
1890 d_status = -EOVERFLOW;
1893 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
1894 rx_count, d->length);
1899 d->status = d_status;
1900 buf = urb->transfer_dma + d->offset;
1903 buf = urb->transfer_dma +
1907 dma->desired_mode = 0;
1909 /* because of the issue below, mode 1 will
1910 * only rarely behave with correct semantics.
1912 if ((urb->transfer_flags &
1914 && (urb->transfer_buffer_length -
1917 dma->desired_mode = 1;
1918 if (rx_count < hw_ep->max_packet_sz_rx) {
1920 dma->desired_mode = 0;
1922 length = urb->transfer_buffer_length;
1926 /* Disadvantage of using mode 1:
1927 * It's basically usable only for mass storage class; essentially all
1928 * other protocols also terminate transfers on short packets.
1931 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1932 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1933 * to use the extra IN token to grab the last packet using mode 0, then
1934 * the problem is that you cannot be sure when the device will send the
1935 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1936 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1937 * transfer, while sometimes it is recd just a little late so that if you
1938 * try to configure for mode 0 soon after the mode 1 transfer is
1939 * completed, you will find rxcount 0. Okay, so you might think why not
1940 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1943 val = musb_readw(epio, MUSB_RXCSR);
1944 val &= ~MUSB_RXCSR_H_REQPKT;
1946 if (dma->desired_mode == 0)
1947 val &= ~MUSB_RXCSR_H_AUTOREQ;
1949 val |= MUSB_RXCSR_H_AUTOREQ;
1950 val |= MUSB_RXCSR_DMAENAB;
1952 /* autoclear shouldn't be set in high bandwidth */
1953 if (qh->hb_mult == 1)
1954 val |= MUSB_RXCSR_AUTOCLEAR;
1956 musb_writew(epio, MUSB_RXCSR,
1957 MUSB_RXCSR_H_WZC_BITS | val);
1959 /* REVISIT if when actual_length != 0,
1960 * transfer_buffer_length needs to be
1963 ret = c->channel_program(
1965 dma->desired_mode, buf, length);
1968 c->channel_release(dma);
1969 hw_ep->rx_channel = NULL;
1971 val = musb_readw(epio, MUSB_RXCSR);
1972 val &= ~(MUSB_RXCSR_DMAENAB
1973 | MUSB_RXCSR_H_AUTOREQ
1974 | MUSB_RXCSR_AUTOCLEAR);
1975 musb_writew(epio, MUSB_RXCSR, val);
1980 unsigned int received_len;
1982 /* Unmap the buffer so that CPU can use it */
1983 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1986 * We need to map sg if the transfer_buffer is
1989 if (!urb->transfer_buffer) {
1991 sg_miter_start(&qh->sg_miter, urb->sg, 1,
1996 if (!sg_miter_next(&qh->sg_miter)) {
1997 dev_err(musb->controller, "error: sg list empty\n");
1998 sg_miter_stop(&qh->sg_miter);
2003 urb->transfer_buffer = qh->sg_miter.addr;
2004 received_len = urb->actual_length;
2006 done = musb_host_packet_rx(musb, urb, epnum,
2008 /* Calculate the number of bytes received */
2009 received_len = urb->actual_length -
2011 qh->sg_miter.consumed = received_len;
2012 sg_miter_stop(&qh->sg_miter);
2014 done = musb_host_packet_rx(musb, urb,
2017 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
2022 urb->actual_length += xfer_len;
2023 qh->offset += xfer_len;
2028 if (urb->status == -EINPROGRESS)
2029 urb->status = status;
2030 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
2034 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
2035 * the software schedule associates multiple such nodes with a given
2036 * host side hardware endpoint + direction; scheduling may activate
2037 * that hardware endpoint.
2039 static int musb_schedule(
2046 int best_end, epnum;
2047 struct musb_hw_ep *hw_ep = NULL;
2048 struct list_head *head = NULL;
2051 struct urb *urb = next_urb(qh);
2053 /* use fixed hardware for control and bulk */
2054 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
2055 head = &musb->control;
2056 hw_ep = musb->control_ep;
2060 /* else, periodic transfers get muxed to other endpoints */
2063 * We know this qh hasn't been scheduled, so all we need to do
2064 * is choose which hardware endpoint to put it on ...
2066 * REVISIT what we really want here is a regular schedule tree
2067 * like e.g. OHCI uses.
2072 for (epnum = 1, hw_ep = musb->endpoints + 1;
2073 epnum < musb->nr_endpoints;
2077 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
2080 if (hw_ep == musb->bulk_ep)
2084 diff = hw_ep->max_packet_sz_rx;
2086 diff = hw_ep->max_packet_sz_tx;
2087 diff -= (qh->maxpacket * qh->hb_mult);
2089 if (diff >= 0 && best_diff > diff) {
2092 * Mentor controller has a bug in that if we schedule
2093 * a BULK Tx transfer on an endpoint that had earlier
2094 * handled ISOC then the BULK transfer has to start on
2095 * a zero toggle. If the BULK transfer starts on a 1
2096 * toggle then this transfer will fail as the mentor
2097 * controller starts the Bulk transfer on a 0 toggle
2098 * irrespective of the programming of the toggle bits
2099 * in the TXCSR register. Check for this condition
2100 * while allocating the EP for a Tx Bulk transfer. If
2103 hw_ep = musb->endpoints + epnum;
2104 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
2105 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
2107 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
2108 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
2115 /* use bulk reserved ep1 if no other ep is free */
2116 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
2117 hw_ep = musb->bulk_ep;
2119 head = &musb->in_bulk;
2121 head = &musb->out_bulk;
2123 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are
2124 * multiplexed. This scheme does not work in high speed to full
2125 * speed scenario as NAK interrupts are not coming from a
2126 * full speed device connected to a high speed device.
2127 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
2128 * 4 (8 frame or 8ms) for FS device.
2132 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
2134 } else if (best_end < 0) {
2140 hw_ep = musb->endpoints + best_end;
2141 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
2144 idle = list_empty(head);
2145 list_add_tail(&qh->ring, head);
2149 qh->hep->hcpriv = qh;
2151 musb_start_urb(musb, is_in, qh);
2155 static int musb_urb_enqueue(
2156 struct usb_hcd *hcd,
2160 unsigned long flags;
2161 struct musb *musb = hcd_to_musb(hcd);
2162 struct usb_host_endpoint *hep = urb->ep;
2164 struct usb_endpoint_descriptor *epd = &hep->desc;
2169 /* host role must be active */
2170 if (!is_host_active(musb) || !musb->is_active)
2173 spin_lock_irqsave(&musb->lock, flags);
2174 ret = usb_hcd_link_urb_to_ep(hcd, urb);
2175 qh = ret ? NULL : hep->hcpriv;
2178 spin_unlock_irqrestore(&musb->lock, flags);
2180 /* DMA mapping was already done, if needed, and this urb is on
2181 * hep->urb_list now ... so we're done, unless hep wasn't yet
2182 * scheduled onto a live qh.
2184 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
2185 * disabled, testing for empty qh->ring and avoiding qh setup costs
2186 * except for the first urb queued after a config change.
2191 /* Allocate and initialize qh, minimizing the work done each time
2192 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
2194 * REVISIT consider a dedicated qh kmem_cache, so it's harder
2195 * for bugs in other kernel code to break this driver...
2197 qh = kzalloc(sizeof *qh, mem_flags);
2199 spin_lock_irqsave(&musb->lock, flags);
2200 usb_hcd_unlink_urb_from_ep(hcd, urb);
2201 spin_unlock_irqrestore(&musb->lock, flags);
2207 INIT_LIST_HEAD(&qh->ring);
2210 qh->maxpacket = usb_endpoint_maxp(epd);
2211 qh->type = usb_endpoint_type(epd);
2213 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
2214 * Some musb cores don't support high bandwidth ISO transfers; and
2215 * we don't (yet!) support high bandwidth interrupt transfers.
2217 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
2218 if (qh->hb_mult > 1) {
2219 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
2222 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
2223 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
2228 qh->maxpacket &= 0x7ff;
2231 qh->epnum = usb_endpoint_num(epd);
2233 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
2234 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
2236 /* precompute rxtype/txtype/type0 register */
2237 type_reg = (qh->type << 4) | qh->epnum;
2238 switch (urb->dev->speed) {
2242 case USB_SPEED_FULL:
2248 qh->type_reg = type_reg;
2250 /* Precompute RXINTERVAL/TXINTERVAL register */
2252 case USB_ENDPOINT_XFER_INT:
2254 * Full/low speeds use the linear encoding,
2255 * high speed uses the logarithmic encoding.
2257 if (urb->dev->speed <= USB_SPEED_FULL) {
2258 interval = max_t(u8, epd->bInterval, 1);
2262 case USB_ENDPOINT_XFER_ISOC:
2263 /* ISO always uses logarithmic encoding */
2264 interval = min_t(u8, epd->bInterval, 16);
2267 /* REVISIT we actually want to use NAK limits, hinting to the
2268 * transfer scheduling logic to try some other qh, e.g. try
2271 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2273 * The downside of disabling this is that transfer scheduling
2274 * gets VERY unfair for nonperiodic transfers; a misbehaving
2275 * peripheral could make that hurt. That's perfectly normal
2276 * for reads from network or serial adapters ... so we have
2277 * partial NAKlimit support for bulk RX.
2279 * The upside of disabling it is simpler transfer scheduling.
2283 qh->intv_reg = interval;
2285 /* precompute addressing for external hub/tt ports */
2286 if (musb->is_multipoint) {
2287 struct usb_device *parent = urb->dev->parent;
2289 if (parent != hcd->self.root_hub) {
2290 qh->h_addr_reg = (u8) parent->devnum;
2292 /* set up tt info if needed */
2294 qh->h_port_reg = (u8) urb->dev->ttport;
2295 if (urb->dev->tt->hub)
2297 (u8) urb->dev->tt->hub->devnum;
2298 if (urb->dev->tt->multi)
2299 qh->h_addr_reg |= 0x80;
2304 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2305 * until we get real dma queues (with an entry for each urb/buffer),
2306 * we only have work to do in the former case.
2308 spin_lock_irqsave(&musb->lock, flags);
2309 if (hep->hcpriv || !next_urb(qh)) {
2310 /* some concurrent activity submitted another urb to hep...
2311 * odd, rare, error prone, but legal.
2317 ret = musb_schedule(musb, qh,
2318 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2322 /* FIXME set urb->start_frame for iso/intr, it's tested in
2323 * musb_start_urb(), but otherwise only konicawc cares ...
2326 spin_unlock_irqrestore(&musb->lock, flags);
2330 spin_lock_irqsave(&musb->lock, flags);
2331 usb_hcd_unlink_urb_from_ep(hcd, urb);
2332 spin_unlock_irqrestore(&musb->lock, flags);
2340 * abort a transfer that's at the head of a hardware queue.
2341 * called with controller locked, irqs blocked
2342 * that hardware queue advances to the next transfer, unless prevented
2344 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2346 struct musb_hw_ep *ep = qh->hw_ep;
2347 struct musb *musb = ep->musb;
2348 void __iomem *epio = ep->regs;
2349 unsigned hw_end = ep->epnum;
2350 void __iomem *regs = ep->musb->mregs;
2351 int is_in = usb_pipein(urb->pipe);
2355 musb_ep_select(regs, hw_end);
2357 if (is_dma_capable()) {
2358 struct dma_channel *dma;
2360 dma = is_in ? ep->rx_channel : ep->tx_channel;
2362 status = ep->musb->dma_controller->channel_abort(dma);
2363 dev_dbg(musb->controller,
2364 "abort %cX%d DMA for urb %p --> %d\n",
2365 is_in ? 'R' : 'T', ep->epnum,
2367 urb->actual_length += dma->actual_len;
2371 /* turn off DMA requests, discard state, stop polling ... */
2372 if (ep->epnum && is_in) {
2373 /* giveback saves bulk toggle */
2374 csr = musb_h_flush_rxfifo(ep, 0);
2376 /* REVISIT we still get an irq; should likely clear the
2377 * endpoint's irq status here to avoid bogus irqs.
2378 * clearing that status is platform-specific...
2380 } else if (ep->epnum) {
2381 musb_h_tx_flush_fifo(ep);
2382 csr = musb_readw(epio, MUSB_TXCSR);
2383 csr &= ~(MUSB_TXCSR_AUTOSET
2384 | MUSB_TXCSR_DMAENAB
2385 | MUSB_TXCSR_H_RXSTALL
2386 | MUSB_TXCSR_H_NAKTIMEOUT
2387 | MUSB_TXCSR_H_ERROR
2388 | MUSB_TXCSR_TXPKTRDY);
2389 musb_writew(epio, MUSB_TXCSR, csr);
2390 /* REVISIT may need to clear FLUSHFIFO ... */
2391 musb_writew(epio, MUSB_TXCSR, csr);
2392 /* flush cpu writebuffer */
2393 csr = musb_readw(epio, MUSB_TXCSR);
2395 musb_h_ep0_flush_fifo(ep);
2398 musb_advance_schedule(ep->musb, urb, ep, is_in);
2402 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2404 struct musb *musb = hcd_to_musb(hcd);
2406 unsigned long flags;
2407 int is_in = usb_pipein(urb->pipe);
2410 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2411 usb_pipedevice(urb->pipe),
2412 usb_pipeendpoint(urb->pipe),
2413 is_in ? "in" : "out");
2415 spin_lock_irqsave(&musb->lock, flags);
2416 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2425 * Any URB not actively programmed into endpoint hardware can be
2426 * immediately given back; that's any URB not at the head of an
2427 * endpoint queue, unless someday we get real DMA queues. And even
2428 * if it's at the head, it might not be known to the hardware...
2430 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2431 * has already been updated. This is a synchronous abort; it'd be
2432 * OK to hold off until after some IRQ, though.
2434 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2437 || urb->urb_list.prev != &qh->hep->urb_list
2438 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2439 int ready = qh->is_ready;
2442 musb_giveback(musb, urb, 0);
2443 qh->is_ready = ready;
2445 /* If nothing else (usually musb_giveback) is using it
2446 * and its URB list has emptied, recycle this qh.
2448 if (ready && list_empty(&qh->hep->urb_list)) {
2449 qh->hep->hcpriv = NULL;
2450 list_del(&qh->ring);
2454 ret = musb_cleanup_urb(urb, qh);
2456 spin_unlock_irqrestore(&musb->lock, flags);
2460 /* disable an endpoint */
2462 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2464 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2465 unsigned long flags;
2466 struct musb *musb = hcd_to_musb(hcd);
2470 spin_lock_irqsave(&musb->lock, flags);
2476 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2478 /* Kick the first URB off the hardware, if needed */
2480 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2483 /* make software (then hardware) stop ASAP */
2485 urb->status = -ESHUTDOWN;
2488 musb_cleanup_urb(urb, qh);
2490 /* Then nuke all the others ... and advance the
2491 * queue on hw_ep (e.g. bulk ring) when we're done.
2493 while (!list_empty(&hep->urb_list)) {
2495 urb->status = -ESHUTDOWN;
2496 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2499 /* Just empty the queue; the hardware is busy with
2500 * other transfers, and since !qh->is_ready nothing
2501 * will activate any of these as it advances.
2503 while (!list_empty(&hep->urb_list))
2504 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2507 list_del(&qh->ring);
2511 spin_unlock_irqrestore(&musb->lock, flags);
2514 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2516 struct musb *musb = hcd_to_musb(hcd);
2518 return musb_readw(musb->mregs, MUSB_FRAME);
2521 static int musb_h_start(struct usb_hcd *hcd)
2523 struct musb *musb = hcd_to_musb(hcd);
2525 /* NOTE: musb_start() is called when the hub driver turns
2526 * on port power, or when (OTG) peripheral starts.
2528 hcd->state = HC_STATE_RUNNING;
2529 musb->port1_status = 0;
2533 static void musb_h_stop(struct usb_hcd *hcd)
2535 musb_stop(hcd_to_musb(hcd));
2536 hcd->state = HC_STATE_HALT;
2539 static int musb_bus_suspend(struct usb_hcd *hcd)
2541 struct musb *musb = hcd_to_musb(hcd);
2544 musb_port_suspend(musb, true);
2546 if (!is_host_active(musb))
2549 switch (musb->xceiv->otg->state) {
2550 case OTG_STATE_A_SUSPEND:
2552 case OTG_STATE_A_WAIT_VRISE:
2553 /* ID could be grounded even if there's no device
2554 * on the other end of the cable. NOTE that the
2555 * A_WAIT_VRISE timers are messy with MUSB...
2557 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2558 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2559 musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
2565 if (musb->is_active) {
2566 WARNING("trying to suspend as %s while active\n",
2567 usb_otg_state_string(musb->xceiv->otg->state));
2573 static int musb_bus_resume(struct usb_hcd *hcd)
2575 struct musb *musb = hcd_to_musb(hcd);
2578 musb->config->host_port_deassert_reset_at_resume)
2579 musb_port_reset(musb, false);
2584 #ifndef CONFIG_MUSB_PIO_ONLY
2586 #define MUSB_USB_DMA_ALIGN 4
2588 struct musb_temp_buffer {
2590 void *old_xfer_buffer;
2594 static void musb_free_temp_buffer(struct urb *urb)
2596 enum dma_data_direction dir;
2597 struct musb_temp_buffer *temp;
2600 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2603 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2605 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer,
2608 if (dir == DMA_FROM_DEVICE) {
2609 if (usb_pipeisoc(urb->pipe))
2610 length = urb->transfer_buffer_length;
2612 length = urb->actual_length;
2614 memcpy(temp->old_xfer_buffer, temp->data, length);
2616 urb->transfer_buffer = temp->old_xfer_buffer;
2617 kfree(temp->kmalloc_ptr);
2619 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2622 static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
2624 enum dma_data_direction dir;
2625 struct musb_temp_buffer *temp;
2627 size_t kmalloc_size;
2629 if (urb->num_sgs || urb->sg ||
2630 urb->transfer_buffer_length == 0 ||
2631 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1)))
2634 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2636 /* Allocate a buffer with enough padding for alignment */
2637 kmalloc_size = urb->transfer_buffer_length +
2638 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1;
2640 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2644 /* Position our struct temp_buffer such that data is aligned */
2645 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN);
2648 temp->kmalloc_ptr = kmalloc_ptr;
2649 temp->old_xfer_buffer = urb->transfer_buffer;
2650 if (dir == DMA_TO_DEVICE)
2651 memcpy(temp->data, urb->transfer_buffer,
2652 urb->transfer_buffer_length);
2653 urb->transfer_buffer = temp->data;
2655 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2660 static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2663 struct musb *musb = hcd_to_musb(hcd);
2667 * The DMA engine in RTL1.8 and above cannot handle
2668 * DMA addresses that are not aligned to a 4 byte boundary.
2669 * For such engine implemented (un)map_urb_for_dma hooks.
2670 * Do not use these hooks for RTL<1.8
2672 if (musb->hwvers < MUSB_HWVERS_1800)
2673 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2675 ret = musb_alloc_temp_buffer(urb, mem_flags);
2679 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2681 musb_free_temp_buffer(urb);
2686 static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2688 struct musb *musb = hcd_to_musb(hcd);
2690 usb_hcd_unmap_urb_for_dma(hcd, urb);
2692 /* Do not use this hook for RTL<1.8 (see description above) */
2693 if (musb->hwvers < MUSB_HWVERS_1800)
2696 musb_free_temp_buffer(urb);
2698 #endif /* !CONFIG_MUSB_PIO_ONLY */
2700 static const struct hc_driver musb_hc_driver = {
2701 .description = "musb-hcd",
2702 .product_desc = "MUSB HDRC host driver",
2703 .hcd_priv_size = sizeof(struct musb *),
2704 .flags = HCD_USB2 | HCD_MEMORY | HCD_BH,
2706 /* not using irq handler or reset hooks from usbcore, since
2707 * those must be shared with peripheral code for OTG configs
2710 .start = musb_h_start,
2711 .stop = musb_h_stop,
2713 .get_frame_number = musb_h_get_frame_number,
2715 .urb_enqueue = musb_urb_enqueue,
2716 .urb_dequeue = musb_urb_dequeue,
2717 .endpoint_disable = musb_h_disable,
2719 #ifndef CONFIG_MUSB_PIO_ONLY
2720 .map_urb_for_dma = musb_map_urb_for_dma,
2721 .unmap_urb_for_dma = musb_unmap_urb_for_dma,
2724 .hub_status_data = musb_hub_status_data,
2725 .hub_control = musb_hub_control,
2726 .bus_suspend = musb_bus_suspend,
2727 .bus_resume = musb_bus_resume,
2728 /* .start_port_reset = NULL, */
2729 /* .hub_irq_enable = NULL, */
2732 int musb_host_alloc(struct musb *musb)
2734 struct device *dev = musb->controller;
2736 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2737 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2741 *musb->hcd->hcd_priv = (unsigned long) musb;
2742 musb->hcd->self.uses_pio_for_control = 1;
2743 musb->hcd->uses_new_polling = 1;
2744 musb->hcd->has_tt = 1;
2749 void musb_host_cleanup(struct musb *musb)
2751 if (musb->port_mode == MUSB_PORT_MODE_GADGET)
2753 usb_remove_hcd(musb->hcd);
2756 void musb_host_free(struct musb *musb)
2758 usb_put_hcd(musb->hcd);
2761 int musb_host_setup(struct musb *musb, int power_budget)
2764 struct usb_hcd *hcd = musb->hcd;
2766 MUSB_HST_MODE(musb);
2767 musb->xceiv->otg->default_a = 1;
2768 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2770 otg_set_host(musb->xceiv->otg, &hcd->self);
2771 hcd->self.otg_port = 1;
2772 musb->xceiv->otg->host = &hcd->self;
2773 hcd->power_budget = 2 * (power_budget ? : 250);
2775 ret = usb_add_hcd(hcd, 0, 0);
2779 device_wakeup_enable(hcd->self.controller);
2783 void musb_host_resume_root_hub(struct musb *musb)
2785 usb_hcd_resume_root_hub(musb->hcd);
2788 void musb_host_poke_root_hub(struct musb *musb)
2790 MUSB_HST_MODE(musb);
2791 if (musb->hcd->status_urb)
2792 usb_hcd_poll_rh_status(musb->hcd);
2794 usb_hcd_resume_root_hub(musb->hcd);