2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
30 #include <linux/dma-mapping.h>
33 #include "xhci-trace.h"
35 #define DRIVER_AUTHOR "Sarah Sharp"
36 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
38 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
40 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
41 static int link_quirk;
42 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
43 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
45 static unsigned int quirks;
46 module_param(quirks, uint, S_IRUGO);
47 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
49 /* TODO: copied from ehci-hcd.c - can this be refactored? */
51 * xhci_handshake - spin reading hc until handshake completes or fails
52 * @ptr: address of hc register to be read
53 * @mask: bits to look at in result of read
54 * @done: value of those bits when handshake succeeds
55 * @usec: timeout in microseconds
57 * Returns negative errno, or zero on success
59 * Success happens when the "mask" bits have the specified value (hardware
60 * handshake done). There are two failure modes: "usec" have passed (major
61 * hardware flakeout), or the register reads as all-ones (hardware removed).
63 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
69 if (result == ~(u32)0) /* card removed */
81 * Disable interrupts and begin the xHCI halting process.
83 void xhci_quiesce(struct xhci_hcd *xhci)
90 halted = readl(&xhci->op_regs->status) & STS_HALT;
94 cmd = readl(&xhci->op_regs->command);
96 writel(cmd, &xhci->op_regs->command);
100 * Force HC into halt state.
102 * Disable any IRQs and clear the run/stop bit.
103 * HC will complete any current and actively pipelined transactions, and
104 * should halt within 16 ms of the run/stop bit being cleared.
105 * Read HC Halted bit in the status register to see when the HC is finished.
107 int xhci_halt(struct xhci_hcd *xhci)
110 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
113 ret = xhci_handshake(&xhci->op_regs->status,
114 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
116 xhci->xhc_state |= XHCI_STATE_HALTED;
117 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
119 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
125 * Set the run bit and wait for the host to be running.
127 static int xhci_start(struct xhci_hcd *xhci)
132 temp = readl(&xhci->op_regs->command);
134 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
136 writel(temp, &xhci->op_regs->command);
139 * Wait for the HCHalted Status bit to be 0 to indicate the host is
142 ret = xhci_handshake(&xhci->op_regs->status,
143 STS_HALT, 0, XHCI_MAX_HALT_USEC);
144 if (ret == -ETIMEDOUT)
145 xhci_err(xhci, "Host took too long to start, "
146 "waited %u microseconds.\n",
149 /* clear state flags. Including dying, halted or removing */
158 * This resets pipelines, timers, counters, state machines, etc.
159 * Transactions will be terminated immediately, and operational registers
160 * will be set to their defaults.
162 int xhci_reset(struct xhci_hcd *xhci)
168 state = readl(&xhci->op_regs->status);
169 if ((state & STS_HALT) == 0) {
170 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
174 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
175 command = readl(&xhci->op_regs->command);
176 command |= CMD_RESET;
177 writel(command, &xhci->op_regs->command);
179 /* Existing Intel xHCI controllers require a delay of 1 mS,
180 * after setting the CMD_RESET bit, and before accessing any
181 * HC registers. This allows the HC to complete the
182 * reset operation and be ready for HC register access.
183 * Without this delay, the subsequent HC register access,
184 * may result in a system hang very rarely.
186 if (xhci->quirks & XHCI_INTEL_HOST)
189 ret = xhci_handshake(&xhci->op_regs->command,
190 CMD_RESET, 0, 10 * 1000 * 1000);
194 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
195 "Wait for controller to be ready for doorbell rings");
197 * xHCI cannot write to any doorbells or operational registers other
198 * than status until the "Controller Not Ready" flag is cleared.
200 ret = xhci_handshake(&xhci->op_regs->status,
201 STS_CNR, 0, 10 * 1000 * 1000);
203 for (i = 0; i < 2; ++i) {
204 xhci->bus_state[i].port_c_suspend = 0;
205 xhci->bus_state[i].suspended_ports = 0;
206 xhci->bus_state[i].resuming_ports = 0;
213 static int xhci_free_msi(struct xhci_hcd *xhci)
217 if (!xhci->msix_entries)
220 for (i = 0; i < xhci->msix_count; i++)
221 if (xhci->msix_entries[i].vector)
222 free_irq(xhci->msix_entries[i].vector,
230 static int xhci_setup_msi(struct xhci_hcd *xhci)
233 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
235 ret = pci_enable_msi(pdev);
237 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
238 "failed to allocate MSI entry");
242 ret = request_irq(pdev->irq, xhci_msi_irq,
243 0, "xhci_hcd", xhci_to_hcd(xhci));
245 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
246 "disable MSI interrupt");
247 pci_disable_msi(pdev);
255 * free all IRQs request
257 static void xhci_free_irq(struct xhci_hcd *xhci)
259 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
262 /* return if using legacy interrupt */
263 if (xhci_to_hcd(xhci)->irq > 0)
266 ret = xhci_free_msi(xhci);
270 free_irq(pdev->irq, xhci_to_hcd(xhci));
278 static int xhci_setup_msix(struct xhci_hcd *xhci)
281 struct usb_hcd *hcd = xhci_to_hcd(xhci);
282 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
285 * calculate number of msi-x vectors supported.
286 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
287 * with max number of interrupters based on the xhci HCSPARAMS1.
288 * - num_online_cpus: maximum msi-x vectors per CPUs core.
289 * Add additional 1 vector to ensure always available interrupt.
291 xhci->msix_count = min(num_online_cpus() + 1,
292 HCS_MAX_INTRS(xhci->hcs_params1));
295 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
297 if (!xhci->msix_entries) {
298 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
302 for (i = 0; i < xhci->msix_count; i++) {
303 xhci->msix_entries[i].entry = i;
304 xhci->msix_entries[i].vector = 0;
307 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
309 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
310 "Failed to enable MSI-X");
314 for (i = 0; i < xhci->msix_count; i++) {
315 ret = request_irq(xhci->msix_entries[i].vector,
317 0, "xhci_hcd", xhci_to_hcd(xhci));
322 hcd->msix_enabled = 1;
326 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
328 pci_disable_msix(pdev);
330 kfree(xhci->msix_entries);
331 xhci->msix_entries = NULL;
335 /* Free any IRQs and disable MSI-X */
336 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
338 struct usb_hcd *hcd = xhci_to_hcd(xhci);
339 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
341 if (xhci->quirks & XHCI_PLAT)
346 if (xhci->msix_entries) {
347 pci_disable_msix(pdev);
348 kfree(xhci->msix_entries);
349 xhci->msix_entries = NULL;
351 pci_disable_msi(pdev);
354 hcd->msix_enabled = 0;
358 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
362 if (xhci->msix_entries) {
363 for (i = 0; i < xhci->msix_count; i++)
364 synchronize_irq(xhci->msix_entries[i].vector);
368 static int xhci_try_enable_msi(struct usb_hcd *hcd)
370 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
371 struct pci_dev *pdev;
374 /* The xhci platform device has set up IRQs through usb_add_hcd. */
375 if (xhci->quirks & XHCI_PLAT)
378 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
380 * Some Fresco Logic host controllers advertise MSI, but fail to
381 * generate interrupts. Don't even try to enable MSI.
383 if (xhci->quirks & XHCI_BROKEN_MSI)
386 /* unregister the legacy interrupt */
388 free_irq(hcd->irq, hcd);
391 ret = xhci_setup_msix(xhci);
393 /* fall back to msi*/
394 ret = xhci_setup_msi(xhci);
397 /* hcd->irq is 0, we have MSI */
401 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
406 if (!strlen(hcd->irq_descr))
407 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
408 hcd->driver->description, hcd->self.busnum);
410 /* fall back to legacy interrupt*/
411 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
412 hcd->irq_descr, hcd);
414 xhci_err(xhci, "request interrupt %d failed\n",
418 hcd->irq = pdev->irq;
424 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
429 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
433 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
439 static void compliance_mode_recovery(unsigned long arg)
441 struct xhci_hcd *xhci;
446 xhci = (struct xhci_hcd *)arg;
448 for (i = 0; i < xhci->num_usb3_ports; i++) {
449 temp = readl(xhci->usb3_ports[i]);
450 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
452 * Compliance Mode Detected. Letting USB Core
453 * handle the Warm Reset
455 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
456 "Compliance mode detected->port %d",
458 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
459 "Attempting compliance mode recovery");
460 hcd = xhci->shared_hcd;
462 if (hcd->state == HC_STATE_SUSPENDED)
463 usb_hcd_resume_root_hub(hcd);
465 usb_hcd_poll_rh_status(hcd);
469 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
470 mod_timer(&xhci->comp_mode_recovery_timer,
471 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
475 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
476 * that causes ports behind that hardware to enter compliance mode sometimes.
477 * The quirk creates a timer that polls every 2 seconds the link state of
478 * each host controller's port and recovers it by issuing a Warm reset
479 * if Compliance mode is detected, otherwise the port will become "dead" (no
480 * device connections or disconnections will be detected anymore). Becasue no
481 * status event is generated when entering compliance mode (per xhci spec),
482 * this quirk is needed on systems that have the failing hardware installed.
484 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
486 xhci->port_status_u0 = 0;
487 setup_timer(&xhci->comp_mode_recovery_timer,
488 compliance_mode_recovery, (unsigned long)xhci);
489 xhci->comp_mode_recovery_timer.expires = jiffies +
490 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
492 set_timer_slack(&xhci->comp_mode_recovery_timer,
493 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
494 add_timer(&xhci->comp_mode_recovery_timer);
495 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
496 "Compliance mode recovery timer initialized");
500 * This function identifies the systems that have installed the SN65LVPE502CP
501 * USB3.0 re-driver and that need the Compliance Mode Quirk.
503 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
505 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
507 const char *dmi_product_name, *dmi_sys_vendor;
509 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
510 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
511 if (!dmi_product_name || !dmi_sys_vendor)
514 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
517 if (strstr(dmi_product_name, "Z420") ||
518 strstr(dmi_product_name, "Z620") ||
519 strstr(dmi_product_name, "Z820") ||
520 strstr(dmi_product_name, "Z1 Workstation"))
526 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
528 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
533 * Initialize memory for HCD and xHC (one-time init).
535 * Program the PAGESIZE register, initialize the device context array, create
536 * device contexts (?), set up a command ring segment (or two?), create event
537 * ring (one for now).
539 int xhci_init(struct usb_hcd *hcd)
541 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
544 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
545 spin_lock_init(&xhci->lock);
546 if (xhci->hci_version == 0x95 && link_quirk) {
547 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
548 "QUIRK: Not clearing Link TRB chain bits.");
549 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
551 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
552 "xHCI doesn't need link TRB QUIRK");
554 retval = xhci_mem_init(xhci, GFP_KERNEL);
555 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
557 /* Initializing Compliance Mode Recovery Data If Needed */
558 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
559 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
560 compliance_mode_recovery_timer_init(xhci);
566 /*-------------------------------------------------------------------------*/
569 static int xhci_run_finished(struct xhci_hcd *xhci)
571 if (xhci_start(xhci)) {
575 xhci->shared_hcd->state = HC_STATE_RUNNING;
576 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
578 if (xhci->quirks & XHCI_NEC_HOST)
579 xhci_ring_cmd_db(xhci);
581 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
582 "Finished xhci_run for USB3 roothub");
587 * Start the HC after it was halted.
589 * This function is called by the USB core when the HC driver is added.
590 * Its opposite is xhci_stop().
592 * xhci_init() must be called once before this function can be called.
593 * Reset the HC, enable device slot contexts, program DCBAAP, and
594 * set command ring pointer and event ring pointer.
596 * Setup MSI-X vectors and enable interrupts.
598 int xhci_run(struct usb_hcd *hcd)
603 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
605 /* Start the xHCI host controller running only after the USB 2.0 roothub
609 hcd->uses_new_polling = 1;
610 if (!usb_hcd_is_primary_hcd(hcd))
611 return xhci_run_finished(xhci);
613 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
615 ret = xhci_try_enable_msi(hcd);
619 xhci_dbg(xhci, "Command ring memory map follows:\n");
620 xhci_debug_ring(xhci, xhci->cmd_ring);
621 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
622 xhci_dbg_cmd_ptrs(xhci);
624 xhci_dbg(xhci, "ERST memory map follows:\n");
625 xhci_dbg_erst(xhci, &xhci->erst);
626 xhci_dbg(xhci, "Event ring:\n");
627 xhci_debug_ring(xhci, xhci->event_ring);
628 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
629 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
630 temp_64 &= ~ERST_PTR_MASK;
631 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
632 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
634 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
635 "// Set the interrupt modulation register");
636 temp = readl(&xhci->ir_set->irq_control);
637 temp &= ~ER_IRQ_INTERVAL_MASK;
639 writel(temp, &xhci->ir_set->irq_control);
641 /* Set the HCD state before we enable the irqs */
642 temp = readl(&xhci->op_regs->command);
644 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
645 "// Enable interrupts, cmd = 0x%x.", temp);
646 writel(temp, &xhci->op_regs->command);
648 temp = readl(&xhci->ir_set->irq_pending);
649 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
650 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
651 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
652 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
653 xhci_print_ir_set(xhci, 0);
655 if (xhci->quirks & XHCI_NEC_HOST) {
656 struct xhci_command *command;
657 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
660 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
661 TRB_TYPE(TRB_NEC_GET_FW));
663 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
664 "Finished xhci_run for USB2 roothub");
667 EXPORT_SYMBOL_GPL(xhci_run);
672 * This function is called by the USB core when the HC driver is removed.
673 * Its opposite is xhci_run().
675 * Disable device contexts, disable IRQs, and quiesce the HC.
676 * Reset the HC, finish any completed transactions, and cleanup memory.
678 void xhci_stop(struct usb_hcd *hcd)
681 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
683 if (xhci->xhc_state & XHCI_STATE_HALTED)
686 mutex_lock(&xhci->mutex);
687 spin_lock_irq(&xhci->lock);
688 xhci->xhc_state |= XHCI_STATE_HALTED;
689 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
691 /* Make sure the xHC is halted for a USB3 roothub
692 * (xhci_stop() could be called as part of failed init).
696 spin_unlock_irq(&xhci->lock);
698 xhci_cleanup_msix(xhci);
700 /* Deleting Compliance Mode Recovery Timer */
701 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
702 (!(xhci_all_ports_seen_u0(xhci)))) {
703 del_timer_sync(&xhci->comp_mode_recovery_timer);
704 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
705 "%s: compliance mode recovery timer deleted",
709 if (xhci->quirks & XHCI_AMD_PLL_FIX)
712 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
713 "// Disabling event ring interrupts");
714 temp = readl(&xhci->op_regs->status);
715 writel(temp & ~STS_EINT, &xhci->op_regs->status);
716 temp = readl(&xhci->ir_set->irq_pending);
717 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
718 xhci_print_ir_set(xhci, 0);
720 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
721 xhci_mem_cleanup(xhci);
722 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
723 "xhci_stop completed - status = %x",
724 readl(&xhci->op_regs->status));
725 mutex_unlock(&xhci->mutex);
729 * Shutdown HC (not bus-specific)
731 * This is called when the machine is rebooting or halting. We assume that the
732 * machine will be powered off, and the HC's internal state will be reset.
733 * Don't bother to free memory.
735 * This will only ever be called with the main usb_hcd (the USB3 roothub).
737 void xhci_shutdown(struct usb_hcd *hcd)
739 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
741 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
742 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
744 spin_lock_irq(&xhci->lock);
746 /* Workaround for spurious wakeups at shutdown with HSW */
747 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
749 spin_unlock_irq(&xhci->lock);
751 xhci_cleanup_msix(xhci);
753 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
754 "xhci_shutdown completed - status = %x",
755 readl(&xhci->op_regs->status));
757 /* Yet another workaround for spurious wakeups at shutdown with HSW */
758 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
759 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
763 static void xhci_save_registers(struct xhci_hcd *xhci)
765 xhci->s3.command = readl(&xhci->op_regs->command);
766 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
767 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
768 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
769 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
770 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
771 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
772 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
773 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
776 static void xhci_restore_registers(struct xhci_hcd *xhci)
778 writel(xhci->s3.command, &xhci->op_regs->command);
779 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
780 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
781 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
782 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
783 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
784 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
785 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
786 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
789 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
793 /* step 2: initialize command ring buffer */
794 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
795 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
796 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
797 xhci->cmd_ring->dequeue) &
798 (u64) ~CMD_RING_RSVD_BITS) |
799 xhci->cmd_ring->cycle_state;
800 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
801 "// Setting command ring address to 0x%llx",
802 (long unsigned long) val_64);
803 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
807 * The whole command ring must be cleared to zero when we suspend the host.
809 * The host doesn't save the command ring pointer in the suspend well, so we
810 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
811 * aligned, because of the reserved bits in the command ring dequeue pointer
812 * register. Therefore, we can't just set the dequeue pointer back in the
813 * middle of the ring (TRBs are 16-byte aligned).
815 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
817 struct xhci_ring *ring;
818 struct xhci_segment *seg;
820 ring = xhci->cmd_ring;
824 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
825 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
826 cpu_to_le32(~TRB_CYCLE);
828 } while (seg != ring->deq_seg);
830 /* Reset the software enqueue and dequeue pointers */
831 ring->deq_seg = ring->first_seg;
832 ring->dequeue = ring->first_seg->trbs;
833 ring->enq_seg = ring->deq_seg;
834 ring->enqueue = ring->dequeue;
836 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
838 * Ring is now zeroed, so the HW should look for change of ownership
839 * when the cycle bit is set to 1.
841 ring->cycle_state = 1;
844 * Reset the hardware dequeue pointer.
845 * Yes, this will need to be re-written after resume, but we're paranoid
846 * and want to make sure the hardware doesn't access bogus memory
847 * because, say, the BIOS or an SMI started the host without changing
848 * the command ring pointers.
850 xhci_set_cmd_ring_deq(xhci);
853 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
856 __le32 __iomem **port_array;
860 spin_lock_irqsave(&xhci->lock, flags);
862 /* disble usb3 ports Wake bits*/
863 port_index = xhci->num_usb3_ports;
864 port_array = xhci->usb3_ports;
865 while (port_index--) {
866 t1 = readl(port_array[port_index]);
867 t1 = xhci_port_state_to_neutral(t1);
868 t2 = t1 & ~PORT_WAKE_BITS;
870 writel(t2, port_array[port_index]);
873 /* disble usb2 ports Wake bits*/
874 port_index = xhci->num_usb2_ports;
875 port_array = xhci->usb2_ports;
876 while (port_index--) {
877 t1 = readl(port_array[port_index]);
878 t1 = xhci_port_state_to_neutral(t1);
879 t2 = t1 & ~PORT_WAKE_BITS;
881 writel(t2, port_array[port_index]);
884 spin_unlock_irqrestore(&xhci->lock, flags);
888 * Stop HC (not bus-specific)
890 * This is called when the machine transition into S3/S4 mode.
893 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
896 unsigned int delay = XHCI_MAX_HALT_USEC;
897 struct usb_hcd *hcd = xhci_to_hcd(xhci);
903 if (hcd->state != HC_STATE_SUSPENDED ||
904 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
907 /* Clear root port wake on bits if wakeup not allowed. */
909 xhci_disable_port_wake_on_bits(xhci);
911 /* Don't poll the roothubs on bus suspend. */
912 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
913 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
914 del_timer_sync(&hcd->rh_timer);
915 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
916 del_timer_sync(&xhci->shared_hcd->rh_timer);
918 spin_lock_irq(&xhci->lock);
919 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
920 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
921 /* step 1: stop endpoint */
922 /* skipped assuming that port suspend has done */
924 /* step 2: clear Run/Stop bit */
925 command = readl(&xhci->op_regs->command);
927 writel(command, &xhci->op_regs->command);
929 /* Some chips from Fresco Logic need an extraordinary delay */
930 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
932 if (xhci_handshake(&xhci->op_regs->status,
933 STS_HALT, STS_HALT, delay)) {
934 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
935 spin_unlock_irq(&xhci->lock);
938 xhci_clear_command_ring(xhci);
940 /* step 3: save registers */
941 xhci_save_registers(xhci);
943 /* step 4: set CSS flag */
944 command = readl(&xhci->op_regs->command);
946 writel(command, &xhci->op_regs->command);
947 if (xhci_handshake(&xhci->op_regs->status,
948 STS_SAVE, 0, 10 * 1000)) {
949 xhci_warn(xhci, "WARN: xHC save state timeout\n");
950 spin_unlock_irq(&xhci->lock);
953 spin_unlock_irq(&xhci->lock);
956 * Deleting Compliance Mode Recovery Timer because the xHCI Host
957 * is about to be suspended.
959 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
960 (!(xhci_all_ports_seen_u0(xhci)))) {
961 del_timer_sync(&xhci->comp_mode_recovery_timer);
962 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
963 "%s: compliance mode recovery timer deleted",
967 /* step 5: remove core well power */
968 /* synchronize irq when using MSI-X */
969 xhci_msix_sync_irqs(xhci);
973 EXPORT_SYMBOL_GPL(xhci_suspend);
976 * start xHC (not bus-specific)
978 * This is called when the machine transition from S3/S4 mode.
981 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
983 u32 command, temp = 0, status;
984 struct usb_hcd *hcd = xhci_to_hcd(xhci);
985 struct usb_hcd *secondary_hcd;
987 bool comp_timer_running = false;
992 /* Wait a bit if either of the roothubs need to settle from the
993 * transition into bus suspend.
995 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
997 xhci->bus_state[1].next_statechange))
1000 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1001 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1003 spin_lock_irq(&xhci->lock);
1004 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1008 /* step 1: restore register */
1009 xhci_restore_registers(xhci);
1010 /* step 2: initialize command ring buffer */
1011 xhci_set_cmd_ring_deq(xhci);
1012 /* step 3: restore state and start state*/
1013 /* step 3: set CRS flag */
1014 command = readl(&xhci->op_regs->command);
1016 writel(command, &xhci->op_regs->command);
1017 if (xhci_handshake(&xhci->op_regs->status,
1018 STS_RESTORE, 0, 10 * 1000)) {
1019 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1020 spin_unlock_irq(&xhci->lock);
1023 temp = readl(&xhci->op_regs->status);
1026 /* If restore operation fails, re-initialize the HC during resume */
1027 if ((temp & STS_SRE) || hibernated) {
1029 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1030 !(xhci_all_ports_seen_u0(xhci))) {
1031 del_timer_sync(&xhci->comp_mode_recovery_timer);
1032 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1033 "Compliance Mode Recovery Timer deleted!");
1036 /* Let the USB core know _both_ roothubs lost power. */
1037 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1038 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1040 xhci_dbg(xhci, "Stop HCD\n");
1043 spin_unlock_irq(&xhci->lock);
1044 xhci_cleanup_msix(xhci);
1046 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1047 temp = readl(&xhci->op_regs->status);
1048 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1049 temp = readl(&xhci->ir_set->irq_pending);
1050 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1051 xhci_print_ir_set(xhci, 0);
1053 xhci_dbg(xhci, "cleaning up memory\n");
1054 xhci_mem_cleanup(xhci);
1055 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1056 readl(&xhci->op_regs->status));
1058 /* USB core calls the PCI reinit and start functions twice:
1059 * first with the primary HCD, and then with the secondary HCD.
1060 * If we don't do the same, the host will never be started.
1062 if (!usb_hcd_is_primary_hcd(hcd))
1063 secondary_hcd = hcd;
1065 secondary_hcd = xhci->shared_hcd;
1067 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1068 retval = xhci_init(hcd->primary_hcd);
1071 comp_timer_running = true;
1073 xhci_dbg(xhci, "Start the primary HCD\n");
1074 retval = xhci_run(hcd->primary_hcd);
1076 xhci_dbg(xhci, "Start the secondary HCD\n");
1077 retval = xhci_run(secondary_hcd);
1079 hcd->state = HC_STATE_SUSPENDED;
1080 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1084 /* step 4: set Run/Stop bit */
1085 command = readl(&xhci->op_regs->command);
1087 writel(command, &xhci->op_regs->command);
1088 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1091 /* step 5: walk topology and initialize portsc,
1092 * portpmsc and portli
1094 /* this is done in bus_resume */
1096 /* step 6: restart each of the previously
1097 * Running endpoints by ringing their doorbells
1100 spin_unlock_irq(&xhci->lock);
1104 /* Resume root hubs only when have pending events. */
1105 status = readl(&xhci->op_regs->status);
1106 if (status & STS_EINT) {
1107 usb_hcd_resume_root_hub(xhci->shared_hcd);
1108 usb_hcd_resume_root_hub(hcd);
1113 * If system is subject to the Quirk, Compliance Mode Timer needs to
1114 * be re-initialized Always after a system resume. Ports are subject
1115 * to suffer the Compliance Mode issue again. It doesn't matter if
1116 * ports have entered previously to U0 before system's suspension.
1118 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1119 compliance_mode_recovery_timer_init(xhci);
1121 /* Re-enable port polling. */
1122 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1123 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1124 usb_hcd_poll_rh_status(xhci->shared_hcd);
1125 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1126 usb_hcd_poll_rh_status(hcd);
1130 EXPORT_SYMBOL_GPL(xhci_resume);
1131 #endif /* CONFIG_PM */
1133 /*-------------------------------------------------------------------------*/
1136 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1137 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1138 * value to right shift 1 for the bitmask.
1140 * Index = (epnum * 2) + direction - 1,
1141 * where direction = 0 for OUT, 1 for IN.
1142 * For control endpoints, the IN index is used (OUT index is unused), so
1143 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1145 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1148 if (usb_endpoint_xfer_control(desc))
1149 index = (unsigned int) (usb_endpoint_num(desc)*2);
1151 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1152 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1156 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1157 * address from the XHCI endpoint index.
1159 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1161 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1162 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1163 return direction | number;
1166 /* Find the flag for this endpoint (for use in the control context). Use the
1167 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1170 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1172 return 1 << (xhci_get_endpoint_index(desc) + 1);
1175 /* Find the flag for this endpoint (for use in the control context). Use the
1176 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1179 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1181 return 1 << (ep_index + 1);
1184 /* Compute the last valid endpoint context index. Basically, this is the
1185 * endpoint index plus one. For slot contexts with more than valid endpoint,
1186 * we find the most significant bit set in the added contexts flags.
1187 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1188 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1190 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1192 return fls(added_ctxs) - 1;
1195 /* Returns 1 if the arguments are OK;
1196 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1198 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1199 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1201 struct xhci_hcd *xhci;
1202 struct xhci_virt_device *virt_dev;
1204 if (!hcd || (check_ep && !ep) || !udev) {
1205 pr_debug("xHCI %s called with invalid args\n", func);
1208 if (!udev->parent) {
1209 pr_debug("xHCI %s called for root hub\n", func);
1213 xhci = hcd_to_xhci(hcd);
1214 if (check_virt_dev) {
1215 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1216 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1221 virt_dev = xhci->devs[udev->slot_id];
1222 if (virt_dev->udev != udev) {
1223 xhci_dbg(xhci, "xHCI %s called with udev and "
1224 "virt_dev does not match\n", func);
1229 if (xhci->xhc_state & XHCI_STATE_HALTED)
1235 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1236 struct usb_device *udev, struct xhci_command *command,
1237 bool ctx_change, bool must_succeed);
1240 * Full speed devices may have a max packet size greater than 8 bytes, but the
1241 * USB core doesn't know that until it reads the first 8 bytes of the
1242 * descriptor. If the usb_device's max packet size changes after that point,
1243 * we need to issue an evaluate context command and wait on it.
1245 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1246 unsigned int ep_index, struct urb *urb)
1248 struct xhci_container_ctx *out_ctx;
1249 struct xhci_input_control_ctx *ctrl_ctx;
1250 struct xhci_ep_ctx *ep_ctx;
1251 struct xhci_command *command;
1252 int max_packet_size;
1253 int hw_max_packet_size;
1256 out_ctx = xhci->devs[slot_id]->out_ctx;
1257 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1258 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1259 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1260 if (hw_max_packet_size != max_packet_size) {
1261 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1262 "Max Packet Size for ep 0 changed.");
1263 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1264 "Max packet size in usb_device = %d",
1266 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1267 "Max packet size in xHCI HW = %d",
1268 hw_max_packet_size);
1269 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1270 "Issuing evaluate context command.");
1272 /* Set up the input context flags for the command */
1273 /* FIXME: This won't work if a non-default control endpoint
1274 * changes max packet sizes.
1277 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1281 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1282 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1284 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1287 goto command_cleanup;
1289 /* Set up the modified control endpoint 0 */
1290 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1291 xhci->devs[slot_id]->out_ctx, ep_index);
1293 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1294 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1295 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1297 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1298 ctrl_ctx->drop_flags = 0;
1300 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1301 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1302 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1303 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1305 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1308 /* Clean up the input context for later use by bandwidth
1311 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1313 kfree(command->completion);
1320 * non-error returns are a promise to giveback() the urb later
1321 * we drop ownership so next owner (or urb unlink) can get it
1323 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1325 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1326 struct xhci_td *buffer;
1327 unsigned long flags;
1329 unsigned int slot_id, ep_index;
1330 struct urb_priv *urb_priv;
1333 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1334 true, true, __func__) <= 0)
1337 slot_id = urb->dev->slot_id;
1338 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1340 if (!HCD_HW_ACCESSIBLE(hcd)) {
1341 if (!in_interrupt())
1342 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1347 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1348 size = urb->number_of_packets;
1349 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1350 urb->transfer_buffer_length > 0 &&
1351 urb->transfer_flags & URB_ZERO_PACKET &&
1352 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1357 urb_priv = kzalloc(sizeof(struct urb_priv) +
1358 size * sizeof(struct xhci_td *), mem_flags);
1362 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1368 for (i = 0; i < size; i++) {
1369 urb_priv->td[i] = buffer;
1373 urb_priv->length = size;
1374 urb_priv->td_cnt = 0;
1375 urb->hcpriv = urb_priv;
1377 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1378 /* Check to see if the max packet size for the default control
1379 * endpoint changed during FS device enumeration
1381 if (urb->dev->speed == USB_SPEED_FULL) {
1382 ret = xhci_check_maxpacket(xhci, slot_id,
1385 xhci_urb_free_priv(urb_priv);
1391 /* We have a spinlock and interrupts disabled, so we must pass
1392 * atomic context to this function, which may allocate memory.
1394 spin_lock_irqsave(&xhci->lock, flags);
1395 if (xhci->xhc_state & XHCI_STATE_DYING)
1397 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1401 spin_unlock_irqrestore(&xhci->lock, flags);
1402 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1403 spin_lock_irqsave(&xhci->lock, flags);
1404 if (xhci->xhc_state & XHCI_STATE_DYING)
1406 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1407 EP_GETTING_STREAMS) {
1408 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1409 "is transitioning to using streams.\n");
1411 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1412 EP_GETTING_NO_STREAMS) {
1413 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1414 "is transitioning to "
1415 "not having streams.\n");
1418 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1423 spin_unlock_irqrestore(&xhci->lock, flags);
1424 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1425 spin_lock_irqsave(&xhci->lock, flags);
1426 if (xhci->xhc_state & XHCI_STATE_DYING)
1428 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1432 spin_unlock_irqrestore(&xhci->lock, flags);
1434 spin_lock_irqsave(&xhci->lock, flags);
1435 if (xhci->xhc_state & XHCI_STATE_DYING)
1437 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1441 spin_unlock_irqrestore(&xhci->lock, flags);
1446 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1447 "non-responsive xHCI host.\n",
1448 urb->ep->desc.bEndpointAddress, urb);
1451 xhci_urb_free_priv(urb_priv);
1453 spin_unlock_irqrestore(&xhci->lock, flags);
1457 /* Get the right ring for the given URB.
1458 * If the endpoint supports streams, boundary check the URB's stream ID.
1459 * If the endpoint doesn't support streams, return the singular endpoint ring.
1461 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1464 unsigned int slot_id;
1465 unsigned int ep_index;
1466 unsigned int stream_id;
1467 struct xhci_virt_ep *ep;
1469 slot_id = urb->dev->slot_id;
1470 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1471 stream_id = urb->stream_id;
1472 ep = &xhci->devs[slot_id]->eps[ep_index];
1473 /* Common case: no streams */
1474 if (!(ep->ep_state & EP_HAS_STREAMS))
1477 if (stream_id == 0) {
1479 "WARN: Slot ID %u, ep index %u has streams, "
1480 "but URB has no stream ID.\n",
1485 if (stream_id < ep->stream_info->num_streams)
1486 return ep->stream_info->stream_rings[stream_id];
1489 "WARN: Slot ID %u, ep index %u has "
1490 "stream IDs 1 to %u allocated, "
1491 "but stream ID %u is requested.\n",
1493 ep->stream_info->num_streams - 1,
1499 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1500 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1501 * should pick up where it left off in the TD, unless a Set Transfer Ring
1502 * Dequeue Pointer is issued.
1504 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1505 * the ring. Since the ring is a contiguous structure, they can't be physically
1506 * removed. Instead, there are two options:
1508 * 1) If the HC is in the middle of processing the URB to be canceled, we
1509 * simply move the ring's dequeue pointer past those TRBs using the Set
1510 * Transfer Ring Dequeue Pointer command. This will be the common case,
1511 * when drivers timeout on the last submitted URB and attempt to cancel.
1513 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1514 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1515 * HC will need to invalidate the any TRBs it has cached after the stop
1516 * endpoint command, as noted in the xHCI 0.95 errata.
1518 * 3) The TD may have completed by the time the Stop Endpoint Command
1519 * completes, so software needs to handle that case too.
1521 * This function should protect against the TD enqueueing code ringing the
1522 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1523 * It also needs to account for multiple cancellations on happening at the same
1524 * time for the same endpoint.
1526 * Note that this function can be called in any context, or so says
1527 * usb_hcd_unlink_urb()
1529 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1531 unsigned long flags;
1534 struct xhci_hcd *xhci;
1535 struct urb_priv *urb_priv;
1537 unsigned int ep_index;
1538 struct xhci_ring *ep_ring;
1539 struct xhci_virt_ep *ep;
1540 struct xhci_command *command;
1542 xhci = hcd_to_xhci(hcd);
1543 spin_lock_irqsave(&xhci->lock, flags);
1544 /* Make sure the URB hasn't completed or been unlinked already */
1545 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1546 if (ret || !urb->hcpriv)
1548 temp = readl(&xhci->op_regs->status);
1549 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1550 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1551 "HW died, freeing TD.");
1552 urb_priv = urb->hcpriv;
1553 for (i = urb_priv->td_cnt;
1554 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1556 td = urb_priv->td[i];
1557 if (!list_empty(&td->td_list))
1558 list_del_init(&td->td_list);
1559 if (!list_empty(&td->cancelled_td_list))
1560 list_del_init(&td->cancelled_td_list);
1563 usb_hcd_unlink_urb_from_ep(hcd, urb);
1564 spin_unlock_irqrestore(&xhci->lock, flags);
1565 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1566 xhci_urb_free_priv(urb_priv);
1569 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1570 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1571 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1572 "Ep 0x%x: URB %p to be canceled on "
1573 "non-responsive xHCI host.",
1574 urb->ep->desc.bEndpointAddress, urb);
1575 /* Let the stop endpoint command watchdog timer (which set this
1576 * state) finish cleaning up the endpoint TD lists. We must
1577 * have caught it in the middle of dropping a lock and giving
1583 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1584 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1585 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1591 urb_priv = urb->hcpriv;
1592 i = urb_priv->td_cnt;
1593 if (i < urb_priv->length)
1594 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1595 "Cancel URB %p, dev %s, ep 0x%x, "
1596 "starting at offset 0x%llx",
1597 urb, urb->dev->devpath,
1598 urb->ep->desc.bEndpointAddress,
1599 (unsigned long long) xhci_trb_virt_to_dma(
1600 urb_priv->td[i]->start_seg,
1601 urb_priv->td[i]->first_trb));
1603 for (; i < urb_priv->length; i++) {
1604 td = urb_priv->td[i];
1605 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1608 /* Queue a stop endpoint command, but only if this is
1609 * the first cancellation to be handled.
1611 if (!(ep->ep_state & EP_HALT_PENDING)) {
1612 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1617 ep->ep_state |= EP_HALT_PENDING;
1618 ep->stop_cmds_pending++;
1619 ep->stop_cmd_timer.expires = jiffies +
1620 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1621 add_timer(&ep->stop_cmd_timer);
1622 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1624 xhci_ring_cmd_db(xhci);
1627 spin_unlock_irqrestore(&xhci->lock, flags);
1631 /* Drop an endpoint from a new bandwidth configuration for this device.
1632 * Only one call to this function is allowed per endpoint before
1633 * check_bandwidth() or reset_bandwidth() must be called.
1634 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1635 * add the endpoint to the schedule with possibly new parameters denoted by a
1636 * different endpoint descriptor in usb_host_endpoint.
1637 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1640 * The USB core will not allow URBs to be queued to an endpoint that is being
1641 * disabled, so there's no need for mutual exclusion to protect
1642 * the xhci->devs[slot_id] structure.
1644 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1645 struct usb_host_endpoint *ep)
1647 struct xhci_hcd *xhci;
1648 struct xhci_container_ctx *in_ctx, *out_ctx;
1649 struct xhci_input_control_ctx *ctrl_ctx;
1650 unsigned int ep_index;
1651 struct xhci_ep_ctx *ep_ctx;
1653 u32 new_add_flags, new_drop_flags;
1656 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1659 xhci = hcd_to_xhci(hcd);
1660 if (xhci->xhc_state & XHCI_STATE_DYING)
1663 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1664 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1665 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1666 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1667 __func__, drop_flag);
1671 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1672 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1673 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1675 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1680 ep_index = xhci_get_endpoint_index(&ep->desc);
1681 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1682 /* If the HC already knows the endpoint is disabled,
1683 * or the HCD has noted it is disabled, ignore this request
1685 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1686 cpu_to_le32(EP_STATE_DISABLED)) ||
1687 le32_to_cpu(ctrl_ctx->drop_flags) &
1688 xhci_get_endpoint_flag(&ep->desc)) {
1689 /* Do not warn when called after a usb_device_reset */
1690 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1691 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1696 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1697 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1699 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1700 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1702 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1704 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1705 (unsigned int) ep->desc.bEndpointAddress,
1707 (unsigned int) new_drop_flags,
1708 (unsigned int) new_add_flags);
1712 /* Add an endpoint to a new possible bandwidth configuration for this device.
1713 * Only one call to this function is allowed per endpoint before
1714 * check_bandwidth() or reset_bandwidth() must be called.
1715 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1716 * add the endpoint to the schedule with possibly new parameters denoted by a
1717 * different endpoint descriptor in usb_host_endpoint.
1718 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1721 * The USB core will not allow URBs to be queued to an endpoint until the
1722 * configuration or alt setting is installed in the device, so there's no need
1723 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1725 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1726 struct usb_host_endpoint *ep)
1728 struct xhci_hcd *xhci;
1729 struct xhci_container_ctx *in_ctx;
1730 unsigned int ep_index;
1731 struct xhci_input_control_ctx *ctrl_ctx;
1733 u32 new_add_flags, new_drop_flags;
1734 struct xhci_virt_device *virt_dev;
1737 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1739 /* So we won't queue a reset ep command for a root hub */
1743 xhci = hcd_to_xhci(hcd);
1744 if (xhci->xhc_state & XHCI_STATE_DYING)
1747 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1748 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1749 /* FIXME when we have to issue an evaluate endpoint command to
1750 * deal with ep0 max packet size changing once we get the
1753 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1754 __func__, added_ctxs);
1758 virt_dev = xhci->devs[udev->slot_id];
1759 in_ctx = virt_dev->in_ctx;
1760 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1762 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1767 ep_index = xhci_get_endpoint_index(&ep->desc);
1768 /* If this endpoint is already in use, and the upper layers are trying
1769 * to add it again without dropping it, reject the addition.
1771 if (virt_dev->eps[ep_index].ring &&
1772 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1773 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1774 "without dropping it.\n",
1775 (unsigned int) ep->desc.bEndpointAddress);
1779 /* If the HCD has already noted the endpoint is enabled,
1780 * ignore this request.
1782 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1783 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1789 * Configuration and alternate setting changes must be done in
1790 * process context, not interrupt context (or so documenation
1791 * for usb_set_interface() and usb_set_configuration() claim).
1793 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1794 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1795 __func__, ep->desc.bEndpointAddress);
1799 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1800 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1802 /* If xhci_endpoint_disable() was called for this endpoint, but the
1803 * xHC hasn't been notified yet through the check_bandwidth() call,
1804 * this re-adds a new state for the endpoint from the new endpoint
1805 * descriptors. We must drop and re-add this endpoint, so we leave the
1808 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1810 /* Store the usb_device pointer for later use */
1813 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1814 (unsigned int) ep->desc.bEndpointAddress,
1816 (unsigned int) new_drop_flags,
1817 (unsigned int) new_add_flags);
1821 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1823 struct xhci_input_control_ctx *ctrl_ctx;
1824 struct xhci_ep_ctx *ep_ctx;
1825 struct xhci_slot_ctx *slot_ctx;
1828 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1830 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1835 /* When a device's add flag and drop flag are zero, any subsequent
1836 * configure endpoint command will leave that endpoint's state
1837 * untouched. Make sure we don't leave any old state in the input
1838 * endpoint contexts.
1840 ctrl_ctx->drop_flags = 0;
1841 ctrl_ctx->add_flags = 0;
1842 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1843 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1844 /* Endpoint 0 is always valid */
1845 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1846 for (i = 1; i < 31; ++i) {
1847 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1848 ep_ctx->ep_info = 0;
1849 ep_ctx->ep_info2 = 0;
1851 ep_ctx->tx_info = 0;
1855 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1856 struct usb_device *udev, u32 *cmd_status)
1860 switch (*cmd_status) {
1861 case COMP_CMD_ABORT:
1863 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1867 dev_warn(&udev->dev,
1868 "Not enough host controller resources for new device state.\n");
1870 /* FIXME: can we allocate more resources for the HC? */
1873 case COMP_2ND_BW_ERR:
1874 dev_warn(&udev->dev,
1875 "Not enough bandwidth for new device state.\n");
1877 /* FIXME: can we go back to the old state? */
1880 /* the HCD set up something wrong */
1881 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1883 "and endpoint is not disabled.\n");
1887 dev_warn(&udev->dev,
1888 "ERROR: Incompatible device for endpoint configure command.\n");
1892 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1893 "Successful Endpoint Configure command");
1897 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1905 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1906 struct usb_device *udev, u32 *cmd_status)
1909 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1911 switch (*cmd_status) {
1912 case COMP_CMD_ABORT:
1914 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1918 dev_warn(&udev->dev,
1919 "WARN: xHCI driver setup invalid evaluate context command.\n");
1923 dev_warn(&udev->dev,
1924 "WARN: slot not enabled for evaluate context command.\n");
1927 case COMP_CTX_STATE:
1928 dev_warn(&udev->dev,
1929 "WARN: invalid context state for evaluate context command.\n");
1930 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1934 dev_warn(&udev->dev,
1935 "ERROR: Incompatible device for evaluate context command.\n");
1939 /* Max Exit Latency too large error */
1940 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1944 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1945 "Successful evaluate context command");
1949 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1957 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1958 struct xhci_input_control_ctx *ctrl_ctx)
1960 u32 valid_add_flags;
1961 u32 valid_drop_flags;
1963 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1964 * (bit 1). The default control endpoint is added during the Address
1965 * Device command and is never removed until the slot is disabled.
1967 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1968 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1970 /* Use hweight32 to count the number of ones in the add flags, or
1971 * number of endpoints added. Don't count endpoints that are changed
1972 * (both added and dropped).
1974 return hweight32(valid_add_flags) -
1975 hweight32(valid_add_flags & valid_drop_flags);
1978 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1979 struct xhci_input_control_ctx *ctrl_ctx)
1981 u32 valid_add_flags;
1982 u32 valid_drop_flags;
1984 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1985 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1987 return hweight32(valid_drop_flags) -
1988 hweight32(valid_add_flags & valid_drop_flags);
1992 * We need to reserve the new number of endpoints before the configure endpoint
1993 * command completes. We can't subtract the dropped endpoints from the number
1994 * of active endpoints until the command completes because we can oversubscribe
1995 * the host in this case:
1997 * - the first configure endpoint command drops more endpoints than it adds
1998 * - a second configure endpoint command that adds more endpoints is queued
1999 * - the first configure endpoint command fails, so the config is unchanged
2000 * - the second command may succeed, even though there isn't enough resources
2002 * Must be called with xhci->lock held.
2004 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2005 struct xhci_input_control_ctx *ctrl_ctx)
2009 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2010 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2011 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2012 "Not enough ep ctxs: "
2013 "%u active, need to add %u, limit is %u.",
2014 xhci->num_active_eps, added_eps,
2015 xhci->limit_active_eps);
2018 xhci->num_active_eps += added_eps;
2019 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2020 "Adding %u ep ctxs, %u now active.", added_eps,
2021 xhci->num_active_eps);
2026 * The configure endpoint was failed by the xHC for some other reason, so we
2027 * need to revert the resources that failed configuration would have used.
2029 * Must be called with xhci->lock held.
2031 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2032 struct xhci_input_control_ctx *ctrl_ctx)
2036 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2037 xhci->num_active_eps -= num_failed_eps;
2038 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2039 "Removing %u failed ep ctxs, %u now active.",
2041 xhci->num_active_eps);
2045 * Now that the command has completed, clean up the active endpoint count by
2046 * subtracting out the endpoints that were dropped (but not changed).
2048 * Must be called with xhci->lock held.
2050 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2051 struct xhci_input_control_ctx *ctrl_ctx)
2053 u32 num_dropped_eps;
2055 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2056 xhci->num_active_eps -= num_dropped_eps;
2057 if (num_dropped_eps)
2058 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2059 "Removing %u dropped ep ctxs, %u now active.",
2061 xhci->num_active_eps);
2064 static unsigned int xhci_get_block_size(struct usb_device *udev)
2066 switch (udev->speed) {
2068 case USB_SPEED_FULL:
2070 case USB_SPEED_HIGH:
2072 case USB_SPEED_SUPER:
2074 case USB_SPEED_UNKNOWN:
2075 case USB_SPEED_WIRELESS:
2077 /* Should never happen */
2083 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2085 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2087 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2092 /* If we are changing a LS/FS device under a HS hub,
2093 * make sure (if we are activating a new TT) that the HS bus has enough
2094 * bandwidth for this new TT.
2096 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2097 struct xhci_virt_device *virt_dev,
2100 struct xhci_interval_bw_table *bw_table;
2101 struct xhci_tt_bw_info *tt_info;
2103 /* Find the bandwidth table for the root port this TT is attached to. */
2104 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2105 tt_info = virt_dev->tt_info;
2106 /* If this TT already had active endpoints, the bandwidth for this TT
2107 * has already been added. Removing all periodic endpoints (and thus
2108 * making the TT enactive) will only decrease the bandwidth used.
2112 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2113 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2117 /* Not sure why we would have no new active endpoints...
2119 * Maybe because of an Evaluate Context change for a hub update or a
2120 * control endpoint 0 max packet size change?
2121 * FIXME: skip the bandwidth calculation in that case.
2126 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2127 struct xhci_virt_device *virt_dev)
2129 unsigned int bw_reserved;
2131 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2132 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2135 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2136 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2143 * This algorithm is a very conservative estimate of the worst-case scheduling
2144 * scenario for any one interval. The hardware dynamically schedules the
2145 * packets, so we can't tell which microframe could be the limiting factor in
2146 * the bandwidth scheduling. This only takes into account periodic endpoints.
2148 * Obviously, we can't solve an NP complete problem to find the minimum worst
2149 * case scenario. Instead, we come up with an estimate that is no less than
2150 * the worst case bandwidth used for any one microframe, but may be an
2153 * We walk the requirements for each endpoint by interval, starting with the
2154 * smallest interval, and place packets in the schedule where there is only one
2155 * possible way to schedule packets for that interval. In order to simplify
2156 * this algorithm, we record the largest max packet size for each interval, and
2157 * assume all packets will be that size.
2159 * For interval 0, we obviously must schedule all packets for each interval.
2160 * The bandwidth for interval 0 is just the amount of data to be transmitted
2161 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2162 * the number of packets).
2164 * For interval 1, we have two possible microframes to schedule those packets
2165 * in. For this algorithm, if we can schedule the same number of packets for
2166 * each possible scheduling opportunity (each microframe), we will do so. The
2167 * remaining number of packets will be saved to be transmitted in the gaps in
2168 * the next interval's scheduling sequence.
2170 * As we move those remaining packets to be scheduled with interval 2 packets,
2171 * we have to double the number of remaining packets to transmit. This is
2172 * because the intervals are actually powers of 2, and we would be transmitting
2173 * the previous interval's packets twice in this interval. We also have to be
2174 * sure that when we look at the largest max packet size for this interval, we
2175 * also look at the largest max packet size for the remaining packets and take
2176 * the greater of the two.
2178 * The algorithm continues to evenly distribute packets in each scheduling
2179 * opportunity, and push the remaining packets out, until we get to the last
2180 * interval. Then those packets and their associated overhead are just added
2181 * to the bandwidth used.
2183 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2184 struct xhci_virt_device *virt_dev,
2187 unsigned int bw_reserved;
2188 unsigned int max_bandwidth;
2189 unsigned int bw_used;
2190 unsigned int block_size;
2191 struct xhci_interval_bw_table *bw_table;
2192 unsigned int packet_size = 0;
2193 unsigned int overhead = 0;
2194 unsigned int packets_transmitted = 0;
2195 unsigned int packets_remaining = 0;
2198 if (virt_dev->udev->speed == USB_SPEED_SUPER)
2199 return xhci_check_ss_bw(xhci, virt_dev);
2201 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2202 max_bandwidth = HS_BW_LIMIT;
2203 /* Convert percent of bus BW reserved to blocks reserved */
2204 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2206 max_bandwidth = FS_BW_LIMIT;
2207 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2210 bw_table = virt_dev->bw_table;
2211 /* We need to translate the max packet size and max ESIT payloads into
2212 * the units the hardware uses.
2214 block_size = xhci_get_block_size(virt_dev->udev);
2216 /* If we are manipulating a LS/FS device under a HS hub, double check
2217 * that the HS bus has enough bandwidth if we are activing a new TT.
2219 if (virt_dev->tt_info) {
2220 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2221 "Recalculating BW for rootport %u",
2222 virt_dev->real_port);
2223 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2224 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2225 "newly activated TT.\n");
2228 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2229 "Recalculating BW for TT slot %u port %u",
2230 virt_dev->tt_info->slot_id,
2231 virt_dev->tt_info->ttport);
2233 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2234 "Recalculating BW for rootport %u",
2235 virt_dev->real_port);
2238 /* Add in how much bandwidth will be used for interval zero, or the
2239 * rounded max ESIT payload + number of packets * largest overhead.
2241 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2242 bw_table->interval_bw[0].num_packets *
2243 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2245 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2246 unsigned int bw_added;
2247 unsigned int largest_mps;
2248 unsigned int interval_overhead;
2251 * How many packets could we transmit in this interval?
2252 * If packets didn't fit in the previous interval, we will need
2253 * to transmit that many packets twice within this interval.
2255 packets_remaining = 2 * packets_remaining +
2256 bw_table->interval_bw[i].num_packets;
2258 /* Find the largest max packet size of this or the previous
2261 if (list_empty(&bw_table->interval_bw[i].endpoints))
2264 struct xhci_virt_ep *virt_ep;
2265 struct list_head *ep_entry;
2267 ep_entry = bw_table->interval_bw[i].endpoints.next;
2268 virt_ep = list_entry(ep_entry,
2269 struct xhci_virt_ep, bw_endpoint_list);
2270 /* Convert to blocks, rounding up */
2271 largest_mps = DIV_ROUND_UP(
2272 virt_ep->bw_info.max_packet_size,
2275 if (largest_mps > packet_size)
2276 packet_size = largest_mps;
2278 /* Use the larger overhead of this or the previous interval. */
2279 interval_overhead = xhci_get_largest_overhead(
2280 &bw_table->interval_bw[i]);
2281 if (interval_overhead > overhead)
2282 overhead = interval_overhead;
2284 /* How many packets can we evenly distribute across
2285 * (1 << (i + 1)) possible scheduling opportunities?
2287 packets_transmitted = packets_remaining >> (i + 1);
2289 /* Add in the bandwidth used for those scheduled packets */
2290 bw_added = packets_transmitted * (overhead + packet_size);
2292 /* How many packets do we have remaining to transmit? */
2293 packets_remaining = packets_remaining % (1 << (i + 1));
2295 /* What largest max packet size should those packets have? */
2296 /* If we've transmitted all packets, don't carry over the
2297 * largest packet size.
2299 if (packets_remaining == 0) {
2302 } else if (packets_transmitted > 0) {
2303 /* Otherwise if we do have remaining packets, and we've
2304 * scheduled some packets in this interval, take the
2305 * largest max packet size from endpoints with this
2308 packet_size = largest_mps;
2309 overhead = interval_overhead;
2311 /* Otherwise carry over packet_size and overhead from the last
2312 * time we had a remainder.
2314 bw_used += bw_added;
2315 if (bw_used > max_bandwidth) {
2316 xhci_warn(xhci, "Not enough bandwidth. "
2317 "Proposed: %u, Max: %u\n",
2318 bw_used, max_bandwidth);
2323 * Ok, we know we have some packets left over after even-handedly
2324 * scheduling interval 15. We don't know which microframes they will
2325 * fit into, so we over-schedule and say they will be scheduled every
2328 if (packets_remaining > 0)
2329 bw_used += overhead + packet_size;
2331 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2332 unsigned int port_index = virt_dev->real_port - 1;
2334 /* OK, we're manipulating a HS device attached to a
2335 * root port bandwidth domain. Include the number of active TTs
2336 * in the bandwidth used.
2338 bw_used += TT_HS_OVERHEAD *
2339 xhci->rh_bw[port_index].num_active_tts;
2342 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2343 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2344 "Available: %u " "percent",
2345 bw_used, max_bandwidth, bw_reserved,
2346 (max_bandwidth - bw_used - bw_reserved) * 100 /
2349 bw_used += bw_reserved;
2350 if (bw_used > max_bandwidth) {
2351 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2352 bw_used, max_bandwidth);
2356 bw_table->bw_used = bw_used;
2360 static bool xhci_is_async_ep(unsigned int ep_type)
2362 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2363 ep_type != ISOC_IN_EP &&
2364 ep_type != INT_IN_EP);
2367 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2369 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2372 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2374 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2376 if (ep_bw->ep_interval == 0)
2377 return SS_OVERHEAD_BURST +
2378 (ep_bw->mult * ep_bw->num_packets *
2379 (SS_OVERHEAD + mps));
2380 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2381 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2382 1 << ep_bw->ep_interval);
2386 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2387 struct xhci_bw_info *ep_bw,
2388 struct xhci_interval_bw_table *bw_table,
2389 struct usb_device *udev,
2390 struct xhci_virt_ep *virt_ep,
2391 struct xhci_tt_bw_info *tt_info)
2393 struct xhci_interval_bw *interval_bw;
2394 int normalized_interval;
2396 if (xhci_is_async_ep(ep_bw->type))
2399 if (udev->speed == USB_SPEED_SUPER) {
2400 if (xhci_is_sync_in_ep(ep_bw->type))
2401 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2402 xhci_get_ss_bw_consumed(ep_bw);
2404 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2405 xhci_get_ss_bw_consumed(ep_bw);
2409 /* SuperSpeed endpoints never get added to intervals in the table, so
2410 * this check is only valid for HS/FS/LS devices.
2412 if (list_empty(&virt_ep->bw_endpoint_list))
2414 /* For LS/FS devices, we need to translate the interval expressed in
2415 * microframes to frames.
2417 if (udev->speed == USB_SPEED_HIGH)
2418 normalized_interval = ep_bw->ep_interval;
2420 normalized_interval = ep_bw->ep_interval - 3;
2422 if (normalized_interval == 0)
2423 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2424 interval_bw = &bw_table->interval_bw[normalized_interval];
2425 interval_bw->num_packets -= ep_bw->num_packets;
2426 switch (udev->speed) {
2428 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2430 case USB_SPEED_FULL:
2431 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2433 case USB_SPEED_HIGH:
2434 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2436 case USB_SPEED_SUPER:
2437 case USB_SPEED_UNKNOWN:
2438 case USB_SPEED_WIRELESS:
2439 /* Should never happen because only LS/FS/HS endpoints will get
2440 * added to the endpoint list.
2445 tt_info->active_eps -= 1;
2446 list_del_init(&virt_ep->bw_endpoint_list);
2449 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2450 struct xhci_bw_info *ep_bw,
2451 struct xhci_interval_bw_table *bw_table,
2452 struct usb_device *udev,
2453 struct xhci_virt_ep *virt_ep,
2454 struct xhci_tt_bw_info *tt_info)
2456 struct xhci_interval_bw *interval_bw;
2457 struct xhci_virt_ep *smaller_ep;
2458 int normalized_interval;
2460 if (xhci_is_async_ep(ep_bw->type))
2463 if (udev->speed == USB_SPEED_SUPER) {
2464 if (xhci_is_sync_in_ep(ep_bw->type))
2465 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2466 xhci_get_ss_bw_consumed(ep_bw);
2468 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2469 xhci_get_ss_bw_consumed(ep_bw);
2473 /* For LS/FS devices, we need to translate the interval expressed in
2474 * microframes to frames.
2476 if (udev->speed == USB_SPEED_HIGH)
2477 normalized_interval = ep_bw->ep_interval;
2479 normalized_interval = ep_bw->ep_interval - 3;
2481 if (normalized_interval == 0)
2482 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2483 interval_bw = &bw_table->interval_bw[normalized_interval];
2484 interval_bw->num_packets += ep_bw->num_packets;
2485 switch (udev->speed) {
2487 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2489 case USB_SPEED_FULL:
2490 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2492 case USB_SPEED_HIGH:
2493 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2495 case USB_SPEED_SUPER:
2496 case USB_SPEED_UNKNOWN:
2497 case USB_SPEED_WIRELESS:
2498 /* Should never happen because only LS/FS/HS endpoints will get
2499 * added to the endpoint list.
2505 tt_info->active_eps += 1;
2506 /* Insert the endpoint into the list, largest max packet size first. */
2507 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2509 if (ep_bw->max_packet_size >=
2510 smaller_ep->bw_info.max_packet_size) {
2511 /* Add the new ep before the smaller endpoint */
2512 list_add_tail(&virt_ep->bw_endpoint_list,
2513 &smaller_ep->bw_endpoint_list);
2517 /* Add the new endpoint at the end of the list. */
2518 list_add_tail(&virt_ep->bw_endpoint_list,
2519 &interval_bw->endpoints);
2522 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2523 struct xhci_virt_device *virt_dev,
2526 struct xhci_root_port_bw_info *rh_bw_info;
2527 if (!virt_dev->tt_info)
2530 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2531 if (old_active_eps == 0 &&
2532 virt_dev->tt_info->active_eps != 0) {
2533 rh_bw_info->num_active_tts += 1;
2534 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2535 } else if (old_active_eps != 0 &&
2536 virt_dev->tt_info->active_eps == 0) {
2537 rh_bw_info->num_active_tts -= 1;
2538 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2542 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2543 struct xhci_virt_device *virt_dev,
2544 struct xhci_container_ctx *in_ctx)
2546 struct xhci_bw_info ep_bw_info[31];
2548 struct xhci_input_control_ctx *ctrl_ctx;
2549 int old_active_eps = 0;
2551 if (virt_dev->tt_info)
2552 old_active_eps = virt_dev->tt_info->active_eps;
2554 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2556 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2561 for (i = 0; i < 31; i++) {
2562 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2565 /* Make a copy of the BW info in case we need to revert this */
2566 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2567 sizeof(ep_bw_info[i]));
2568 /* Drop the endpoint from the interval table if the endpoint is
2569 * being dropped or changed.
2571 if (EP_IS_DROPPED(ctrl_ctx, i))
2572 xhci_drop_ep_from_interval_table(xhci,
2573 &virt_dev->eps[i].bw_info,
2579 /* Overwrite the information stored in the endpoints' bw_info */
2580 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2581 for (i = 0; i < 31; i++) {
2582 /* Add any changed or added endpoints to the interval table */
2583 if (EP_IS_ADDED(ctrl_ctx, i))
2584 xhci_add_ep_to_interval_table(xhci,
2585 &virt_dev->eps[i].bw_info,
2592 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2593 /* Ok, this fits in the bandwidth we have.
2594 * Update the number of active TTs.
2596 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2600 /* We don't have enough bandwidth for this, revert the stored info. */
2601 for (i = 0; i < 31; i++) {
2602 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2605 /* Drop the new copies of any added or changed endpoints from
2606 * the interval table.
2608 if (EP_IS_ADDED(ctrl_ctx, i)) {
2609 xhci_drop_ep_from_interval_table(xhci,
2610 &virt_dev->eps[i].bw_info,
2616 /* Revert the endpoint back to its old information */
2617 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2618 sizeof(ep_bw_info[i]));
2619 /* Add any changed or dropped endpoints back into the table */
2620 if (EP_IS_DROPPED(ctrl_ctx, i))
2621 xhci_add_ep_to_interval_table(xhci,
2622 &virt_dev->eps[i].bw_info,
2632 /* Issue a configure endpoint command or evaluate context command
2633 * and wait for it to finish.
2635 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2636 struct usb_device *udev,
2637 struct xhci_command *command,
2638 bool ctx_change, bool must_succeed)
2641 unsigned long flags;
2642 struct xhci_input_control_ctx *ctrl_ctx;
2643 struct xhci_virt_device *virt_dev;
2648 spin_lock_irqsave(&xhci->lock, flags);
2649 virt_dev = xhci->devs[udev->slot_id];
2651 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2653 spin_unlock_irqrestore(&xhci->lock, flags);
2654 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2659 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2660 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2661 spin_unlock_irqrestore(&xhci->lock, flags);
2662 xhci_warn(xhci, "Not enough host resources, "
2663 "active endpoint contexts = %u\n",
2664 xhci->num_active_eps);
2667 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2668 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2669 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2670 xhci_free_host_resources(xhci, ctrl_ctx);
2671 spin_unlock_irqrestore(&xhci->lock, flags);
2672 xhci_warn(xhci, "Not enough bandwidth\n");
2677 ret = xhci_queue_configure_endpoint(xhci, command,
2678 command->in_ctx->dma,
2679 udev->slot_id, must_succeed);
2681 ret = xhci_queue_evaluate_context(xhci, command,
2682 command->in_ctx->dma,
2683 udev->slot_id, must_succeed);
2685 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2686 xhci_free_host_resources(xhci, ctrl_ctx);
2687 spin_unlock_irqrestore(&xhci->lock, flags);
2688 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2689 "FIXME allocate a new ring segment");
2692 xhci_ring_cmd_db(xhci);
2693 spin_unlock_irqrestore(&xhci->lock, flags);
2695 /* Wait for the configure endpoint command to complete */
2696 wait_for_completion(command->completion);
2699 ret = xhci_configure_endpoint_result(xhci, udev,
2702 ret = xhci_evaluate_context_result(xhci, udev,
2705 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2706 spin_lock_irqsave(&xhci->lock, flags);
2707 /* If the command failed, remove the reserved resources.
2708 * Otherwise, clean up the estimate to include dropped eps.
2711 xhci_free_host_resources(xhci, ctrl_ctx);
2713 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2714 spin_unlock_irqrestore(&xhci->lock, flags);
2719 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2720 struct xhci_virt_device *vdev, int i)
2722 struct xhci_virt_ep *ep = &vdev->eps[i];
2724 if (ep->ep_state & EP_HAS_STREAMS) {
2725 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2726 xhci_get_endpoint_address(i));
2727 xhci_free_stream_info(xhci, ep->stream_info);
2728 ep->stream_info = NULL;
2729 ep->ep_state &= ~EP_HAS_STREAMS;
2733 /* Called after one or more calls to xhci_add_endpoint() or
2734 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2735 * to call xhci_reset_bandwidth().
2737 * Since we are in the middle of changing either configuration or
2738 * installing a new alt setting, the USB core won't allow URBs to be
2739 * enqueued for any endpoint on the old config or interface. Nothing
2740 * else should be touching the xhci->devs[slot_id] structure, so we
2741 * don't need to take the xhci->lock for manipulating that.
2743 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2747 struct xhci_hcd *xhci;
2748 struct xhci_virt_device *virt_dev;
2749 struct xhci_input_control_ctx *ctrl_ctx;
2750 struct xhci_slot_ctx *slot_ctx;
2751 struct xhci_command *command;
2753 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2756 xhci = hcd_to_xhci(hcd);
2757 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2758 (xhci->xhc_state & XHCI_STATE_REMOVING))
2761 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2762 virt_dev = xhci->devs[udev->slot_id];
2764 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2768 command->in_ctx = virt_dev->in_ctx;
2770 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2771 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2773 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2776 goto command_cleanup;
2778 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2779 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2780 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2782 /* Don't issue the command if there's no endpoints to update. */
2783 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2784 ctrl_ctx->drop_flags == 0) {
2786 goto command_cleanup;
2788 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2789 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2790 for (i = 31; i >= 1; i--) {
2791 __le32 le32 = cpu_to_le32(BIT(i));
2793 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2794 || (ctrl_ctx->add_flags & le32) || i == 1) {
2795 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2796 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2800 xhci_dbg(xhci, "New Input Control Context:\n");
2801 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2802 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2804 ret = xhci_configure_endpoint(xhci, udev, command,
2807 /* Callee should call reset_bandwidth() */
2808 goto command_cleanup;
2810 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2811 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2812 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2814 /* Free any rings that were dropped, but not changed. */
2815 for (i = 1; i < 31; ++i) {
2816 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2817 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2818 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2819 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2822 xhci_zero_in_ctx(xhci, virt_dev);
2824 * Install any rings for completely new endpoints or changed endpoints,
2825 * and free or cache any old rings from changed endpoints.
2827 for (i = 1; i < 31; ++i) {
2828 if (!virt_dev->eps[i].new_ring)
2830 /* Only cache or free the old ring if it exists.
2831 * It may not if this is the first add of an endpoint.
2833 if (virt_dev->eps[i].ring) {
2834 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2836 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2837 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2838 virt_dev->eps[i].new_ring = NULL;
2841 kfree(command->completion);
2847 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2849 struct xhci_hcd *xhci;
2850 struct xhci_virt_device *virt_dev;
2853 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2856 xhci = hcd_to_xhci(hcd);
2858 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2859 virt_dev = xhci->devs[udev->slot_id];
2860 /* Free any rings allocated for added endpoints */
2861 for (i = 0; i < 31; ++i) {
2862 if (virt_dev->eps[i].new_ring) {
2863 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2864 virt_dev->eps[i].new_ring = NULL;
2867 xhci_zero_in_ctx(xhci, virt_dev);
2870 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2871 struct xhci_container_ctx *in_ctx,
2872 struct xhci_container_ctx *out_ctx,
2873 struct xhci_input_control_ctx *ctrl_ctx,
2874 u32 add_flags, u32 drop_flags)
2876 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2877 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2878 xhci_slot_copy(xhci, in_ctx, out_ctx);
2879 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2881 xhci_dbg(xhci, "Input Context:\n");
2882 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2885 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2886 unsigned int slot_id, unsigned int ep_index,
2887 struct xhci_dequeue_state *deq_state)
2889 struct xhci_input_control_ctx *ctrl_ctx;
2890 struct xhci_container_ctx *in_ctx;
2891 struct xhci_ep_ctx *ep_ctx;
2895 in_ctx = xhci->devs[slot_id]->in_ctx;
2896 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2898 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2903 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2904 xhci->devs[slot_id]->out_ctx, ep_index);
2905 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2906 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2907 deq_state->new_deq_ptr);
2909 xhci_warn(xhci, "WARN Cannot submit config ep after "
2910 "reset ep command\n");
2911 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2912 deq_state->new_deq_seg,
2913 deq_state->new_deq_ptr);
2916 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2918 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2919 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2920 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2921 added_ctxs, added_ctxs);
2924 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2925 unsigned int ep_index, struct xhci_td *td)
2927 struct xhci_dequeue_state deq_state;
2928 struct xhci_virt_ep *ep;
2929 struct usb_device *udev = td->urb->dev;
2931 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2932 "Cleaning up stalled endpoint ring");
2933 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2934 /* We need to move the HW's dequeue pointer past this TD,
2935 * or it will attempt to resend it on the next doorbell ring.
2937 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2938 ep_index, ep->stopped_stream, td, &deq_state);
2940 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2943 /* HW with the reset endpoint quirk will use the saved dequeue state to
2944 * issue a configure endpoint command later.
2946 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2947 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2948 "Queueing new dequeue state");
2949 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2950 ep_index, ep->stopped_stream, &deq_state);
2952 /* Better hope no one uses the input context between now and the
2953 * reset endpoint completion!
2954 * XXX: No idea how this hardware will react when stream rings
2957 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2958 "Setting up input context for "
2959 "configure endpoint command");
2960 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2961 ep_index, &deq_state);
2965 /* Called when clearing halted device. The core should have sent the control
2966 * message to clear the device halt condition. The host side of the halt should
2967 * already be cleared with a reset endpoint command issued when the STALL tx
2968 * event was received.
2970 * Context: in_interrupt
2973 void xhci_endpoint_reset(struct usb_hcd *hcd,
2974 struct usb_host_endpoint *ep)
2976 struct xhci_hcd *xhci;
2978 xhci = hcd_to_xhci(hcd);
2981 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2982 * The Reset Endpoint Command may only be issued to endpoints in the
2983 * Halted state. If software wishes reset the Data Toggle or Sequence
2984 * Number of an endpoint that isn't in the Halted state, then software
2985 * may issue a Configure Endpoint Command with the Drop and Add bits set
2986 * for the target endpoint. that is in the Stopped state.
2989 /* For now just print debug to follow the situation */
2990 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
2991 ep->desc.bEndpointAddress);
2994 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2995 struct usb_device *udev, struct usb_host_endpoint *ep,
2996 unsigned int slot_id)
2999 unsigned int ep_index;
3000 unsigned int ep_state;
3004 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3007 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3008 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3009 " descriptor for ep 0x%x does not support streams\n",
3010 ep->desc.bEndpointAddress);
3014 ep_index = xhci_get_endpoint_index(&ep->desc);
3015 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3016 if (ep_state & EP_HAS_STREAMS ||
3017 ep_state & EP_GETTING_STREAMS) {
3018 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3019 "already has streams set up.\n",
3020 ep->desc.bEndpointAddress);
3021 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3022 "dynamic stream context array reallocation.\n");
3025 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3026 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3027 "endpoint 0x%x; URBs are pending.\n",
3028 ep->desc.bEndpointAddress);
3034 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3035 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3037 unsigned int max_streams;
3039 /* The stream context array size must be a power of two */
3040 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3042 * Find out how many primary stream array entries the host controller
3043 * supports. Later we may use secondary stream arrays (similar to 2nd
3044 * level page entries), but that's an optional feature for xHCI host
3045 * controllers. xHCs must support at least 4 stream IDs.
3047 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3048 if (*num_stream_ctxs > max_streams) {
3049 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3051 *num_stream_ctxs = max_streams;
3052 *num_streams = max_streams;
3056 /* Returns an error code if one of the endpoint already has streams.
3057 * This does not change any data structures, it only checks and gathers
3060 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3061 struct usb_device *udev,
3062 struct usb_host_endpoint **eps, unsigned int num_eps,
3063 unsigned int *num_streams, u32 *changed_ep_bitmask)
3065 unsigned int max_streams;
3066 unsigned int endpoint_flag;
3070 for (i = 0; i < num_eps; i++) {
3071 ret = xhci_check_streams_endpoint(xhci, udev,
3072 eps[i], udev->slot_id);
3076 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3077 if (max_streams < (*num_streams - 1)) {
3078 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3079 eps[i]->desc.bEndpointAddress,
3081 *num_streams = max_streams+1;
3084 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3085 if (*changed_ep_bitmask & endpoint_flag)
3087 *changed_ep_bitmask |= endpoint_flag;
3092 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3093 struct usb_device *udev,
3094 struct usb_host_endpoint **eps, unsigned int num_eps)
3096 u32 changed_ep_bitmask = 0;
3097 unsigned int slot_id;
3098 unsigned int ep_index;
3099 unsigned int ep_state;
3102 slot_id = udev->slot_id;
3103 if (!xhci->devs[slot_id])
3106 for (i = 0; i < num_eps; i++) {
3107 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3108 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3109 /* Are streams already being freed for the endpoint? */
3110 if (ep_state & EP_GETTING_NO_STREAMS) {
3111 xhci_warn(xhci, "WARN Can't disable streams for "
3113 "streams are being disabled already\n",
3114 eps[i]->desc.bEndpointAddress);
3117 /* Are there actually any streams to free? */
3118 if (!(ep_state & EP_HAS_STREAMS) &&
3119 !(ep_state & EP_GETTING_STREAMS)) {
3120 xhci_warn(xhci, "WARN Can't disable streams for "
3122 "streams are already disabled!\n",
3123 eps[i]->desc.bEndpointAddress);
3124 xhci_warn(xhci, "WARN xhci_free_streams() called "
3125 "with non-streams endpoint\n");
3128 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3130 return changed_ep_bitmask;
3134 * The USB device drivers use this function (through the HCD interface in USB
3135 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3136 * coordinate mass storage command queueing across multiple endpoints (basically
3137 * a stream ID == a task ID).
3139 * Setting up streams involves allocating the same size stream context array
3140 * for each endpoint and issuing a configure endpoint command for all endpoints.
3142 * Don't allow the call to succeed if one endpoint only supports one stream
3143 * (which means it doesn't support streams at all).
3145 * Drivers may get less stream IDs than they asked for, if the host controller
3146 * hardware or endpoints claim they can't support the number of requested
3149 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3150 struct usb_host_endpoint **eps, unsigned int num_eps,
3151 unsigned int num_streams, gfp_t mem_flags)
3154 struct xhci_hcd *xhci;
3155 struct xhci_virt_device *vdev;
3156 struct xhci_command *config_cmd;
3157 struct xhci_input_control_ctx *ctrl_ctx;
3158 unsigned int ep_index;
3159 unsigned int num_stream_ctxs;
3160 unsigned long flags;
3161 u32 changed_ep_bitmask = 0;
3166 /* Add one to the number of streams requested to account for
3167 * stream 0 that is reserved for xHCI usage.
3170 xhci = hcd_to_xhci(hcd);
3171 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3174 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3175 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3176 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3177 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3181 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3183 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3186 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3188 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3190 xhci_free_command(xhci, config_cmd);
3194 /* Check to make sure all endpoints are not already configured for
3195 * streams. While we're at it, find the maximum number of streams that
3196 * all the endpoints will support and check for duplicate endpoints.
3198 spin_lock_irqsave(&xhci->lock, flags);
3199 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3200 num_eps, &num_streams, &changed_ep_bitmask);
3202 xhci_free_command(xhci, config_cmd);
3203 spin_unlock_irqrestore(&xhci->lock, flags);
3206 if (num_streams <= 1) {
3207 xhci_warn(xhci, "WARN: endpoints can't handle "
3208 "more than one stream.\n");
3209 xhci_free_command(xhci, config_cmd);
3210 spin_unlock_irqrestore(&xhci->lock, flags);
3213 vdev = xhci->devs[udev->slot_id];
3214 /* Mark each endpoint as being in transition, so
3215 * xhci_urb_enqueue() will reject all URBs.
3217 for (i = 0; i < num_eps; i++) {
3218 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3219 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3221 spin_unlock_irqrestore(&xhci->lock, flags);
3223 /* Setup internal data structures and allocate HW data structures for
3224 * streams (but don't install the HW structures in the input context
3225 * until we're sure all memory allocation succeeded).
3227 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3228 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3229 num_stream_ctxs, num_streams);
3231 for (i = 0; i < num_eps; i++) {
3232 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3233 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3235 num_streams, mem_flags);
3236 if (!vdev->eps[ep_index].stream_info)
3238 /* Set maxPstreams in endpoint context and update deq ptr to
3239 * point to stream context array. FIXME
3243 /* Set up the input context for a configure endpoint command. */
3244 for (i = 0; i < num_eps; i++) {
3245 struct xhci_ep_ctx *ep_ctx;
3247 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3248 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3250 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3251 vdev->out_ctx, ep_index);
3252 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3253 vdev->eps[ep_index].stream_info);
3255 /* Tell the HW to drop its old copy of the endpoint context info
3256 * and add the updated copy from the input context.
3258 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3259 vdev->out_ctx, ctrl_ctx,
3260 changed_ep_bitmask, changed_ep_bitmask);
3262 /* Issue and wait for the configure endpoint command */
3263 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3266 /* xHC rejected the configure endpoint command for some reason, so we
3267 * leave the old ring intact and free our internal streams data
3273 spin_lock_irqsave(&xhci->lock, flags);
3274 for (i = 0; i < num_eps; i++) {
3275 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3276 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3277 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3278 udev->slot_id, ep_index);
3279 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3281 xhci_free_command(xhci, config_cmd);
3282 spin_unlock_irqrestore(&xhci->lock, flags);
3284 /* Subtract 1 for stream 0, which drivers can't use */
3285 return num_streams - 1;
3288 /* If it didn't work, free the streams! */
3289 for (i = 0; i < num_eps; i++) {
3290 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3291 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3292 vdev->eps[ep_index].stream_info = NULL;
3293 /* FIXME Unset maxPstreams in endpoint context and
3294 * update deq ptr to point to normal string ring.
3296 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3297 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3298 xhci_endpoint_zero(xhci, vdev, eps[i]);
3300 xhci_free_command(xhci, config_cmd);
3304 /* Transition the endpoint from using streams to being a "normal" endpoint
3307 * Modify the endpoint context state, submit a configure endpoint command,
3308 * and free all endpoint rings for streams if that completes successfully.
3310 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3311 struct usb_host_endpoint **eps, unsigned int num_eps,
3315 struct xhci_hcd *xhci;
3316 struct xhci_virt_device *vdev;
3317 struct xhci_command *command;
3318 struct xhci_input_control_ctx *ctrl_ctx;
3319 unsigned int ep_index;
3320 unsigned long flags;
3321 u32 changed_ep_bitmask;
3323 xhci = hcd_to_xhci(hcd);
3324 vdev = xhci->devs[udev->slot_id];
3326 /* Set up a configure endpoint command to remove the streams rings */
3327 spin_lock_irqsave(&xhci->lock, flags);
3328 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3329 udev, eps, num_eps);
3330 if (changed_ep_bitmask == 0) {
3331 spin_unlock_irqrestore(&xhci->lock, flags);
3335 /* Use the xhci_command structure from the first endpoint. We may have
3336 * allocated too many, but the driver may call xhci_free_streams() for
3337 * each endpoint it grouped into one call to xhci_alloc_streams().
3339 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3340 command = vdev->eps[ep_index].stream_info->free_streams_command;
3341 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3343 spin_unlock_irqrestore(&xhci->lock, flags);
3344 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3349 for (i = 0; i < num_eps; i++) {
3350 struct xhci_ep_ctx *ep_ctx;
3352 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3353 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3354 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3355 EP_GETTING_NO_STREAMS;
3357 xhci_endpoint_copy(xhci, command->in_ctx,
3358 vdev->out_ctx, ep_index);
3359 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3360 &vdev->eps[ep_index]);
3362 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3363 vdev->out_ctx, ctrl_ctx,
3364 changed_ep_bitmask, changed_ep_bitmask);
3365 spin_unlock_irqrestore(&xhci->lock, flags);
3367 /* Issue and wait for the configure endpoint command,
3368 * which must succeed.
3370 ret = xhci_configure_endpoint(xhci, udev, command,
3373 /* xHC rejected the configure endpoint command for some reason, so we
3374 * leave the streams rings intact.
3379 spin_lock_irqsave(&xhci->lock, flags);
3380 for (i = 0; i < num_eps; i++) {
3381 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3382 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3383 vdev->eps[ep_index].stream_info = NULL;
3384 /* FIXME Unset maxPstreams in endpoint context and
3385 * update deq ptr to point to normal string ring.
3387 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3388 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3390 spin_unlock_irqrestore(&xhci->lock, flags);
3396 * Deletes endpoint resources for endpoints that were active before a Reset
3397 * Device command, or a Disable Slot command. The Reset Device command leaves
3398 * the control endpoint intact, whereas the Disable Slot command deletes it.
3400 * Must be called with xhci->lock held.
3402 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3403 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3406 unsigned int num_dropped_eps = 0;
3407 unsigned int drop_flags = 0;
3409 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3410 if (virt_dev->eps[i].ring) {
3411 drop_flags |= 1 << i;
3415 xhci->num_active_eps -= num_dropped_eps;
3416 if (num_dropped_eps)
3417 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3418 "Dropped %u ep ctxs, flags = 0x%x, "
3420 num_dropped_eps, drop_flags,
3421 xhci->num_active_eps);
3425 * This submits a Reset Device Command, which will set the device state to 0,
3426 * set the device address to 0, and disable all the endpoints except the default
3427 * control endpoint. The USB core should come back and call
3428 * xhci_address_device(), and then re-set up the configuration. If this is
3429 * called because of a usb_reset_and_verify_device(), then the old alternate
3430 * settings will be re-installed through the normal bandwidth allocation
3433 * Wait for the Reset Device command to finish. Remove all structures
3434 * associated with the endpoints that were disabled. Clear the input device
3435 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3437 * If the virt_dev to be reset does not exist or does not match the udev,
3438 * it means the device is lost, possibly due to the xHC restore error and
3439 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3440 * re-allocate the device.
3442 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3445 unsigned long flags;
3446 struct xhci_hcd *xhci;
3447 unsigned int slot_id;
3448 struct xhci_virt_device *virt_dev;
3449 struct xhci_command *reset_device_cmd;
3450 int last_freed_endpoint;
3451 struct xhci_slot_ctx *slot_ctx;
3452 int old_active_eps = 0;
3454 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3457 xhci = hcd_to_xhci(hcd);
3458 slot_id = udev->slot_id;
3459 virt_dev = xhci->devs[slot_id];
3461 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3462 "not exist. Re-allocate the device\n", slot_id);
3463 ret = xhci_alloc_dev(hcd, udev);
3470 if (virt_dev->tt_info)
3471 old_active_eps = virt_dev->tt_info->active_eps;
3473 if (virt_dev->udev != udev) {
3474 /* If the virt_dev and the udev does not match, this virt_dev
3475 * may belong to another udev.
3476 * Re-allocate the device.
3478 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3479 "not match the udev. Re-allocate the device\n",
3481 ret = xhci_alloc_dev(hcd, udev);
3488 /* If device is not setup, there is no point in resetting it */
3489 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3490 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3491 SLOT_STATE_DISABLED)
3494 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3495 /* Allocate the command structure that holds the struct completion.
3496 * Assume we're in process context, since the normal device reset
3497 * process has to wait for the device anyway. Storage devices are
3498 * reset as part of error handling, so use GFP_NOIO instead of
3501 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3502 if (!reset_device_cmd) {
3503 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3507 /* Attempt to submit the Reset Device command to the command ring */
3508 spin_lock_irqsave(&xhci->lock, flags);
3510 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3512 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3513 spin_unlock_irqrestore(&xhci->lock, flags);
3514 goto command_cleanup;
3516 xhci_ring_cmd_db(xhci);
3517 spin_unlock_irqrestore(&xhci->lock, flags);
3519 /* Wait for the Reset Device command to finish */
3520 wait_for_completion(reset_device_cmd->completion);
3522 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3523 * unless we tried to reset a slot ID that wasn't enabled,
3524 * or the device wasn't in the addressed or configured state.
3526 ret = reset_device_cmd->status;
3528 case COMP_CMD_ABORT:
3530 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3532 goto command_cleanup;
3533 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3534 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3535 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3537 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3538 xhci_dbg(xhci, "Not freeing device rings.\n");
3539 /* Don't treat this as an error. May change my mind later. */
3541 goto command_cleanup;
3543 xhci_dbg(xhci, "Successful reset device command.\n");
3546 if (xhci_is_vendor_info_code(xhci, ret))
3548 xhci_warn(xhci, "Unknown completion code %u for "
3549 "reset device command.\n", ret);
3551 goto command_cleanup;
3554 /* Free up host controller endpoint resources */
3555 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3556 spin_lock_irqsave(&xhci->lock, flags);
3557 /* Don't delete the default control endpoint resources */
3558 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3559 spin_unlock_irqrestore(&xhci->lock, flags);
3562 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3563 last_freed_endpoint = 1;
3564 for (i = 1; i < 31; ++i) {
3565 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3567 if (ep->ep_state & EP_HAS_STREAMS) {
3568 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3569 xhci_get_endpoint_address(i));
3570 xhci_free_stream_info(xhci, ep->stream_info);
3571 ep->stream_info = NULL;
3572 ep->ep_state &= ~EP_HAS_STREAMS;
3576 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3577 last_freed_endpoint = i;
3579 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3580 xhci_drop_ep_from_interval_table(xhci,
3581 &virt_dev->eps[i].bw_info,
3586 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3588 /* If necessary, update the number of active TTs on this root port */
3589 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3591 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3592 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3596 xhci_free_command(xhci, reset_device_cmd);
3601 * At this point, the struct usb_device is about to go away, the device has
3602 * disconnected, and all traffic has been stopped and the endpoints have been
3603 * disabled. Free any HC data structures associated with that device.
3605 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3607 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3608 struct xhci_virt_device *virt_dev;
3609 unsigned long flags;
3612 struct xhci_command *command;
3614 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3618 #ifndef CONFIG_USB_DEFAULT_PERSIST
3620 * We called pm_runtime_get_noresume when the device was attached.
3621 * Decrement the counter here to allow controller to runtime suspend
3622 * if no devices remain.
3624 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3625 pm_runtime_put_noidle(hcd->self.controller);
3628 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3629 /* If the host is halted due to driver unload, we still need to free the
3632 if (ret <= 0 && ret != -ENODEV) {
3637 virt_dev = xhci->devs[udev->slot_id];
3639 /* Stop any wayward timer functions (which may grab the lock) */
3640 for (i = 0; i < 31; ++i) {
3641 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3642 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3645 spin_lock_irqsave(&xhci->lock, flags);
3646 /* Don't disable the slot if the host controller is dead. */
3647 state = readl(&xhci->op_regs->status);
3648 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3649 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3650 xhci_free_virt_device(xhci, udev->slot_id);
3651 spin_unlock_irqrestore(&xhci->lock, flags);
3656 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3658 spin_unlock_irqrestore(&xhci->lock, flags);
3659 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3662 xhci_ring_cmd_db(xhci);
3663 spin_unlock_irqrestore(&xhci->lock, flags);
3666 * Event command completion handler will free any data structures
3667 * associated with the slot. XXX Can free sleep?
3672 * Checks if we have enough host controller resources for the default control
3675 * Must be called with xhci->lock held.
3677 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3679 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3680 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3681 "Not enough ep ctxs: "
3682 "%u active, need to add 1, limit is %u.",
3683 xhci->num_active_eps, xhci->limit_active_eps);
3686 xhci->num_active_eps += 1;
3687 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3688 "Adding 1 ep ctx, %u now active.",
3689 xhci->num_active_eps);
3695 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3696 * timed out, or allocating memory failed. Returns 1 on success.
3698 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3700 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3701 unsigned long flags;
3703 struct xhci_command *command;
3705 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3709 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3710 mutex_lock(&xhci->mutex);
3711 spin_lock_irqsave(&xhci->lock, flags);
3712 command->completion = &xhci->addr_dev;
3713 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3715 spin_unlock_irqrestore(&xhci->lock, flags);
3716 mutex_unlock(&xhci->mutex);
3717 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3721 xhci_ring_cmd_db(xhci);
3722 spin_unlock_irqrestore(&xhci->lock, flags);
3724 wait_for_completion(command->completion);
3725 slot_id = xhci->slot_id;
3726 mutex_unlock(&xhci->mutex);
3728 if (!slot_id || command->status != COMP_SUCCESS) {
3729 xhci_err(xhci, "Error while assigning device slot ID\n");
3730 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3732 readl(&xhci->cap_regs->hcs_params1)));
3737 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3738 spin_lock_irqsave(&xhci->lock, flags);
3739 ret = xhci_reserve_host_control_ep_resources(xhci);
3741 spin_unlock_irqrestore(&xhci->lock, flags);
3742 xhci_warn(xhci, "Not enough host resources, "
3743 "active endpoint contexts = %u\n",
3744 xhci->num_active_eps);
3747 spin_unlock_irqrestore(&xhci->lock, flags);
3749 /* Use GFP_NOIO, since this function can be called from
3750 * xhci_discover_or_reset_device(), which may be called as part of
3751 * mass storage driver error handling.
3753 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3754 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3757 udev->slot_id = slot_id;
3759 #ifndef CONFIG_USB_DEFAULT_PERSIST
3761 * If resetting upon resume, we can't put the controller into runtime
3762 * suspend if there is a device attached.
3764 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3765 pm_runtime_get_noresume(hcd->self.controller);
3770 /* Is this a LS or FS device under a HS hub? */
3771 /* Hub or peripherial? */
3775 /* Disable slot, if we can do it without mem alloc */
3776 spin_lock_irqsave(&xhci->lock, flags);
3777 command->completion = NULL;
3778 command->status = 0;
3779 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3781 xhci_ring_cmd_db(xhci);
3782 spin_unlock_irqrestore(&xhci->lock, flags);
3787 * Issue an Address Device command and optionally send a corresponding
3788 * SetAddress request to the device.
3790 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3791 enum xhci_setup_dev setup)
3793 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3794 unsigned long flags;
3795 struct xhci_virt_device *virt_dev;
3797 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3798 struct xhci_slot_ctx *slot_ctx;
3799 struct xhci_input_control_ctx *ctrl_ctx;
3801 struct xhci_command *command = NULL;
3803 mutex_lock(&xhci->mutex);
3805 if (xhci->xhc_state) /* dying, removing or halted */
3808 if (!udev->slot_id) {
3809 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3810 "Bad Slot ID %d", udev->slot_id);
3815 virt_dev = xhci->devs[udev->slot_id];
3817 if (WARN_ON(!virt_dev)) {
3819 * In plug/unplug torture test with an NEC controller,
3820 * a zero-dereference was observed once due to virt_dev = 0.
3821 * Print useful debug rather than crash if it is observed again!
3823 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3829 if (setup == SETUP_CONTEXT_ONLY) {
3830 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3831 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3832 SLOT_STATE_DEFAULT) {
3833 xhci_dbg(xhci, "Slot already in default state\n");
3838 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3844 command->in_ctx = virt_dev->in_ctx;
3845 command->completion = &xhci->addr_dev;
3847 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3848 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3850 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3856 * If this is the first Set Address since device plug-in or
3857 * virt_device realloaction after a resume with an xHCI power loss,
3858 * then set up the slot context.
3860 if (!slot_ctx->dev_info)
3861 xhci_setup_addressable_virt_dev(xhci, udev);
3862 /* Otherwise, update the control endpoint ring enqueue pointer. */
3864 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3865 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3866 ctrl_ctx->drop_flags = 0;
3868 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3869 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3870 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3871 le32_to_cpu(slot_ctx->dev_info) >> 27);
3873 spin_lock_irqsave(&xhci->lock, flags);
3874 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3875 udev->slot_id, setup);
3877 spin_unlock_irqrestore(&xhci->lock, flags);
3878 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3879 "FIXME: allocate a command ring segment");
3882 xhci_ring_cmd_db(xhci);
3883 spin_unlock_irqrestore(&xhci->lock, flags);
3885 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3886 wait_for_completion(command->completion);
3888 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3889 * the SetAddress() "recovery interval" required by USB and aborting the
3890 * command on a timeout.
3892 switch (command->status) {
3893 case COMP_CMD_ABORT:
3895 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3898 case COMP_CTX_STATE:
3900 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3901 act, udev->slot_id);
3905 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3909 dev_warn(&udev->dev,
3910 "ERROR: Incompatible device for setup %s command\n", act);
3914 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3915 "Successful setup %s command", act);
3919 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3920 act, command->status);
3921 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3922 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3923 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3929 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3930 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3931 "Op regs DCBAA ptr = %#016llx", temp_64);
3932 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3933 "Slot ID %d dcbaa entry @%p = %#016llx",
3935 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3936 (unsigned long long)
3937 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3938 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3939 "Output Context DMA address = %#08llx",
3940 (unsigned long long)virt_dev->out_ctx->dma);
3941 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3942 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3943 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3944 le32_to_cpu(slot_ctx->dev_info) >> 27);
3945 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3946 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3948 * USB core uses address 1 for the roothubs, so we add one to the
3949 * address given back to us by the HC.
3951 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3952 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3953 le32_to_cpu(slot_ctx->dev_info) >> 27);
3954 /* Zero the input context control for later use */
3955 ctrl_ctx->add_flags = 0;
3956 ctrl_ctx->drop_flags = 0;
3958 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3959 "Internal device address = %d",
3960 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3962 mutex_unlock(&xhci->mutex);
3967 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3969 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3972 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3974 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3978 * Transfer the port index into real index in the HW port status
3979 * registers. Caculate offset between the port's PORTSC register
3980 * and port status base. Divide the number of per port register
3981 * to get the real index. The raw port number bases 1.
3983 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3985 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3986 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3987 __le32 __iomem *addr;
3990 if (hcd->speed < HCD_USB3)
3991 addr = xhci->usb2_ports[port1 - 1];
3993 addr = xhci->usb3_ports[port1 - 1];
3995 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
4000 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4001 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4003 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4004 struct usb_device *udev, u16 max_exit_latency)
4006 struct xhci_virt_device *virt_dev;
4007 struct xhci_command *command;
4008 struct xhci_input_control_ctx *ctrl_ctx;
4009 struct xhci_slot_ctx *slot_ctx;
4010 unsigned long flags;
4013 spin_lock_irqsave(&xhci->lock, flags);
4015 virt_dev = xhci->devs[udev->slot_id];
4018 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4019 * xHC was re-initialized. Exit latency will be set later after
4020 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4023 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4024 spin_unlock_irqrestore(&xhci->lock, flags);
4028 /* Attempt to issue an Evaluate Context command to change the MEL. */
4029 command = xhci->lpm_command;
4030 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4032 spin_unlock_irqrestore(&xhci->lock, flags);
4033 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4038 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4039 spin_unlock_irqrestore(&xhci->lock, flags);
4041 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4042 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4043 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4044 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4045 slot_ctx->dev_state = 0;
4047 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4048 "Set up evaluate context for LPM MEL change.");
4049 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4050 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4052 /* Issue and wait for the evaluate context command. */
4053 ret = xhci_configure_endpoint(xhci, udev, command,
4055 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4056 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4059 spin_lock_irqsave(&xhci->lock, flags);
4060 virt_dev->current_mel = max_exit_latency;
4061 spin_unlock_irqrestore(&xhci->lock, flags);
4068 /* BESL to HIRD Encoding array for USB2 LPM */
4069 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4070 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4072 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4073 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4074 struct usb_device *udev)
4076 int u2del, besl, besl_host;
4077 int besl_device = 0;
4080 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4081 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4083 if (field & USB_BESL_SUPPORT) {
4084 for (besl_host = 0; besl_host < 16; besl_host++) {
4085 if (xhci_besl_encoding[besl_host] >= u2del)
4088 /* Use baseline BESL value as default */
4089 if (field & USB_BESL_BASELINE_VALID)
4090 besl_device = USB_GET_BESL_BASELINE(field);
4091 else if (field & USB_BESL_DEEP_VALID)
4092 besl_device = USB_GET_BESL_DEEP(field);
4097 besl_host = (u2del - 51) / 75 + 1;
4100 besl = besl_host + besl_device;
4107 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4108 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4115 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4117 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4118 l1 = udev->l1_params.timeout / 256;
4120 /* device has preferred BESLD */
4121 if (field & USB_BESL_DEEP_VALID) {
4122 besld = USB_GET_BESL_DEEP(field);
4126 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4129 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4130 struct usb_device *udev, int enable)
4132 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4133 __le32 __iomem **port_array;
4134 __le32 __iomem *pm_addr, *hlpm_addr;
4135 u32 pm_val, hlpm_val, field;
4136 unsigned int port_num;
4137 unsigned long flags;
4138 int hird, exit_latency;
4141 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4145 if (!udev->parent || udev->parent->parent ||
4146 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4149 if (udev->usb2_hw_lpm_capable != 1)
4152 spin_lock_irqsave(&xhci->lock, flags);
4154 port_array = xhci->usb2_ports;
4155 port_num = udev->portnum - 1;
4156 pm_addr = port_array[port_num] + PORTPMSC;
4157 pm_val = readl(pm_addr);
4158 hlpm_addr = port_array[port_num] + PORTHLPMC;
4159 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4161 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4162 enable ? "enable" : "disable", port_num + 1);
4165 /* Host supports BESL timeout instead of HIRD */
4166 if (udev->usb2_hw_lpm_besl_capable) {
4167 /* if device doesn't have a preferred BESL value use a
4168 * default one which works with mixed HIRD and BESL
4169 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4171 if ((field & USB_BESL_SUPPORT) &&
4172 (field & USB_BESL_BASELINE_VALID))
4173 hird = USB_GET_BESL_BASELINE(field);
4175 hird = udev->l1_params.besl;
4177 exit_latency = xhci_besl_encoding[hird];
4178 spin_unlock_irqrestore(&xhci->lock, flags);
4180 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4181 * input context for link powermanagement evaluate
4182 * context commands. It is protected by hcd->bandwidth
4183 * mutex and is shared by all devices. We need to set
4184 * the max ext latency in USB 2 BESL LPM as well, so
4185 * use the same mutex and xhci_change_max_exit_latency()
4187 mutex_lock(hcd->bandwidth_mutex);
4188 ret = xhci_change_max_exit_latency(xhci, udev,
4190 mutex_unlock(hcd->bandwidth_mutex);
4194 spin_lock_irqsave(&xhci->lock, flags);
4196 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4197 writel(hlpm_val, hlpm_addr);
4201 hird = xhci_calculate_hird_besl(xhci, udev);
4204 pm_val &= ~PORT_HIRD_MASK;
4205 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4206 writel(pm_val, pm_addr);
4207 pm_val = readl(pm_addr);
4209 writel(pm_val, pm_addr);
4213 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4214 writel(pm_val, pm_addr);
4217 if (udev->usb2_hw_lpm_besl_capable) {
4218 spin_unlock_irqrestore(&xhci->lock, flags);
4219 mutex_lock(hcd->bandwidth_mutex);
4220 xhci_change_max_exit_latency(xhci, udev, 0);
4221 mutex_unlock(hcd->bandwidth_mutex);
4226 spin_unlock_irqrestore(&xhci->lock, flags);
4230 /* check if a usb2 port supports a given extened capability protocol
4231 * only USB2 ports extended protocol capability values are cached.
4232 * Return 1 if capability is supported
4234 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4235 unsigned capability)
4237 u32 port_offset, port_count;
4240 for (i = 0; i < xhci->num_ext_caps; i++) {
4241 if (xhci->ext_caps[i] & capability) {
4242 /* port offsets starts at 1 */
4243 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4244 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4245 if (port >= port_offset &&
4246 port < port_offset + port_count)
4253 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4255 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4256 int portnum = udev->portnum - 1;
4258 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4262 /* we only support lpm for non-hub device connected to root hub yet */
4263 if (!udev->parent || udev->parent->parent ||
4264 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4267 if (xhci->hw_lpm_support == 1 &&
4268 xhci_check_usb2_port_capability(
4269 xhci, portnum, XHCI_HLC)) {
4270 udev->usb2_hw_lpm_capable = 1;
4271 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4272 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4273 if (xhci_check_usb2_port_capability(xhci, portnum,
4275 udev->usb2_hw_lpm_besl_capable = 1;
4281 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4283 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4284 static unsigned long long xhci_service_interval_to_ns(
4285 struct usb_endpoint_descriptor *desc)
4287 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4290 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4291 enum usb3_link_state state)
4293 unsigned long long sel;
4294 unsigned long long pel;
4295 unsigned int max_sel_pel;
4300 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4301 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4302 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4303 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4307 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4308 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4309 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4313 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4315 return USB3_LPM_DISABLED;
4318 if (sel <= max_sel_pel && pel <= max_sel_pel)
4319 return USB3_LPM_DEVICE_INITIATED;
4321 if (sel > max_sel_pel)
4322 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4323 "due to long SEL %llu ms\n",
4326 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4327 "due to long PEL %llu ms\n",
4329 return USB3_LPM_DISABLED;
4332 /* The U1 timeout should be the maximum of the following values:
4333 * - For control endpoints, U1 system exit latency (SEL) * 3
4334 * - For bulk endpoints, U1 SEL * 5
4335 * - For interrupt endpoints:
4336 * - Notification EPs, U1 SEL * 3
4337 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4338 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4340 static unsigned long long xhci_calculate_intel_u1_timeout(
4341 struct usb_device *udev,
4342 struct usb_endpoint_descriptor *desc)
4344 unsigned long long timeout_ns;
4348 ep_type = usb_endpoint_type(desc);
4350 case USB_ENDPOINT_XFER_CONTROL:
4351 timeout_ns = udev->u1_params.sel * 3;
4353 case USB_ENDPOINT_XFER_BULK:
4354 timeout_ns = udev->u1_params.sel * 5;
4356 case USB_ENDPOINT_XFER_INT:
4357 intr_type = usb_endpoint_interrupt_type(desc);
4358 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4359 timeout_ns = udev->u1_params.sel * 3;
4362 /* Otherwise the calculation is the same as isoc eps */
4363 case USB_ENDPOINT_XFER_ISOC:
4364 timeout_ns = xhci_service_interval_to_ns(desc);
4365 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4366 if (timeout_ns < udev->u1_params.sel * 2)
4367 timeout_ns = udev->u1_params.sel * 2;
4376 /* Returns the hub-encoded U1 timeout value. */
4377 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4378 struct usb_device *udev,
4379 struct usb_endpoint_descriptor *desc)
4381 unsigned long long timeout_ns;
4383 if (xhci->quirks & XHCI_INTEL_HOST)
4384 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4386 timeout_ns = udev->u1_params.sel;
4388 /* The U1 timeout is encoded in 1us intervals.
4389 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4391 if (timeout_ns == USB3_LPM_DISABLED)
4394 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4396 /* If the necessary timeout value is bigger than what we can set in the
4397 * USB 3.0 hub, we have to disable hub-initiated U1.
4399 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4401 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4402 "due to long timeout %llu ms\n", timeout_ns);
4403 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4406 /* The U2 timeout should be the maximum of:
4407 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4408 * - largest bInterval of any active periodic endpoint (to avoid going
4409 * into lower power link states between intervals).
4410 * - the U2 Exit Latency of the device
4412 static unsigned long long xhci_calculate_intel_u2_timeout(
4413 struct usb_device *udev,
4414 struct usb_endpoint_descriptor *desc)
4416 unsigned long long timeout_ns;
4417 unsigned long long u2_del_ns;
4419 timeout_ns = 10 * 1000 * 1000;
4421 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4422 (xhci_service_interval_to_ns(desc) > timeout_ns))
4423 timeout_ns = xhci_service_interval_to_ns(desc);
4425 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4426 if (u2_del_ns > timeout_ns)
4427 timeout_ns = u2_del_ns;
4432 /* Returns the hub-encoded U2 timeout value. */
4433 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4434 struct usb_device *udev,
4435 struct usb_endpoint_descriptor *desc)
4437 unsigned long long timeout_ns;
4439 if (xhci->quirks & XHCI_INTEL_HOST)
4440 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4442 timeout_ns = udev->u2_params.sel;
4444 /* The U2 timeout is encoded in 256us intervals */
4445 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4446 /* If the necessary timeout value is bigger than what we can set in the
4447 * USB 3.0 hub, we have to disable hub-initiated U2.
4449 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4451 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4452 "due to long timeout %llu ms\n", timeout_ns);
4453 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4456 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4457 struct usb_device *udev,
4458 struct usb_endpoint_descriptor *desc,
4459 enum usb3_link_state state,
4462 if (state == USB3_LPM_U1)
4463 return xhci_calculate_u1_timeout(xhci, udev, desc);
4464 else if (state == USB3_LPM_U2)
4465 return xhci_calculate_u2_timeout(xhci, udev, desc);
4467 return USB3_LPM_DISABLED;
4470 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4471 struct usb_device *udev,
4472 struct usb_endpoint_descriptor *desc,
4473 enum usb3_link_state state,
4478 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4479 desc, state, timeout);
4481 /* If we found we can't enable hub-initiated LPM, or
4482 * the U1 or U2 exit latency was too high to allow
4483 * device-initiated LPM as well, just stop searching.
4485 if (alt_timeout == USB3_LPM_DISABLED ||
4486 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4487 *timeout = alt_timeout;
4490 if (alt_timeout > *timeout)
4491 *timeout = alt_timeout;
4495 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4496 struct usb_device *udev,
4497 struct usb_host_interface *alt,
4498 enum usb3_link_state state,
4503 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4504 if (xhci_update_timeout_for_endpoint(xhci, udev,
4505 &alt->endpoint[j].desc, state, timeout))
4512 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4513 enum usb3_link_state state)
4515 struct usb_device *parent;
4516 unsigned int num_hubs;
4518 if (state == USB3_LPM_U2)
4521 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4522 for (parent = udev->parent, num_hubs = 0; parent->parent;
4523 parent = parent->parent)
4529 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4530 " below second-tier hub.\n");
4531 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4532 "to decrease power consumption.\n");
4536 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4537 struct usb_device *udev,
4538 enum usb3_link_state state)
4540 if (xhci->quirks & XHCI_INTEL_HOST)
4541 return xhci_check_intel_tier_policy(udev, state);
4546 /* Returns the U1 or U2 timeout that should be enabled.
4547 * If the tier check or timeout setting functions return with a non-zero exit
4548 * code, that means the timeout value has been finalized and we shouldn't look
4549 * at any more endpoints.
4551 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4552 struct usb_device *udev, enum usb3_link_state state)
4554 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4555 struct usb_host_config *config;
4558 u16 timeout = USB3_LPM_DISABLED;
4560 if (state == USB3_LPM_U1)
4562 else if (state == USB3_LPM_U2)
4565 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4570 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4573 /* Gather some information about the currently installed configuration
4574 * and alternate interface settings.
4576 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4580 config = udev->actconfig;
4584 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4585 struct usb_driver *driver;
4586 struct usb_interface *intf = config->interface[i];
4591 /* Check if any currently bound drivers want hub-initiated LPM
4594 if (intf->dev.driver) {
4595 driver = to_usb_driver(intf->dev.driver);
4596 if (driver && driver->disable_hub_initiated_lpm) {
4597 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4598 "at request of driver %s\n",
4599 state_name, driver->name);
4600 return xhci_get_timeout_no_hub_lpm(udev, state);
4604 /* Not sure how this could happen... */
4605 if (!intf->cur_altsetting)
4608 if (xhci_update_timeout_for_interface(xhci, udev,
4609 intf->cur_altsetting,
4616 static int calculate_max_exit_latency(struct usb_device *udev,
4617 enum usb3_link_state state_changed,
4618 u16 hub_encoded_timeout)
4620 unsigned long long u1_mel_us = 0;
4621 unsigned long long u2_mel_us = 0;
4622 unsigned long long mel_us = 0;
4628 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4629 hub_encoded_timeout == USB3_LPM_DISABLED);
4630 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4631 hub_encoded_timeout == USB3_LPM_DISABLED);
4633 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4634 hub_encoded_timeout != USB3_LPM_DISABLED);
4635 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4636 hub_encoded_timeout != USB3_LPM_DISABLED);
4638 /* If U1 was already enabled and we're not disabling it,
4639 * or we're going to enable U1, account for the U1 max exit latency.
4641 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4643 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4644 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4646 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4648 if (u1_mel_us > u2_mel_us)
4652 /* xHCI host controller max exit latency field is only 16 bits wide. */
4653 if (mel_us > MAX_EXIT) {
4654 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4655 "is too big.\n", mel_us);
4661 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4662 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4663 struct usb_device *udev, enum usb3_link_state state)
4665 struct xhci_hcd *xhci;
4666 u16 hub_encoded_timeout;
4670 xhci = hcd_to_xhci(hcd);
4671 /* The LPM timeout values are pretty host-controller specific, so don't
4672 * enable hub-initiated timeouts unless the vendor has provided
4673 * information about their timeout algorithm.
4675 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4676 !xhci->devs[udev->slot_id])
4677 return USB3_LPM_DISABLED;
4679 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4680 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4682 /* Max Exit Latency is too big, disable LPM. */
4683 hub_encoded_timeout = USB3_LPM_DISABLED;
4687 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4690 return hub_encoded_timeout;
4693 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4694 struct usb_device *udev, enum usb3_link_state state)
4696 struct xhci_hcd *xhci;
4699 xhci = hcd_to_xhci(hcd);
4700 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4701 !xhci->devs[udev->slot_id])
4704 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4705 return xhci_change_max_exit_latency(xhci, udev, mel);
4707 #else /* CONFIG_PM */
4709 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4710 struct usb_device *udev, int enable)
4715 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4720 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4721 struct usb_device *udev, enum usb3_link_state state)
4723 return USB3_LPM_DISABLED;
4726 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4727 struct usb_device *udev, enum usb3_link_state state)
4731 #endif /* CONFIG_PM */
4733 /*-------------------------------------------------------------------------*/
4735 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4736 * internal data structures for the device.
4738 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4739 struct usb_tt *tt, gfp_t mem_flags)
4741 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4742 struct xhci_virt_device *vdev;
4743 struct xhci_command *config_cmd;
4744 struct xhci_input_control_ctx *ctrl_ctx;
4745 struct xhci_slot_ctx *slot_ctx;
4746 unsigned long flags;
4747 unsigned think_time;
4750 /* Ignore root hubs */
4754 vdev = xhci->devs[hdev->slot_id];
4756 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4759 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4761 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4764 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4766 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4768 xhci_free_command(xhci, config_cmd);
4772 spin_lock_irqsave(&xhci->lock, flags);
4773 if (hdev->speed == USB_SPEED_HIGH &&
4774 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4775 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4776 xhci_free_command(xhci, config_cmd);
4777 spin_unlock_irqrestore(&xhci->lock, flags);
4781 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4782 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4783 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4784 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4786 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4787 * but it may be already set to 1 when setup an xHCI virtual
4788 * device, so clear it anyway.
4791 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4792 else if (hdev->speed == USB_SPEED_FULL)
4793 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4795 if (xhci->hci_version > 0x95) {
4796 xhci_dbg(xhci, "xHCI version %x needs hub "
4797 "TT think time and number of ports\n",
4798 (unsigned int) xhci->hci_version);
4799 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4800 /* Set TT think time - convert from ns to FS bit times.
4801 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4802 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4804 * xHCI 1.0: this field shall be 0 if the device is not a
4807 think_time = tt->think_time;
4808 if (think_time != 0)
4809 think_time = (think_time / 666) - 1;
4810 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4811 slot_ctx->tt_info |=
4812 cpu_to_le32(TT_THINK_TIME(think_time));
4814 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4815 "TT think time or number of ports\n",
4816 (unsigned int) xhci->hci_version);
4818 slot_ctx->dev_state = 0;
4819 spin_unlock_irqrestore(&xhci->lock, flags);
4821 xhci_dbg(xhci, "Set up %s for hub device.\n",
4822 (xhci->hci_version > 0x95) ?
4823 "configure endpoint" : "evaluate context");
4824 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4825 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4827 /* Issue and wait for the configure endpoint or
4828 * evaluate context command.
4830 if (xhci->hci_version > 0x95)
4831 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4834 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4837 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4838 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4840 xhci_free_command(xhci, config_cmd);
4844 int xhci_get_frame(struct usb_hcd *hcd)
4846 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4847 /* EHCI mods by the periodic size. Why? */
4848 return readl(&xhci->run_regs->microframe_index) >> 3;
4851 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4853 struct xhci_hcd *xhci;
4854 struct device *dev = hcd->self.controller;
4857 /* Accept arbitrarily long scatter-gather lists */
4858 hcd->self.sg_tablesize = ~0;
4860 /* support to build packet from discontinuous buffers */
4861 hcd->self.no_sg_constraint = 1;
4863 /* XHCI controllers don't stop the ep queue on short packets :| */
4864 hcd->self.no_stop_on_short = 1;
4866 xhci = hcd_to_xhci(hcd);
4868 if (usb_hcd_is_primary_hcd(hcd)) {
4869 xhci->main_hcd = hcd;
4870 /* Mark the first roothub as being USB 2.0.
4871 * The xHCI driver will register the USB 3.0 roothub.
4873 hcd->speed = HCD_USB2;
4874 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4876 * USB 2.0 roothub under xHCI has an integrated TT,
4877 * (rate matching hub) as opposed to having an OHCI/UHCI
4878 * companion controller.
4882 if (xhci->sbrn == 0x31) {
4883 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4884 hcd->speed = HCD_USB31;
4886 /* xHCI private pointer was set in xhci_pci_probe for the second
4887 * registered roothub.
4892 mutex_init(&xhci->mutex);
4893 xhci->cap_regs = hcd->regs;
4894 xhci->op_regs = hcd->regs +
4895 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4896 xhci->run_regs = hcd->regs +
4897 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4898 /* Cache read-only capability registers */
4899 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4900 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4901 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4902 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4903 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4904 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4905 if (xhci->hci_version > 0x100)
4906 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4907 xhci_print_registers(xhci);
4909 xhci->quirks = quirks;
4911 get_quirks(dev, xhci);
4913 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4914 * success event after a short transfer. This quirk will ignore such
4917 if (xhci->hci_version > 0x96)
4918 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4920 /* Make sure the HC is halted. */
4921 retval = xhci_halt(xhci);
4925 xhci_dbg(xhci, "Resetting HCD\n");
4926 /* Reset the internal HC memory state and registers. */
4927 retval = xhci_reset(xhci);
4930 xhci_dbg(xhci, "Reset complete\n");
4932 /* Set dma_mask and coherent_dma_mask to 64-bits,
4933 * if xHC supports 64-bit addressing */
4934 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4935 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4936 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4937 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4940 * This is to avoid error in cases where a 32-bit USB
4941 * controller is used on a 64-bit capable system.
4943 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4946 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4947 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4950 xhci_dbg(xhci, "Calling HCD init\n");
4951 /* Initialize HCD and host controller data structures. */
4952 retval = xhci_init(hcd);
4955 xhci_dbg(xhci, "Called HCD init\n");
4957 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4958 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4962 EXPORT_SYMBOL_GPL(xhci_gen_setup);
4964 static const struct hc_driver xhci_hc_driver = {
4965 .description = "xhci-hcd",
4966 .product_desc = "xHCI Host Controller",
4967 .hcd_priv_size = sizeof(struct xhci_hcd *),
4970 * generic hardware linkage
4973 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4976 * basic lifecycle operations
4978 .reset = NULL, /* set in xhci_init_driver() */
4981 .shutdown = xhci_shutdown,
4984 * managing i/o requests and associated device resources
4986 .urb_enqueue = xhci_urb_enqueue,
4987 .urb_dequeue = xhci_urb_dequeue,
4988 .alloc_dev = xhci_alloc_dev,
4989 .free_dev = xhci_free_dev,
4990 .alloc_streams = xhci_alloc_streams,
4991 .free_streams = xhci_free_streams,
4992 .add_endpoint = xhci_add_endpoint,
4993 .drop_endpoint = xhci_drop_endpoint,
4994 .endpoint_reset = xhci_endpoint_reset,
4995 .check_bandwidth = xhci_check_bandwidth,
4996 .reset_bandwidth = xhci_reset_bandwidth,
4997 .address_device = xhci_address_device,
4998 .enable_device = xhci_enable_device,
4999 .update_hub_device = xhci_update_hub_device,
5000 .reset_device = xhci_discover_or_reset_device,
5003 * scheduling support
5005 .get_frame_number = xhci_get_frame,
5010 .hub_control = xhci_hub_control,
5011 .hub_status_data = xhci_hub_status_data,
5012 .bus_suspend = xhci_bus_suspend,
5013 .bus_resume = xhci_bus_resume,
5016 * call back when device connected and addressed
5018 .update_device = xhci_update_device,
5019 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5020 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5021 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5022 .find_raw_port_number = xhci_find_raw_port_number,
5025 void xhci_init_driver(struct hc_driver *drv,
5026 const struct xhci_driver_overrides *over)
5030 /* Copy the generic table to drv then apply the overrides */
5031 *drv = xhci_hc_driver;
5034 drv->hcd_priv_size += over->extra_priv_size;
5036 drv->reset = over->reset;
5038 drv->start = over->start;
5041 EXPORT_SYMBOL_GPL(xhci_init_driver);
5043 MODULE_DESCRIPTION(DRIVER_DESC);
5044 MODULE_AUTHOR(DRIVER_AUTHOR);
5045 MODULE_LICENSE("GPL");
5047 static int __init xhci_hcd_init(void)
5050 * Check the compiler generated sizes of structures that must be laid
5051 * out in specific ways for hardware access.
5053 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5054 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5055 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5056 /* xhci_device_control has eight fields, and also
5057 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5059 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5060 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5061 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5062 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5063 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5064 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5065 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5074 * If an init function is provided, an exit function must also be provided
5075 * to allow module unload.
5077 static void __exit xhci_hcd_fini(void) { }
5079 module_init(xhci_hcd_init);
5080 module_exit(xhci_hcd_fini);