2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/usb/quirks.h>
34 #include "xhci-trace.h"
36 #define DRIVER_AUTHOR "Sarah Sharp"
37 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
39 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
41 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
42 static int link_quirk;
43 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
46 static unsigned int quirks;
47 module_param(quirks, uint, S_IRUGO);
48 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
50 /* TODO: copied from ehci-hcd.c - can this be refactored? */
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
58 * Returns negative errno, or zero on success
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
64 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
70 if (result == ~(u32)0) /* card removed */
82 * Disable interrupts and begin the xHCI halting process.
84 void xhci_quiesce(struct xhci_hcd *xhci)
91 halted = readl(&xhci->op_regs->status) & STS_HALT;
95 cmd = readl(&xhci->op_regs->command);
97 writel(cmd, &xhci->op_regs->command);
101 * Force HC into halt state.
103 * Disable any IRQs and clear the run/stop bit.
104 * HC will complete any current and actively pipelined transactions, and
105 * should halt within 16 ms of the run/stop bit being cleared.
106 * Read HC Halted bit in the status register to see when the HC is finished.
108 int xhci_halt(struct xhci_hcd *xhci)
111 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
114 ret = xhci_handshake(&xhci->op_regs->status,
115 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
117 xhci->xhc_state |= XHCI_STATE_HALTED;
118 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
120 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
126 * Set the run bit and wait for the host to be running.
128 static int xhci_start(struct xhci_hcd *xhci)
133 temp = readl(&xhci->op_regs->command);
135 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
137 writel(temp, &xhci->op_regs->command);
140 * Wait for the HCHalted Status bit to be 0 to indicate the host is
143 ret = xhci_handshake(&xhci->op_regs->status,
144 STS_HALT, 0, XHCI_MAX_HALT_USEC);
145 if (ret == -ETIMEDOUT)
146 xhci_err(xhci, "Host took too long to start, "
147 "waited %u microseconds.\n",
150 /* clear state flags. Including dying, halted or removing */
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
163 int xhci_reset(struct xhci_hcd *xhci)
169 state = readl(&xhci->op_regs->status);
170 if ((state & STS_HALT) == 0) {
171 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
175 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
176 command = readl(&xhci->op_regs->command);
177 command |= CMD_RESET;
178 writel(command, &xhci->op_regs->command);
180 /* Existing Intel xHCI controllers require a delay of 1 mS,
181 * after setting the CMD_RESET bit, and before accessing any
182 * HC registers. This allows the HC to complete the
183 * reset operation and be ready for HC register access.
184 * Without this delay, the subsequent HC register access,
185 * may result in a system hang very rarely.
187 if (xhci->quirks & XHCI_INTEL_HOST)
190 ret = xhci_handshake(&xhci->op_regs->command,
191 CMD_RESET, 0, 10 * 1000 * 1000);
195 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
196 "Wait for controller to be ready for doorbell rings");
198 * xHCI cannot write to any doorbells or operational registers other
199 * than status until the "Controller Not Ready" flag is cleared.
201 ret = xhci_handshake(&xhci->op_regs->status,
202 STS_CNR, 0, 10 * 1000 * 1000);
204 for (i = 0; i < 2; ++i) {
205 xhci->bus_state[i].port_c_suspend = 0;
206 xhci->bus_state[i].suspended_ports = 0;
207 xhci->bus_state[i].resuming_ports = 0;
214 static int xhci_free_msi(struct xhci_hcd *xhci)
218 if (!xhci->msix_entries)
221 for (i = 0; i < xhci->msix_count; i++)
222 if (xhci->msix_entries[i].vector)
223 free_irq(xhci->msix_entries[i].vector,
231 static int xhci_setup_msi(struct xhci_hcd *xhci)
234 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
236 ret = pci_enable_msi(pdev);
238 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
239 "failed to allocate MSI entry");
243 ret = request_irq(pdev->irq, xhci_msi_irq,
244 0, "xhci_hcd", xhci_to_hcd(xhci));
246 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
247 "disable MSI interrupt");
248 pci_disable_msi(pdev);
256 * free all IRQs request
258 static void xhci_free_irq(struct xhci_hcd *xhci)
260 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
263 /* return if using legacy interrupt */
264 if (xhci_to_hcd(xhci)->irq > 0)
267 ret = xhci_free_msi(xhci);
271 free_irq(pdev->irq, xhci_to_hcd(xhci));
279 static int xhci_setup_msix(struct xhci_hcd *xhci)
282 struct usb_hcd *hcd = xhci_to_hcd(xhci);
283 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
286 * calculate number of msi-x vectors supported.
287 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
288 * with max number of interrupters based on the xhci HCSPARAMS1.
289 * - num_online_cpus: maximum msi-x vectors per CPUs core.
290 * Add additional 1 vector to ensure always available interrupt.
292 xhci->msix_count = min(num_online_cpus() + 1,
293 HCS_MAX_INTRS(xhci->hcs_params1));
296 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
298 if (!xhci->msix_entries) {
299 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
303 for (i = 0; i < xhci->msix_count; i++) {
304 xhci->msix_entries[i].entry = i;
305 xhci->msix_entries[i].vector = 0;
308 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
310 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
311 "Failed to enable MSI-X");
315 for (i = 0; i < xhci->msix_count; i++) {
316 ret = request_irq(xhci->msix_entries[i].vector,
318 0, "xhci_hcd", xhci_to_hcd(xhci));
323 hcd->msix_enabled = 1;
327 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
329 pci_disable_msix(pdev);
331 kfree(xhci->msix_entries);
332 xhci->msix_entries = NULL;
336 /* Free any IRQs and disable MSI-X */
337 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
339 struct usb_hcd *hcd = xhci_to_hcd(xhci);
340 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
342 if (xhci->quirks & XHCI_PLAT)
347 if (xhci->msix_entries) {
348 pci_disable_msix(pdev);
349 kfree(xhci->msix_entries);
350 xhci->msix_entries = NULL;
352 pci_disable_msi(pdev);
355 hcd->msix_enabled = 0;
359 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
363 if (xhci->msix_entries) {
364 for (i = 0; i < xhci->msix_count; i++)
365 synchronize_irq(xhci->msix_entries[i].vector);
369 static int xhci_try_enable_msi(struct usb_hcd *hcd)
371 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
372 struct pci_dev *pdev;
375 /* The xhci platform device has set up IRQs through usb_add_hcd. */
376 if (xhci->quirks & XHCI_PLAT)
379 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
381 * Some Fresco Logic host controllers advertise MSI, but fail to
382 * generate interrupts. Don't even try to enable MSI.
384 if (xhci->quirks & XHCI_BROKEN_MSI)
387 /* unregister the legacy interrupt */
389 free_irq(hcd->irq, hcd);
392 ret = xhci_setup_msix(xhci);
394 /* fall back to msi*/
395 ret = xhci_setup_msi(xhci);
398 /* hcd->irq is 0, we have MSI */
402 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
407 if (!strlen(hcd->irq_descr))
408 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
409 hcd->driver->description, hcd->self.busnum);
411 /* fall back to legacy interrupt*/
412 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
413 hcd->irq_descr, hcd);
415 xhci_err(xhci, "request interrupt %d failed\n",
419 hcd->irq = pdev->irq;
425 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
430 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
434 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
440 static void compliance_mode_recovery(unsigned long arg)
442 struct xhci_hcd *xhci;
447 xhci = (struct xhci_hcd *)arg;
449 for (i = 0; i < xhci->num_usb3_ports; i++) {
450 temp = readl(xhci->usb3_ports[i]);
451 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
453 * Compliance Mode Detected. Letting USB Core
454 * handle the Warm Reset
456 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
457 "Compliance mode detected->port %d",
459 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
460 "Attempting compliance mode recovery");
461 hcd = xhci->shared_hcd;
463 if (hcd->state == HC_STATE_SUSPENDED)
464 usb_hcd_resume_root_hub(hcd);
466 usb_hcd_poll_rh_status(hcd);
470 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
471 mod_timer(&xhci->comp_mode_recovery_timer,
472 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
476 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
477 * that causes ports behind that hardware to enter compliance mode sometimes.
478 * The quirk creates a timer that polls every 2 seconds the link state of
479 * each host controller's port and recovers it by issuing a Warm reset
480 * if Compliance mode is detected, otherwise the port will become "dead" (no
481 * device connections or disconnections will be detected anymore). Becasue no
482 * status event is generated when entering compliance mode (per xhci spec),
483 * this quirk is needed on systems that have the failing hardware installed.
485 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
487 xhci->port_status_u0 = 0;
488 setup_timer(&xhci->comp_mode_recovery_timer,
489 compliance_mode_recovery, (unsigned long)xhci);
490 xhci->comp_mode_recovery_timer.expires = jiffies +
491 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
493 set_timer_slack(&xhci->comp_mode_recovery_timer,
494 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
495 add_timer(&xhci->comp_mode_recovery_timer);
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Compliance mode recovery timer initialized");
501 * This function identifies the systems that have installed the SN65LVPE502CP
502 * USB3.0 re-driver and that need the Compliance Mode Quirk.
504 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
506 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
508 const char *dmi_product_name, *dmi_sys_vendor;
510 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
511 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
512 if (!dmi_product_name || !dmi_sys_vendor)
515 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
518 if (strstr(dmi_product_name, "Z420") ||
519 strstr(dmi_product_name, "Z620") ||
520 strstr(dmi_product_name, "Z820") ||
521 strstr(dmi_product_name, "Z1 Workstation"))
527 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
529 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
534 * Initialize memory for HCD and xHC (one-time init).
536 * Program the PAGESIZE register, initialize the device context array, create
537 * device contexts (?), set up a command ring segment (or two?), create event
538 * ring (one for now).
540 int xhci_init(struct usb_hcd *hcd)
542 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
545 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
546 spin_lock_init(&xhci->lock);
547 if (xhci->hci_version == 0x95 && link_quirk) {
548 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
549 "QUIRK: Not clearing Link TRB chain bits.");
550 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
552 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
553 "xHCI doesn't need link TRB QUIRK");
555 retval = xhci_mem_init(xhci, GFP_KERNEL);
556 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
558 /* Initializing Compliance Mode Recovery Data If Needed */
559 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
560 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
561 compliance_mode_recovery_timer_init(xhci);
567 /*-------------------------------------------------------------------------*/
570 static int xhci_run_finished(struct xhci_hcd *xhci)
572 if (xhci_start(xhci)) {
576 xhci->shared_hcd->state = HC_STATE_RUNNING;
577 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
579 if (xhci->quirks & XHCI_NEC_HOST)
580 xhci_ring_cmd_db(xhci);
582 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
583 "Finished xhci_run for USB3 roothub");
588 * Start the HC after it was halted.
590 * This function is called by the USB core when the HC driver is added.
591 * Its opposite is xhci_stop().
593 * xhci_init() must be called once before this function can be called.
594 * Reset the HC, enable device slot contexts, program DCBAAP, and
595 * set command ring pointer and event ring pointer.
597 * Setup MSI-X vectors and enable interrupts.
599 int xhci_run(struct usb_hcd *hcd)
604 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
606 /* Start the xHCI host controller running only after the USB 2.0 roothub
610 hcd->uses_new_polling = 1;
611 if (!usb_hcd_is_primary_hcd(hcd))
612 return xhci_run_finished(xhci);
614 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
616 ret = xhci_try_enable_msi(hcd);
620 xhci_dbg(xhci, "Command ring memory map follows:\n");
621 xhci_debug_ring(xhci, xhci->cmd_ring);
622 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
623 xhci_dbg_cmd_ptrs(xhci);
625 xhci_dbg(xhci, "ERST memory map follows:\n");
626 xhci_dbg_erst(xhci, &xhci->erst);
627 xhci_dbg(xhci, "Event ring:\n");
628 xhci_debug_ring(xhci, xhci->event_ring);
629 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
630 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
631 temp_64 &= ~ERST_PTR_MASK;
632 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
633 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
635 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
636 "// Set the interrupt modulation register");
637 temp = readl(&xhci->ir_set->irq_control);
638 temp &= ~ER_IRQ_INTERVAL_MASK;
640 writel(temp, &xhci->ir_set->irq_control);
642 /* Set the HCD state before we enable the irqs */
643 temp = readl(&xhci->op_regs->command);
645 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
646 "// Enable interrupts, cmd = 0x%x.", temp);
647 writel(temp, &xhci->op_regs->command);
649 temp = readl(&xhci->ir_set->irq_pending);
650 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
651 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
652 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
653 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
654 xhci_print_ir_set(xhci, 0);
656 if (xhci->quirks & XHCI_NEC_HOST) {
657 struct xhci_command *command;
658 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
661 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
662 TRB_TYPE(TRB_NEC_GET_FW));
664 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
665 "Finished xhci_run for USB2 roothub");
668 EXPORT_SYMBOL_GPL(xhci_run);
673 * This function is called by the USB core when the HC driver is removed.
674 * Its opposite is xhci_run().
676 * Disable device contexts, disable IRQs, and quiesce the HC.
677 * Reset the HC, finish any completed transactions, and cleanup memory.
679 void xhci_stop(struct usb_hcd *hcd)
682 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
684 mutex_lock(&xhci->mutex);
686 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
687 spin_lock_irq(&xhci->lock);
689 xhci->xhc_state |= XHCI_STATE_HALTED;
690 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
694 spin_unlock_irq(&xhci->lock);
697 if (!usb_hcd_is_primary_hcd(hcd)) {
698 mutex_unlock(&xhci->mutex);
702 xhci_cleanup_msix(xhci);
704 /* Deleting Compliance Mode Recovery Timer */
705 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
706 (!(xhci_all_ports_seen_u0(xhci)))) {
707 del_timer_sync(&xhci->comp_mode_recovery_timer);
708 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
709 "%s: compliance mode recovery timer deleted",
713 if (xhci->quirks & XHCI_AMD_PLL_FIX)
716 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
717 "// Disabling event ring interrupts");
718 temp = readl(&xhci->op_regs->status);
719 writel(temp & ~STS_EINT, &xhci->op_regs->status);
720 temp = readl(&xhci->ir_set->irq_pending);
721 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
722 xhci_print_ir_set(xhci, 0);
724 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
725 xhci_mem_cleanup(xhci);
726 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
727 "xhci_stop completed - status = %x",
728 readl(&xhci->op_regs->status));
729 mutex_unlock(&xhci->mutex);
733 * Shutdown HC (not bus-specific)
735 * This is called when the machine is rebooting or halting. We assume that the
736 * machine will be powered off, and the HC's internal state will be reset.
737 * Don't bother to free memory.
739 * This will only ever be called with the main usb_hcd (the USB3 roothub).
741 void xhci_shutdown(struct usb_hcd *hcd)
743 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
745 if (!hcd->rh_registered)
748 /* Don't poll the roothubs on shutdown */
749 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
750 del_timer_sync(&hcd->rh_timer);
751 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
752 del_timer_sync(&xhci->shared_hcd->rh_timer);
754 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
755 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
757 spin_lock_irq(&xhci->lock);
759 /* Workaround for spurious wakeups at shutdown with HSW */
760 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
762 spin_unlock_irq(&xhci->lock);
764 xhci_cleanup_msix(xhci);
766 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
767 "xhci_shutdown completed - status = %x",
768 readl(&xhci->op_regs->status));
770 /* Yet another workaround for spurious wakeups at shutdown with HSW */
771 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
772 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
776 static void xhci_save_registers(struct xhci_hcd *xhci)
778 xhci->s3.command = readl(&xhci->op_regs->command);
779 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
780 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
781 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
782 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
783 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
784 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
785 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
786 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
789 static void xhci_restore_registers(struct xhci_hcd *xhci)
791 writel(xhci->s3.command, &xhci->op_regs->command);
792 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
793 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
794 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
795 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
796 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
797 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
798 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
799 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
802 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
806 /* step 2: initialize command ring buffer */
807 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
808 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
809 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
810 xhci->cmd_ring->dequeue) &
811 (u64) ~CMD_RING_RSVD_BITS) |
812 xhci->cmd_ring->cycle_state;
813 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
814 "// Setting command ring address to 0x%llx",
815 (long unsigned long) val_64);
816 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
820 * The whole command ring must be cleared to zero when we suspend the host.
822 * The host doesn't save the command ring pointer in the suspend well, so we
823 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
824 * aligned, because of the reserved bits in the command ring dequeue pointer
825 * register. Therefore, we can't just set the dequeue pointer back in the
826 * middle of the ring (TRBs are 16-byte aligned).
828 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
830 struct xhci_ring *ring;
831 struct xhci_segment *seg;
833 ring = xhci->cmd_ring;
837 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
838 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
839 cpu_to_le32(~TRB_CYCLE);
841 } while (seg != ring->deq_seg);
843 /* Reset the software enqueue and dequeue pointers */
844 ring->deq_seg = ring->first_seg;
845 ring->dequeue = ring->first_seg->trbs;
846 ring->enq_seg = ring->deq_seg;
847 ring->enqueue = ring->dequeue;
849 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
851 * Ring is now zeroed, so the HW should look for change of ownership
852 * when the cycle bit is set to 1.
854 ring->cycle_state = 1;
857 * Reset the hardware dequeue pointer.
858 * Yes, this will need to be re-written after resume, but we're paranoid
859 * and want to make sure the hardware doesn't access bogus memory
860 * because, say, the BIOS or an SMI started the host without changing
861 * the command ring pointers.
863 xhci_set_cmd_ring_deq(xhci);
866 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
869 __le32 __iomem **port_array;
873 spin_lock_irqsave(&xhci->lock, flags);
875 /* disble usb3 ports Wake bits*/
876 port_index = xhci->num_usb3_ports;
877 port_array = xhci->usb3_ports;
878 while (port_index--) {
879 t1 = readl(port_array[port_index]);
880 t1 = xhci_port_state_to_neutral(t1);
881 t2 = t1 & ~PORT_WAKE_BITS;
883 writel(t2, port_array[port_index]);
886 /* disble usb2 ports Wake bits*/
887 port_index = xhci->num_usb2_ports;
888 port_array = xhci->usb2_ports;
889 while (port_index--) {
890 t1 = readl(port_array[port_index]);
891 t1 = xhci_port_state_to_neutral(t1);
892 t2 = t1 & ~PORT_WAKE_BITS;
894 writel(t2, port_array[port_index]);
897 spin_unlock_irqrestore(&xhci->lock, flags);
901 * Stop HC (not bus-specific)
903 * This is called when the machine transition into S3/S4 mode.
906 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
909 unsigned int delay = XHCI_MAX_HALT_USEC;
910 struct usb_hcd *hcd = xhci_to_hcd(xhci);
916 if (hcd->state != HC_STATE_SUSPENDED ||
917 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
920 /* Clear root port wake on bits if wakeup not allowed. */
922 xhci_disable_port_wake_on_bits(xhci);
924 /* Don't poll the roothubs on bus suspend. */
925 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
926 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
927 del_timer_sync(&hcd->rh_timer);
928 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
929 del_timer_sync(&xhci->shared_hcd->rh_timer);
931 spin_lock_irq(&xhci->lock);
932 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
933 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
934 /* step 1: stop endpoint */
935 /* skipped assuming that port suspend has done */
937 /* step 2: clear Run/Stop bit */
938 command = readl(&xhci->op_regs->command);
940 writel(command, &xhci->op_regs->command);
942 /* Some chips from Fresco Logic need an extraordinary delay */
943 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
945 if (xhci_handshake(&xhci->op_regs->status,
946 STS_HALT, STS_HALT, delay)) {
947 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
948 spin_unlock_irq(&xhci->lock);
951 xhci_clear_command_ring(xhci);
953 /* step 3: save registers */
954 xhci_save_registers(xhci);
956 /* step 4: set CSS flag */
957 command = readl(&xhci->op_regs->command);
959 writel(command, &xhci->op_regs->command);
960 if (xhci_handshake(&xhci->op_regs->status,
961 STS_SAVE, 0, 10 * 1000)) {
962 xhci_warn(xhci, "WARN: xHC save state timeout\n");
963 spin_unlock_irq(&xhci->lock);
966 spin_unlock_irq(&xhci->lock);
969 * Deleting Compliance Mode Recovery Timer because the xHCI Host
970 * is about to be suspended.
972 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
973 (!(xhci_all_ports_seen_u0(xhci)))) {
974 del_timer_sync(&xhci->comp_mode_recovery_timer);
975 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
976 "%s: compliance mode recovery timer deleted",
980 /* step 5: remove core well power */
981 /* synchronize irq when using MSI-X */
982 xhci_msix_sync_irqs(xhci);
986 EXPORT_SYMBOL_GPL(xhci_suspend);
989 * start xHC (not bus-specific)
991 * This is called when the machine transition from S3/S4 mode.
994 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
996 u32 command, temp = 0, status;
997 struct usb_hcd *hcd = xhci_to_hcd(xhci);
998 struct usb_hcd *secondary_hcd;
1000 bool comp_timer_running = false;
1005 /* Wait a bit if either of the roothubs need to settle from the
1006 * transition into bus suspend.
1008 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1009 time_before(jiffies,
1010 xhci->bus_state[1].next_statechange))
1013 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1014 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1016 spin_lock_irq(&xhci->lock);
1017 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1021 /* step 1: restore register */
1022 xhci_restore_registers(xhci);
1023 /* step 2: initialize command ring buffer */
1024 xhci_set_cmd_ring_deq(xhci);
1025 /* step 3: restore state and start state*/
1026 /* step 3: set CRS flag */
1027 command = readl(&xhci->op_regs->command);
1029 writel(command, &xhci->op_regs->command);
1030 if (xhci_handshake(&xhci->op_regs->status,
1031 STS_RESTORE, 0, 10 * 1000)) {
1032 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1033 spin_unlock_irq(&xhci->lock);
1036 temp = readl(&xhci->op_regs->status);
1039 /* If restore operation fails, re-initialize the HC during resume */
1040 if ((temp & STS_SRE) || hibernated) {
1042 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1043 !(xhci_all_ports_seen_u0(xhci))) {
1044 del_timer_sync(&xhci->comp_mode_recovery_timer);
1045 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1046 "Compliance Mode Recovery Timer deleted!");
1049 /* Let the USB core know _both_ roothubs lost power. */
1050 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1051 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1053 xhci_dbg(xhci, "Stop HCD\n");
1056 spin_unlock_irq(&xhci->lock);
1057 xhci_cleanup_msix(xhci);
1059 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1060 temp = readl(&xhci->op_regs->status);
1061 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1062 temp = readl(&xhci->ir_set->irq_pending);
1063 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1064 xhci_print_ir_set(xhci, 0);
1066 xhci_dbg(xhci, "cleaning up memory\n");
1067 xhci_mem_cleanup(xhci);
1068 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1069 readl(&xhci->op_regs->status));
1071 /* USB core calls the PCI reinit and start functions twice:
1072 * first with the primary HCD, and then with the secondary HCD.
1073 * If we don't do the same, the host will never be started.
1075 if (!usb_hcd_is_primary_hcd(hcd))
1076 secondary_hcd = hcd;
1078 secondary_hcd = xhci->shared_hcd;
1080 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1081 retval = xhci_init(hcd->primary_hcd);
1084 comp_timer_running = true;
1086 xhci_dbg(xhci, "Start the primary HCD\n");
1087 retval = xhci_run(hcd->primary_hcd);
1089 xhci_dbg(xhci, "Start the secondary HCD\n");
1090 retval = xhci_run(secondary_hcd);
1092 hcd->state = HC_STATE_SUSPENDED;
1093 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1097 /* step 4: set Run/Stop bit */
1098 command = readl(&xhci->op_regs->command);
1100 writel(command, &xhci->op_regs->command);
1101 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1104 /* step 5: walk topology and initialize portsc,
1105 * portpmsc and portli
1107 /* this is done in bus_resume */
1109 /* step 6: restart each of the previously
1110 * Running endpoints by ringing their doorbells
1113 spin_unlock_irq(&xhci->lock);
1117 /* Resume root hubs only when have pending events. */
1118 status = readl(&xhci->op_regs->status);
1119 if (status & STS_EINT) {
1120 usb_hcd_resume_root_hub(xhci->shared_hcd);
1121 usb_hcd_resume_root_hub(hcd);
1126 * If system is subject to the Quirk, Compliance Mode Timer needs to
1127 * be re-initialized Always after a system resume. Ports are subject
1128 * to suffer the Compliance Mode issue again. It doesn't matter if
1129 * ports have entered previously to U0 before system's suspension.
1131 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1132 compliance_mode_recovery_timer_init(xhci);
1134 /* Re-enable port polling. */
1135 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1136 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1137 usb_hcd_poll_rh_status(xhci->shared_hcd);
1138 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1139 usb_hcd_poll_rh_status(hcd);
1143 EXPORT_SYMBOL_GPL(xhci_resume);
1144 #endif /* CONFIG_PM */
1146 /*-------------------------------------------------------------------------*/
1149 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1150 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1151 * value to right shift 1 for the bitmask.
1153 * Index = (epnum * 2) + direction - 1,
1154 * where direction = 0 for OUT, 1 for IN.
1155 * For control endpoints, the IN index is used (OUT index is unused), so
1156 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1158 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1161 if (usb_endpoint_xfer_control(desc))
1162 index = (unsigned int) (usb_endpoint_num(desc)*2);
1164 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1165 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1169 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1170 * address from the XHCI endpoint index.
1172 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1174 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1175 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1176 return direction | number;
1179 /* Find the flag for this endpoint (for use in the control context). Use the
1180 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1183 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1185 return 1 << (xhci_get_endpoint_index(desc) + 1);
1188 /* Find the flag for this endpoint (for use in the control context). Use the
1189 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1192 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1194 return 1 << (ep_index + 1);
1197 /* Compute the last valid endpoint context index. Basically, this is the
1198 * endpoint index plus one. For slot contexts with more than valid endpoint,
1199 * we find the most significant bit set in the added contexts flags.
1200 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1201 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1203 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1205 return fls(added_ctxs) - 1;
1208 /* Returns 1 if the arguments are OK;
1209 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1211 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1212 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1214 struct xhci_hcd *xhci;
1215 struct xhci_virt_device *virt_dev;
1217 if (!hcd || (check_ep && !ep) || !udev) {
1218 pr_debug("xHCI %s called with invalid args\n", func);
1221 if (!udev->parent) {
1222 pr_debug("xHCI %s called for root hub\n", func);
1226 xhci = hcd_to_xhci(hcd);
1227 if (check_virt_dev) {
1228 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1229 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1234 virt_dev = xhci->devs[udev->slot_id];
1235 if (virt_dev->udev != udev) {
1236 xhci_dbg(xhci, "xHCI %s called with udev and "
1237 "virt_dev does not match\n", func);
1242 if (xhci->xhc_state & XHCI_STATE_HALTED)
1248 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1249 struct usb_device *udev, struct xhci_command *command,
1250 bool ctx_change, bool must_succeed);
1253 * Full speed devices may have a max packet size greater than 8 bytes, but the
1254 * USB core doesn't know that until it reads the first 8 bytes of the
1255 * descriptor. If the usb_device's max packet size changes after that point,
1256 * we need to issue an evaluate context command and wait on it.
1258 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1259 unsigned int ep_index, struct urb *urb)
1261 struct xhci_container_ctx *out_ctx;
1262 struct xhci_input_control_ctx *ctrl_ctx;
1263 struct xhci_ep_ctx *ep_ctx;
1264 struct xhci_command *command;
1265 int max_packet_size;
1266 int hw_max_packet_size;
1269 out_ctx = xhci->devs[slot_id]->out_ctx;
1270 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1271 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1272 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1273 if (hw_max_packet_size != max_packet_size) {
1274 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1275 "Max Packet Size for ep 0 changed.");
1276 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1277 "Max packet size in usb_device = %d",
1279 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1280 "Max packet size in xHCI HW = %d",
1281 hw_max_packet_size);
1282 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1283 "Issuing evaluate context command.");
1285 /* Set up the input context flags for the command */
1286 /* FIXME: This won't work if a non-default control endpoint
1287 * changes max packet sizes.
1290 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1294 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1295 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1297 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1300 goto command_cleanup;
1302 /* Set up the modified control endpoint 0 */
1303 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1304 xhci->devs[slot_id]->out_ctx, ep_index);
1306 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1307 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1308 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1310 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1311 ctrl_ctx->drop_flags = 0;
1313 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1314 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1315 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1316 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1318 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1321 /* Clean up the input context for later use by bandwidth
1324 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1326 kfree(command->completion);
1333 * non-error returns are a promise to giveback() the urb later
1334 * we drop ownership so next owner (or urb unlink) can get it
1336 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1338 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1339 struct xhci_td *buffer;
1340 unsigned long flags;
1342 unsigned int slot_id, ep_index;
1343 struct urb_priv *urb_priv;
1346 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1347 true, true, __func__) <= 0)
1350 slot_id = urb->dev->slot_id;
1351 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1353 if (!HCD_HW_ACCESSIBLE(hcd)) {
1354 if (!in_interrupt())
1355 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1360 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1361 size = urb->number_of_packets;
1362 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1363 urb->transfer_buffer_length > 0 &&
1364 urb->transfer_flags & URB_ZERO_PACKET &&
1365 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1370 urb_priv = kzalloc(sizeof(struct urb_priv) +
1371 size * sizeof(struct xhci_td *), mem_flags);
1375 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1381 for (i = 0; i < size; i++) {
1382 urb_priv->td[i] = buffer;
1386 urb_priv->length = size;
1387 urb_priv->td_cnt = 0;
1388 urb->hcpriv = urb_priv;
1390 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1391 /* Check to see if the max packet size for the default control
1392 * endpoint changed during FS device enumeration
1394 if (urb->dev->speed == USB_SPEED_FULL) {
1395 ret = xhci_check_maxpacket(xhci, slot_id,
1398 xhci_urb_free_priv(urb_priv);
1404 /* We have a spinlock and interrupts disabled, so we must pass
1405 * atomic context to this function, which may allocate memory.
1407 spin_lock_irqsave(&xhci->lock, flags);
1408 if (xhci->xhc_state & XHCI_STATE_DYING)
1410 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1414 spin_unlock_irqrestore(&xhci->lock, flags);
1415 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1416 spin_lock_irqsave(&xhci->lock, flags);
1417 if (xhci->xhc_state & XHCI_STATE_DYING)
1419 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1420 EP_GETTING_STREAMS) {
1421 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1422 "is transitioning to using streams.\n");
1424 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1425 EP_GETTING_NO_STREAMS) {
1426 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1427 "is transitioning to "
1428 "not having streams.\n");
1431 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1436 spin_unlock_irqrestore(&xhci->lock, flags);
1437 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1438 spin_lock_irqsave(&xhci->lock, flags);
1439 if (xhci->xhc_state & XHCI_STATE_DYING)
1441 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1445 spin_unlock_irqrestore(&xhci->lock, flags);
1447 spin_lock_irqsave(&xhci->lock, flags);
1448 if (xhci->xhc_state & XHCI_STATE_DYING)
1450 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1454 spin_unlock_irqrestore(&xhci->lock, flags);
1459 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1460 "non-responsive xHCI host.\n",
1461 urb->ep->desc.bEndpointAddress, urb);
1464 xhci_urb_free_priv(urb_priv);
1466 spin_unlock_irqrestore(&xhci->lock, flags);
1470 /* Get the right ring for the given URB.
1471 * If the endpoint supports streams, boundary check the URB's stream ID.
1472 * If the endpoint doesn't support streams, return the singular endpoint ring.
1474 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1477 unsigned int slot_id;
1478 unsigned int ep_index;
1479 unsigned int stream_id;
1480 struct xhci_virt_ep *ep;
1482 slot_id = urb->dev->slot_id;
1483 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1484 stream_id = urb->stream_id;
1485 ep = &xhci->devs[slot_id]->eps[ep_index];
1486 /* Common case: no streams */
1487 if (!(ep->ep_state & EP_HAS_STREAMS))
1490 if (stream_id == 0) {
1492 "WARN: Slot ID %u, ep index %u has streams, "
1493 "but URB has no stream ID.\n",
1498 if (stream_id < ep->stream_info->num_streams)
1499 return ep->stream_info->stream_rings[stream_id];
1502 "WARN: Slot ID %u, ep index %u has "
1503 "stream IDs 1 to %u allocated, "
1504 "but stream ID %u is requested.\n",
1506 ep->stream_info->num_streams - 1,
1512 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1513 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1514 * should pick up where it left off in the TD, unless a Set Transfer Ring
1515 * Dequeue Pointer is issued.
1517 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1518 * the ring. Since the ring is a contiguous structure, they can't be physically
1519 * removed. Instead, there are two options:
1521 * 1) If the HC is in the middle of processing the URB to be canceled, we
1522 * simply move the ring's dequeue pointer past those TRBs using the Set
1523 * Transfer Ring Dequeue Pointer command. This will be the common case,
1524 * when drivers timeout on the last submitted URB and attempt to cancel.
1526 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1527 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1528 * HC will need to invalidate the any TRBs it has cached after the stop
1529 * endpoint command, as noted in the xHCI 0.95 errata.
1531 * 3) The TD may have completed by the time the Stop Endpoint Command
1532 * completes, so software needs to handle that case too.
1534 * This function should protect against the TD enqueueing code ringing the
1535 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1536 * It also needs to account for multiple cancellations on happening at the same
1537 * time for the same endpoint.
1539 * Note that this function can be called in any context, or so says
1540 * usb_hcd_unlink_urb()
1542 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1544 unsigned long flags;
1547 struct xhci_hcd *xhci;
1548 struct urb_priv *urb_priv;
1550 unsigned int ep_index;
1551 struct xhci_ring *ep_ring;
1552 struct xhci_virt_ep *ep;
1553 struct xhci_command *command;
1555 xhci = hcd_to_xhci(hcd);
1556 spin_lock_irqsave(&xhci->lock, flags);
1557 /* Make sure the URB hasn't completed or been unlinked already */
1558 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1559 if (ret || !urb->hcpriv)
1561 temp = readl(&xhci->op_regs->status);
1562 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED) ||
1563 (xhci->xhc_state & XHCI_STATE_REMOVING)) {
1564 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1565 "HW died, freeing TD.");
1566 urb_priv = urb->hcpriv;
1567 for (i = urb_priv->td_cnt;
1568 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1570 td = urb_priv->td[i];
1571 if (!list_empty(&td->td_list))
1572 list_del_init(&td->td_list);
1573 if (!list_empty(&td->cancelled_td_list))
1574 list_del_init(&td->cancelled_td_list);
1577 usb_hcd_unlink_urb_from_ep(hcd, urb);
1578 spin_unlock_irqrestore(&xhci->lock, flags);
1579 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1580 xhci_urb_free_priv(urb_priv);
1584 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1585 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1586 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1592 urb_priv = urb->hcpriv;
1593 i = urb_priv->td_cnt;
1594 if (i < urb_priv->length)
1595 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1596 "Cancel URB %p, dev %s, ep 0x%x, "
1597 "starting at offset 0x%llx",
1598 urb, urb->dev->devpath,
1599 urb->ep->desc.bEndpointAddress,
1600 (unsigned long long) xhci_trb_virt_to_dma(
1601 urb_priv->td[i]->start_seg,
1602 urb_priv->td[i]->first_trb));
1604 for (; i < urb_priv->length; i++) {
1605 td = urb_priv->td[i];
1606 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1609 /* Queue a stop endpoint command, but only if this is
1610 * the first cancellation to be handled.
1612 if (!(ep->ep_state & EP_HALT_PENDING)) {
1613 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1618 ep->ep_state |= EP_HALT_PENDING;
1619 ep->stop_cmds_pending++;
1620 ep->stop_cmd_timer.expires = jiffies +
1621 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1622 add_timer(&ep->stop_cmd_timer);
1623 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1625 xhci_ring_cmd_db(xhci);
1628 spin_unlock_irqrestore(&xhci->lock, flags);
1632 /* Drop an endpoint from a new bandwidth configuration for this device.
1633 * Only one call to this function is allowed per endpoint before
1634 * check_bandwidth() or reset_bandwidth() must be called.
1635 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1636 * add the endpoint to the schedule with possibly new parameters denoted by a
1637 * different endpoint descriptor in usb_host_endpoint.
1638 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1641 * The USB core will not allow URBs to be queued to an endpoint that is being
1642 * disabled, so there's no need for mutual exclusion to protect
1643 * the xhci->devs[slot_id] structure.
1645 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1646 struct usb_host_endpoint *ep)
1648 struct xhci_hcd *xhci;
1649 struct xhci_container_ctx *in_ctx, *out_ctx;
1650 struct xhci_input_control_ctx *ctrl_ctx;
1651 unsigned int ep_index;
1652 struct xhci_ep_ctx *ep_ctx;
1654 u32 new_add_flags, new_drop_flags;
1657 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1660 xhci = hcd_to_xhci(hcd);
1661 if (xhci->xhc_state & XHCI_STATE_DYING)
1664 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1665 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1666 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1667 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1668 __func__, drop_flag);
1672 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1673 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1674 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1676 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1681 ep_index = xhci_get_endpoint_index(&ep->desc);
1682 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1683 /* If the HC already knows the endpoint is disabled,
1684 * or the HCD has noted it is disabled, ignore this request
1686 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1687 cpu_to_le32(EP_STATE_DISABLED)) ||
1688 le32_to_cpu(ctrl_ctx->drop_flags) &
1689 xhci_get_endpoint_flag(&ep->desc)) {
1690 /* Do not warn when called after a usb_device_reset */
1691 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1692 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1697 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1698 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1700 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1701 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1703 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1705 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1706 (unsigned int) ep->desc.bEndpointAddress,
1708 (unsigned int) new_drop_flags,
1709 (unsigned int) new_add_flags);
1713 /* Add an endpoint to a new possible bandwidth configuration for this device.
1714 * Only one call to this function is allowed per endpoint before
1715 * check_bandwidth() or reset_bandwidth() must be called.
1716 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1717 * add the endpoint to the schedule with possibly new parameters denoted by a
1718 * different endpoint descriptor in usb_host_endpoint.
1719 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1722 * The USB core will not allow URBs to be queued to an endpoint until the
1723 * configuration or alt setting is installed in the device, so there's no need
1724 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1726 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1727 struct usb_host_endpoint *ep)
1729 struct xhci_hcd *xhci;
1730 struct xhci_container_ctx *in_ctx;
1731 unsigned int ep_index;
1732 struct xhci_input_control_ctx *ctrl_ctx;
1734 u32 new_add_flags, new_drop_flags;
1735 struct xhci_virt_device *virt_dev;
1738 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1740 /* So we won't queue a reset ep command for a root hub */
1744 xhci = hcd_to_xhci(hcd);
1745 if (xhci->xhc_state & XHCI_STATE_DYING)
1748 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1749 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1750 /* FIXME when we have to issue an evaluate endpoint command to
1751 * deal with ep0 max packet size changing once we get the
1754 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1755 __func__, added_ctxs);
1759 virt_dev = xhci->devs[udev->slot_id];
1760 in_ctx = virt_dev->in_ctx;
1761 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1763 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1768 ep_index = xhci_get_endpoint_index(&ep->desc);
1769 /* If this endpoint is already in use, and the upper layers are trying
1770 * to add it again without dropping it, reject the addition.
1772 if (virt_dev->eps[ep_index].ring &&
1773 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1774 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1775 "without dropping it.\n",
1776 (unsigned int) ep->desc.bEndpointAddress);
1780 /* If the HCD has already noted the endpoint is enabled,
1781 * ignore this request.
1783 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1784 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1790 * Configuration and alternate setting changes must be done in
1791 * process context, not interrupt context (or so documenation
1792 * for usb_set_interface() and usb_set_configuration() claim).
1794 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1795 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1796 __func__, ep->desc.bEndpointAddress);
1800 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1801 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1803 /* If xhci_endpoint_disable() was called for this endpoint, but the
1804 * xHC hasn't been notified yet through the check_bandwidth() call,
1805 * this re-adds a new state for the endpoint from the new endpoint
1806 * descriptors. We must drop and re-add this endpoint, so we leave the
1809 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1811 /* Store the usb_device pointer for later use */
1814 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1815 (unsigned int) ep->desc.bEndpointAddress,
1817 (unsigned int) new_drop_flags,
1818 (unsigned int) new_add_flags);
1822 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1824 struct xhci_input_control_ctx *ctrl_ctx;
1825 struct xhci_ep_ctx *ep_ctx;
1826 struct xhci_slot_ctx *slot_ctx;
1829 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1831 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1836 /* When a device's add flag and drop flag are zero, any subsequent
1837 * configure endpoint command will leave that endpoint's state
1838 * untouched. Make sure we don't leave any old state in the input
1839 * endpoint contexts.
1841 ctrl_ctx->drop_flags = 0;
1842 ctrl_ctx->add_flags = 0;
1843 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1844 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1845 /* Endpoint 0 is always valid */
1846 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1847 for (i = 1; i < 31; ++i) {
1848 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1849 ep_ctx->ep_info = 0;
1850 ep_ctx->ep_info2 = 0;
1852 ep_ctx->tx_info = 0;
1856 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1857 struct usb_device *udev, u32 *cmd_status)
1861 switch (*cmd_status) {
1862 case COMP_CMD_ABORT:
1864 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1868 dev_warn(&udev->dev,
1869 "Not enough host controller resources for new device state.\n");
1871 /* FIXME: can we allocate more resources for the HC? */
1874 case COMP_2ND_BW_ERR:
1875 dev_warn(&udev->dev,
1876 "Not enough bandwidth for new device state.\n");
1878 /* FIXME: can we go back to the old state? */
1881 /* the HCD set up something wrong */
1882 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1884 "and endpoint is not disabled.\n");
1888 dev_warn(&udev->dev,
1889 "ERROR: Incompatible device for endpoint configure command.\n");
1893 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1894 "Successful Endpoint Configure command");
1898 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1906 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1907 struct usb_device *udev, u32 *cmd_status)
1910 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1912 switch (*cmd_status) {
1913 case COMP_CMD_ABORT:
1915 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1919 dev_warn(&udev->dev,
1920 "WARN: xHCI driver setup invalid evaluate context command.\n");
1924 dev_warn(&udev->dev,
1925 "WARN: slot not enabled for evaluate context command.\n");
1928 case COMP_CTX_STATE:
1929 dev_warn(&udev->dev,
1930 "WARN: invalid context state for evaluate context command.\n");
1931 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1935 dev_warn(&udev->dev,
1936 "ERROR: Incompatible device for evaluate context command.\n");
1940 /* Max Exit Latency too large error */
1941 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1945 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1946 "Successful evaluate context command");
1950 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1958 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1959 struct xhci_input_control_ctx *ctrl_ctx)
1961 u32 valid_add_flags;
1962 u32 valid_drop_flags;
1964 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1965 * (bit 1). The default control endpoint is added during the Address
1966 * Device command and is never removed until the slot is disabled.
1968 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1969 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1971 /* Use hweight32 to count the number of ones in the add flags, or
1972 * number of endpoints added. Don't count endpoints that are changed
1973 * (both added and dropped).
1975 return hweight32(valid_add_flags) -
1976 hweight32(valid_add_flags & valid_drop_flags);
1979 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1980 struct xhci_input_control_ctx *ctrl_ctx)
1982 u32 valid_add_flags;
1983 u32 valid_drop_flags;
1985 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1986 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1988 return hweight32(valid_drop_flags) -
1989 hweight32(valid_add_flags & valid_drop_flags);
1993 * We need to reserve the new number of endpoints before the configure endpoint
1994 * command completes. We can't subtract the dropped endpoints from the number
1995 * of active endpoints until the command completes because we can oversubscribe
1996 * the host in this case:
1998 * - the first configure endpoint command drops more endpoints than it adds
1999 * - a second configure endpoint command that adds more endpoints is queued
2000 * - the first configure endpoint command fails, so the config is unchanged
2001 * - the second command may succeed, even though there isn't enough resources
2003 * Must be called with xhci->lock held.
2005 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2006 struct xhci_input_control_ctx *ctrl_ctx)
2010 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2011 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2012 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2013 "Not enough ep ctxs: "
2014 "%u active, need to add %u, limit is %u.",
2015 xhci->num_active_eps, added_eps,
2016 xhci->limit_active_eps);
2019 xhci->num_active_eps += added_eps;
2020 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2021 "Adding %u ep ctxs, %u now active.", added_eps,
2022 xhci->num_active_eps);
2027 * The configure endpoint was failed by the xHC for some other reason, so we
2028 * need to revert the resources that failed configuration would have used.
2030 * Must be called with xhci->lock held.
2032 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2033 struct xhci_input_control_ctx *ctrl_ctx)
2037 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2038 xhci->num_active_eps -= num_failed_eps;
2039 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2040 "Removing %u failed ep ctxs, %u now active.",
2042 xhci->num_active_eps);
2046 * Now that the command has completed, clean up the active endpoint count by
2047 * subtracting out the endpoints that were dropped (but not changed).
2049 * Must be called with xhci->lock held.
2051 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2052 struct xhci_input_control_ctx *ctrl_ctx)
2054 u32 num_dropped_eps;
2056 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2057 xhci->num_active_eps -= num_dropped_eps;
2058 if (num_dropped_eps)
2059 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2060 "Removing %u dropped ep ctxs, %u now active.",
2062 xhci->num_active_eps);
2065 static unsigned int xhci_get_block_size(struct usb_device *udev)
2067 switch (udev->speed) {
2069 case USB_SPEED_FULL:
2071 case USB_SPEED_HIGH:
2073 case USB_SPEED_SUPER:
2074 case USB_SPEED_SUPER_PLUS:
2076 case USB_SPEED_UNKNOWN:
2077 case USB_SPEED_WIRELESS:
2079 /* Should never happen */
2085 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2087 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2089 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2094 /* If we are changing a LS/FS device under a HS hub,
2095 * make sure (if we are activating a new TT) that the HS bus has enough
2096 * bandwidth for this new TT.
2098 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2099 struct xhci_virt_device *virt_dev,
2102 struct xhci_interval_bw_table *bw_table;
2103 struct xhci_tt_bw_info *tt_info;
2105 /* Find the bandwidth table for the root port this TT is attached to. */
2106 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2107 tt_info = virt_dev->tt_info;
2108 /* If this TT already had active endpoints, the bandwidth for this TT
2109 * has already been added. Removing all periodic endpoints (and thus
2110 * making the TT enactive) will only decrease the bandwidth used.
2114 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2115 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2119 /* Not sure why we would have no new active endpoints...
2121 * Maybe because of an Evaluate Context change for a hub update or a
2122 * control endpoint 0 max packet size change?
2123 * FIXME: skip the bandwidth calculation in that case.
2128 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2129 struct xhci_virt_device *virt_dev)
2131 unsigned int bw_reserved;
2133 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2134 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2137 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2138 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2145 * This algorithm is a very conservative estimate of the worst-case scheduling
2146 * scenario for any one interval. The hardware dynamically schedules the
2147 * packets, so we can't tell which microframe could be the limiting factor in
2148 * the bandwidth scheduling. This only takes into account periodic endpoints.
2150 * Obviously, we can't solve an NP complete problem to find the minimum worst
2151 * case scenario. Instead, we come up with an estimate that is no less than
2152 * the worst case bandwidth used for any one microframe, but may be an
2155 * We walk the requirements for each endpoint by interval, starting with the
2156 * smallest interval, and place packets in the schedule where there is only one
2157 * possible way to schedule packets for that interval. In order to simplify
2158 * this algorithm, we record the largest max packet size for each interval, and
2159 * assume all packets will be that size.
2161 * For interval 0, we obviously must schedule all packets for each interval.
2162 * The bandwidth for interval 0 is just the amount of data to be transmitted
2163 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2164 * the number of packets).
2166 * For interval 1, we have two possible microframes to schedule those packets
2167 * in. For this algorithm, if we can schedule the same number of packets for
2168 * each possible scheduling opportunity (each microframe), we will do so. The
2169 * remaining number of packets will be saved to be transmitted in the gaps in
2170 * the next interval's scheduling sequence.
2172 * As we move those remaining packets to be scheduled with interval 2 packets,
2173 * we have to double the number of remaining packets to transmit. This is
2174 * because the intervals are actually powers of 2, and we would be transmitting
2175 * the previous interval's packets twice in this interval. We also have to be
2176 * sure that when we look at the largest max packet size for this interval, we
2177 * also look at the largest max packet size for the remaining packets and take
2178 * the greater of the two.
2180 * The algorithm continues to evenly distribute packets in each scheduling
2181 * opportunity, and push the remaining packets out, until we get to the last
2182 * interval. Then those packets and their associated overhead are just added
2183 * to the bandwidth used.
2185 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2186 struct xhci_virt_device *virt_dev,
2189 unsigned int bw_reserved;
2190 unsigned int max_bandwidth;
2191 unsigned int bw_used;
2192 unsigned int block_size;
2193 struct xhci_interval_bw_table *bw_table;
2194 unsigned int packet_size = 0;
2195 unsigned int overhead = 0;
2196 unsigned int packets_transmitted = 0;
2197 unsigned int packets_remaining = 0;
2200 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2201 return xhci_check_ss_bw(xhci, virt_dev);
2203 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2204 max_bandwidth = HS_BW_LIMIT;
2205 /* Convert percent of bus BW reserved to blocks reserved */
2206 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2208 max_bandwidth = FS_BW_LIMIT;
2209 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2212 bw_table = virt_dev->bw_table;
2213 /* We need to translate the max packet size and max ESIT payloads into
2214 * the units the hardware uses.
2216 block_size = xhci_get_block_size(virt_dev->udev);
2218 /* If we are manipulating a LS/FS device under a HS hub, double check
2219 * that the HS bus has enough bandwidth if we are activing a new TT.
2221 if (virt_dev->tt_info) {
2222 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2223 "Recalculating BW for rootport %u",
2224 virt_dev->real_port);
2225 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2226 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2227 "newly activated TT.\n");
2230 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2231 "Recalculating BW for TT slot %u port %u",
2232 virt_dev->tt_info->slot_id,
2233 virt_dev->tt_info->ttport);
2235 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2236 "Recalculating BW for rootport %u",
2237 virt_dev->real_port);
2240 /* Add in how much bandwidth will be used for interval zero, or the
2241 * rounded max ESIT payload + number of packets * largest overhead.
2243 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2244 bw_table->interval_bw[0].num_packets *
2245 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2247 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2248 unsigned int bw_added;
2249 unsigned int largest_mps;
2250 unsigned int interval_overhead;
2253 * How many packets could we transmit in this interval?
2254 * If packets didn't fit in the previous interval, we will need
2255 * to transmit that many packets twice within this interval.
2257 packets_remaining = 2 * packets_remaining +
2258 bw_table->interval_bw[i].num_packets;
2260 /* Find the largest max packet size of this or the previous
2263 if (list_empty(&bw_table->interval_bw[i].endpoints))
2266 struct xhci_virt_ep *virt_ep;
2267 struct list_head *ep_entry;
2269 ep_entry = bw_table->interval_bw[i].endpoints.next;
2270 virt_ep = list_entry(ep_entry,
2271 struct xhci_virt_ep, bw_endpoint_list);
2272 /* Convert to blocks, rounding up */
2273 largest_mps = DIV_ROUND_UP(
2274 virt_ep->bw_info.max_packet_size,
2277 if (largest_mps > packet_size)
2278 packet_size = largest_mps;
2280 /* Use the larger overhead of this or the previous interval. */
2281 interval_overhead = xhci_get_largest_overhead(
2282 &bw_table->interval_bw[i]);
2283 if (interval_overhead > overhead)
2284 overhead = interval_overhead;
2286 /* How many packets can we evenly distribute across
2287 * (1 << (i + 1)) possible scheduling opportunities?
2289 packets_transmitted = packets_remaining >> (i + 1);
2291 /* Add in the bandwidth used for those scheduled packets */
2292 bw_added = packets_transmitted * (overhead + packet_size);
2294 /* How many packets do we have remaining to transmit? */
2295 packets_remaining = packets_remaining % (1 << (i + 1));
2297 /* What largest max packet size should those packets have? */
2298 /* If we've transmitted all packets, don't carry over the
2299 * largest packet size.
2301 if (packets_remaining == 0) {
2304 } else if (packets_transmitted > 0) {
2305 /* Otherwise if we do have remaining packets, and we've
2306 * scheduled some packets in this interval, take the
2307 * largest max packet size from endpoints with this
2310 packet_size = largest_mps;
2311 overhead = interval_overhead;
2313 /* Otherwise carry over packet_size and overhead from the last
2314 * time we had a remainder.
2316 bw_used += bw_added;
2317 if (bw_used > max_bandwidth) {
2318 xhci_warn(xhci, "Not enough bandwidth. "
2319 "Proposed: %u, Max: %u\n",
2320 bw_used, max_bandwidth);
2325 * Ok, we know we have some packets left over after even-handedly
2326 * scheduling interval 15. We don't know which microframes they will
2327 * fit into, so we over-schedule and say they will be scheduled every
2330 if (packets_remaining > 0)
2331 bw_used += overhead + packet_size;
2333 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2334 unsigned int port_index = virt_dev->real_port - 1;
2336 /* OK, we're manipulating a HS device attached to a
2337 * root port bandwidth domain. Include the number of active TTs
2338 * in the bandwidth used.
2340 bw_used += TT_HS_OVERHEAD *
2341 xhci->rh_bw[port_index].num_active_tts;
2344 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2345 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2346 "Available: %u " "percent",
2347 bw_used, max_bandwidth, bw_reserved,
2348 (max_bandwidth - bw_used - bw_reserved) * 100 /
2351 bw_used += bw_reserved;
2352 if (bw_used > max_bandwidth) {
2353 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2354 bw_used, max_bandwidth);
2358 bw_table->bw_used = bw_used;
2362 static bool xhci_is_async_ep(unsigned int ep_type)
2364 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2365 ep_type != ISOC_IN_EP &&
2366 ep_type != INT_IN_EP);
2369 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2371 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2374 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2376 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2378 if (ep_bw->ep_interval == 0)
2379 return SS_OVERHEAD_BURST +
2380 (ep_bw->mult * ep_bw->num_packets *
2381 (SS_OVERHEAD + mps));
2382 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2383 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2384 1 << ep_bw->ep_interval);
2388 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2389 struct xhci_bw_info *ep_bw,
2390 struct xhci_interval_bw_table *bw_table,
2391 struct usb_device *udev,
2392 struct xhci_virt_ep *virt_ep,
2393 struct xhci_tt_bw_info *tt_info)
2395 struct xhci_interval_bw *interval_bw;
2396 int normalized_interval;
2398 if (xhci_is_async_ep(ep_bw->type))
2401 if (udev->speed >= USB_SPEED_SUPER) {
2402 if (xhci_is_sync_in_ep(ep_bw->type))
2403 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2404 xhci_get_ss_bw_consumed(ep_bw);
2406 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2407 xhci_get_ss_bw_consumed(ep_bw);
2411 /* SuperSpeed endpoints never get added to intervals in the table, so
2412 * this check is only valid for HS/FS/LS devices.
2414 if (list_empty(&virt_ep->bw_endpoint_list))
2416 /* For LS/FS devices, we need to translate the interval expressed in
2417 * microframes to frames.
2419 if (udev->speed == USB_SPEED_HIGH)
2420 normalized_interval = ep_bw->ep_interval;
2422 normalized_interval = ep_bw->ep_interval - 3;
2424 if (normalized_interval == 0)
2425 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2426 interval_bw = &bw_table->interval_bw[normalized_interval];
2427 interval_bw->num_packets -= ep_bw->num_packets;
2428 switch (udev->speed) {
2430 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2432 case USB_SPEED_FULL:
2433 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2435 case USB_SPEED_HIGH:
2436 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2438 case USB_SPEED_SUPER:
2439 case USB_SPEED_SUPER_PLUS:
2440 case USB_SPEED_UNKNOWN:
2441 case USB_SPEED_WIRELESS:
2442 /* Should never happen because only LS/FS/HS endpoints will get
2443 * added to the endpoint list.
2448 tt_info->active_eps -= 1;
2449 list_del_init(&virt_ep->bw_endpoint_list);
2452 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2453 struct xhci_bw_info *ep_bw,
2454 struct xhci_interval_bw_table *bw_table,
2455 struct usb_device *udev,
2456 struct xhci_virt_ep *virt_ep,
2457 struct xhci_tt_bw_info *tt_info)
2459 struct xhci_interval_bw *interval_bw;
2460 struct xhci_virt_ep *smaller_ep;
2461 int normalized_interval;
2463 if (xhci_is_async_ep(ep_bw->type))
2466 if (udev->speed == USB_SPEED_SUPER) {
2467 if (xhci_is_sync_in_ep(ep_bw->type))
2468 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2469 xhci_get_ss_bw_consumed(ep_bw);
2471 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2472 xhci_get_ss_bw_consumed(ep_bw);
2476 /* For LS/FS devices, we need to translate the interval expressed in
2477 * microframes to frames.
2479 if (udev->speed == USB_SPEED_HIGH)
2480 normalized_interval = ep_bw->ep_interval;
2482 normalized_interval = ep_bw->ep_interval - 3;
2484 if (normalized_interval == 0)
2485 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2486 interval_bw = &bw_table->interval_bw[normalized_interval];
2487 interval_bw->num_packets += ep_bw->num_packets;
2488 switch (udev->speed) {
2490 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2492 case USB_SPEED_FULL:
2493 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2495 case USB_SPEED_HIGH:
2496 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2498 case USB_SPEED_SUPER:
2499 case USB_SPEED_SUPER_PLUS:
2500 case USB_SPEED_UNKNOWN:
2501 case USB_SPEED_WIRELESS:
2502 /* Should never happen because only LS/FS/HS endpoints will get
2503 * added to the endpoint list.
2509 tt_info->active_eps += 1;
2510 /* Insert the endpoint into the list, largest max packet size first. */
2511 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2513 if (ep_bw->max_packet_size >=
2514 smaller_ep->bw_info.max_packet_size) {
2515 /* Add the new ep before the smaller endpoint */
2516 list_add_tail(&virt_ep->bw_endpoint_list,
2517 &smaller_ep->bw_endpoint_list);
2521 /* Add the new endpoint at the end of the list. */
2522 list_add_tail(&virt_ep->bw_endpoint_list,
2523 &interval_bw->endpoints);
2526 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2527 struct xhci_virt_device *virt_dev,
2530 struct xhci_root_port_bw_info *rh_bw_info;
2531 if (!virt_dev->tt_info)
2534 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2535 if (old_active_eps == 0 &&
2536 virt_dev->tt_info->active_eps != 0) {
2537 rh_bw_info->num_active_tts += 1;
2538 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2539 } else if (old_active_eps != 0 &&
2540 virt_dev->tt_info->active_eps == 0) {
2541 rh_bw_info->num_active_tts -= 1;
2542 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2546 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2547 struct xhci_virt_device *virt_dev,
2548 struct xhci_container_ctx *in_ctx)
2550 struct xhci_bw_info ep_bw_info[31];
2552 struct xhci_input_control_ctx *ctrl_ctx;
2553 int old_active_eps = 0;
2555 if (virt_dev->tt_info)
2556 old_active_eps = virt_dev->tt_info->active_eps;
2558 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2560 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2565 for (i = 0; i < 31; i++) {
2566 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2569 /* Make a copy of the BW info in case we need to revert this */
2570 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2571 sizeof(ep_bw_info[i]));
2572 /* Drop the endpoint from the interval table if the endpoint is
2573 * being dropped or changed.
2575 if (EP_IS_DROPPED(ctrl_ctx, i))
2576 xhci_drop_ep_from_interval_table(xhci,
2577 &virt_dev->eps[i].bw_info,
2583 /* Overwrite the information stored in the endpoints' bw_info */
2584 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2585 for (i = 0; i < 31; i++) {
2586 /* Add any changed or added endpoints to the interval table */
2587 if (EP_IS_ADDED(ctrl_ctx, i))
2588 xhci_add_ep_to_interval_table(xhci,
2589 &virt_dev->eps[i].bw_info,
2596 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2597 /* Ok, this fits in the bandwidth we have.
2598 * Update the number of active TTs.
2600 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2604 /* We don't have enough bandwidth for this, revert the stored info. */
2605 for (i = 0; i < 31; i++) {
2606 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2609 /* Drop the new copies of any added or changed endpoints from
2610 * the interval table.
2612 if (EP_IS_ADDED(ctrl_ctx, i)) {
2613 xhci_drop_ep_from_interval_table(xhci,
2614 &virt_dev->eps[i].bw_info,
2620 /* Revert the endpoint back to its old information */
2621 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2622 sizeof(ep_bw_info[i]));
2623 /* Add any changed or dropped endpoints back into the table */
2624 if (EP_IS_DROPPED(ctrl_ctx, i))
2625 xhci_add_ep_to_interval_table(xhci,
2626 &virt_dev->eps[i].bw_info,
2636 /* Issue a configure endpoint command or evaluate context command
2637 * and wait for it to finish.
2639 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2640 struct usb_device *udev,
2641 struct xhci_command *command,
2642 bool ctx_change, bool must_succeed)
2645 unsigned long flags;
2646 struct xhci_input_control_ctx *ctrl_ctx;
2647 struct xhci_virt_device *virt_dev;
2652 spin_lock_irqsave(&xhci->lock, flags);
2653 virt_dev = xhci->devs[udev->slot_id];
2655 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2657 spin_unlock_irqrestore(&xhci->lock, flags);
2658 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2663 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2664 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2665 spin_unlock_irqrestore(&xhci->lock, flags);
2666 xhci_warn(xhci, "Not enough host resources, "
2667 "active endpoint contexts = %u\n",
2668 xhci->num_active_eps);
2671 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2672 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2673 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2674 xhci_free_host_resources(xhci, ctrl_ctx);
2675 spin_unlock_irqrestore(&xhci->lock, flags);
2676 xhci_warn(xhci, "Not enough bandwidth\n");
2681 ret = xhci_queue_configure_endpoint(xhci, command,
2682 command->in_ctx->dma,
2683 udev->slot_id, must_succeed);
2685 ret = xhci_queue_evaluate_context(xhci, command,
2686 command->in_ctx->dma,
2687 udev->slot_id, must_succeed);
2689 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2690 xhci_free_host_resources(xhci, ctrl_ctx);
2691 spin_unlock_irqrestore(&xhci->lock, flags);
2692 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2693 "FIXME allocate a new ring segment");
2696 xhci_ring_cmd_db(xhci);
2697 spin_unlock_irqrestore(&xhci->lock, flags);
2699 /* Wait for the configure endpoint command to complete */
2700 wait_for_completion(command->completion);
2703 ret = xhci_configure_endpoint_result(xhci, udev,
2706 ret = xhci_evaluate_context_result(xhci, udev,
2709 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2710 spin_lock_irqsave(&xhci->lock, flags);
2711 /* If the command failed, remove the reserved resources.
2712 * Otherwise, clean up the estimate to include dropped eps.
2715 xhci_free_host_resources(xhci, ctrl_ctx);
2717 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2718 spin_unlock_irqrestore(&xhci->lock, flags);
2723 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2724 struct xhci_virt_device *vdev, int i)
2726 struct xhci_virt_ep *ep = &vdev->eps[i];
2728 if (ep->ep_state & EP_HAS_STREAMS) {
2729 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2730 xhci_get_endpoint_address(i));
2731 xhci_free_stream_info(xhci, ep->stream_info);
2732 ep->stream_info = NULL;
2733 ep->ep_state &= ~EP_HAS_STREAMS;
2737 /* Called after one or more calls to xhci_add_endpoint() or
2738 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2739 * to call xhci_reset_bandwidth().
2741 * Since we are in the middle of changing either configuration or
2742 * installing a new alt setting, the USB core won't allow URBs to be
2743 * enqueued for any endpoint on the old config or interface. Nothing
2744 * else should be touching the xhci->devs[slot_id] structure, so we
2745 * don't need to take the xhci->lock for manipulating that.
2747 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2751 struct xhci_hcd *xhci;
2752 struct xhci_virt_device *virt_dev;
2753 struct xhci_input_control_ctx *ctrl_ctx;
2754 struct xhci_slot_ctx *slot_ctx;
2755 struct xhci_command *command;
2757 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2760 xhci = hcd_to_xhci(hcd);
2761 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2762 (xhci->xhc_state & XHCI_STATE_REMOVING))
2765 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2766 virt_dev = xhci->devs[udev->slot_id];
2768 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2772 command->in_ctx = virt_dev->in_ctx;
2774 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2775 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2777 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2780 goto command_cleanup;
2782 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2783 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2784 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2786 /* Don't issue the command if there's no endpoints to update. */
2787 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2788 ctrl_ctx->drop_flags == 0) {
2790 goto command_cleanup;
2792 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2793 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2794 for (i = 31; i >= 1; i--) {
2795 __le32 le32 = cpu_to_le32(BIT(i));
2797 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2798 || (ctrl_ctx->add_flags & le32) || i == 1) {
2799 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2800 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2804 xhci_dbg(xhci, "New Input Control Context:\n");
2805 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2806 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2808 ret = xhci_configure_endpoint(xhci, udev, command,
2811 /* Callee should call reset_bandwidth() */
2812 goto command_cleanup;
2814 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2815 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2816 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2818 /* Free any rings that were dropped, but not changed. */
2819 for (i = 1; i < 31; ++i) {
2820 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2821 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2822 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2823 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2826 xhci_zero_in_ctx(xhci, virt_dev);
2828 * Install any rings for completely new endpoints or changed endpoints,
2829 * and free or cache any old rings from changed endpoints.
2831 for (i = 1; i < 31; ++i) {
2832 if (!virt_dev->eps[i].new_ring)
2834 /* Only cache or free the old ring if it exists.
2835 * It may not if this is the first add of an endpoint.
2837 if (virt_dev->eps[i].ring) {
2838 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2840 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2841 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2842 virt_dev->eps[i].new_ring = NULL;
2845 kfree(command->completion);
2851 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2853 struct xhci_hcd *xhci;
2854 struct xhci_virt_device *virt_dev;
2857 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2860 xhci = hcd_to_xhci(hcd);
2862 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2863 virt_dev = xhci->devs[udev->slot_id];
2864 /* Free any rings allocated for added endpoints */
2865 for (i = 0; i < 31; ++i) {
2866 if (virt_dev->eps[i].new_ring) {
2867 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2868 virt_dev->eps[i].new_ring = NULL;
2871 xhci_zero_in_ctx(xhci, virt_dev);
2874 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2875 struct xhci_container_ctx *in_ctx,
2876 struct xhci_container_ctx *out_ctx,
2877 struct xhci_input_control_ctx *ctrl_ctx,
2878 u32 add_flags, u32 drop_flags)
2880 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2881 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2882 xhci_slot_copy(xhci, in_ctx, out_ctx);
2883 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2885 xhci_dbg(xhci, "Input Context:\n");
2886 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2889 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2890 unsigned int slot_id, unsigned int ep_index,
2891 struct xhci_dequeue_state *deq_state)
2893 struct xhci_input_control_ctx *ctrl_ctx;
2894 struct xhci_container_ctx *in_ctx;
2895 struct xhci_ep_ctx *ep_ctx;
2899 in_ctx = xhci->devs[slot_id]->in_ctx;
2900 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2902 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2907 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2908 xhci->devs[slot_id]->out_ctx, ep_index);
2909 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2910 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2911 deq_state->new_deq_ptr);
2913 xhci_warn(xhci, "WARN Cannot submit config ep after "
2914 "reset ep command\n");
2915 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2916 deq_state->new_deq_seg,
2917 deq_state->new_deq_ptr);
2920 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2922 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2923 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2924 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2925 added_ctxs, added_ctxs);
2928 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2929 unsigned int ep_index, struct xhci_td *td)
2931 struct xhci_dequeue_state deq_state;
2932 struct xhci_virt_ep *ep;
2933 struct usb_device *udev = td->urb->dev;
2935 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2936 "Cleaning up stalled endpoint ring");
2937 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2938 /* We need to move the HW's dequeue pointer past this TD,
2939 * or it will attempt to resend it on the next doorbell ring.
2941 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2942 ep_index, ep->stopped_stream, td, &deq_state);
2944 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2947 /* HW with the reset endpoint quirk will use the saved dequeue state to
2948 * issue a configure endpoint command later.
2950 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2951 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2952 "Queueing new dequeue state");
2953 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2954 ep_index, ep->stopped_stream, &deq_state);
2956 /* Better hope no one uses the input context between now and the
2957 * reset endpoint completion!
2958 * XXX: No idea how this hardware will react when stream rings
2961 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2962 "Setting up input context for "
2963 "configure endpoint command");
2964 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2965 ep_index, &deq_state);
2969 /* Called when clearing halted device. The core should have sent the control
2970 * message to clear the device halt condition. The host side of the halt should
2971 * already be cleared with a reset endpoint command issued when the STALL tx
2972 * event was received.
2974 * Context: in_interrupt
2977 void xhci_endpoint_reset(struct usb_hcd *hcd,
2978 struct usb_host_endpoint *ep)
2980 struct xhci_hcd *xhci;
2982 xhci = hcd_to_xhci(hcd);
2985 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2986 * The Reset Endpoint Command may only be issued to endpoints in the
2987 * Halted state. If software wishes reset the Data Toggle or Sequence
2988 * Number of an endpoint that isn't in the Halted state, then software
2989 * may issue a Configure Endpoint Command with the Drop and Add bits set
2990 * for the target endpoint. that is in the Stopped state.
2993 /* For now just print debug to follow the situation */
2994 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
2995 ep->desc.bEndpointAddress);
2998 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2999 struct usb_device *udev, struct usb_host_endpoint *ep,
3000 unsigned int slot_id)
3003 unsigned int ep_index;
3004 unsigned int ep_state;
3008 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3011 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3012 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3013 " descriptor for ep 0x%x does not support streams\n",
3014 ep->desc.bEndpointAddress);
3018 ep_index = xhci_get_endpoint_index(&ep->desc);
3019 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3020 if (ep_state & EP_HAS_STREAMS ||
3021 ep_state & EP_GETTING_STREAMS) {
3022 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3023 "already has streams set up.\n",
3024 ep->desc.bEndpointAddress);
3025 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3026 "dynamic stream context array reallocation.\n");
3029 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3030 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3031 "endpoint 0x%x; URBs are pending.\n",
3032 ep->desc.bEndpointAddress);
3038 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3039 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3041 unsigned int max_streams;
3043 /* The stream context array size must be a power of two */
3044 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3046 * Find out how many primary stream array entries the host controller
3047 * supports. Later we may use secondary stream arrays (similar to 2nd
3048 * level page entries), but that's an optional feature for xHCI host
3049 * controllers. xHCs must support at least 4 stream IDs.
3051 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3052 if (*num_stream_ctxs > max_streams) {
3053 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3055 *num_stream_ctxs = max_streams;
3056 *num_streams = max_streams;
3060 /* Returns an error code if one of the endpoint already has streams.
3061 * This does not change any data structures, it only checks and gathers
3064 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3065 struct usb_device *udev,
3066 struct usb_host_endpoint **eps, unsigned int num_eps,
3067 unsigned int *num_streams, u32 *changed_ep_bitmask)
3069 unsigned int max_streams;
3070 unsigned int endpoint_flag;
3074 for (i = 0; i < num_eps; i++) {
3075 ret = xhci_check_streams_endpoint(xhci, udev,
3076 eps[i], udev->slot_id);
3080 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3081 if (max_streams < (*num_streams - 1)) {
3082 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3083 eps[i]->desc.bEndpointAddress,
3085 *num_streams = max_streams+1;
3088 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3089 if (*changed_ep_bitmask & endpoint_flag)
3091 *changed_ep_bitmask |= endpoint_flag;
3096 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3097 struct usb_device *udev,
3098 struct usb_host_endpoint **eps, unsigned int num_eps)
3100 u32 changed_ep_bitmask = 0;
3101 unsigned int slot_id;
3102 unsigned int ep_index;
3103 unsigned int ep_state;
3106 slot_id = udev->slot_id;
3107 if (!xhci->devs[slot_id])
3110 for (i = 0; i < num_eps; i++) {
3111 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3112 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3113 /* Are streams already being freed for the endpoint? */
3114 if (ep_state & EP_GETTING_NO_STREAMS) {
3115 xhci_warn(xhci, "WARN Can't disable streams for "
3117 "streams are being disabled already\n",
3118 eps[i]->desc.bEndpointAddress);
3121 /* Are there actually any streams to free? */
3122 if (!(ep_state & EP_HAS_STREAMS) &&
3123 !(ep_state & EP_GETTING_STREAMS)) {
3124 xhci_warn(xhci, "WARN Can't disable streams for "
3126 "streams are already disabled!\n",
3127 eps[i]->desc.bEndpointAddress);
3128 xhci_warn(xhci, "WARN xhci_free_streams() called "
3129 "with non-streams endpoint\n");
3132 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3134 return changed_ep_bitmask;
3138 * The USB device drivers use this function (through the HCD interface in USB
3139 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3140 * coordinate mass storage command queueing across multiple endpoints (basically
3141 * a stream ID == a task ID).
3143 * Setting up streams involves allocating the same size stream context array
3144 * for each endpoint and issuing a configure endpoint command for all endpoints.
3146 * Don't allow the call to succeed if one endpoint only supports one stream
3147 * (which means it doesn't support streams at all).
3149 * Drivers may get less stream IDs than they asked for, if the host controller
3150 * hardware or endpoints claim they can't support the number of requested
3153 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3154 struct usb_host_endpoint **eps, unsigned int num_eps,
3155 unsigned int num_streams, gfp_t mem_flags)
3158 struct xhci_hcd *xhci;
3159 struct xhci_virt_device *vdev;
3160 struct xhci_command *config_cmd;
3161 struct xhci_input_control_ctx *ctrl_ctx;
3162 unsigned int ep_index;
3163 unsigned int num_stream_ctxs;
3164 unsigned long flags;
3165 u32 changed_ep_bitmask = 0;
3170 /* Add one to the number of streams requested to account for
3171 * stream 0 that is reserved for xHCI usage.
3174 xhci = hcd_to_xhci(hcd);
3175 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3178 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3179 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3180 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3181 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3185 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3187 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3190 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3192 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3194 xhci_free_command(xhci, config_cmd);
3198 /* Check to make sure all endpoints are not already configured for
3199 * streams. While we're at it, find the maximum number of streams that
3200 * all the endpoints will support and check for duplicate endpoints.
3202 spin_lock_irqsave(&xhci->lock, flags);
3203 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3204 num_eps, &num_streams, &changed_ep_bitmask);
3206 xhci_free_command(xhci, config_cmd);
3207 spin_unlock_irqrestore(&xhci->lock, flags);
3210 if (num_streams <= 1) {
3211 xhci_warn(xhci, "WARN: endpoints can't handle "
3212 "more than one stream.\n");
3213 xhci_free_command(xhci, config_cmd);
3214 spin_unlock_irqrestore(&xhci->lock, flags);
3217 vdev = xhci->devs[udev->slot_id];
3218 /* Mark each endpoint as being in transition, so
3219 * xhci_urb_enqueue() will reject all URBs.
3221 for (i = 0; i < num_eps; i++) {
3222 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3223 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3225 spin_unlock_irqrestore(&xhci->lock, flags);
3227 /* Setup internal data structures and allocate HW data structures for
3228 * streams (but don't install the HW structures in the input context
3229 * until we're sure all memory allocation succeeded).
3231 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3232 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3233 num_stream_ctxs, num_streams);
3235 for (i = 0; i < num_eps; i++) {
3236 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3237 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3239 num_streams, mem_flags);
3240 if (!vdev->eps[ep_index].stream_info)
3242 /* Set maxPstreams in endpoint context and update deq ptr to
3243 * point to stream context array. FIXME
3247 /* Set up the input context for a configure endpoint command. */
3248 for (i = 0; i < num_eps; i++) {
3249 struct xhci_ep_ctx *ep_ctx;
3251 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3252 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3254 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3255 vdev->out_ctx, ep_index);
3256 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3257 vdev->eps[ep_index].stream_info);
3259 /* Tell the HW to drop its old copy of the endpoint context info
3260 * and add the updated copy from the input context.
3262 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3263 vdev->out_ctx, ctrl_ctx,
3264 changed_ep_bitmask, changed_ep_bitmask);
3266 /* Issue and wait for the configure endpoint command */
3267 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3270 /* xHC rejected the configure endpoint command for some reason, so we
3271 * leave the old ring intact and free our internal streams data
3277 spin_lock_irqsave(&xhci->lock, flags);
3278 for (i = 0; i < num_eps; i++) {
3279 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3280 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3281 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3282 udev->slot_id, ep_index);
3283 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3285 xhci_free_command(xhci, config_cmd);
3286 spin_unlock_irqrestore(&xhci->lock, flags);
3288 /* Subtract 1 for stream 0, which drivers can't use */
3289 return num_streams - 1;
3292 /* If it didn't work, free the streams! */
3293 for (i = 0; i < num_eps; i++) {
3294 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3295 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3296 vdev->eps[ep_index].stream_info = NULL;
3297 /* FIXME Unset maxPstreams in endpoint context and
3298 * update deq ptr to point to normal string ring.
3300 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3301 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3302 xhci_endpoint_zero(xhci, vdev, eps[i]);
3304 xhci_free_command(xhci, config_cmd);
3308 /* Transition the endpoint from using streams to being a "normal" endpoint
3311 * Modify the endpoint context state, submit a configure endpoint command,
3312 * and free all endpoint rings for streams if that completes successfully.
3314 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3315 struct usb_host_endpoint **eps, unsigned int num_eps,
3319 struct xhci_hcd *xhci;
3320 struct xhci_virt_device *vdev;
3321 struct xhci_command *command;
3322 struct xhci_input_control_ctx *ctrl_ctx;
3323 unsigned int ep_index;
3324 unsigned long flags;
3325 u32 changed_ep_bitmask;
3327 xhci = hcd_to_xhci(hcd);
3328 vdev = xhci->devs[udev->slot_id];
3330 /* Set up a configure endpoint command to remove the streams rings */
3331 spin_lock_irqsave(&xhci->lock, flags);
3332 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3333 udev, eps, num_eps);
3334 if (changed_ep_bitmask == 0) {
3335 spin_unlock_irqrestore(&xhci->lock, flags);
3339 /* Use the xhci_command structure from the first endpoint. We may have
3340 * allocated too many, but the driver may call xhci_free_streams() for
3341 * each endpoint it grouped into one call to xhci_alloc_streams().
3343 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3344 command = vdev->eps[ep_index].stream_info->free_streams_command;
3345 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3347 spin_unlock_irqrestore(&xhci->lock, flags);
3348 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3353 for (i = 0; i < num_eps; i++) {
3354 struct xhci_ep_ctx *ep_ctx;
3356 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3357 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3358 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3359 EP_GETTING_NO_STREAMS;
3361 xhci_endpoint_copy(xhci, command->in_ctx,
3362 vdev->out_ctx, ep_index);
3363 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3364 &vdev->eps[ep_index]);
3366 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3367 vdev->out_ctx, ctrl_ctx,
3368 changed_ep_bitmask, changed_ep_bitmask);
3369 spin_unlock_irqrestore(&xhci->lock, flags);
3371 /* Issue and wait for the configure endpoint command,
3372 * which must succeed.
3374 ret = xhci_configure_endpoint(xhci, udev, command,
3377 /* xHC rejected the configure endpoint command for some reason, so we
3378 * leave the streams rings intact.
3383 spin_lock_irqsave(&xhci->lock, flags);
3384 for (i = 0; i < num_eps; i++) {
3385 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3386 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3387 vdev->eps[ep_index].stream_info = NULL;
3388 /* FIXME Unset maxPstreams in endpoint context and
3389 * update deq ptr to point to normal string ring.
3391 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3392 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3394 spin_unlock_irqrestore(&xhci->lock, flags);
3400 * Deletes endpoint resources for endpoints that were active before a Reset
3401 * Device command, or a Disable Slot command. The Reset Device command leaves
3402 * the control endpoint intact, whereas the Disable Slot command deletes it.
3404 * Must be called with xhci->lock held.
3406 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3407 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3410 unsigned int num_dropped_eps = 0;
3411 unsigned int drop_flags = 0;
3413 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3414 if (virt_dev->eps[i].ring) {
3415 drop_flags |= 1 << i;
3419 xhci->num_active_eps -= num_dropped_eps;
3420 if (num_dropped_eps)
3421 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3422 "Dropped %u ep ctxs, flags = 0x%x, "
3424 num_dropped_eps, drop_flags,
3425 xhci->num_active_eps);
3429 * This submits a Reset Device Command, which will set the device state to 0,
3430 * set the device address to 0, and disable all the endpoints except the default
3431 * control endpoint. The USB core should come back and call
3432 * xhci_address_device(), and then re-set up the configuration. If this is
3433 * called because of a usb_reset_and_verify_device(), then the old alternate
3434 * settings will be re-installed through the normal bandwidth allocation
3437 * Wait for the Reset Device command to finish. Remove all structures
3438 * associated with the endpoints that were disabled. Clear the input device
3439 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3441 * If the virt_dev to be reset does not exist or does not match the udev,
3442 * it means the device is lost, possibly due to the xHC restore error and
3443 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3444 * re-allocate the device.
3446 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3449 unsigned long flags;
3450 struct xhci_hcd *xhci;
3451 unsigned int slot_id;
3452 struct xhci_virt_device *virt_dev;
3453 struct xhci_command *reset_device_cmd;
3454 int last_freed_endpoint;
3455 struct xhci_slot_ctx *slot_ctx;
3456 int old_active_eps = 0;
3458 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3461 xhci = hcd_to_xhci(hcd);
3462 slot_id = udev->slot_id;
3463 virt_dev = xhci->devs[slot_id];
3465 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3466 "not exist. Re-allocate the device\n", slot_id);
3467 ret = xhci_alloc_dev(hcd, udev);
3474 if (virt_dev->tt_info)
3475 old_active_eps = virt_dev->tt_info->active_eps;
3477 if (virt_dev->udev != udev) {
3478 /* If the virt_dev and the udev does not match, this virt_dev
3479 * may belong to another udev.
3480 * Re-allocate the device.
3482 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3483 "not match the udev. Re-allocate the device\n",
3485 ret = xhci_alloc_dev(hcd, udev);
3492 /* If device is not setup, there is no point in resetting it */
3493 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3494 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3495 SLOT_STATE_DISABLED)
3498 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3499 /* Allocate the command structure that holds the struct completion.
3500 * Assume we're in process context, since the normal device reset
3501 * process has to wait for the device anyway. Storage devices are
3502 * reset as part of error handling, so use GFP_NOIO instead of
3505 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3506 if (!reset_device_cmd) {
3507 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3511 /* Attempt to submit the Reset Device command to the command ring */
3512 spin_lock_irqsave(&xhci->lock, flags);
3514 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3516 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3517 spin_unlock_irqrestore(&xhci->lock, flags);
3518 goto command_cleanup;
3520 xhci_ring_cmd_db(xhci);
3521 spin_unlock_irqrestore(&xhci->lock, flags);
3523 /* Wait for the Reset Device command to finish */
3524 wait_for_completion(reset_device_cmd->completion);
3526 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3527 * unless we tried to reset a slot ID that wasn't enabled,
3528 * or the device wasn't in the addressed or configured state.
3530 ret = reset_device_cmd->status;
3532 case COMP_CMD_ABORT:
3534 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3536 goto command_cleanup;
3537 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3538 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3539 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3541 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3542 xhci_dbg(xhci, "Not freeing device rings.\n");
3543 /* Don't treat this as an error. May change my mind later. */
3545 goto command_cleanup;
3547 xhci_dbg(xhci, "Successful reset device command.\n");
3550 if (xhci_is_vendor_info_code(xhci, ret))
3552 xhci_warn(xhci, "Unknown completion code %u for "
3553 "reset device command.\n", ret);
3555 goto command_cleanup;
3558 /* Free up host controller endpoint resources */
3559 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3560 spin_lock_irqsave(&xhci->lock, flags);
3561 /* Don't delete the default control endpoint resources */
3562 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3563 spin_unlock_irqrestore(&xhci->lock, flags);
3566 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3567 last_freed_endpoint = 1;
3568 for (i = 1; i < 31; ++i) {
3569 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3571 if (ep->ep_state & EP_HAS_STREAMS) {
3572 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3573 xhci_get_endpoint_address(i));
3574 xhci_free_stream_info(xhci, ep->stream_info);
3575 ep->stream_info = NULL;
3576 ep->ep_state &= ~EP_HAS_STREAMS;
3580 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3581 last_freed_endpoint = i;
3583 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3584 xhci_drop_ep_from_interval_table(xhci,
3585 &virt_dev->eps[i].bw_info,
3590 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3592 /* If necessary, update the number of active TTs on this root port */
3593 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3595 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3596 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3600 xhci_free_command(xhci, reset_device_cmd);
3605 * At this point, the struct usb_device is about to go away, the device has
3606 * disconnected, and all traffic has been stopped and the endpoints have been
3607 * disabled. Free any HC data structures associated with that device.
3609 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3611 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3612 struct xhci_virt_device *virt_dev;
3613 unsigned long flags;
3616 struct xhci_command *command;
3618 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3622 #ifndef CONFIG_USB_DEFAULT_PERSIST
3624 * We called pm_runtime_get_noresume when the device was attached.
3625 * Decrement the counter here to allow controller to runtime suspend
3626 * if no devices remain.
3628 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3629 pm_runtime_put_noidle(hcd->self.controller);
3632 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3633 /* If the host is halted due to driver unload, we still need to free the
3636 if (ret <= 0 && ret != -ENODEV) {
3641 virt_dev = xhci->devs[udev->slot_id];
3643 /* Stop any wayward timer functions (which may grab the lock) */
3644 for (i = 0; i < 31; ++i) {
3645 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3646 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3649 spin_lock_irqsave(&xhci->lock, flags);
3650 /* Don't disable the slot if the host controller is dead. */
3651 state = readl(&xhci->op_regs->status);
3652 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3653 (xhci->xhc_state & XHCI_STATE_HALTED) ||
3654 (xhci->xhc_state & XHCI_STATE_REMOVING)) {
3655 xhci_free_virt_device(xhci, udev->slot_id);
3656 spin_unlock_irqrestore(&xhci->lock, flags);
3661 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3663 spin_unlock_irqrestore(&xhci->lock, flags);
3664 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3667 xhci_ring_cmd_db(xhci);
3668 spin_unlock_irqrestore(&xhci->lock, flags);
3671 * Event command completion handler will free any data structures
3672 * associated with the slot. XXX Can free sleep?
3677 * Checks if we have enough host controller resources for the default control
3680 * Must be called with xhci->lock held.
3682 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3684 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3685 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3686 "Not enough ep ctxs: "
3687 "%u active, need to add 1, limit is %u.",
3688 xhci->num_active_eps, xhci->limit_active_eps);
3691 xhci->num_active_eps += 1;
3692 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3693 "Adding 1 ep ctx, %u now active.",
3694 xhci->num_active_eps);
3700 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3701 * timed out, or allocating memory failed. Returns 1 on success.
3703 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3705 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3706 unsigned long flags;
3708 struct xhci_command *command;
3710 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3714 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3715 mutex_lock(&xhci->mutex);
3716 spin_lock_irqsave(&xhci->lock, flags);
3717 command->completion = &xhci->addr_dev;
3718 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3720 spin_unlock_irqrestore(&xhci->lock, flags);
3721 mutex_unlock(&xhci->mutex);
3722 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3726 xhci_ring_cmd_db(xhci);
3727 spin_unlock_irqrestore(&xhci->lock, flags);
3729 wait_for_completion(command->completion);
3730 slot_id = xhci->slot_id;
3731 mutex_unlock(&xhci->mutex);
3733 if (!slot_id || command->status != COMP_SUCCESS) {
3734 xhci_err(xhci, "Error while assigning device slot ID\n");
3735 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3737 readl(&xhci->cap_regs->hcs_params1)));
3742 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3743 spin_lock_irqsave(&xhci->lock, flags);
3744 ret = xhci_reserve_host_control_ep_resources(xhci);
3746 spin_unlock_irqrestore(&xhci->lock, flags);
3747 xhci_warn(xhci, "Not enough host resources, "
3748 "active endpoint contexts = %u\n",
3749 xhci->num_active_eps);
3752 spin_unlock_irqrestore(&xhci->lock, flags);
3754 /* Use GFP_NOIO, since this function can be called from
3755 * xhci_discover_or_reset_device(), which may be called as part of
3756 * mass storage driver error handling.
3758 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3759 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3762 udev->slot_id = slot_id;
3764 #ifndef CONFIG_USB_DEFAULT_PERSIST
3766 * If resetting upon resume, we can't put the controller into runtime
3767 * suspend if there is a device attached.
3769 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3770 pm_runtime_get_noresume(hcd->self.controller);
3775 /* Is this a LS or FS device under a HS hub? */
3776 /* Hub or peripherial? */
3780 /* Disable slot, if we can do it without mem alloc */
3781 spin_lock_irqsave(&xhci->lock, flags);
3782 command->completion = NULL;
3783 command->status = 0;
3784 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3786 xhci_ring_cmd_db(xhci);
3787 spin_unlock_irqrestore(&xhci->lock, flags);
3792 * Issue an Address Device command and optionally send a corresponding
3793 * SetAddress request to the device.
3795 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3796 enum xhci_setup_dev setup)
3798 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3799 unsigned long flags;
3800 struct xhci_virt_device *virt_dev;
3802 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3803 struct xhci_slot_ctx *slot_ctx;
3804 struct xhci_input_control_ctx *ctrl_ctx;
3806 struct xhci_command *command = NULL;
3808 mutex_lock(&xhci->mutex);
3810 if (xhci->xhc_state) { /* dying, removing or halted */
3815 if (!udev->slot_id) {
3816 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3817 "Bad Slot ID %d", udev->slot_id);
3822 virt_dev = xhci->devs[udev->slot_id];
3824 if (WARN_ON(!virt_dev)) {
3826 * In plug/unplug torture test with an NEC controller,
3827 * a zero-dereference was observed once due to virt_dev = 0.
3828 * Print useful debug rather than crash if it is observed again!
3830 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3836 if (setup == SETUP_CONTEXT_ONLY) {
3837 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3838 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3839 SLOT_STATE_DEFAULT) {
3840 xhci_dbg(xhci, "Slot already in default state\n");
3845 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3851 command->in_ctx = virt_dev->in_ctx;
3852 command->completion = &xhci->addr_dev;
3854 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3855 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3857 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3863 * If this is the first Set Address since device plug-in or
3864 * virt_device realloaction after a resume with an xHCI power loss,
3865 * then set up the slot context.
3867 if (!slot_ctx->dev_info)
3868 xhci_setup_addressable_virt_dev(xhci, udev);
3869 /* Otherwise, update the control endpoint ring enqueue pointer. */
3871 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3872 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3873 ctrl_ctx->drop_flags = 0;
3875 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3876 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3877 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3878 le32_to_cpu(slot_ctx->dev_info) >> 27);
3880 spin_lock_irqsave(&xhci->lock, flags);
3881 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3882 udev->slot_id, setup);
3884 spin_unlock_irqrestore(&xhci->lock, flags);
3885 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3886 "FIXME: allocate a command ring segment");
3889 xhci_ring_cmd_db(xhci);
3890 spin_unlock_irqrestore(&xhci->lock, flags);
3892 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3893 wait_for_completion(command->completion);
3895 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3896 * the SetAddress() "recovery interval" required by USB and aborting the
3897 * command on a timeout.
3899 switch (command->status) {
3900 case COMP_CMD_ABORT:
3902 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3905 case COMP_CTX_STATE:
3907 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3908 act, udev->slot_id);
3912 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3916 dev_warn(&udev->dev,
3917 "ERROR: Incompatible device for setup %s command\n", act);
3921 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3922 "Successful setup %s command", act);
3926 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3927 act, command->status);
3928 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3929 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3930 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3936 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3937 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3938 "Op regs DCBAA ptr = %#016llx", temp_64);
3939 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3940 "Slot ID %d dcbaa entry @%p = %#016llx",
3942 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3943 (unsigned long long)
3944 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3945 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3946 "Output Context DMA address = %#08llx",
3947 (unsigned long long)virt_dev->out_ctx->dma);
3948 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3949 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3950 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3951 le32_to_cpu(slot_ctx->dev_info) >> 27);
3952 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3953 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3955 * USB core uses address 1 for the roothubs, so we add one to the
3956 * address given back to us by the HC.
3958 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3959 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3960 le32_to_cpu(slot_ctx->dev_info) >> 27);
3961 /* Zero the input context control for later use */
3962 ctrl_ctx->add_flags = 0;
3963 ctrl_ctx->drop_flags = 0;
3965 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3966 "Internal device address = %d",
3967 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3969 mutex_unlock(&xhci->mutex);
3974 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3976 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3979 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3981 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3985 * Transfer the port index into real index in the HW port status
3986 * registers. Caculate offset between the port's PORTSC register
3987 * and port status base. Divide the number of per port register
3988 * to get the real index. The raw port number bases 1.
3990 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3992 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3993 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3994 __le32 __iomem *addr;
3997 if (hcd->speed < HCD_USB3)
3998 addr = xhci->usb2_ports[port1 - 1];
4000 addr = xhci->usb3_ports[port1 - 1];
4002 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
4007 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4008 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4010 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4011 struct usb_device *udev, u16 max_exit_latency)
4013 struct xhci_virt_device *virt_dev;
4014 struct xhci_command *command;
4015 struct xhci_input_control_ctx *ctrl_ctx;
4016 struct xhci_slot_ctx *slot_ctx;
4017 unsigned long flags;
4020 spin_lock_irqsave(&xhci->lock, flags);
4022 virt_dev = xhci->devs[udev->slot_id];
4025 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4026 * xHC was re-initialized. Exit latency will be set later after
4027 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4030 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4031 spin_unlock_irqrestore(&xhci->lock, flags);
4035 /* Attempt to issue an Evaluate Context command to change the MEL. */
4036 command = xhci->lpm_command;
4037 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4039 spin_unlock_irqrestore(&xhci->lock, flags);
4040 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4045 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4046 spin_unlock_irqrestore(&xhci->lock, flags);
4048 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4049 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4050 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4051 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4052 slot_ctx->dev_state = 0;
4054 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4055 "Set up evaluate context for LPM MEL change.");
4056 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4057 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4059 /* Issue and wait for the evaluate context command. */
4060 ret = xhci_configure_endpoint(xhci, udev, command,
4062 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4063 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4066 spin_lock_irqsave(&xhci->lock, flags);
4067 virt_dev->current_mel = max_exit_latency;
4068 spin_unlock_irqrestore(&xhci->lock, flags);
4075 /* BESL to HIRD Encoding array for USB2 LPM */
4076 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4077 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4079 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4080 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4081 struct usb_device *udev)
4083 int u2del, besl, besl_host;
4084 int besl_device = 0;
4087 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4088 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4090 if (field & USB_BESL_SUPPORT) {
4091 for (besl_host = 0; besl_host < 16; besl_host++) {
4092 if (xhci_besl_encoding[besl_host] >= u2del)
4095 /* Use baseline BESL value as default */
4096 if (field & USB_BESL_BASELINE_VALID)
4097 besl_device = USB_GET_BESL_BASELINE(field);
4098 else if (field & USB_BESL_DEEP_VALID)
4099 besl_device = USB_GET_BESL_DEEP(field);
4104 besl_host = (u2del - 51) / 75 + 1;
4107 besl = besl_host + besl_device;
4114 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4115 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4122 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4124 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4125 l1 = udev->l1_params.timeout / 256;
4127 /* device has preferred BESLD */
4128 if (field & USB_BESL_DEEP_VALID) {
4129 besld = USB_GET_BESL_DEEP(field);
4133 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4136 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4137 struct usb_device *udev, int enable)
4139 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4140 __le32 __iomem **port_array;
4141 __le32 __iomem *pm_addr, *hlpm_addr;
4142 u32 pm_val, hlpm_val, field;
4143 unsigned int port_num;
4144 unsigned long flags;
4145 int hird, exit_latency;
4148 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4152 if (!udev->parent || udev->parent->parent ||
4153 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4156 if (udev->usb2_hw_lpm_capable != 1)
4159 spin_lock_irqsave(&xhci->lock, flags);
4161 port_array = xhci->usb2_ports;
4162 port_num = udev->portnum - 1;
4163 pm_addr = port_array[port_num] + PORTPMSC;
4164 pm_val = readl(pm_addr);
4165 hlpm_addr = port_array[port_num] + PORTHLPMC;
4166 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4168 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4169 enable ? "enable" : "disable", port_num + 1);
4172 /* Host supports BESL timeout instead of HIRD */
4173 if (udev->usb2_hw_lpm_besl_capable) {
4174 /* if device doesn't have a preferred BESL value use a
4175 * default one which works with mixed HIRD and BESL
4176 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4178 if ((field & USB_BESL_SUPPORT) &&
4179 (field & USB_BESL_BASELINE_VALID))
4180 hird = USB_GET_BESL_BASELINE(field);
4182 hird = udev->l1_params.besl;
4184 exit_latency = xhci_besl_encoding[hird];
4185 spin_unlock_irqrestore(&xhci->lock, flags);
4187 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4188 * input context for link powermanagement evaluate
4189 * context commands. It is protected by hcd->bandwidth
4190 * mutex and is shared by all devices. We need to set
4191 * the max ext latency in USB 2 BESL LPM as well, so
4192 * use the same mutex and xhci_change_max_exit_latency()
4194 mutex_lock(hcd->bandwidth_mutex);
4195 ret = xhci_change_max_exit_latency(xhci, udev,
4197 mutex_unlock(hcd->bandwidth_mutex);
4201 spin_lock_irqsave(&xhci->lock, flags);
4203 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4204 writel(hlpm_val, hlpm_addr);
4208 hird = xhci_calculate_hird_besl(xhci, udev);
4211 pm_val &= ~PORT_HIRD_MASK;
4212 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4213 writel(pm_val, pm_addr);
4214 pm_val = readl(pm_addr);
4216 writel(pm_val, pm_addr);
4220 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4221 writel(pm_val, pm_addr);
4224 if (udev->usb2_hw_lpm_besl_capable) {
4225 spin_unlock_irqrestore(&xhci->lock, flags);
4226 mutex_lock(hcd->bandwidth_mutex);
4227 xhci_change_max_exit_latency(xhci, udev, 0);
4228 mutex_unlock(hcd->bandwidth_mutex);
4233 spin_unlock_irqrestore(&xhci->lock, flags);
4237 /* check if a usb2 port supports a given extened capability protocol
4238 * only USB2 ports extended protocol capability values are cached.
4239 * Return 1 if capability is supported
4241 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4242 unsigned capability)
4244 u32 port_offset, port_count;
4247 for (i = 0; i < xhci->num_ext_caps; i++) {
4248 if (xhci->ext_caps[i] & capability) {
4249 /* port offsets starts at 1 */
4250 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4251 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4252 if (port >= port_offset &&
4253 port < port_offset + port_count)
4260 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4262 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4263 int portnum = udev->portnum - 1;
4265 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4269 /* we only support lpm for non-hub device connected to root hub yet */
4270 if (!udev->parent || udev->parent->parent ||
4271 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4274 if (xhci->hw_lpm_support == 1 &&
4275 xhci_check_usb2_port_capability(
4276 xhci, portnum, XHCI_HLC)) {
4277 udev->usb2_hw_lpm_capable = 1;
4278 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4279 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4280 if (xhci_check_usb2_port_capability(xhci, portnum,
4282 udev->usb2_hw_lpm_besl_capable = 1;
4288 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4290 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4291 static unsigned long long xhci_service_interval_to_ns(
4292 struct usb_endpoint_descriptor *desc)
4294 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4297 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4298 enum usb3_link_state state)
4300 unsigned long long sel;
4301 unsigned long long pel;
4302 unsigned int max_sel_pel;
4307 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4308 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4309 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4310 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4314 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4315 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4316 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4320 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4322 return USB3_LPM_DISABLED;
4325 if (sel <= max_sel_pel && pel <= max_sel_pel)
4326 return USB3_LPM_DEVICE_INITIATED;
4328 if (sel > max_sel_pel)
4329 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4330 "due to long SEL %llu ms\n",
4333 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4334 "due to long PEL %llu ms\n",
4336 return USB3_LPM_DISABLED;
4339 /* The U1 timeout should be the maximum of the following values:
4340 * - For control endpoints, U1 system exit latency (SEL) * 3
4341 * - For bulk endpoints, U1 SEL * 5
4342 * - For interrupt endpoints:
4343 * - Notification EPs, U1 SEL * 3
4344 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4345 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4347 static unsigned long long xhci_calculate_intel_u1_timeout(
4348 struct usb_device *udev,
4349 struct usb_endpoint_descriptor *desc)
4351 unsigned long long timeout_ns;
4355 ep_type = usb_endpoint_type(desc);
4357 case USB_ENDPOINT_XFER_CONTROL:
4358 timeout_ns = udev->u1_params.sel * 3;
4360 case USB_ENDPOINT_XFER_BULK:
4361 timeout_ns = udev->u1_params.sel * 5;
4363 case USB_ENDPOINT_XFER_INT:
4364 intr_type = usb_endpoint_interrupt_type(desc);
4365 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4366 timeout_ns = udev->u1_params.sel * 3;
4369 /* Otherwise the calculation is the same as isoc eps */
4370 case USB_ENDPOINT_XFER_ISOC:
4371 timeout_ns = xhci_service_interval_to_ns(desc);
4372 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4373 if (timeout_ns < udev->u1_params.sel * 2)
4374 timeout_ns = udev->u1_params.sel * 2;
4383 /* Returns the hub-encoded U1 timeout value. */
4384 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4385 struct usb_device *udev,
4386 struct usb_endpoint_descriptor *desc)
4388 unsigned long long timeout_ns;
4390 if (xhci->quirks & XHCI_INTEL_HOST)
4391 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4393 timeout_ns = udev->u1_params.sel;
4395 /* The U1 timeout is encoded in 1us intervals.
4396 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4398 if (timeout_ns == USB3_LPM_DISABLED)
4401 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4403 /* If the necessary timeout value is bigger than what we can set in the
4404 * USB 3.0 hub, we have to disable hub-initiated U1.
4406 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4408 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4409 "due to long timeout %llu ms\n", timeout_ns);
4410 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4413 /* The U2 timeout should be the maximum of:
4414 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4415 * - largest bInterval of any active periodic endpoint (to avoid going
4416 * into lower power link states between intervals).
4417 * - the U2 Exit Latency of the device
4419 static unsigned long long xhci_calculate_intel_u2_timeout(
4420 struct usb_device *udev,
4421 struct usb_endpoint_descriptor *desc)
4423 unsigned long long timeout_ns;
4424 unsigned long long u2_del_ns;
4426 timeout_ns = 10 * 1000 * 1000;
4428 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4429 (xhci_service_interval_to_ns(desc) > timeout_ns))
4430 timeout_ns = xhci_service_interval_to_ns(desc);
4432 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4433 if (u2_del_ns > timeout_ns)
4434 timeout_ns = u2_del_ns;
4439 /* Returns the hub-encoded U2 timeout value. */
4440 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4441 struct usb_device *udev,
4442 struct usb_endpoint_descriptor *desc)
4444 unsigned long long timeout_ns;
4446 if (xhci->quirks & XHCI_INTEL_HOST)
4447 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4449 timeout_ns = udev->u2_params.sel;
4451 /* The U2 timeout is encoded in 256us intervals */
4452 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4453 /* If the necessary timeout value is bigger than what we can set in the
4454 * USB 3.0 hub, we have to disable hub-initiated U2.
4456 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4458 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4459 "due to long timeout %llu ms\n", timeout_ns);
4460 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4463 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4464 struct usb_device *udev,
4465 struct usb_endpoint_descriptor *desc,
4466 enum usb3_link_state state,
4469 if (state == USB3_LPM_U1)
4470 return xhci_calculate_u1_timeout(xhci, udev, desc);
4471 else if (state == USB3_LPM_U2)
4472 return xhci_calculate_u2_timeout(xhci, udev, desc);
4474 return USB3_LPM_DISABLED;
4477 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4478 struct usb_device *udev,
4479 struct usb_endpoint_descriptor *desc,
4480 enum usb3_link_state state,
4485 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4486 desc, state, timeout);
4488 /* If we found we can't enable hub-initiated LPM, or
4489 * the U1 or U2 exit latency was too high to allow
4490 * device-initiated LPM as well, just stop searching.
4492 if (alt_timeout == USB3_LPM_DISABLED ||
4493 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4494 *timeout = alt_timeout;
4497 if (alt_timeout > *timeout)
4498 *timeout = alt_timeout;
4502 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4503 struct usb_device *udev,
4504 struct usb_host_interface *alt,
4505 enum usb3_link_state state,
4510 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4511 if (xhci_update_timeout_for_endpoint(xhci, udev,
4512 &alt->endpoint[j].desc, state, timeout))
4519 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4520 enum usb3_link_state state)
4522 struct usb_device *parent;
4523 unsigned int num_hubs;
4525 if (state == USB3_LPM_U2)
4528 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4529 for (parent = udev->parent, num_hubs = 0; parent->parent;
4530 parent = parent->parent)
4536 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4537 " below second-tier hub.\n");
4538 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4539 "to decrease power consumption.\n");
4543 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4544 struct usb_device *udev,
4545 enum usb3_link_state state)
4547 if (xhci->quirks & XHCI_INTEL_HOST)
4548 return xhci_check_intel_tier_policy(udev, state);
4553 /* Returns the U1 or U2 timeout that should be enabled.
4554 * If the tier check or timeout setting functions return with a non-zero exit
4555 * code, that means the timeout value has been finalized and we shouldn't look
4556 * at any more endpoints.
4558 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4559 struct usb_device *udev, enum usb3_link_state state)
4561 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4562 struct usb_host_config *config;
4565 u16 timeout = USB3_LPM_DISABLED;
4567 if (state == USB3_LPM_U1)
4569 else if (state == USB3_LPM_U2)
4572 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4577 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4580 /* Gather some information about the currently installed configuration
4581 * and alternate interface settings.
4583 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4587 config = udev->actconfig;
4591 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4592 struct usb_driver *driver;
4593 struct usb_interface *intf = config->interface[i];
4598 /* Check if any currently bound drivers want hub-initiated LPM
4601 if (intf->dev.driver) {
4602 driver = to_usb_driver(intf->dev.driver);
4603 if (driver && driver->disable_hub_initiated_lpm) {
4604 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4605 "at request of driver %s\n",
4606 state_name, driver->name);
4607 return xhci_get_timeout_no_hub_lpm(udev, state);
4611 /* Not sure how this could happen... */
4612 if (!intf->cur_altsetting)
4615 if (xhci_update_timeout_for_interface(xhci, udev,
4616 intf->cur_altsetting,
4623 static int calculate_max_exit_latency(struct usb_device *udev,
4624 enum usb3_link_state state_changed,
4625 u16 hub_encoded_timeout)
4627 unsigned long long u1_mel_us = 0;
4628 unsigned long long u2_mel_us = 0;
4629 unsigned long long mel_us = 0;
4635 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4636 hub_encoded_timeout == USB3_LPM_DISABLED);
4637 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4638 hub_encoded_timeout == USB3_LPM_DISABLED);
4640 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4641 hub_encoded_timeout != USB3_LPM_DISABLED);
4642 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4643 hub_encoded_timeout != USB3_LPM_DISABLED);
4645 /* If U1 was already enabled and we're not disabling it,
4646 * or we're going to enable U1, account for the U1 max exit latency.
4648 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4650 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4651 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4653 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4655 if (u1_mel_us > u2_mel_us)
4659 /* xHCI host controller max exit latency field is only 16 bits wide. */
4660 if (mel_us > MAX_EXIT) {
4661 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4662 "is too big.\n", mel_us);
4668 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4669 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4670 struct usb_device *udev, enum usb3_link_state state)
4672 struct xhci_hcd *xhci;
4673 u16 hub_encoded_timeout;
4677 xhci = hcd_to_xhci(hcd);
4678 /* The LPM timeout values are pretty host-controller specific, so don't
4679 * enable hub-initiated timeouts unless the vendor has provided
4680 * information about their timeout algorithm.
4682 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4683 !xhci->devs[udev->slot_id])
4684 return USB3_LPM_DISABLED;
4686 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4687 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4689 /* Max Exit Latency is too big, disable LPM. */
4690 hub_encoded_timeout = USB3_LPM_DISABLED;
4694 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4697 return hub_encoded_timeout;
4700 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4701 struct usb_device *udev, enum usb3_link_state state)
4703 struct xhci_hcd *xhci;
4706 xhci = hcd_to_xhci(hcd);
4707 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4708 !xhci->devs[udev->slot_id])
4711 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4712 return xhci_change_max_exit_latency(xhci, udev, mel);
4714 #else /* CONFIG_PM */
4716 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4717 struct usb_device *udev, int enable)
4722 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4727 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4728 struct usb_device *udev, enum usb3_link_state state)
4730 return USB3_LPM_DISABLED;
4733 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4734 struct usb_device *udev, enum usb3_link_state state)
4738 #endif /* CONFIG_PM */
4740 /*-------------------------------------------------------------------------*/
4742 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4743 * internal data structures for the device.
4745 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4746 struct usb_tt *tt, gfp_t mem_flags)
4748 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4749 struct xhci_virt_device *vdev;
4750 struct xhci_command *config_cmd;
4751 struct xhci_input_control_ctx *ctrl_ctx;
4752 struct xhci_slot_ctx *slot_ctx;
4753 unsigned long flags;
4754 unsigned think_time;
4757 /* Ignore root hubs */
4761 vdev = xhci->devs[hdev->slot_id];
4763 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4766 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4768 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4771 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4773 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4775 xhci_free_command(xhci, config_cmd);
4779 spin_lock_irqsave(&xhci->lock, flags);
4780 if (hdev->speed == USB_SPEED_HIGH &&
4781 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4782 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4783 xhci_free_command(xhci, config_cmd);
4784 spin_unlock_irqrestore(&xhci->lock, flags);
4788 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4789 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4790 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4791 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4793 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4794 * but it may be already set to 1 when setup an xHCI virtual
4795 * device, so clear it anyway.
4798 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4799 else if (hdev->speed == USB_SPEED_FULL)
4800 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4802 if (xhci->hci_version > 0x95) {
4803 xhci_dbg(xhci, "xHCI version %x needs hub "
4804 "TT think time and number of ports\n",
4805 (unsigned int) xhci->hci_version);
4806 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4807 /* Set TT think time - convert from ns to FS bit times.
4808 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4809 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4811 * xHCI 1.0: this field shall be 0 if the device is not a
4814 think_time = tt->think_time;
4815 if (think_time != 0)
4816 think_time = (think_time / 666) - 1;
4817 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4818 slot_ctx->tt_info |=
4819 cpu_to_le32(TT_THINK_TIME(think_time));
4821 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4822 "TT think time or number of ports\n",
4823 (unsigned int) xhci->hci_version);
4825 slot_ctx->dev_state = 0;
4826 spin_unlock_irqrestore(&xhci->lock, flags);
4828 xhci_dbg(xhci, "Set up %s for hub device.\n",
4829 (xhci->hci_version > 0x95) ?
4830 "configure endpoint" : "evaluate context");
4831 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4832 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4834 /* Issue and wait for the configure endpoint or
4835 * evaluate context command.
4837 if (xhci->hci_version > 0x95)
4838 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4841 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4844 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4845 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4847 xhci_free_command(xhci, config_cmd);
4851 int xhci_get_frame(struct usb_hcd *hcd)
4853 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4854 /* EHCI mods by the periodic size. Why? */
4855 return readl(&xhci->run_regs->microframe_index) >> 3;
4858 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4860 struct xhci_hcd *xhci;
4861 struct device *dev = hcd->self.controller;
4864 /* Accept arbitrarily long scatter-gather lists */
4865 hcd->self.sg_tablesize = ~0;
4867 /* support to build packet from discontinuous buffers */
4868 hcd->self.no_sg_constraint = 1;
4870 /* XHCI controllers don't stop the ep queue on short packets :| */
4871 hcd->self.no_stop_on_short = 1;
4873 xhci = hcd_to_xhci(hcd);
4875 if (usb_hcd_is_primary_hcd(hcd)) {
4876 xhci->main_hcd = hcd;
4877 /* Mark the first roothub as being USB 2.0.
4878 * The xHCI driver will register the USB 3.0 roothub.
4880 hcd->speed = HCD_USB2;
4881 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4883 * USB 2.0 roothub under xHCI has an integrated TT,
4884 * (rate matching hub) as opposed to having an OHCI/UHCI
4885 * companion controller.
4889 if (xhci->sbrn == 0x31) {
4890 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4891 hcd->speed = HCD_USB31;
4893 /* xHCI private pointer was set in xhci_pci_probe for the second
4894 * registered roothub.
4896 if (xhci->quirks & XHCI_DIS_AUTOSUSPEND)
4897 xhci->shared_hcd->self.root_hub->quirks |=
4898 USB_QUIRK_AUTO_SUSPEND;
4903 mutex_init(&xhci->mutex);
4904 xhci->cap_regs = hcd->regs;
4905 xhci->op_regs = hcd->regs +
4906 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4907 xhci->run_regs = hcd->regs +
4908 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4909 /* Cache read-only capability registers */
4910 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4911 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4912 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4913 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4914 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4915 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4916 if (xhci->hci_version > 0x100)
4917 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4918 xhci_print_registers(xhci);
4920 xhci->quirks |= quirks;
4922 get_quirks(dev, xhci);
4924 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4925 * success event after a short transfer. This quirk will ignore such
4928 if (xhci->hci_version > 0x96)
4929 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4931 /* Make sure the HC is halted. */
4932 retval = xhci_halt(xhci);
4936 xhci_dbg(xhci, "Resetting HCD\n");
4937 /* Reset the internal HC memory state and registers. */
4938 retval = xhci_reset(xhci);
4941 xhci_dbg(xhci, "Reset complete\n");
4943 /* Set dma_mask and coherent_dma_mask to 64-bits,
4944 * if xHC supports 64-bit addressing */
4945 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4946 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4947 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4948 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4951 * This is to avoid error in cases where a 32-bit USB
4952 * controller is used on a 64-bit capable system.
4954 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4957 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4958 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4961 xhci_dbg(xhci, "Calling HCD init\n");
4962 /* Initialize HCD and host controller data structures. */
4963 retval = xhci_init(hcd);
4966 xhci_dbg(xhci, "Called HCD init\n");
4968 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4969 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4973 EXPORT_SYMBOL_GPL(xhci_gen_setup);
4975 static const struct hc_driver xhci_hc_driver = {
4976 .description = "xhci-hcd",
4977 .product_desc = "xHCI Host Controller",
4978 .hcd_priv_size = sizeof(struct xhci_hcd *),
4981 * generic hardware linkage
4984 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4987 * basic lifecycle operations
4989 .reset = NULL, /* set in xhci_init_driver() */
4992 .shutdown = xhci_shutdown,
4995 * managing i/o requests and associated device resources
4997 .urb_enqueue = xhci_urb_enqueue,
4998 .urb_dequeue = xhci_urb_dequeue,
4999 .alloc_dev = xhci_alloc_dev,
5000 .free_dev = xhci_free_dev,
5001 .alloc_streams = xhci_alloc_streams,
5002 .free_streams = xhci_free_streams,
5003 .add_endpoint = xhci_add_endpoint,
5004 .drop_endpoint = xhci_drop_endpoint,
5005 .endpoint_reset = xhci_endpoint_reset,
5006 .check_bandwidth = xhci_check_bandwidth,
5007 .reset_bandwidth = xhci_reset_bandwidth,
5008 .address_device = xhci_address_device,
5009 .enable_device = xhci_enable_device,
5010 .update_hub_device = xhci_update_hub_device,
5011 .reset_device = xhci_discover_or_reset_device,
5014 * scheduling support
5016 .get_frame_number = xhci_get_frame,
5021 .hub_control = xhci_hub_control,
5022 .hub_status_data = xhci_hub_status_data,
5023 .bus_suspend = xhci_bus_suspend,
5024 .bus_resume = xhci_bus_resume,
5027 * call back when device connected and addressed
5029 .update_device = xhci_update_device,
5030 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5031 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5032 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5033 .find_raw_port_number = xhci_find_raw_port_number,
5036 void xhci_init_driver(struct hc_driver *drv,
5037 const struct xhci_driver_overrides *over)
5041 /* Copy the generic table to drv then apply the overrides */
5042 *drv = xhci_hc_driver;
5045 drv->hcd_priv_size += over->extra_priv_size;
5047 drv->reset = over->reset;
5049 drv->start = over->start;
5052 EXPORT_SYMBOL_GPL(xhci_init_driver);
5054 MODULE_DESCRIPTION(DRIVER_DESC);
5055 MODULE_AUTHOR(DRIVER_AUTHOR);
5056 MODULE_LICENSE("GPL");
5058 static int __init xhci_hcd_init(void)
5061 * Check the compiler generated sizes of structures that must be laid
5062 * out in specific ways for hardware access.
5064 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5065 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5066 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5067 /* xhci_device_control has eight fields, and also
5068 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5070 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5071 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5072 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5073 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5074 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5075 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5076 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5085 * If an init function is provided, an exit function must also be provided
5086 * to allow module unload.
5088 static void __exit xhci_hcd_fini(void) { }
5090 module_init(xhci_hcd_init);
5091 module_exit(xhci_hcd_fini);