drivers/usb/host/ohci-q.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 #include <linux/irq.h>
  11 #include <linux/slab.h>
  12
  13 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  14 {
  15         int             last = urb_priv->length - 1;
  16
  17         if (last >= 0) {
  18                 int             i;
  19                 struct td       *td;
  20
  21                 for (i = 0; i <= last; i++) {
  22                         td = urb_priv->td [i];
  23                         if (td)
  24                                 td_free (hc, td);
  25                 }
  26         }
  27
  28         list_del (&urb_priv->pending);
  29         kfree (urb_priv);
  30 }
  31
  32 /*-------------------------------------------------------------------------*/
  33
  34 /*
  35  * URB goes back to driver, and isn't reissued.
  36  * It's completely gone from HC data structures.
  37  * PRECONDITION:  ohci lock held, irqs blocked.
  38  */
  39 static void
  40 finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
  41 __releases(ohci->lock)
  42 __acquires(ohci->lock)
  43 {
  44         // ASSERT (urb->hcpriv != 0);
  45
  46         urb_free_priv (ohci, urb->hcpriv);
  47         urb->hcpriv = NULL;
  48         if (likely(status == -EINPROGRESS))
  49                 status = 0;
  50
  51         switch (usb_pipetype (urb->pipe)) {
  52         case PIPE_ISOCHRONOUS:
  53                 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  54                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
  55                         if (quirk_amdiso(ohci))
  56                                 usb_amd_quirk_pll_enable();
  57                         if (quirk_amdprefetch(ohci))
  58                                 sb800_prefetch(ohci, 0);
  59                 }
  60                 break;
  61         case PIPE_INTERRUPT:
  62                 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  63                 break;
  64         }
  65
  66 #ifdef OHCI_VERBOSE_DEBUG
  67         urb_print(urb, "RET", usb_pipeout (urb->pipe), status);
  68 #endif
  69
  70         /* urb->complete() can reenter this HCD */
  71         usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
  72         spin_unlock (&ohci->lock);
  73         usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
  74         spin_lock (&ohci->lock);
  75
  76         /* stop periodic dma if it's not needed */
  77         if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  78                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  79                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  80                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  81         }
  82 }
  83
  84
  85 /*-------------------------------------------------------------------------*
  86  * ED handling functions
  87  *-------------------------------------------------------------------------*/
  88
  89 /* search for the right schedule branch to use for a periodic ed.
  90  * does some load balancing; returns the branch, or negative errno.
  91  */
  92 static int balance (struct ohci_hcd *ohci, int interval, int load)
  93 {
  94         int     i, branch = -ENOSPC;
  95
  96         /* iso periods can be huge; iso tds specify frame numbers */
  97         if (interval > NUM_INTS)
  98                 interval = NUM_INTS;
  99
 100         /* search for the least loaded schedule branch of that period
 101          * that has enough bandwidth left unreserved.
 102          */
 103         for (i = 0; i < interval ; i++) {
 104                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
 105                         int     j;
 106
 107                         /* usb 1.1 says 90% of one frame */
 108                         for (j = i; j < NUM_INTS; j += interval) {
 109                                 if ((ohci->load [j] + load) > 900)
 110                                         break;
 111                         }
 112                         if (j < NUM_INTS)
 113                                 continue;
 114                         branch = i;
 115                 }
 116         }
 117         return branch;
 118 }
 119
 120 /*-------------------------------------------------------------------------*/
 121
 122 /* both iso and interrupt requests have periods; this routine puts them
 123  * into the schedule tree in the apppropriate place.  most iso devices use
 124  * 1msec periods, but that's not required.
 125  */
 126 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
 127 {
 128         unsigned        i;
 129
 130         ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
 131                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 132                 ed, ed->branch, ed->load, ed->interval);
 133
 134         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 135                 struct ed       **prev = &ohci->periodic [i];
 136                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 137                 struct ed       *here = *prev;
 138
 139                 /* sorting each branch by period (slow before fast)
 140                  * lets us share the faster parts of the tree.
 141                  * (plus maybe: put interrupt eds before iso)
 142                  */
 143                 while (here && ed != here) {
 144                         if (ed->interval > here->interval)
 145                                 break;
 146                         prev = &here->ed_next;
 147                         prev_p = &here->hwNextED;
 148                         here = *prev;
 149                 }
 150                 if (ed != here) {
 151                         ed->ed_next = here;
 152                         if (here)
 153                                 ed->hwNextED = *prev_p;
 154                         wmb ();
 155                         *prev = ed;
 156                         *prev_p = cpu_to_hc32(ohci, ed->dma);
 157                         wmb();
 158                 }
 159                 ohci->load [i] += ed->load;
 160         }
 161         ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
 162 }
 163
 164 /* link an ed into one of the HC chains */
 165
 166 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
 167 {
 168         int     branch;
 169
 170         ed->state = ED_OPER;
 171         ed->ed_prev = NULL;
 172         ed->ed_next = NULL;
 173         ed->hwNextED = 0;
 174         if (quirk_zfmicro(ohci)
 175                         && (ed->type == PIPE_INTERRUPT)
 176                         && !(ohci->eds_scheduled++))
 177                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
 178         wmb ();
 179
 180         /* we care about rm_list when setting CLE/BLE in case the HC was at
 181          * work on some TD when CLE/BLE was turned off, and isn't quiesced
 182          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
 183          *
 184          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
 185          * periodic ones are singly linked (ed_next). that's because the
 186          * periodic schedule encodes a tree like figure 3-5 in the ohci
 187          * spec:  each qh can have several "previous" nodes, and the tree
 188          * doesn't have unused/idle descriptors.
 189          */
 190         switch (ed->type) {
 191         case PIPE_CONTROL:
 192                 if (ohci->ed_controltail == NULL) {
 193                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
 194                         ohci_writel (ohci, ed->dma,
 195                                         &ohci->regs->ed_controlhead);
 196                 } else {
 197                         ohci->ed_controltail->ed_next = ed;
 198                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
 199                                                                 ed->dma);
 200                 }
 201                 ed->ed_prev = ohci->ed_controltail;
 202                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
 203                         wmb();
 204                         ohci->hc_control |= OHCI_CTRL_CLE;
 205                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
 206                         ohci_writel (ohci, ohci->hc_control,
 207                                         &ohci->regs->control);
 208                 }
 209                 ohci->ed_controltail = ed;
 210                 break;
 211
 212         case PIPE_BULK:
 213                 if (ohci->ed_bulktail == NULL) {
 214                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
 215                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
 216                 } else {
 217                         ohci->ed_bulktail->ed_next = ed;
 218                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
 219                                                                 ed->dma);
 220                 }
 221                 ed->ed_prev = ohci->ed_bulktail;
 222                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
 223                         wmb();
 224                         ohci->hc_control |= OHCI_CTRL_BLE;
 225                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
 226                         ohci_writel (ohci, ohci->hc_control,
 227                                         &ohci->regs->control);
 228                 }
 229                 ohci->ed_bulktail = ed;
 230                 break;
 231
 232         // case PIPE_INTERRUPT:
 233         // case PIPE_ISOCHRONOUS:
 234         default:
 235                 branch = balance (ohci, ed->interval, ed->load);
 236                 if (branch < 0) {
 237                         ohci_dbg (ohci,
 238                                 "ERR %d, interval %d msecs, load %d\n",
 239                                 branch, ed->interval, ed->load);
 240                         // FIXME if there are TDs queued, fail them!
 241                         return branch;
 242                 }
 243                 ed->branch = branch;
 244                 periodic_link (ohci, ed);
 245         }
 246
 247         /* the HC may not see the schedule updates yet, but if it does
 248          * then they'll be properly ordered.
 249          */
 250         return 0;
 251 }
 252
 253 /*-------------------------------------------------------------------------*/
 254
 255 /* scan the periodic table to find and unlink this ED */
 256 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
 257 {
 258         int     i;
 259
 260         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 261                 struct ed       *temp;
 262                 struct ed       **prev = &ohci->periodic [i];
 263                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 264
 265                 while (*prev && (temp = *prev) != ed) {
 266                         prev_p = &temp->hwNextED;
 267                         prev = &temp->ed_next;
 268                 }
 269                 if (*prev) {
 270                         *prev_p = ed->hwNextED;
 271                         *prev = ed->ed_next;
 272                 }
 273                 ohci->load [i] -= ed->load;
 274         }
 275         ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
 276
 277         ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
 278                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 279                 ed, ed->branch, ed->load, ed->interval);
 280 }
 281
 282 /* unlink an ed from one of the HC chains.
 283  * just the link to the ed is unlinked.
 284  * the link from the ed still points to another operational ed or 0
 285  * so the HC can eventually finish the processing of the unlinked ed
 286  * (assuming it already started that, which needn't be true).
 287  *
 288  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
 289  * it won't.  ED_SKIP means the HC will finish its current transaction,
 290  * but won't start anything new.  The TD queue may still grow; device
 291  * drivers don't know about this HCD-internal state.
 292  *
 293  * When the HC can't see the ED, something changes ED_UNLINK to one of:
 294  *
 295  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
 296  *    immediately.  HC should be working on them.
 297  *
 298  *  - ED_IDLE:  when there's no TD queue. there's no reason for the HC
 299  *    to care about this ED; safe to disable the endpoint.
 300  *
 301  * When finish_unlinks() runs later, after SOF interrupt, it will often
 302  * complete one or more URB unlinks before making that state change.
 303  */
 304 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
 305 {
 306         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 307         wmb ();
 308         ed->state = ED_UNLINK;
 309
 310         /* To deschedule something from the control or bulk list, just
 311          * clear CLE/BLE and wait.  There's no safe way to scrub out list
 312          * head/current registers until later, and "later" isn't very
 313          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
 314          * the HC is reading the ED queues (while we modify them).
 315          *
 316          * For now, ed_schedule() is "later".  It might be good paranoia
 317          * to scrub those registers in finish_unlinks(), in case of bugs
 318          * that make the HC try to use them.
 319          */
 320         switch (ed->type) {
 321         case PIPE_CONTROL:
 322                 /* remove ED from the HC's list: */
 323                 if (ed->ed_prev == NULL) {
 324                         if (!ed->hwNextED) {
 325                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 326                                 ohci_writel (ohci, ohci->hc_control,
 327                                                 &ohci->regs->control);
 328                                 // a ohci_readl() later syncs CLE with the HC
 329                         } else
 330                                 ohci_writel (ohci,
 331                                         hc32_to_cpup (ohci, &ed->hwNextED),
 332                                         &ohci->regs->ed_controlhead);
 333                 } else {
 334                         ed->ed_prev->ed_next = ed->ed_next;
 335                         ed->ed_prev->hwNextED = ed->hwNextED;
 336                 }
 337                 /* remove ED from the HCD's list: */
 338                 if (ohci->ed_controltail == ed) {
 339                         ohci->ed_controltail = ed->ed_prev;
 340                         if (ohci->ed_controltail)
 341                                 ohci->ed_controltail->ed_next = NULL;
 342                 } else if (ed->ed_next) {
 343                         ed->ed_next->ed_prev = ed->ed_prev;
 344                 }
 345                 break;
 346
 347         case PIPE_BULK:
 348                 /* remove ED from the HC's list: */
 349                 if (ed->ed_prev == NULL) {
 350                         if (!ed->hwNextED) {
 351                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 352                                 ohci_writel (ohci, ohci->hc_control,
 353                                                 &ohci->regs->control);
 354                                 // a ohci_readl() later syncs BLE with the HC
 355                         } else
 356                                 ohci_writel (ohci,
 357                                         hc32_to_cpup (ohci, &ed->hwNextED),
 358                                         &ohci->regs->ed_bulkhead);
 359                 } else {
 360                         ed->ed_prev->ed_next = ed->ed_next;
 361                         ed->ed_prev->hwNextED = ed->hwNextED;
 362                 }
 363                 /* remove ED from the HCD's list: */
 364                 if (ohci->ed_bulktail == ed) {
 365                         ohci->ed_bulktail = ed->ed_prev;
 366                         if (ohci->ed_bulktail)
 367                                 ohci->ed_bulktail->ed_next = NULL;
 368                 } else if (ed->ed_next) {
 369                         ed->ed_next->ed_prev = ed->ed_prev;
 370                 }
 371                 break;
 372
 373         // case PIPE_INTERRUPT:
 374         // case PIPE_ISOCHRONOUS:
 375         default:
 376                 periodic_unlink (ohci, ed);
 377                 break;
 378         }
 379 }
 380
 381
 382 /*-------------------------------------------------------------------------*/
 383
 384 /* get and maybe (re)init an endpoint. init _should_ be done only as part
 385  * of enumeration, usb_set_configuration() or usb_set_interface().
 386  */
 387 static struct ed *ed_get (
 388         struct ohci_hcd         *ohci,
 389         struct usb_host_endpoint *ep,
 390         struct usb_device       *udev,
 391         unsigned int            pipe,
 392         int                     interval
 393 ) {
 394         struct ed               *ed;
 395         unsigned long           flags;
 396
 397         spin_lock_irqsave (&ohci->lock, flags);
 398
 399         if (!(ed = ep->hcpriv)) {
 400                 struct td       *td;
 401                 int             is_out;
 402                 u32             info;
 403
 404                 ed = ed_alloc (ohci, GFP_ATOMIC);
 405                 if (!ed) {
 406                         /* out of memory */
 407                         goto done;
 408                 }
 409
 410                 /* dummy td; end of td list for ed */
 411                 td = td_alloc (ohci, GFP_ATOMIC);
 412                 if (!td) {
 413                         /* out of memory */
 414                         ed_free (ohci, ed);
 415                         ed = NULL;
 416                         goto done;
 417                 }
 418                 ed->dummy = td;
 419                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
 420                 ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
 421                 ed->state = ED_IDLE;
 422
 423                 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
 424
 425                 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
 426                  * succeeds ... otherwise we wouldn't need "pipe".
 427                  */
 428                 info = usb_pipedevice (pipe);
 429                 ed->type = usb_pipetype(pipe);
 430
 431                 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
 432                 info |= usb_endpoint_maxp(&ep->desc) << 16;
 433                 if (udev->speed == USB_SPEED_LOW)
 434                         info |= ED_LOWSPEED;
 435                 /* only control transfers store pids in tds */
 436                 if (ed->type != PIPE_CONTROL) {
 437                         info |= is_out ? ED_OUT : ED_IN;
 438                         if (ed->type != PIPE_BULK) {
 439                                 /* periodic transfers... */
 440                                 if (ed->type == PIPE_ISOCHRONOUS)
 441                                         info |= ED_ISO;
 442                                 else if (interval > 32) /* iso can be bigger */
 443                                         interval = 32;
 444                                 ed->interval = interval;
 445                                 ed->load = usb_calc_bus_time (
 446                                         udev->speed, !is_out,
 447                                         ed->type == PIPE_ISOCHRONOUS,
 448                                         usb_endpoint_maxp(&ep->desc))
 449                                                 / 1000;
 450                         }
 451                 }
 452                 ed->hwINFO = cpu_to_hc32(ohci, info);
 453
 454                 ep->hcpriv = ed;
 455         }
 456
 457 done:
 458         spin_unlock_irqrestore (&ohci->lock, flags);
 459         return ed;
 460 }
 461
 462 /*-------------------------------------------------------------------------*/
 463
 464 /* request unlinking of an endpoint from an operational HC.
 465  * put the ep on the rm_list
 466  * real work is done at the next start frame (SF) hardware interrupt
 467  * caller guarantees HCD is running, so hardware access is safe,
 468  * and that ed->state is ED_OPER
 469  */
 470 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
 471 {
 472         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
 473         ed_deschedule (ohci, ed);
 474
 475         /* rm_list is just singly linked, for simplicity */
 476         ed->ed_next = ohci->ed_rm_list;
 477         ed->ed_prev = NULL;
 478         ohci->ed_rm_list = ed;
 479
 480         /* enable SOF interrupt */
 481         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
 482         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
 483         // flush those writes, and get latest HCCA contents
 484         (void) ohci_readl (ohci, &ohci->regs->control);
 485
 486         /* SF interrupt might get delayed; record the frame counter value that
 487          * indicates when the HC isn't looking at it, so concurrent unlinks
 488          * behave.  frame_no wraps every 2^16 msec, and changes right before
 489          * SF is triggered.
 490          */
 491         ed->tick = ohci_frame_no(ohci) + 1;
 492
 493 }
 494
 495 /*-------------------------------------------------------------------------*
 496  * TD handling functions
 497  *-------------------------------------------------------------------------*/
 498
 499 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 500
 501 static void
 502 td_fill (struct ohci_hcd *ohci, u32 info,
 503         dma_addr_t data, int len,
 504         struct urb *urb, int index)
 505 {
 506         struct td               *td, *td_pt;
 507         struct urb_priv         *urb_priv = urb->hcpriv;
 508         int                     is_iso = info & TD_ISO;
 509         int                     hash;
 510
 511         // ASSERT (index < urb_priv->length);
 512
 513         /* aim for only one interrupt per urb.  mostly applies to control
 514          * and iso; other urbs rarely need more than one TD per urb.
 515          * this way, only final tds (or ones with an error) cause IRQs.
 516          * at least immediately; use DI=6 in case any control request is
 517          * tempted to die part way through.  (and to force the hc to flush
 518          * its donelist soonish, even on unlink paths.)
 519          *
 520          * NOTE: could delay interrupts even for the last TD, and get fewer
 521          * interrupts ... increasing per-urb latency by sharing interrupts.
 522          * Drivers that queue bulk urbs may request that behavior.
 523          */
 524         if (index != (urb_priv->length - 1)
 525                         || (urb->transfer_flags & URB_NO_INTERRUPT))
 526                 info |= TD_DI_SET (6);
 527
 528         /* use this td as the next dummy */
 529         td_pt = urb_priv->td [index];
 530
 531         /* fill the old dummy TD */
 532         td = urb_priv->td [index] = urb_priv->ed->dummy;
 533         urb_priv->ed->dummy = td_pt;
 534
 535         td->ed = urb_priv->ed;
 536         td->next_dl_td = NULL;
 537         td->index = index;
 538         td->urb = urb;
 539         td->data_dma = data;
 540         if (!len)
 541                 data = 0;
 542
 543         td->hwINFO = cpu_to_hc32 (ohci, info);
 544         if (is_iso) {
 545                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
 546                 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
 547                                                 (data & 0x0FFF) | 0xE000);
 548                 td->ed->last_iso = info & 0xffff;
 549         } else {
 550                 td->hwCBP = cpu_to_hc32 (ohci, data);
 551         }
 552         if (data)
 553                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
 554         else
 555                 td->hwBE = 0;
 556         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
 557
 558         /* append to queue */
 559         list_add_tail (&td->td_list, &td->ed->td_list);
 560
 561         /* hash it for later reverse mapping */
 562         hash = TD_HASH_FUNC (td->td_dma);
 563         td->td_hash = ohci->td_hash [hash];
 564         ohci->td_hash [hash] = td;
 565
 566         /* HC might read the TD (or cachelines) right away ... */
 567         wmb ();
 568         td->ed->hwTailP = td->hwNextTD;
 569 }
 570
 571 /*-------------------------------------------------------------------------*/
 572
 573 /* Prepare all TDs of a transfer, and queue them onto the ED.
 574  * Caller guarantees HC is active.
 575  * Usually the ED is already on the schedule, so TDs might be
 576  * processed as soon as they're queued.
 577  */
 578 static void td_submit_urb (
 579         struct ohci_hcd *ohci,
 580         struct urb      *urb
 581 ) {
 582         struct urb_priv *urb_priv = urb->hcpriv;
 583         dma_addr_t      data;
 584         int             data_len = urb->transfer_buffer_length;
 585         int             cnt = 0;
 586         u32             info = 0;
 587         int             is_out = usb_pipeout (urb->pipe);
 588         int             periodic = 0;
 589
 590         /* OHCI handles the bulk/interrupt data toggles itself.  We just
 591          * use the device toggle bits for resetting, and rely on the fact
 592          * that resetting toggle is meaningless if the endpoint is active.
 593          */
 594         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
 595                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
 596                         is_out, 1);
 597                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
 598         }
 599
 600         list_add (&urb_priv->pending, &ohci->pending);
 601
 602         if (data_len)
 603                 data = urb->transfer_dma;
 604         else
 605                 data = 0;
 606
 607         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
 608          * using TD_CC_GET, as well as by seeing them on the done list.
 609          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
 610          */
 611         switch (urb_priv->ed->type) {
 612
 613         /* Bulk and interrupt are identical except for where in the schedule
 614          * their EDs live.
 615          */
 616         case PIPE_INTERRUPT:
 617                 /* ... and periodic urbs have extra accounting */
 618                 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
 619                         && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
 620                 /* FALLTHROUGH */
 621         case PIPE_BULK:
 622                 info = is_out
 623                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
 624                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
 625                 /* TDs _could_ transfer up to 8K each */
 626                 while (data_len > 4096) {
 627                         td_fill (ohci, info, data, 4096, urb, cnt);
 628                         data += 4096;
 629                         data_len -= 4096;
 630                         cnt++;
 631                 }
 632                 /* maybe avoid ED halt on final TD short read */
 633                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
 634                         info |= TD_R;
 635                 td_fill (ohci, info, data, data_len, urb, cnt);
 636                 cnt++;
 637                 if ((urb->transfer_flags & URB_ZERO_PACKET)
 638                                 && cnt < urb_priv->length) {
 639                         td_fill (ohci, info, 0, 0, urb, cnt);
 640                         cnt++;
 641                 }
 642                 /* maybe kickstart bulk list */
 643                 if (urb_priv->ed->type == PIPE_BULK) {
 644                         wmb ();
 645                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
 646                 }
 647                 break;
 648
 649         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
 650          * any DATA phase works normally, and the STATUS ack is special.
 651          */
 652         case PIPE_CONTROL:
 653                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 654                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
 655                 if (data_len > 0) {
 656                         info = TD_CC | TD_R | TD_T_DATA1;
 657                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
 658                         /* NOTE:  mishandles transfers >8K, some >4K */
 659                         td_fill (ohci, info, data, data_len, urb, cnt++);
 660                 }
 661                 info = (is_out || data_len == 0)
 662                         ? TD_CC | TD_DP_IN | TD_T_DATA1
 663                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
 664                 td_fill (ohci, info, data, 0, urb, cnt++);
 665                 /* maybe kickstart control list */
 666                 wmb ();
 667                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
 668                 break;
 669
 670         /* ISO has no retransmit, so no toggle; and it uses special TDs.
 671          * Each TD could handle multiple consecutive frames (interval 1);
 672          * we could often reduce the number of TDs here.
 673          */
 674         case PIPE_ISOCHRONOUS:
 675                 for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
 676                                 cnt++) {
 677                         int     frame = urb->start_frame;
 678
 679                         // FIXME scheduling should handle frame counter
 680                         // roll-around ... exotic case (and OHCI has
 681                         // a 2^16 iso range, vs other HCs max of 2^10)
 682                         frame += cnt * urb->interval;
 683                         frame &= 0xffff;
 684                         td_fill (ohci, TD_CC | TD_ISO | frame,
 685                                 data + urb->iso_frame_desc [cnt].offset,
 686                                 urb->iso_frame_desc [cnt].length, urb, cnt);
 687                 }
 688                 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
 689                         if (quirk_amdiso(ohci))
 690                                 usb_amd_quirk_pll_disable();
 691                         if (quirk_amdprefetch(ohci))
 692                                 sb800_prefetch(ohci, 1);
 693                 }
 694                 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 695                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
 696                 break;
 697         }
 698
 699         /* start periodic dma if needed */
 700         if (periodic) {
 701                 wmb ();
 702                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
 703                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 704         }
 705
 706         // ASSERT (urb_priv->length == cnt);
 707 }
 708
 709 /*-------------------------------------------------------------------------*
 710  * Done List handling functions
 711  *-------------------------------------------------------------------------*/
 712
 713 /* calculate transfer length/status and update the urb */
 714 static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
 715 {
 716         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
 717         int     cc = 0;
 718         int     status = -EINPROGRESS;
 719
 720         list_del (&td->td_list);
 721
 722         /* ISO ... drivers see per-TD length/status */
 723         if (tdINFO & TD_ISO) {
 724                 u16     tdPSW = ohci_hwPSW(ohci, td, 0);
 725                 int     dlen = 0;
 726
 727                 /* NOTE:  assumes FC in tdINFO == 0, and that
 728                  * only the first of 0..MAXPSW psws is used.
 729                  */
 730
 731                 cc = (tdPSW >> 12) & 0xF;
 732                 if (tdINFO & TD_CC)     /* hc didn't touch? */
 733                         return status;
 734
 735                 if (usb_pipeout (urb->pipe))
 736                         dlen = urb->iso_frame_desc [td->index].length;
 737                 else {
 738                         /* short reads are always OK for ISO */
 739                         if (cc == TD_DATAUNDERRUN)
 740                                 cc = TD_CC_NOERROR;
 741                         dlen = tdPSW & 0x3ff;
 742                 }
 743                 urb->actual_length += dlen;
 744                 urb->iso_frame_desc [td->index].actual_length = dlen;
 745                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
 746
 747                 if (cc != TD_CC_NOERROR)
 748                         ohci_vdbg (ohci,
 749                                 "urb %p iso td %p (%d) len %d cc %d\n",
 750                                 urb, td, 1 + td->index, dlen, cc);
 751
 752         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
 753          * except that "setup" bytes aren't counted and "short" transfers
 754          * might not be reported as errors.
 755          */
 756         } else {
 757                 int     type = usb_pipetype (urb->pipe);
 758                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
 759
 760                 cc = TD_CC_GET (tdINFO);
 761
 762                 /* update packet status if needed (short is normally ok) */
 763                 if (cc == TD_DATAUNDERRUN
 764                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
 765                         cc = TD_CC_NOERROR;
 766                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 767                         status = cc_to_error[cc];
 768
 769                 /* count all non-empty packets except control SETUP packet */
 770                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
 771                         if (td->hwCBP == 0)
 772                                 urb->actual_length += tdBE - td->data_dma + 1;
 773                         else
 774                                 urb->actual_length +=
 775                                           hc32_to_cpup (ohci, &td->hwCBP)
 776                                         - td->data_dma;
 777                 }
 778
 779                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 780                         ohci_vdbg (ohci,
 781                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
 782                                 urb, td, 1 + td->index, cc,
 783                                 urb->actual_length,
 784                                 urb->transfer_buffer_length);
 785         }
 786         return status;
 787 }
 788
 789 /*-------------------------------------------------------------------------*/
 790
 791 static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
 792 {
 793         struct urb              *urb = td->urb;
 794         urb_priv_t              *urb_priv = urb->hcpriv;
 795         struct ed               *ed = td->ed;
 796         struct list_head        *tmp = td->td_list.next;
 797         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
 798
 799         /* clear ed halt; this is the td that caused it, but keep it inactive
 800          * until its urb->complete() has a chance to clean up.
 801          */
 802         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 803         wmb ();
 804         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
 805
 806         /* Get rid of all later tds from this urb.  We don't have
 807          * to be careful: no errors and nothing was transferred.
 808          * Also patch the ed so it looks as if those tds completed normally.
 809          */
 810         while (tmp != &ed->td_list) {
 811                 struct td       *next;
 812
 813                 next = list_entry (tmp, struct td, td_list);
 814                 tmp = next->td_list.next;
 815
 816                 if (next->urb != urb)
 817                         break;
 818
 819                 /* NOTE: if multi-td control DATA segments get supported,
 820                  * this urb had one of them, this td wasn't the last td
 821                  * in that segment (TD_R clear), this ed halted because
 822                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
 823                  * then we need to leave the control STATUS packet queued
 824                  * and clear ED_SKIP.
 825                  */
 826
 827                 list_del(&next->td_list);
 828                 urb_priv->td_cnt++;
 829                 ed->hwHeadP = next->hwNextTD | toggle;
 830         }
 831
 832         /* help for troubleshooting:  report anything that
 833          * looks odd ... that doesn't include protocol stalls
 834          * (or maybe some other things)
 835          */
 836         switch (cc) {
 837         case TD_DATAUNDERRUN:
 838                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
 839                         break;
 840                 /* fallthrough */
 841         case TD_CC_STALL:
 842                 if (usb_pipecontrol (urb->pipe))
 843                         break;
 844                 /* fallthrough */
 845         default:
 846                 ohci_dbg (ohci,
 847                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
 848                         urb, urb->dev->devpath,
 849                         usb_pipeendpoint (urb->pipe),
 850                         usb_pipein (urb->pipe) ? "in" : "out",
 851                         hc32_to_cpu (ohci, td->hwINFO),
 852                         cc, cc_to_error [cc]);
 853         }
 854 }
 855
 856 /* replies to the request have to be on a FIFO basis so
 857  * we unreverse the hc-reversed done-list
 858  */
 859 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
 860 {
 861         u32             td_dma;
 862         struct td       *td_rev = NULL;
 863         struct td       *td = NULL;
 864
 865         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
 866         ohci->hcca->done_head = 0;
 867         wmb();
 868
 869         /* get TD from hc's singly linked list, and
 870          * prepend to ours.  ed->td_list changes later.
 871          */
 872         while (td_dma) {
 873                 int             cc;
 874
 875                 td = dma_to_td (ohci, td_dma);
 876                 if (!td) {
 877                         ohci_err (ohci, "bad entry %8x\n", td_dma);
 878                         break;
 879                 }
 880
 881                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
 882                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
 883
 884                 /* Non-iso endpoints can halt on error; un-halt,
 885                  * and dequeue any other TDs from this urb.
 886                  * No other TD could have caused the halt.
 887                  */
 888                 if (cc != TD_CC_NOERROR
 889                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
 890                         ed_halted(ohci, td, cc);
 891
 892                 td->next_dl_td = td_rev;
 893                 td_rev = td;
 894                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
 895         }
 896         return td_rev;
 897 }
 898
 899 /*-------------------------------------------------------------------------*/
 900
 901 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
 902 static void
 903 finish_unlinks (struct ohci_hcd *ohci, u16 tick)
 904 {
 905         struct ed       *ed, **last;
 906
 907 rescan_all:
 908         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
 909                 struct list_head        *entry, *tmp;
 910                 int                     completed, modified;
 911                 __hc32                  *prev;
 912
 913                 /* only take off EDs that the HC isn't using, accounting for
 914                  * frame counter wraps and EDs with partially retired TDs
 915                  */
 916                 if (likely(ohci->rh_state == OHCI_RH_RUNNING)) {
 917                         if (tick_before (tick, ed->tick)) {
 918 skip_ed:
 919                                 last = &ed->ed_next;
 920                                 continue;
 921                         }
 922
 923                         if (!list_empty (&ed->td_list)) {
 924                                 struct td       *td;
 925                                 u32             head;
 926
 927                                 td = list_entry (ed->td_list.next, struct td,
 928                                                         td_list);
 929                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
 930                                                                 TD_MASK;
 931
 932                                 /* INTR_WDH may need to clean up first */
 933                                 if (td->td_dma != head) {
 934                                         if (ed == ohci->ed_to_check)
 935                                                 ohci->ed_to_check = NULL;
 936                                         else
 937                                                 goto skip_ed;
 938                                 }
 939                         }
 940                 }
 941
 942                 /* reentrancy:  if we drop the schedule lock, someone might
 943                  * have modified this list.  normally it's just prepending
 944                  * entries (which we'd ignore), but paranoia won't hurt.
 945                  */
 946                 *last = ed->ed_next;
 947                 ed->ed_next = NULL;
 948                 modified = 0;
 949
 950                 /* unlink urbs as requested, but rescan the list after
 951                  * we call a completion since it might have unlinked
 952                  * another (earlier) urb
 953                  *
 954                  * When we get here, the HC doesn't see this ed.  But it
 955                  * must not be rescheduled until all completed URBs have
 956                  * been given back to the driver.
 957                  */
 958 rescan_this:
 959                 completed = 0;
 960                 prev = &ed->hwHeadP;
 961                 list_for_each_safe (entry, tmp, &ed->td_list) {
 962                         struct td       *td;
 963                         struct urb      *urb;
 964                         urb_priv_t      *urb_priv;
 965                         __hc32          savebits;
 966                         u32             tdINFO;
 967
 968                         td = list_entry (entry, struct td, td_list);
 969                         urb = td->urb;
 970                         urb_priv = td->urb->hcpriv;
 971
 972                         if (!urb->unlinked) {
 973                                 prev = &td->hwNextTD;
 974                                 continue;
 975                         }
 976
 977                         /* patch pointer hc uses */
 978                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
 979                         *prev = td->hwNextTD | savebits;
 980
 981                         /* If this was unlinked, the TD may not have been
 982                          * retired ... so manually save the data toggle.
 983                          * The controller ignores the value we save for
 984                          * control and ISO endpoints.
 985                          */
 986                         tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
 987                         if ((tdINFO & TD_T) == TD_T_DATA0)
 988                                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
 989                         else if ((tdINFO & TD_T) == TD_T_DATA1)
 990                                 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
 991
 992                         /* HC may have partly processed this TD */
 993                         td_done (ohci, urb, td);
 994                         urb_priv->td_cnt++;
 995
 996                         /* if URB is done, clean up */
 997                         if (urb_priv->td_cnt == urb_priv->length) {
 998                                 modified = completed = 1;
 999                                 finish_urb(ohci, urb, 0);
1000                         }
1001                 }
1002                 if (completed && !list_empty (&ed->td_list))
1003                         goto rescan_this;
1004
1005                 /* ED's now officially unlinked, hc doesn't see */
1006                 ed->state = ED_IDLE;
1007                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
1008                         ohci->eds_scheduled--;
1009                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1010                 ed->hwNextED = 0;
1011                 wmb ();
1012                 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1013
1014                 /* but if there's work queued, reschedule */
1015                 if (!list_empty (&ed->td_list)) {
1016                         if (ohci->rh_state == OHCI_RH_RUNNING)
1017                                 ed_schedule (ohci, ed);
1018                 }
1019
1020                 if (modified)
1021                         goto rescan_all;
1022         }
1023
1024         /* maybe reenable control and bulk lists */
1025         if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
1026                 u32     command = 0, control = 0;
1027
1028                 if (ohci->ed_controltail) {
1029                         command |= OHCI_CLF;
1030                         if (quirk_zfmicro(ohci))
1031                                 mdelay(1);
1032                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1033                                 control |= OHCI_CTRL_CLE;
1034                                 ohci_writel (ohci, 0,
1035                                         &ohci->regs->ed_controlcurrent);
1036                         }
1037                 }
1038                 if (ohci->ed_bulktail) {
1039                         command |= OHCI_BLF;
1040                         if (quirk_zfmicro(ohci))
1041                                 mdelay(1);
1042                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1043                                 control |= OHCI_CTRL_BLE;
1044                                 ohci_writel (ohci, 0,
1045                                         &ohci->regs->ed_bulkcurrent);
1046                         }
1047                 }
1048
1049                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1050                 if (control) {
1051                         ohci->hc_control |= control;
1052                         if (quirk_zfmicro(ohci))
1053                                 mdelay(1);
1054                         ohci_writel (ohci, ohci->hc_control,
1055                                         &ohci->regs->control);
1056                 }
1057                 if (command) {
1058                         if (quirk_zfmicro(ohci))
1059                                 mdelay(1);
1060                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1061                 }
1062         }
1063 }
1064
1065
1066
1067 /*-------------------------------------------------------------------------*/
1068
1069 /*
1070  * Used to take back a TD from the host controller. This would normally be
1071  * called from within dl_done_list, however it may be called directly if the
1072  * HC no longer sees the TD and it has not appeared on the donelist (after
1073  * two frames).  This bug has been observed on ZF Micro systems.
1074  */
1075 static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1076 {
1077         struct urb      *urb = td->urb;
1078         urb_priv_t      *urb_priv = urb->hcpriv;
1079         struct ed       *ed = td->ed;
1080         int             status;
1081
1082         /* update URB's length and status from TD */
1083         status = td_done(ohci, urb, td);
1084         urb_priv->td_cnt++;
1085
1086         /* If all this urb's TDs are done, call complete() */
1087         if (urb_priv->td_cnt == urb_priv->length)
1088                 finish_urb(ohci, urb, status);
1089
1090         /* clean schedule:  unlink EDs that are no longer busy */
1091         if (list_empty(&ed->td_list)) {
1092                 if (ed->state == ED_OPER)
1093                         start_ed_unlink(ohci, ed);
1094
1095         /* ... reenabling halted EDs only after fault cleanup */
1096         } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1097                         == cpu_to_hc32(ohci, ED_SKIP)) {
1098                 td = list_entry(ed->td_list.next, struct td, td_list);
1099                 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1100                         ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1101                         /* ... hc may need waking-up */
1102                         switch (ed->type) {
1103                         case PIPE_CONTROL:
1104                                 ohci_writel(ohci, OHCI_CLF,
1105                                                 &ohci->regs->cmdstatus);
1106                                 break;
1107                         case PIPE_BULK:
1108                                 ohci_writel(ohci, OHCI_BLF,
1109                                                 &ohci->regs->cmdstatus);
1110                                 break;
1111                         }
1112                 }
1113         }
1114 }
1115
1116 /*
1117  * Process normal completions (error or success) and clean the schedules.
1118  *
1119  * This is the main path for handing urbs back to drivers.  The only other
1120  * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1121  * instead of scanning the (re-reversed) donelist as this does.  There's
1122  * an abnormal path too, handling a quirk in some Compaq silicon:  URBs
1123  * with TDs that appear to be orphaned are directly reclaimed.
1124  */
1125 static void
1126 dl_done_list (struct ohci_hcd *ohci)
1127 {
1128         struct td       *td = dl_reverse_done_list (ohci);
1129
1130         while (td) {
1131                 struct td       *td_next = td->next_dl_td;
1132                 struct ed       *ed = td->ed;
1133
1134                 /*
1135                  * Some OHCI controllers (NVIDIA for sure, maybe others)
1136                  * occasionally forget to add TDs to the done queue.  Since
1137                  * TDs for a given endpoint are always processed in order,
1138                  * if we find a TD on the donelist then all of its
1139                  * predecessors must be finished as well.
1140                  */
1141                 for (;;) {
1142                         struct td       *td2;
1143
1144                         td2 = list_first_entry(&ed->td_list, struct td,
1145                                         td_list);
1146                         if (td2 == td)
1147                                 break;
1148                         takeback_td(ohci, td2);
1149                 }
1150
1151                 takeback_td(ohci, td);
1152                 td = td_next;
1153         }
1154 }