drivers/usb/host/ohci-hcd.c

   1 /*
   2  * Open Host Controller Interface (OHCI) driver for USB.
   3  *
   4  * Maintainer: Alan Stern <stern@rowland.harvard.edu>
   5  *
   6  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   7  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
   8  *
   9  * [ Initialisation is based on Linus'  ]
  10  * [ uhci code and gregs ohci fragments ]
  11  * [ (C) Copyright 1999 Linus Torvalds  ]
  12  * [ (C) Copyright 1999 Gregory P. Smith]
  13  *
  14  *
  15  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  16  * interfaces (though some non-x86 Intel chips use it).  It supports
  17  * smarter hardware than UHCI.  A download link for the spec available
  18  * through the http://www.usb.org website.
  19  *
  20  * This file is licenced under the GPL.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/moduleparam.h>
  25 #include <linux/pci.h>
  26 #include <linux/kernel.h>
  27 #include <linux/delay.h>
  28 #include <linux/ioport.h>
  29 #include <linux/sched.h>
  30 #include <linux/slab.h>
  31 #include <linux/errno.h>
  32 #include <linux/init.h>
  33 #include <linux/timer.h>
  34 #include <linux/list.h>
  35 #include <linux/usb.h>
  36 #include <linux/usb/otg.h>
  37 #include <linux/usb/hcd.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/dmapool.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/debugfs.h>
  42
  43 #include <asm/io.h>
  44 #include <asm/irq.h>
  45 #include <asm/unaligned.h>
  46 #include <asm/byteorder.h>
  47
  48
  49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  51
  52 /*-------------------------------------------------------------------------*/
  53
  54 #undef OHCI_VERBOSE_DEBUG       /* not always helpful */
  55
  56 /* For initializing controller (mask in an HCFS mode too) */
  57 #define OHCI_CONTROL_INIT       OHCI_CTRL_CBSR
  58 #define OHCI_INTR_INIT \
  59                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
  60                 | OHCI_INTR_RD | OHCI_INTR_WDH)
  61
  62 #ifdef __hppa__
  63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  64 #define IR_DISABLE
  65 #endif
  66
  67 #ifdef CONFIG_ARCH_OMAP
  68 /* OMAP doesn't support IR (no SMM; not needed) */
  69 #define IR_DISABLE
  70 #endif
  71
  72 /*-------------------------------------------------------------------------*/
  73
  74 static const char       hcd_name [] = "ohci_hcd";
  75
  76 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
  77
  78 #include "ohci.h"
  79 #include "pci-quirks.h"
  80
  81 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
  82 static int ohci_init (struct ohci_hcd *ohci);
  83 static void ohci_stop (struct usb_hcd *hcd);
  84
  85 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
  86 static int ohci_restart (struct ohci_hcd *ohci);
  87 #endif
  88
  89 #ifdef CONFIG_PCI
  90 static void sb800_prefetch(struct ohci_hcd *ohci, int on);
  91 #else
  92 static inline void sb800_prefetch(struct ohci_hcd *ohci, int on)
  93 {
  94         return;
  95 }
  96 #endif
  97
  98
  99 #include "ohci-hub.c"
 100 #include "ohci-dbg.c"
 101 #include "ohci-mem.c"
 102 #include "ohci-q.c"
 103
 104
 105 /*
 106  * On architectures with edge-triggered interrupts we must never return
 107  * IRQ_NONE.
 108  */
 109 #if defined(CONFIG_SA1111)  /* ... or other edge-triggered systems */
 110 #define IRQ_NOTMINE     IRQ_HANDLED
 111 #else
 112 #define IRQ_NOTMINE     IRQ_NONE
 113 #endif
 114
 115
 116 /* Some boards misreport power switching/overcurrent */
 117 static bool distrust_firmware = 1;
 118 module_param (distrust_firmware, bool, 0);
 119 MODULE_PARM_DESC (distrust_firmware,
 120         "true to distrust firmware power/overcurrent setup");
 121
 122 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
 123 static bool no_handshake = 0;
 124 module_param (no_handshake, bool, 0);
 125 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
 126
 127 /*-------------------------------------------------------------------------*/
 128
 129 /*
 130  * queue up an urb for anything except the root hub
 131  */
 132 static int ohci_urb_enqueue (
 133         struct usb_hcd  *hcd,
 134         struct urb      *urb,
 135         gfp_t           mem_flags
 136 ) {
 137         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 138         struct ed       *ed;
 139         urb_priv_t      *urb_priv;
 140         unsigned int    pipe = urb->pipe;
 141         int             i, size = 0;
 142         unsigned long   flags;
 143         int             retval = 0;
 144
 145 #ifdef OHCI_VERBOSE_DEBUG
 146         urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS);
 147 #endif
 148
 149         /* every endpoint has a ed, locate and maybe (re)initialize it */
 150         if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
 151                 return -ENOMEM;
 152
 153         /* for the private part of the URB we need the number of TDs (size) */
 154         switch (ed->type) {
 155                 case PIPE_CONTROL:
 156                         /* td_submit_urb() doesn't yet handle these */
 157                         if (urb->transfer_buffer_length > 4096)
 158                                 return -EMSGSIZE;
 159
 160                         /* 1 TD for setup, 1 for ACK, plus ... */
 161                         size = 2;
 162                         /* FALLTHROUGH */
 163                 // case PIPE_INTERRUPT:
 164                 // case PIPE_BULK:
 165                 default:
 166                         /* one TD for every 4096 Bytes (can be up to 8K) */
 167                         size += urb->transfer_buffer_length / 4096;
 168                         /* ... and for any remaining bytes ... */
 169                         if ((urb->transfer_buffer_length % 4096) != 0)
 170                                 size++;
 171                         /* ... and maybe a zero length packet to wrap it up */
 172                         if (size == 0)
 173                                 size++;
 174                         else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
 175                                 && (urb->transfer_buffer_length
 176                                         % usb_maxpacket (urb->dev, pipe,
 177                                                 usb_pipeout (pipe))) == 0)
 178                                 size++;
 179                         break;
 180                 case PIPE_ISOCHRONOUS: /* number of packets from URB */
 181                         size = urb->number_of_packets;
 182                         break;
 183         }
 184
 185         /* allocate the private part of the URB */
 186         urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
 187                         mem_flags);
 188         if (!urb_priv)
 189                 return -ENOMEM;
 190         INIT_LIST_HEAD (&urb_priv->pending);
 191         urb_priv->length = size;
 192         urb_priv->ed = ed;
 193
 194         /* allocate the TDs (deferring hash chain updates) */
 195         for (i = 0; i < size; i++) {
 196                 urb_priv->td [i] = td_alloc (ohci, mem_flags);
 197                 if (!urb_priv->td [i]) {
 198                         urb_priv->length = i;
 199                         urb_free_priv (ohci, urb_priv);
 200                         return -ENOMEM;
 201                 }
 202         }
 203
 204         spin_lock_irqsave (&ohci->lock, flags);
 205
 206         /* don't submit to a dead HC */
 207         if (!HCD_HW_ACCESSIBLE(hcd)) {
 208                 retval = -ENODEV;
 209                 goto fail;
 210         }
 211         if (ohci->rh_state != OHCI_RH_RUNNING) {
 212                 retval = -ENODEV;
 213                 goto fail;
 214         }
 215         retval = usb_hcd_link_urb_to_ep(hcd, urb);
 216         if (retval)
 217                 goto fail;
 218
 219         /* schedule the ed if needed */
 220         if (ed->state == ED_IDLE) {
 221                 retval = ed_schedule (ohci, ed);
 222                 if (retval < 0) {
 223                         usb_hcd_unlink_urb_from_ep(hcd, urb);
 224                         goto fail;
 225                 }
 226                 if (ed->type == PIPE_ISOCHRONOUS) {
 227                         u16     frame = ohci_frame_no(ohci);
 228
 229                         /* delay a few frames before the first TD */
 230                         frame += max_t (u16, 8, ed->interval);
 231                         frame &= ~(ed->interval - 1);
 232                         frame |= ed->branch;
 233                         urb->start_frame = frame;
 234                         ed->last_iso = frame + ed->interval * (size - 1);
 235                 }
 236         } else if (ed->type == PIPE_ISOCHRONOUS) {
 237                 u16     next = ohci_frame_no(ohci) + 1;
 238                 u16     frame = ed->last_iso + ed->interval;
 239                 u16     length = ed->interval * (size - 1);
 240
 241                 /* Behind the scheduling threshold? */
 242                 if (unlikely(tick_before(frame, next))) {
 243
 244                         /* URB_ISO_ASAP: Round up to the first available slot */
 245                         if (urb->transfer_flags & URB_ISO_ASAP) {
 246                                 frame += (next - frame + ed->interval - 1) &
 247                                                 -ed->interval;
 248
 249                         /*
 250                          * Not ASAP: Use the next slot in the stream,
 251                          * no matter what.
 252                          */
 253                         } else {
 254                                 /*
 255                                  * Some OHCI hardware doesn't handle late TDs
 256                                  * correctly.  After retiring them it proceeds
 257                                  * to the next ED instead of the next TD.
 258                                  * Therefore we have to omit the late TDs
 259                                  * entirely.
 260                                  */
 261                                 urb_priv->td_cnt = DIV_ROUND_UP(
 262                                                 (u16) (next - frame),
 263                                                 ed->interval);
 264                                 if (urb_priv->td_cnt >= urb_priv->length) {
 265                                         ++urb_priv->td_cnt;     /* Mark it */
 266                                         ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
 267                                                         urb, frame, length,
 268                                                         next);
 269                                 }
 270                         }
 271                 }
 272                 urb->start_frame = frame;
 273                 ed->last_iso = frame + length;
 274         }
 275
 276         /* fill the TDs and link them to the ed; and
 277          * enable that part of the schedule, if needed
 278          * and update count of queued periodic urbs
 279          */
 280         urb->hcpriv = urb_priv;
 281         td_submit_urb (ohci, urb);
 282
 283 fail:
 284         if (retval)
 285                 urb_free_priv (ohci, urb_priv);
 286         spin_unlock_irqrestore (&ohci->lock, flags);
 287         return retval;
 288 }
 289
 290 /*
 291  * decouple the URB from the HC queues (TDs, urb_priv).
 292  * reporting is always done
 293  * asynchronously, and we might be dealing with an urb that's
 294  * partially transferred, or an ED with other urbs being unlinked.
 295  */
 296 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 297 {
 298         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 299         unsigned long           flags;
 300         int                     rc;
 301
 302 #ifdef OHCI_VERBOSE_DEBUG
 303         urb_print(urb, "UNLINK", 1, status);
 304 #endif
 305
 306         spin_lock_irqsave (&ohci->lock, flags);
 307         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
 308         if (rc) {
 309                 ;       /* Do nothing */
 310         } else if (ohci->rh_state == OHCI_RH_RUNNING) {
 311                 urb_priv_t  *urb_priv;
 312
 313                 /* Unless an IRQ completed the unlink while it was being
 314                  * handed to us, flag it for unlink and giveback, and force
 315                  * some upcoming INTR_SF to call finish_unlinks()
 316                  */
 317                 urb_priv = urb->hcpriv;
 318                 if (urb_priv) {
 319                         if (urb_priv->ed->state == ED_OPER)
 320                                 start_ed_unlink (ohci, urb_priv->ed);
 321                 }
 322         } else {
 323                 /*
 324                  * with HC dead, we won't respect hc queue pointers
 325                  * any more ... just clean up every urb's memory.
 326                  */
 327                 if (urb->hcpriv)
 328                         finish_urb(ohci, urb, status);
 329         }
 330         spin_unlock_irqrestore (&ohci->lock, flags);
 331         return rc;
 332 }
 333
 334 /*-------------------------------------------------------------------------*/
 335
 336 /* frees config/altsetting state for endpoints,
 337  * including ED memory, dummy TD, and bulk/intr data toggle
 338  */
 339
 340 static void
 341 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
 342 {
 343         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 344         unsigned long           flags;
 345         struct ed               *ed = ep->hcpriv;
 346         unsigned                limit = 1000;
 347
 348         /* ASSERT:  any requests/urbs are being unlinked */
 349         /* ASSERT:  nobody can be submitting urbs for this any more */
 350
 351         if (!ed)
 352                 return;
 353
 354 rescan:
 355         spin_lock_irqsave (&ohci->lock, flags);
 356
 357         if (ohci->rh_state != OHCI_RH_RUNNING) {
 358 sanitize:
 359                 ed->state = ED_IDLE;
 360                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
 361                         ohci->eds_scheduled--;
 362                 finish_unlinks (ohci, 0);
 363         }
 364
 365         switch (ed->state) {
 366         case ED_UNLINK:         /* wait for hw to finish? */
 367                 /* major IRQ delivery trouble loses INTR_SF too... */
 368                 if (limit-- == 0) {
 369                         ohci_warn(ohci, "ED unlink timeout\n");
 370                         if (quirk_zfmicro(ohci)) {
 371                                 ohci_warn(ohci, "Attempting ZF TD recovery\n");
 372                                 ohci->ed_to_check = ed;
 373                                 ohci->zf_delay = 2;
 374                         }
 375                         goto sanitize;
 376                 }
 377                 spin_unlock_irqrestore (&ohci->lock, flags);
 378                 schedule_timeout_uninterruptible(1);
 379                 goto rescan;
 380         case ED_IDLE:           /* fully unlinked */
 381                 if (list_empty (&ed->td_list)) {
 382                         td_free (ohci, ed->dummy);
 383                         ed_free (ohci, ed);
 384                         break;
 385                 }
 386                 /* else FALL THROUGH */
 387         default:
 388                 /* caller was supposed to have unlinked any requests;
 389                  * that's not our job.  can't recover; must leak ed.
 390                  */
 391                 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
 392                         ed, ep->desc.bEndpointAddress, ed->state,
 393                         list_empty (&ed->td_list) ? "" : " (has tds)");
 394                 td_free (ohci, ed->dummy);
 395                 break;
 396         }
 397         ep->hcpriv = NULL;
 398         spin_unlock_irqrestore (&ohci->lock, flags);
 399 }
 400
 401 static int ohci_get_frame (struct usb_hcd *hcd)
 402 {
 403         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 404
 405         return ohci_frame_no(ohci);
 406 }
 407
 408 static void ohci_usb_reset (struct ohci_hcd *ohci)
 409 {
 410         ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
 411         ohci->hc_control &= OHCI_CTRL_RWC;
 412         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 413         ohci->rh_state = OHCI_RH_HALTED;
 414 }
 415
 416 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
 417  * other cases where the next software may expect clean state from the
 418  * "firmware".  this is bus-neutral, unlike shutdown() methods.
 419  */
 420 static void
 421 ohci_shutdown (struct usb_hcd *hcd)
 422 {
 423         struct ohci_hcd *ohci;
 424
 425         ohci = hcd_to_ohci (hcd);
 426         ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
 427
 428         /* Software reset, after which the controller goes into SUSPEND */
 429         ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
 430         ohci_readl(ohci, &ohci->regs->cmdstatus);       /* flush the writes */
 431         udelay(10);
 432
 433         ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
 434 }
 435
 436 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
 437 {
 438         return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
 439                 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
 440                         == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
 441                 && !list_empty(&ed->td_list);
 442 }
 443
 444 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
 445  * an interrupt TD but neglects to add it to the donelist.  On systems with
 446  * this chipset, we need to periodically check the state of the queues to look
 447  * for such "lost" TDs.
 448  */
 449 static void unlink_watchdog_func(unsigned long _ohci)
 450 {
 451         unsigned long   flags;
 452         unsigned        max;
 453         unsigned        seen_count = 0;
 454         unsigned        i;
 455         struct ed       **seen = NULL;
 456         struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
 457
 458         spin_lock_irqsave(&ohci->lock, flags);
 459         max = ohci->eds_scheduled;
 460         if (!max)
 461                 goto done;
 462
 463         if (ohci->ed_to_check)
 464                 goto out;
 465
 466         seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
 467         if (!seen)
 468                 goto out;
 469
 470         for (i = 0; i < NUM_INTS; i++) {
 471                 struct ed       *ed = ohci->periodic[i];
 472
 473                 while (ed) {
 474                         unsigned        temp;
 475
 476                         /* scan this branch of the periodic schedule tree */
 477                         for (temp = 0; temp < seen_count; temp++) {
 478                                 if (seen[temp] == ed) {
 479                                         /* we've checked it and what's after */
 480                                         ed = NULL;
 481                                         break;
 482                                 }
 483                         }
 484                         if (!ed)
 485                                 break;
 486                         seen[seen_count++] = ed;
 487                         if (!check_ed(ohci, ed)) {
 488                                 ed = ed->ed_next;
 489                                 continue;
 490                         }
 491
 492                         /* HC's TD list is empty, but HCD sees at least one
 493                          * TD that's not been sent through the donelist.
 494                          */
 495                         ohci->ed_to_check = ed;
 496                         ohci->zf_delay = 2;
 497
 498                         /* The HC may wait until the next frame to report the
 499                          * TD as done through the donelist and INTR_WDH.  (We
 500                          * just *assume* it's not a multi-TD interrupt URB;
 501                          * those could defer the IRQ more than one frame, using
 502                          * DI...)  Check again after the next INTR_SF.
 503                          */
 504                         ohci_writel(ohci, OHCI_INTR_SF,
 505                                         &ohci->regs->intrstatus);
 506                         ohci_writel(ohci, OHCI_INTR_SF,
 507                                         &ohci->regs->intrenable);
 508
 509                         /* flush those writes */
 510                         (void) ohci_readl(ohci, &ohci->regs->control);
 511
 512                         goto out;
 513                 }
 514         }
 515 out:
 516         kfree(seen);
 517         if (ohci->eds_scheduled)
 518                 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
 519 done:
 520         spin_unlock_irqrestore(&ohci->lock, flags);
 521 }
 522
 523 /*-------------------------------------------------------------------------*
 524  * HC functions
 525  *-------------------------------------------------------------------------*/
 526
 527 /* init memory, and kick BIOS/SMM off */
 528
 529 static int ohci_init (struct ohci_hcd *ohci)
 530 {
 531         int ret;
 532         struct usb_hcd *hcd = ohci_to_hcd(ohci);
 533
 534         if (distrust_firmware)
 535                 ohci->flags |= OHCI_QUIRK_HUB_POWER;
 536
 537         ohci->rh_state = OHCI_RH_HALTED;
 538         ohci->regs = hcd->regs;
 539
 540         /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
 541          * was never needed for most non-PCI systems ... remove the code?
 542          */
 543
 544 #ifndef IR_DISABLE
 545         /* SMM owns the HC?  not for long! */
 546         if (!no_handshake && ohci_readl (ohci,
 547                                         &ohci->regs->control) & OHCI_CTRL_IR) {
 548                 u32 temp;
 549
 550                 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
 551
 552                 /* this timeout is arbitrary.  we make it long, so systems
 553                  * depending on usb keyboards may be usable even if the
 554                  * BIOS/SMM code seems pretty broken.
 555                  */
 556                 temp = 500;     /* arbitrary: five seconds */
 557
 558                 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
 559                 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
 560                 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
 561                         msleep (10);
 562                         if (--temp == 0) {
 563                                 ohci_err (ohci, "USB HC takeover failed!"
 564                                         "  (BIOS/SMM bug)\n");
 565                                 return -EBUSY;
 566                         }
 567                 }
 568                 ohci_usb_reset (ohci);
 569         }
 570 #endif
 571
 572         /* Disable HC interrupts */
 573         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 574
 575         /* flush the writes, and save key bits like RWC */
 576         if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
 577                 ohci->hc_control |= OHCI_CTRL_RWC;
 578
 579         /* Read the number of ports unless overridden */
 580         if (ohci->num_ports == 0)
 581                 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
 582
 583         if (ohci->hcca)
 584                 return 0;
 585
 586         ohci->hcca = dma_alloc_coherent (hcd->self.controller,
 587                         sizeof *ohci->hcca, &ohci->hcca_dma, 0);
 588         if (!ohci->hcca)
 589                 return -ENOMEM;
 590
 591         if ((ret = ohci_mem_init (ohci)) < 0)
 592                 ohci_stop (hcd);
 593         else {
 594                 create_debug_files (ohci);
 595         }
 596
 597         return ret;
 598 }
 599
 600 /*-------------------------------------------------------------------------*/
 601
 602 /* Start an OHCI controller, set the BUS operational
 603  * resets USB and controller
 604  * enable interrupts
 605  */
 606 static int ohci_run (struct ohci_hcd *ohci)
 607 {
 608         u32                     mask, val;
 609         int                     first = ohci->fminterval == 0;
 610         struct usb_hcd          *hcd = ohci_to_hcd(ohci);
 611
 612         ohci->rh_state = OHCI_RH_HALTED;
 613
 614         /* boot firmware should have set this up (5.1.1.3.1) */
 615         if (first) {
 616
 617                 val = ohci_readl (ohci, &ohci->regs->fminterval);
 618                 ohci->fminterval = val & 0x3fff;
 619                 if (ohci->fminterval != FI)
 620                         ohci_dbg (ohci, "fminterval delta %d\n",
 621                                 ohci->fminterval - FI);
 622                 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
 623                 /* also: power/overcurrent flags in roothub.a */
 624         }
 625
 626         /* Reset USB nearly "by the book".  RemoteWakeupConnected has
 627          * to be checked in case boot firmware (BIOS/SMM/...) has set up
 628          * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
 629          * If the bus glue detected wakeup capability then it should
 630          * already be enabled; if so we'll just enable it again.
 631          */
 632         if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
 633                 device_set_wakeup_capable(hcd->self.controller, 1);
 634
 635         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
 636         case OHCI_USB_OPER:
 637                 val = 0;
 638                 break;
 639         case OHCI_USB_SUSPEND:
 640         case OHCI_USB_RESUME:
 641                 ohci->hc_control &= OHCI_CTRL_RWC;
 642                 ohci->hc_control |= OHCI_USB_RESUME;
 643                 val = 10 /* msec wait */;
 644                 break;
 645         // case OHCI_USB_RESET:
 646         default:
 647                 ohci->hc_control &= OHCI_CTRL_RWC;
 648                 ohci->hc_control |= OHCI_USB_RESET;
 649                 val = 50 /* msec wait */;
 650                 break;
 651         }
 652         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 653         // flush the writes
 654         (void) ohci_readl (ohci, &ohci->regs->control);
 655         msleep(val);
 656
 657         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
 658
 659         /* 2msec timelimit here means no irqs/preempt */
 660         spin_lock_irq (&ohci->lock);
 661
 662 retry:
 663         /* HC Reset requires max 10 us delay */
 664         ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
 665         val = 30;       /* ... allow extra time */
 666         while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
 667                 if (--val == 0) {
 668                         spin_unlock_irq (&ohci->lock);
 669                         ohci_err (ohci, "USB HC reset timed out!\n");
 670                         return -1;
 671                 }
 672                 udelay (1);
 673         }
 674
 675         /* now we're in the SUSPEND state ... must go OPERATIONAL
 676          * within 2msec else HC enters RESUME
 677          *
 678          * ... but some hardware won't init fmInterval "by the book"
 679          * (SiS, OPTi ...), so reset again instead.  SiS doesn't need
 680          * this if we write fmInterval after we're OPERATIONAL.
 681          * Unclear about ALi, ServerWorks, and others ... this could
 682          * easily be a longstanding bug in chip init on Linux.
 683          */
 684         if (ohci->flags & OHCI_QUIRK_INITRESET) {
 685                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 686                 // flush those writes
 687                 (void) ohci_readl (ohci, &ohci->regs->control);
 688         }
 689
 690         /* Tell the controller where the control and bulk lists are
 691          * The lists are empty now. */
 692         ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
 693         ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
 694
 695         /* a reset clears this */
 696         ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
 697
 698         periodic_reinit (ohci);
 699
 700         /* some OHCI implementations are finicky about how they init.
 701          * bogus values here mean not even enumeration could work.
 702          */
 703         if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
 704                         || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
 705                 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
 706                         ohci->flags |= OHCI_QUIRK_INITRESET;
 707                         ohci_dbg (ohci, "enabling initreset quirk\n");
 708                         goto retry;
 709                 }
 710                 spin_unlock_irq (&ohci->lock);
 711                 ohci_err (ohci, "init err (%08x %04x)\n",
 712                         ohci_readl (ohci, &ohci->regs->fminterval),
 713                         ohci_readl (ohci, &ohci->regs->periodicstart));
 714                 return -EOVERFLOW;
 715         }
 716
 717         /* use rhsc irqs after khubd is fully initialized */
 718         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 719         hcd->uses_new_polling = 1;
 720
 721         /* start controller operations */
 722         ohci->hc_control &= OHCI_CTRL_RWC;
 723         ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
 724         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 725         ohci->rh_state = OHCI_RH_RUNNING;
 726
 727         /* wake on ConnectStatusChange, matching external hubs */
 728         ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
 729
 730         /* Choose the interrupts we care about now, others later on demand */
 731         mask = OHCI_INTR_INIT;
 732         ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
 733         ohci_writel (ohci, mask, &ohci->regs->intrenable);
 734
 735         /* handle root hub init quirks ... */
 736         val = roothub_a (ohci);
 737         val &= ~(RH_A_PSM | RH_A_OCPM);
 738         if (ohci->flags & OHCI_QUIRK_SUPERIO) {
 739                 /* NSC 87560 and maybe others */
 740                 val |= RH_A_NOCP;
 741                 val &= ~(RH_A_POTPGT | RH_A_NPS);
 742                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 743         } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
 744                         (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
 745                 /* hub power always on; required for AMD-756 and some
 746                  * Mac platforms.  ganged overcurrent reporting, if any.
 747                  */
 748                 val |= RH_A_NPS;
 749                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 750         }
 751         ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
 752         ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
 753                                                 &ohci->regs->roothub.b);
 754         // flush those writes
 755         (void) ohci_readl (ohci, &ohci->regs->control);
 756
 757         ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 758         spin_unlock_irq (&ohci->lock);
 759
 760         // POTPGT delay is bits 24-31, in 2 ms units.
 761         mdelay ((val >> 23) & 0x1fe);
 762
 763         if (quirk_zfmicro(ohci)) {
 764                 /* Create timer to watch for bad queue state on ZF Micro */
 765                 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
 766                                 (unsigned long) ohci);
 767
 768                 ohci->eds_scheduled = 0;
 769                 ohci->ed_to_check = NULL;
 770         }
 771
 772         ohci_dump (ohci, 1);
 773
 774         return 0;
 775 }
 776
 777 /* ohci_setup routine for generic controller initialization */
 778
 779 int ohci_setup(struct usb_hcd *hcd)
 780 {
 781         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 782
 783         ohci_hcd_init(ohci);
 784
 785         return ohci_init(ohci);
 786 }
 787 EXPORT_SYMBOL_GPL(ohci_setup);
 788
 789 /* ohci_start routine for generic controller start of all OHCI bus glue */
 790 static int ohci_start(struct usb_hcd *hcd)
 791 {
 792         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 793         int     ret;
 794
 795         ret = ohci_run(ohci);
 796         if (ret < 0) {
 797                 ohci_err(ohci, "can't start\n");
 798                 ohci_stop(hcd);
 799         }
 800         return ret;
 801 }
 802
 803 /*-------------------------------------------------------------------------*/
 804
 805 /* an interrupt happens */
 806
 807 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
 808 {
 809         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 810         struct ohci_regs __iomem *regs = ohci->regs;
 811         int                     ints;
 812
 813         /* Read interrupt status (and flush pending writes).  We ignore the
 814          * optimization of checking the LSB of hcca->done_head; it doesn't
 815          * work on all systems (edge triggering for OHCI can be a factor).
 816          */
 817         ints = ohci_readl(ohci, &regs->intrstatus);
 818
 819         /* Check for an all 1's result which is a typical consequence
 820          * of dead, unclocked, or unplugged (CardBus...) devices
 821          */
 822         if (ints == ~(u32)0) {
 823                 ohci->rh_state = OHCI_RH_HALTED;
 824                 ohci_dbg (ohci, "device removed!\n");
 825                 usb_hc_died(hcd);
 826                 return IRQ_HANDLED;
 827         }
 828
 829         /* We only care about interrupts that are enabled */
 830         ints &= ohci_readl(ohci, &regs->intrenable);
 831
 832         /* interrupt for some other device? */
 833         if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
 834                 return IRQ_NOTMINE;
 835
 836         if (ints & OHCI_INTR_UE) {
 837                 // e.g. due to PCI Master/Target Abort
 838                 if (quirk_nec(ohci)) {
 839                         /* Workaround for a silicon bug in some NEC chips used
 840                          * in Apple's PowerBooks. Adapted from Darwin code.
 841                          */
 842                         ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
 843
 844                         ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
 845
 846                         schedule_work (&ohci->nec_work);
 847                 } else {
 848                         ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
 849                         ohci->rh_state = OHCI_RH_HALTED;
 850                         usb_hc_died(hcd);
 851                 }
 852
 853                 ohci_dump (ohci, 1);
 854                 ohci_usb_reset (ohci);
 855         }
 856
 857         if (ints & OHCI_INTR_RHSC) {
 858                 ohci_vdbg(ohci, "rhsc\n");
 859                 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 860                 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
 861                                 &regs->intrstatus);
 862
 863                 /* NOTE: Vendors didn't always make the same implementation
 864                  * choices for RHSC.  Many followed the spec; RHSC triggers
 865                  * on an edge, like setting and maybe clearing a port status
 866                  * change bit.  With others it's level-triggered, active
 867                  * until khubd clears all the port status change bits.  We'll
 868                  * always disable it here and rely on polling until khubd
 869                  * re-enables it.
 870                  */
 871                 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
 872                 usb_hcd_poll_rh_status(hcd);
 873         }
 874
 875         /* For connect and disconnect events, we expect the controller
 876          * to turn on RHSC along with RD.  But for remote wakeup events
 877          * this might not happen.
 878          */
 879         else if (ints & OHCI_INTR_RD) {
 880                 ohci_vdbg(ohci, "resume detect\n");
 881                 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
 882                 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 883                 if (ohci->autostop) {
 884                         spin_lock (&ohci->lock);
 885                         ohci_rh_resume (ohci);
 886                         spin_unlock (&ohci->lock);
 887                 } else
 888                         usb_hcd_resume_root_hub(hcd);
 889         }
 890
 891         if (ints & OHCI_INTR_WDH) {
 892                 spin_lock (&ohci->lock);
 893                 dl_done_list (ohci);
 894                 spin_unlock (&ohci->lock);
 895         }
 896
 897         if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
 898                 spin_lock(&ohci->lock);
 899                 if (ohci->ed_to_check) {
 900                         struct ed *ed = ohci->ed_to_check;
 901
 902                         if (check_ed(ohci, ed)) {
 903                                 /* HC thinks the TD list is empty; HCD knows
 904                                  * at least one TD is outstanding
 905                                  */
 906                                 if (--ohci->zf_delay == 0) {
 907                                         struct td *td = list_entry(
 908                                                 ed->td_list.next,
 909                                                 struct td, td_list);
 910                                         ohci_warn(ohci,
 911                                                   "Reclaiming orphan TD %p\n",
 912                                                   td);
 913                                         takeback_td(ohci, td);
 914                                         ohci->ed_to_check = NULL;
 915                                 }
 916                         } else
 917                                 ohci->ed_to_check = NULL;
 918                 }
 919                 spin_unlock(&ohci->lock);
 920         }
 921
 922         /* could track INTR_SO to reduce available PCI/... bandwidth */
 923
 924         /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
 925          * when there's still unlinking to be done (next frame).
 926          */
 927         spin_lock (&ohci->lock);
 928         if (ohci->ed_rm_list)
 929                 finish_unlinks (ohci, ohci_frame_no(ohci));
 930         if ((ints & OHCI_INTR_SF) != 0
 931                         && !ohci->ed_rm_list
 932                         && !ohci->ed_to_check
 933                         && ohci->rh_state == OHCI_RH_RUNNING)
 934                 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
 935         spin_unlock (&ohci->lock);
 936
 937         if (ohci->rh_state == OHCI_RH_RUNNING) {
 938                 ohci_writel (ohci, ints, &regs->intrstatus);
 939                 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
 940                 // flush those writes
 941                 (void) ohci_readl (ohci, &ohci->regs->control);
 942         }
 943
 944         return IRQ_HANDLED;
 945 }
 946
 947 /*-------------------------------------------------------------------------*/
 948
 949 static void ohci_stop (struct usb_hcd *hcd)
 950 {
 951         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 952
 953         ohci_dump (ohci, 1);
 954
 955         if (quirk_nec(ohci))
 956                 flush_work(&ohci->nec_work);
 957
 958         ohci_usb_reset (ohci);
 959         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 960         free_irq(hcd->irq, hcd);
 961         hcd->irq = 0;
 962
 963         if (quirk_zfmicro(ohci))
 964                 del_timer(&ohci->unlink_watchdog);
 965         if (quirk_amdiso(ohci))
 966                 usb_amd_dev_put();
 967
 968         remove_debug_files (ohci);
 969         ohci_mem_cleanup (ohci);
 970         if (ohci->hcca) {
 971                 dma_free_coherent (hcd->self.controller,
 972                                 sizeof *ohci->hcca,
 973                                 ohci->hcca, ohci->hcca_dma);
 974                 ohci->hcca = NULL;
 975                 ohci->hcca_dma = 0;
 976         }
 977 }
 978
 979 /*-------------------------------------------------------------------------*/
 980
 981 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
 982
 983 /* must not be called from interrupt context */
 984 static int ohci_restart (struct ohci_hcd *ohci)
 985 {
 986         int temp;
 987         int i;
 988         struct urb_priv *priv;
 989
 990         spin_lock_irq(&ohci->lock);
 991         ohci->rh_state = OHCI_RH_HALTED;
 992
 993         /* Recycle any "live" eds/tds (and urbs). */
 994         if (!list_empty (&ohci->pending))
 995                 ohci_dbg(ohci, "abort schedule...\n");
 996         list_for_each_entry (priv, &ohci->pending, pending) {
 997                 struct urb      *urb = priv->td[0]->urb;
 998                 struct ed       *ed = priv->ed;
 999
1000                 switch (ed->state) {
1001                 case ED_OPER:
1002                         ed->state = ED_UNLINK;
1003                         ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
1004                         ed_deschedule (ohci, ed);
1005
1006                         ed->ed_next = ohci->ed_rm_list;
1007                         ed->ed_prev = NULL;
1008                         ohci->ed_rm_list = ed;
1009                         /* FALLTHROUGH */
1010                 case ED_UNLINK:
1011                         break;
1012                 default:
1013                         ohci_dbg(ohci, "bogus ed %p state %d\n",
1014                                         ed, ed->state);
1015                 }
1016
1017                 if (!urb->unlinked)
1018                         urb->unlinked = -ESHUTDOWN;
1019         }
1020         finish_unlinks (ohci, 0);
1021         spin_unlock_irq(&ohci->lock);
1022
1023         /* paranoia, in case that didn't work: */
1024
1025         /* empty the interrupt branches */
1026         for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1027         for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1028
1029         /* no EDs to remove */
1030         ohci->ed_rm_list = NULL;
1031
1032         /* empty control and bulk lists */
1033         ohci->ed_controltail = NULL;
1034         ohci->ed_bulktail    = NULL;
1035
1036         if ((temp = ohci_run (ohci)) < 0) {
1037                 ohci_err (ohci, "can't restart, %d\n", temp);
1038                 return temp;
1039         }
1040         ohci_dbg(ohci, "restart complete\n");
1041         return 0;
1042 }
1043
1044 #endif
1045
1046 #ifdef CONFIG_PM
1047
1048 int __maybe_unused ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1049 {
1050         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1051         unsigned long   flags;
1052
1053         /* Disable irq emission and mark HW unaccessible. Use
1054          * the spinlock to properly synchronize with possible pending
1055          * RH suspend or resume activity.
1056          */
1057         spin_lock_irqsave (&ohci->lock, flags);
1058         ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1059         (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1060
1061         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1062         spin_unlock_irqrestore (&ohci->lock, flags);
1063
1064         return 0;
1065 }
1066
1067
1068 int __maybe_unused ohci_resume(struct usb_hcd *hcd, bool hibernated)
1069 {
1070         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
1071         int                     port;
1072         bool                    need_reinit = false;
1073
1074         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1075
1076         /* Make sure resume from hibernation re-enumerates everything */
1077         if (hibernated)
1078                 ohci_usb_reset(ohci);
1079
1080         /* See if the controller is already running or has been reset */
1081         ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1082         if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1083                 need_reinit = true;
1084         } else {
1085                 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1086                 case OHCI_USB_OPER:
1087                 case OHCI_USB_RESET:
1088                         need_reinit = true;
1089                 }
1090         }
1091
1092         /* If needed, reinitialize and suspend the root hub */
1093         if (need_reinit) {
1094                 spin_lock_irq(&ohci->lock);
1095                 ohci_rh_resume(ohci);
1096                 ohci_rh_suspend(ohci, 0);
1097                 spin_unlock_irq(&ohci->lock);
1098         }
1099
1100         /* Normally just turn on port power and enable interrupts */
1101         else {
1102                 ohci_dbg(ohci, "powerup ports\n");
1103                 for (port = 0; port < ohci->num_ports; port++)
1104                         ohci_writel(ohci, RH_PS_PPS,
1105                                         &ohci->regs->roothub.portstatus[port]);
1106
1107                 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1108                 ohci_readl(ohci, &ohci->regs->intrenable);
1109                 msleep(20);
1110         }
1111
1112         usb_hcd_resume_root_hub(hcd);
1113
1114         return 0;
1115 }
1116
1117 #endif
1118 /*-------------------------------------------------------------------------*/
1119
1120 /*
1121  * Generic structure: This gets copied for platform drivers so that
1122  * individual entries can be overridden as needed.
1123  */
1124
1125 static const struct hc_driver ohci_hc_driver = {
1126         .description =          hcd_name,
1127         .product_desc =         "OHCI Host Controller",
1128         .hcd_priv_size =        sizeof(struct ohci_hcd),
1129
1130         /*
1131          * generic hardware linkage
1132         */
1133         .irq =                  ohci_irq,
1134         .flags =                HCD_MEMORY | HCD_USB11,
1135
1136         /*
1137         * basic lifecycle operations
1138         */
1139         .reset =                ohci_setup,
1140         .start =                ohci_start,
1141         .stop =                 ohci_stop,
1142         .shutdown =             ohci_shutdown,
1143
1144         /*
1145          * managing i/o requests and associated device resources
1146         */
1147         .urb_enqueue =          ohci_urb_enqueue,
1148         .urb_dequeue =          ohci_urb_dequeue,
1149         .endpoint_disable =     ohci_endpoint_disable,
1150
1151         /*
1152         * scheduling support
1153         */
1154         .get_frame_number =     ohci_get_frame,
1155
1156         /*
1157         * root hub support
1158         */
1159         .hub_status_data =      ohci_hub_status_data,
1160         .hub_control =          ohci_hub_control,
1161 #ifdef CONFIG_PM
1162         .bus_suspend =          ohci_bus_suspend,
1163         .bus_resume =           ohci_bus_resume,
1164 #endif
1165         .start_port_reset =     ohci_start_port_reset,
1166 };
1167
1168 void ohci_init_driver(struct hc_driver *drv,
1169                 const struct ohci_driver_overrides *over)
1170 {
1171         /* Copy the generic table to drv and then apply the overrides */
1172         *drv = ohci_hc_driver;
1173
1174         if (over) {
1175                 drv->product_desc = over->product_desc;
1176                 drv->hcd_priv_size += over->extra_priv_size;
1177                 if (over->reset)
1178                         drv->reset = over->reset;
1179         }
1180 }
1181 EXPORT_SYMBOL_GPL(ohci_init_driver);
1182
1183 /*-------------------------------------------------------------------------*/
1184
1185 MODULE_AUTHOR (DRIVER_AUTHOR);
1186 MODULE_DESCRIPTION(DRIVER_DESC);
1187 MODULE_LICENSE ("GPL");
1188
1189 #ifdef CONFIG_PCI
1190 #include "ohci-pci.c"
1191 #define PCI_DRIVER              ohci_pci_driver
1192 #endif
1193
1194 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1195 #include "ohci-sa1111.c"
1196 #define SA1111_DRIVER           ohci_hcd_sa1111_driver
1197 #endif
1198
1199 #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX)
1200 #include "ohci-s3c2410.c"
1201 #define S3C2410_PLATFORM_DRIVER ohci_hcd_s3c2410_driver
1202 #endif
1203
1204 #ifdef CONFIG_USB_OHCI_EXYNOS
1205 #include "ohci-exynos.c"
1206 #define EXYNOS_PLATFORM_DRIVER  exynos_ohci_driver
1207 #endif
1208
1209 #ifdef CONFIG_USB_OHCI_HCD_OMAP1
1210 #include "ohci-omap.c"
1211 #define OMAP1_PLATFORM_DRIVER   ohci_hcd_omap_driver
1212 #endif
1213
1214 #ifdef CONFIG_USB_OHCI_HCD_OMAP3
1215 #include "ohci-omap3.c"
1216 #define OMAP3_PLATFORM_DRIVER   ohci_hcd_omap3_driver
1217 #endif
1218
1219 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1220 #include "ohci-pxa27x.c"
1221 #define PLATFORM_DRIVER         ohci_hcd_pxa27x_driver
1222 #endif
1223
1224 #ifdef CONFIG_ARCH_EP93XX
1225 #include "ohci-ep93xx.c"
1226 #define EP93XX_PLATFORM_DRIVER  ohci_hcd_ep93xx_driver
1227 #endif
1228
1229 #ifdef CONFIG_ARCH_AT91
1230 #include "ohci-at91.c"
1231 #define AT91_PLATFORM_DRIVER    ohci_hcd_at91_driver
1232 #endif
1233
1234 #ifdef CONFIG_ARCH_LPC32XX
1235 #include "ohci-nxp.c"
1236 #define NXP_PLATFORM_DRIVER     usb_hcd_nxp_driver
1237 #endif
1238
1239 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1240 #include "ohci-da8xx.c"
1241 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1242 #endif
1243
1244 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1245 #include "ohci-ppc-of.c"
1246 #define OF_PLATFORM_DRIVER      ohci_hcd_ppc_of_driver
1247 #endif
1248
1249 #ifdef CONFIG_PLAT_SPEAR
1250 #include "ohci-spear.c"
1251 #define SPEAR_PLATFORM_DRIVER   spear_ohci_hcd_driver
1252 #endif
1253
1254 #ifdef CONFIG_PPC_PS3
1255 #include "ohci-ps3.c"
1256 #define PS3_SYSTEM_BUS_DRIVER   ps3_ohci_driver
1257 #endif
1258
1259 #ifdef CONFIG_MFD_SM501
1260 #include "ohci-sm501.c"
1261 #define SM501_OHCI_DRIVER       ohci_hcd_sm501_driver
1262 #endif
1263
1264 #ifdef CONFIG_MFD_TC6393XB
1265 #include "ohci-tmio.c"
1266 #define TMIO_OHCI_DRIVER        ohci_hcd_tmio_driver
1267 #endif
1268
1269 #ifdef CONFIG_MACH_JZ4740
1270 #include "ohci-jz4740.c"
1271 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1272 #endif
1273
1274 #ifdef CONFIG_USB_OCTEON_OHCI
1275 #include "ohci-octeon.c"
1276 #define PLATFORM_DRIVER         ohci_octeon_driver
1277 #endif
1278
1279 #ifdef CONFIG_TILE_USB
1280 #include "ohci-tilegx.c"
1281 #define PLATFORM_DRIVER         ohci_hcd_tilegx_driver
1282 #endif
1283
1284 #ifdef CONFIG_USB_OHCI_HCD_RK
1285 #include "ohci-rockchip.c"
1286 #define PLATFORM_DRIVER         ohci_hcd_rk_driver
1287 #endif
1288
1289 static int __init ohci_hcd_mod_init(void)
1290 {
1291         int retval = 0;
1292
1293         if (usb_disabled())
1294                 return -ENODEV;
1295
1296         printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1297         pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1298                 sizeof (struct ed), sizeof (struct td));
1299         set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1300
1301 #ifdef DEBUG
1302         ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1303         if (!ohci_debug_root) {
1304                 retval = -ENOENT;
1305                 goto error_debug;
1306         }
1307 #endif
1308
1309 #ifdef PS3_SYSTEM_BUS_DRIVER
1310         retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1311         if (retval < 0)
1312                 goto error_ps3;
1313 #endif
1314
1315 #ifdef PLATFORM_DRIVER
1316         retval = platform_driver_register(&PLATFORM_DRIVER);
1317         if (retval < 0)
1318                 goto error_platform;
1319 #endif
1320
1321 #ifdef OMAP1_PLATFORM_DRIVER
1322         retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER);
1323         if (retval < 0)
1324                 goto error_omap1_platform;
1325 #endif
1326
1327 #ifdef OMAP3_PLATFORM_DRIVER
1328         retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER);
1329         if (retval < 0)
1330                 goto error_omap3_platform;
1331 #endif
1332
1333 #ifdef OF_PLATFORM_DRIVER
1334         retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1335         if (retval < 0)
1336                 goto error_of_platform;
1337 #endif
1338
1339 #ifdef SA1111_DRIVER
1340         retval = sa1111_driver_register(&SA1111_DRIVER);
1341         if (retval < 0)
1342                 goto error_sa1111;
1343 #endif
1344
1345 #ifdef PCI_DRIVER
1346         retval = pci_register_driver(&PCI_DRIVER);
1347         if (retval < 0)
1348                 goto error_pci;
1349 #endif
1350
1351 #ifdef SM501_OHCI_DRIVER
1352         retval = platform_driver_register(&SM501_OHCI_DRIVER);
1353         if (retval < 0)
1354                 goto error_sm501;
1355 #endif
1356
1357 #ifdef TMIO_OHCI_DRIVER
1358         retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1359         if (retval < 0)
1360                 goto error_tmio;
1361 #endif
1362
1363 #ifdef S3C2410_PLATFORM_DRIVER
1364         retval = platform_driver_register(&S3C2410_PLATFORM_DRIVER);
1365         if (retval < 0)
1366                 goto error_s3c2410;
1367 #endif
1368
1369 #ifdef EXYNOS_PLATFORM_DRIVER
1370         retval = platform_driver_register(&EXYNOS_PLATFORM_DRIVER);
1371         if (retval < 0)
1372                 goto error_exynos;
1373 #endif
1374
1375 #ifdef EP93XX_PLATFORM_DRIVER
1376         retval = platform_driver_register(&EP93XX_PLATFORM_DRIVER);
1377         if (retval < 0)
1378                 goto error_ep93xx;
1379 #endif
1380
1381 #ifdef AT91_PLATFORM_DRIVER
1382         retval = platform_driver_register(&AT91_PLATFORM_DRIVER);
1383         if (retval < 0)
1384                 goto error_at91;
1385 #endif
1386
1387 #ifdef NXP_PLATFORM_DRIVER
1388         retval = platform_driver_register(&NXP_PLATFORM_DRIVER);
1389         if (retval < 0)
1390                 goto error_nxp;
1391 #endif
1392
1393 #ifdef DAVINCI_PLATFORM_DRIVER
1394         retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER);
1395         if (retval < 0)
1396                 goto error_davinci;
1397 #endif
1398
1399 #ifdef SPEAR_PLATFORM_DRIVER
1400         retval = platform_driver_register(&SPEAR_PLATFORM_DRIVER);
1401         if (retval < 0)
1402                 goto error_spear;
1403 #endif
1404
1405         return retval;
1406
1407         /* Error path */
1408 #ifdef SPEAR_PLATFORM_DRIVER
1409         platform_driver_unregister(&SPEAR_PLATFORM_DRIVER);
1410  error_spear:
1411 #endif
1412 #ifdef DAVINCI_PLATFORM_DRIVER
1413         platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1414  error_davinci:
1415 #endif
1416 #ifdef NXP_PLATFORM_DRIVER
1417         platform_driver_unregister(&NXP_PLATFORM_DRIVER);
1418  error_nxp:
1419 #endif
1420 #ifdef AT91_PLATFORM_DRIVER
1421         platform_driver_unregister(&AT91_PLATFORM_DRIVER);
1422  error_at91:
1423 #endif
1424 #ifdef EP93XX_PLATFORM_DRIVER
1425         platform_driver_unregister(&EP93XX_PLATFORM_DRIVER);
1426  error_ep93xx:
1427 #endif
1428 #ifdef EXYNOS_PLATFORM_DRIVER
1429         platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER);
1430  error_exynos:
1431 #endif
1432 #ifdef S3C2410_PLATFORM_DRIVER
1433         platform_driver_unregister(&S3C2410_PLATFORM_DRIVER);
1434  error_s3c2410:
1435 #endif
1436 #ifdef TMIO_OHCI_DRIVER
1437         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1438  error_tmio:
1439 #endif
1440 #ifdef SM501_OHCI_DRIVER
1441         platform_driver_unregister(&SM501_OHCI_DRIVER);
1442  error_sm501:
1443 #endif
1444 #ifdef PCI_DRIVER
1445         pci_unregister_driver(&PCI_DRIVER);
1446  error_pci:
1447 #endif
1448 #ifdef SA1111_DRIVER
1449         sa1111_driver_unregister(&SA1111_DRIVER);
1450  error_sa1111:
1451 #endif
1452 #ifdef OF_PLATFORM_DRIVER
1453         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1454  error_of_platform:
1455 #endif
1456 #ifdef OMAP3_PLATFORM_DRIVER
1457         platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1458  error_omap3_platform:
1459 #endif
1460 #ifdef OMAP1_PLATFORM_DRIVER
1461         platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1462  error_omap1_platform:
1463 #endif
1464 #ifdef PLATFORM_DRIVER
1465         platform_driver_unregister(&PLATFORM_DRIVER);
1466  error_platform:
1467 #endif
1468 #ifdef PS3_SYSTEM_BUS_DRIVER
1469         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1470  error_ps3:
1471 #endif
1472 #ifdef DEBUG
1473         debugfs_remove(ohci_debug_root);
1474         ohci_debug_root = NULL;
1475  error_debug:
1476 #endif
1477
1478         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1479         return retval;
1480 }
1481 module_init(ohci_hcd_mod_init);
1482
1483 static void __exit ohci_hcd_mod_exit(void)
1484 {
1485 #ifdef SPEAR_PLATFORM_DRIVER
1486         platform_driver_unregister(&SPEAR_PLATFORM_DRIVER);
1487 #endif
1488 #ifdef DAVINCI_PLATFORM_DRIVER
1489         platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1490 #endif
1491 #ifdef NXP_PLATFORM_DRIVER
1492         platform_driver_unregister(&NXP_PLATFORM_DRIVER);
1493 #endif
1494 #ifdef AT91_PLATFORM_DRIVER
1495         platform_driver_unregister(&AT91_PLATFORM_DRIVER);
1496 #endif
1497 #ifdef EP93XX_PLATFORM_DRIVER
1498         platform_driver_unregister(&EP93XX_PLATFORM_DRIVER);
1499 #endif
1500 #ifdef EXYNOS_PLATFORM_DRIVER
1501         platform_driver_unregister(&EXYNOS_PLATFORM_DRIVER);
1502 #endif
1503 #ifdef S3C2410_PLATFORM_DRIVER
1504         platform_driver_unregister(&S3C2410_PLATFORM_DRIVER);
1505 #endif
1506 #ifdef TMIO_OHCI_DRIVER
1507         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1508 #endif
1509 #ifdef SM501_OHCI_DRIVER
1510         platform_driver_unregister(&SM501_OHCI_DRIVER);
1511 #endif
1512 #ifdef PCI_DRIVER
1513         pci_unregister_driver(&PCI_DRIVER);
1514 #endif
1515 #ifdef SA1111_DRIVER
1516         sa1111_driver_unregister(&SA1111_DRIVER);
1517 #endif
1518 #ifdef OF_PLATFORM_DRIVER
1519         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1520 #endif
1521 #ifdef OMAP3_PLATFORM_DRIVER
1522         platform_driver_unregister(&OMAP3_PLATFORM_DRIVER);
1523 #endif
1524 #ifdef OMAP1_PLATFORM_DRIVER
1525         platform_driver_unregister(&OMAP1_PLATFORM_DRIVER);
1526 #endif
1527 #ifdef PLATFORM_DRIVER
1528         platform_driver_unregister(&PLATFORM_DRIVER);
1529 #endif
1530 #ifdef PS3_SYSTEM_BUS_DRIVER
1531         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1532 #endif
1533 #ifdef DEBUG
1534         debugfs_remove(ohci_debug_root);
1535 #endif
1536         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1537 }
1538 module_exit(ohci_hcd_mod_exit);
1539