3 #include "usbdev_grf_regs.h"
4 #include "dwc_otg_regs.h"
6 static struct dwc_otg_control_usb *control_usb;
8 #ifdef CONFIG_USB20_OTG
10 static void usb20otg_hw_init(void)
12 #ifndef CONFIG_USB20_HOST
14 control_usb->grf_uoc1_base->CON2 = (0x01<<2)|((0x01<<2)<<16);
16 control_usb->grf_uoc1_base->CON3 = 0x2A|(0x3F<<16);
18 /* usb phy config init
19 * usb phy enter usb mode */
20 control_usb->grf_uoc0_base->CON0 = (0x0300 << 16);
22 /* other haredware init,include:
23 * DRV_VBUS GPIO init */
24 if(gpio_get_value(control_usb->otg_gpios->gpio)){
25 gpio_set_value(control_usb->otg_gpios->gpio, 0);
29 static void usb20otg_phy_suspend(void* pdata, int suspend)
31 struct dwc_otg_platform_data *usbpdata=pdata;
35 control_usb->grf_uoc0_base->CON2 = (0x01<<2)|((0x01<<2)<<16);
37 control_usb->grf_uoc0_base->CON3 = 0x2A|(0x3F<<16);
38 usbpdata->phy_status = 1;
41 control_usb->grf_uoc0_base->CON2 = ((0x01<<2)<<16);
42 usbpdata->phy_status = 0;
46 static void usb20otg_soft_reset(void)
50 static void usb20otg_clock_init(void* pdata)
52 struct dwc_otg_platform_data *usbpdata=pdata;
53 struct clk* ahbclk,*phyclk;
55 ahbclk = devm_clk_get(usbpdata->dev, "hclk_usb0");
57 dev_err(usbpdata->dev, "Failed to get hclk_usb0\n");
61 phyclk = devm_clk_get(usbpdata->dev, "clk_usbphy0");
63 dev_err(usbpdata->dev, "Failed to get clk_usbphy0\n");
67 usbpdata->phyclk = phyclk;
68 usbpdata->ahbclk = ahbclk;
71 static void usb20otg_clock_enable(void* pdata, int enable)
73 struct dwc_otg_platform_data *usbpdata=pdata;
76 clk_prepare_enable(usbpdata->ahbclk);
77 clk_prepare_enable(usbpdata->phyclk);
79 clk_disable_unprepare(usbpdata->ahbclk);
80 clk_disable_unprepare(usbpdata->phyclk);
84 static int usb20otg_get_status(int id)
89 case USB_STATUS_BVABLID:
91 ret = control_usb->grf_soc_status0_rk3188->otg_bvalid;
95 ret = control_usb->grf_soc_status0_rk3188->otg_linestate;
99 ret = control_usb->grf_soc_status0_rk3188->otg_iddig;
102 ret = control_usb->chip_id;
104 case USB_REMOTE_WAKEUP:
105 ret = control_usb->remote_wakeup;
108 ret = control_usb->usb_irq_wakeup;
117 #ifdef CONFIG_RK_USB_UART
118 static void dwc_otg_uart_mode(void* pdata, int enter_usb_uart_mode)
120 if(1 == enter_usb_uart_mode){
122 * note: can't disable otg here! If otg disable, the ID change
123 * interrupt can't be triggered when otg cable connect without
124 * device.At the same time, uart can't be used normally
126 /* bypass dm, enter uart mode */
127 control_usb->grf_uoc0_base->CON0 = (0x0300 | (0x0300 << 16));
128 }else if(0 == enter_usb_uart_mode){
130 control_usb->grf_uoc0_base->CON0 = (0x0300 << 16);
135 static void usb20otg_power_enable(int enable)
137 if(0 == enable){//disable otg_drv power
138 gpio_set_value(control_usb->otg_gpios->gpio, 0);
139 }else if(1 == enable){//enable otg_drv power
140 gpio_set_value(control_usb->otg_gpios->gpio, 1);
144 struct dwc_otg_platform_data usb20otg_pdata_rk3188 = {
149 .hw_init = usb20otg_hw_init,
150 .phy_suspend = usb20otg_phy_suspend,
151 .soft_reset = usb20otg_soft_reset,
152 .clock_init = usb20otg_clock_init,
153 .clock_enable = usb20otg_clock_enable,
154 .get_status = usb20otg_get_status,
155 .power_enable = usb20otg_power_enable,
156 #ifdef CONFIG_RK_USB_UART
157 .dwc_otg_uart_mode = dwc_otg_uart_mode,
159 .bc_detect_cb=usb20otg_battery_charger_detect_cb,
164 #ifdef CONFIG_USB20_HOST
165 static void usb20host_hw_init(void)
167 /* usb phy config init */
169 /* other haredware init,include:
170 * DRV_VBUS GPIO init */
171 if(!gpio_get_value(control_usb->host_gpios->gpio)){
172 gpio_set_value(control_usb->host_gpios->gpio, 1);
176 static void usb20host_phy_suspend(void* pdata, int suspend)
178 struct dwc_otg_platform_data *usbpdata=pdata;
181 // enable soft control
182 control_usb->grf_uoc1_base->CON2 = (0x01<<2)|((0x01<<2)<<16);
184 control_usb->grf_uoc1_base->CON3 = 0x2A|(0x3F<<16);
185 usbpdata->phy_status = 1;
188 control_usb->grf_uoc1_base->CON2 = ((0x01<<2)<<16);
189 usbpdata->phy_status = 0;
193 static void usb20host_soft_reset(void)
197 static void usb20host_clock_init(void* pdata)
199 struct dwc_otg_platform_data *usbpdata=pdata;
200 struct clk* ahbclk,*phyclk;
202 ahbclk = devm_clk_get(usbpdata->dev, "hclk_usb1");
203 if (IS_ERR(ahbclk)) {
204 dev_err(usbpdata->dev, "Failed to get hclk_usb1\n");
208 phyclk = devm_clk_get(usbpdata->dev, "clk_usbphy1");
209 if (IS_ERR(phyclk)) {
210 dev_err(usbpdata->dev, "Failed to get clk_usbphy1\n");
214 usbpdata->phyclk = phyclk;
215 usbpdata->ahbclk = ahbclk;
218 static void usb20host_clock_enable(void* pdata, int enable)
220 struct dwc_otg_platform_data *usbpdata=pdata;
223 clk_prepare_enable(usbpdata->ahbclk);
224 clk_prepare_enable(usbpdata->phyclk);
226 clk_disable_unprepare(usbpdata->ahbclk);
227 clk_disable_unprepare(usbpdata->phyclk);
231 static int usb20host_get_status(int id)
236 case USB_STATUS_BVABLID:
238 ret = control_usb->grf_soc_status0_rk3188->uhost_bvalid;
240 case USB_STATUS_DPDM:
242 ret = control_usb->grf_soc_status0_rk3188->uhost_linestate;
246 ret = control_usb->grf_soc_status0_rk3188->uhost_iddig;
249 ret = control_usb->chip_id;
251 case USB_REMOTE_WAKEUP:
252 ret = control_usb->remote_wakeup;
255 ret = control_usb->usb_irq_wakeup;
264 static void usb20host_power_enable(int enable)
266 if(0 == enable){//disable host_drv power
267 //do not disable power in default
268 }else if(1 == enable){//enable host_drv power
269 gpio_set_value(control_usb->host_gpios->gpio, 1);
273 struct dwc_otg_platform_data usb20host_pdata_rk3188 = {
278 .hw_init = usb20host_hw_init,
279 .phy_suspend = usb20host_phy_suspend,
280 .soft_reset = usb20host_soft_reset,
281 .clock_init = usb20host_clock_init,
282 .clock_enable = usb20host_clock_enable,
283 .get_status = usb20host_get_status,
284 .power_enable = usb20host_power_enable,
288 #ifdef CONFIG_USB_EHCI_RKHSIC
289 static void rk_hsic_hw_init(void)
291 // usb phy config init
292 // hsic phy config init, set hsicphy_txsrtune
293 control_usb->grf_uoc2_base->CON0 = ((0xf<<6)<<16)|(0xf<<6);
295 /* other haredware init
296 * set common_on, in suspend mode, otg/host PLL blocks remain powered
297 * for RK3168 set control_usb->grf_uoc0_base->CON0 = (1<<16)|0;
298 * for Rk3188 set control_usb->grf_uoc1_base->CON0 = (1<<16)|0;
300 control_usb->grf_uoc1_base->CON0 = (1<<16)|0;
302 /* change INCR to INCR16 or INCR8(beats less than 16)
303 * or INCR4(beats less than 8) or SINGLE(beats less than 4)
305 control_usb->grf_uoc3_base->CON0 = 0x00ff00bc;
308 static void rk_hsic_clock_init(void* pdata)
310 /* By default, hsicphy_480m's parent is otg phy 480MHz clk
311 * rk3188 must use host phy 480MHz clk, because if otg bypass
312 * to uart mode, otg phy 480MHz clk will be closed automatically
314 struct rkehci_platform_data *usbpdata=pdata;
315 struct clk *ahbclk, *phyclk480m_hsic, *phyclk12m_hsic, *phyclk_usbphy1;
317 phyclk480m_hsic = devm_clk_get(usbpdata->dev, "hsicphy_480m");
318 if (IS_ERR(phyclk480m_hsic)) {
319 dev_err(usbpdata->dev, "Failed to get hsicphy_480m\n");
323 phyclk12m_hsic = devm_clk_get(usbpdata->dev, "hsicphy_12m");
324 if (IS_ERR(phyclk12m_hsic)) {
325 dev_err(usbpdata->dev, "Failed to get hsicphy_12m\n");
329 phyclk_usbphy1 = devm_clk_get(usbpdata->dev, "hsic_usbphy1");
330 if (IS_ERR(phyclk_usbphy1)) {
331 dev_err(usbpdata->dev, "Failed to get hsic_usbphy1\n");
335 ahbclk = devm_clk_get(usbpdata->dev, "hclk_hsic");
336 if (IS_ERR(ahbclk)) {
337 dev_err(usbpdata->dev, "Failed to get hclk_hsic\n");
341 clk_set_parent(phyclk480m_hsic, phyclk_usbphy1);
343 usbpdata->hclk_hsic = ahbclk;
344 usbpdata->hsic_phy_480m = phyclk480m_hsic;
345 usbpdata->hsic_phy_12m = phyclk12m_hsic;
348 static void rk_hsic_clock_enable(void* pdata, int enable)
350 struct rkehci_platform_data *usbpdata=pdata;
352 if(enable == usbpdata->clk_status)
355 clk_prepare_enable(usbpdata->hclk_hsic);
356 clk_prepare_enable(usbpdata->hsic_phy_480m);
357 clk_prepare_enable(usbpdata->hsic_phy_12m);
358 usbpdata->clk_status = 1;
360 clk_disable_unprepare(usbpdata->hclk_hsic);
361 clk_disable_unprepare(usbpdata->hsic_phy_480m);
362 clk_disable_unprepare(usbpdata->hsic_phy_12m);
363 usbpdata->clk_status = 0;
367 static void rk_hsic_soft_reset(void)
372 struct rkehci_platform_data rkhsic_pdata_rk3188 = {
374 .hsic_phy_12m = NULL,
375 .hsic_phy_480m = NULL,
377 .hw_init = rk_hsic_hw_init,
378 .clock_init = rk_hsic_clock_init,
379 .clock_enable = rk_hsic_clock_enable,
380 .soft_reset = rk_hsic_soft_reset,
384 #define WAKE_LOCK_TIMEOUT (HZ * 10)
386 inline static void do_wakeup(struct work_struct *work)
388 // rk28_send_wakeup_key();
391 /********** handler for bvalid irq **********/
392 static irqreturn_t bvalid_irq_handler(int irq, void *dev_id)
395 control_usb->grf_uoc0_base->CON3 = (1 << 31) | (1 << 15);
397 #ifdef CONFIG_RK_USB_UART
398 /* usb otg dp/dm switch to usb phy */
399 dwc_otg_uart_mode(NULL, PHY_USB_MODE);
402 if(control_usb->usb_irq_wakeup){
403 wake_lock_timeout(&control_usb->usb_wakelock, WAKE_LOCK_TIMEOUT);
404 schedule_delayed_work(&control_usb->usb_det_wakeup_work, HZ/10);
410 /************* register bvalid irq **************/
411 static int otg_irq_detect_init(struct platform_device *pdev)
416 if(control_usb->usb_irq_wakeup){
417 wake_lock_init(&control_usb->usb_wakelock, WAKE_LOCK_SUSPEND, "usb_detect");
418 INIT_DELAYED_WORK(&control_usb->usb_det_wakeup_work, do_wakeup);
421 irq = platform_get_irq_byname(pdev, "otg_bvalid");
423 ret = request_irq(irq, bvalid_irq_handler, 0, "otg_bvalid", NULL);
425 dev_err(&pdev->dev, "request_irq %d failed!\n", irq);
429 /* clear & enable bvalid irq */
430 control_usb->grf_uoc0_base->CON3 = (3 << 30) | (3 << 14);
432 if(control_usb->usb_irq_wakeup){
433 enable_irq_wake(irq);
440 static int usb_grf_ioremap(struct platform_device *pdev)
443 struct resource *res;
444 void *grf_soc_status0;
450 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
452 grf_soc_status0 = devm_ioremap_resource(&pdev->dev, res);
453 if (IS_ERR(grf_soc_status0)){
454 ret = PTR_ERR(grf_soc_status0);
457 control_usb->grf_soc_status0_rk3188 = (pGRF_SOC_STATUS_RK3188)grf_soc_status0;
459 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
461 grf_uoc0_base = devm_ioremap_resource(&pdev->dev, res);
462 if (IS_ERR(grf_uoc0_base)){
463 ret = PTR_ERR(grf_uoc0_base);
466 control_usb->grf_uoc0_base = (pGRF_UOC0_REG)grf_uoc0_base;
468 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
470 grf_uoc1_base = devm_ioremap_resource(&pdev->dev, res);
471 if (IS_ERR(grf_uoc1_base)){
472 ret = PTR_ERR(grf_uoc1_base);
475 control_usb->grf_uoc1_base = (pGRF_UOC1_REG)grf_uoc1_base;
477 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
479 grf_uoc2_base = devm_ioremap_resource(&pdev->dev, res);
480 if (IS_ERR(grf_uoc2_base)){
481 ret = PTR_ERR(grf_uoc2_base);
484 control_usb->grf_uoc2_base = (pGRF_UOC2_REG)grf_uoc2_base;
486 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
488 grf_uoc3_base = devm_ioremap_resource(&pdev->dev, res);
489 if (IS_ERR(grf_uoc3_base)){
490 ret = PTR_ERR(grf_uoc3_base);
493 control_usb->grf_uoc3_base = (pGRF_UOC3_REG)grf_uoc3_base;
500 static const struct of_device_id dwc_otg_control_usb_id_table[] = {
502 .compatible = "rockchip,rk3188-dwc-control-usb",
506 MODULE_DEVICE_TABLE(of, dwc_otg_control_usb_id_table);
509 static int dwc_otg_control_usb_probe(struct platform_device *pdev)
512 struct device_node *np = pdev->dev.of_node;
513 struct clk* hclk_usb_peri;
516 control_usb = devm_kzalloc(&pdev->dev, sizeof(*control_usb),GFP_KERNEL);
519 dev_err(&pdev->dev, "unable to alloc memory for control usb\n");
524 control_usb->chip_id = RK3188_USB_CTLR;
525 control_usb->remote_wakeup = of_property_read_bool(np,
526 "rockchip,remote_wakeup");
527 control_usb->usb_irq_wakeup = of_property_read_bool(np,
528 "rockchip,usb_irq_wakeup");
530 hclk_usb_peri = devm_clk_get(&pdev->dev, "hclk_usb_peri");
531 if (IS_ERR(hclk_usb_peri)) {
532 dev_err(&pdev->dev, "Failed to get hclk_usb_peri\n");
537 control_usb->hclk_usb_peri = hclk_usb_peri;
538 clk_prepare_enable(hclk_usb_peri);
540 ret = usb_grf_ioremap(pdev);
542 dev_err(&pdev->dev, "Failed to ioremap usb grf\n");
547 control_usb->host_gpios = devm_kzalloc(&pdev->dev, sizeof(struct gpio), GFP_KERNEL);
548 if(!control_usb->host_gpios){
549 dev_err(&pdev->dev, "unable to alloc memory for host_gpios\n");
554 gpio = of_get_named_gpio(np, "gpios", 0);
555 if(!gpio_is_valid(gpio)){
556 dev_err(&pdev->dev, "invalid host gpio%d\n", gpio);
561 control_usb->host_gpios->gpio = gpio;
563 err = devm_gpio_request(&pdev->dev, gpio, "host_drv_gpio");
566 "failed to request GPIO%d for host_drv\n",
571 gpio_direction_output(control_usb->host_gpios->gpio, 1);
574 control_usb->otg_gpios = devm_kzalloc(&pdev->dev, sizeof(struct gpio), GFP_KERNEL);
575 if(!control_usb->otg_gpios){
576 dev_err(&pdev->dev, "unable to alloc memory for otg_gpios\n");
581 gpio = of_get_named_gpio(np, "gpios", 1);
582 if(!gpio_is_valid(gpio)){
583 dev_err(&pdev->dev, "invalid otg gpio%d\n", gpio);
587 control_usb->otg_gpios->gpio = gpio;
588 err = devm_gpio_request(&pdev->dev, gpio, "otg_drv_gpio");
591 "failed to request GPIO%d for otg_drv\n",
596 gpio_direction_output(control_usb->otg_gpios->gpio, 0);
598 ret = otg_irq_detect_init(pdev);
605 clk_disable_unprepare(hclk_usb_peri);
610 static int dwc_otg_control_usb_remove(struct platform_device *pdev)
612 clk_disable_unprepare(control_usb->hclk_usb_peri);
616 static struct platform_driver dwc_otg_control_usb_driver = {
617 .probe = dwc_otg_control_usb_probe,
618 .remove = dwc_otg_control_usb_remove,
620 .name = "rk3188-dwc-control-usb",
621 .owner = THIS_MODULE,
622 .of_match_table = of_match_ptr(dwc_otg_control_usb_id_table),
626 static int __init dwc_otg_control_usb_init(void)
628 return platform_driver_register(&dwc_otg_control_usb_driver);
630 subsys_initcall(dwc_otg_control_usb_init);
632 static void __exit dwc_otg_control_usb_exit(void)
634 platform_driver_unregister(&dwc_otg_control_usb_driver);
637 module_exit(dwc_otg_control_usb_exit);
638 MODULE_ALIAS("platform: dwc_control_usb");
639 MODULE_AUTHOR("RockChip Inc.");
640 MODULE_DESCRIPTION("RockChip Control Module USB Driver");
641 MODULE_LICENSE("GPL v2");