drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
   3  * $Revision: #92 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 #include "dwc_otg_hcd.h"
  36 #include "dwc_otg_regs.h"
  37 #include <linux/usb.h>
  38 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
  39 #include <../drivers/usb/core/hcd.h>
  40 #else
  41 #include <linux/usb/hcd.h>
  42 #endif
  43 /** @file
  44  * This file contains the implementation of the HCD Interrupt handlers.
  45  */
  46
  47 /** This function handles interrupts for the HCD. */
  48 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
  49 {
  50         int retval = 0;
  51
  52         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  53         gintsts_data_t gintsts;
  54 #ifdef DEBUG
  55         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
  56 #endif
  57
  58         if (dwc_otg_check_haps_status(core_if) == -1 ) {
  59                 DWC_WARN("HAPS is disconnected");
  60                 return retval;
  61         }
  62
  63         /* Exit from ISR if core is hibernated */
  64         if (core_if->hibernation_suspend == 1) {
  65                 return retval;
  66         }
  67         DWC_SPINLOCK(dwc_otg_hcd->lock);
  68         /* Check if HOST Mode */
  69         if (dwc_otg_is_host_mode(core_if)) {
  70                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
  71                 if (!gintsts.d32) {
  72                         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
  73                         return 0;
  74                 }
  75 #ifdef DEBUG
  76                 /* Don't print debug message in the interrupt handler on SOF */
  77 #ifndef DEBUG_SOF
  78                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  79 #endif
  80                         DWC_DEBUGPL(DBG_HCD, "\n");
  81 #endif
  82
  83 #ifdef DEBUG
  84 #ifndef DEBUG_SOF
  85                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  86 #endif
  87                         DWC_DEBUGPL(DBG_HCD,
  88                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
  89                                     gintsts.d32);
  90 #endif
  91
  92                 if (gintsts.b.sofintr) {
  93                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
  94                 }
  95                 if (gintsts.b.rxstsqlvl) {
  96                         retval |=
  97                             dwc_otg_hcd_handle_rx_status_q_level_intr
  98                             (dwc_otg_hcd);
  99                 }
 100                 if (gintsts.b.nptxfempty) {
 101                         retval |=
 102                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
 103                             (dwc_otg_hcd);
 104                 }
 105                 if (gintsts.b.i2cintr) {
 106                         /** @todo Implement i2cintr handler. */
 107                 }
 108                 if (gintsts.b.portintr) {
 109                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
 110                 }
 111                 if (gintsts.b.hcintr) {
 112                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
 113                 }
 114                 if (gintsts.b.ptxfempty) {
 115                         retval |=
 116                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
 117                             (dwc_otg_hcd);
 118                 }
 119 #ifdef DEBUG
 120 #ifndef DEBUG_SOF
 121                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 122 #endif
 123                 {
 124                         DWC_DEBUGPL(DBG_HCD,
 125                                     "DWC OTG HCD Finished Servicing Interrupts\n");
 126                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
 127                                     DWC_READ_REG32(&global_regs->gintsts));
 128                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
 129                                     DWC_READ_REG32(&global_regs->gintmsk));
 130                 }
 131 #endif
 132
 133 #ifdef DEBUG
 134 #ifndef DEBUG_SOF
 135                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 136 #endif
 137                         DWC_DEBUGPL(DBG_HCD, "\n");
 138 #endif
 139
 140         }
 141         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
 142         return retval;
 143 }
 144
 145 #ifdef DWC_TRACK_MISSED_SOFS
 146 #warning Compiling code to track missed SOFs
 147 #define FRAME_NUM_ARRAY_SIZE 1000
 148 /**
 149  * This function is for debug only.
 150  */
 151 static inline void track_missed_sofs(uint16_t curr_frame_number)
 152 {
 153         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
 154         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
 155         static int frame_num_idx = 0;
 156         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
 157         static int dumped_frame_num_array = 0;
 158
 159         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
 160                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
 161                     curr_frame_number) {
 162                         frame_num_array[frame_num_idx] = curr_frame_number;
 163                         last_frame_num_array[frame_num_idx++] = last_frame_num;
 164                 }
 165         } else if (!dumped_frame_num_array) {
 166                 int i;
 167                 DWC_PRINTF("Frame     Last Frame\n");
 168                 DWC_PRINTF("-----     ----------\n");
 169                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
 170                         DWC_PRINTF("0x%04x    0x%04x\n",
 171                                    frame_num_array[i], last_frame_num_array[i]);
 172                 }
 173                 dumped_frame_num_array = 1;
 174         }
 175         last_frame_num = curr_frame_number;
 176 }
 177 #endif
 178
 179 /**
 180  * Handles the start-of-frame interrupt in host mode. Non-periodic
 181  * transactions may be queued to the DWC_otg controller for the current
 182  * (micro)frame. Periodic transactions may be queued to the controller for the
 183  * next (micro)frame.
 184  */
 185 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
 186 {
 187         hfnum_data_t hfnum;
 188         dwc_list_link_t *qh_entry;
 189         dwc_otg_qh_t *qh;
 190         dwc_otg_transaction_type_e tr_type;
 191         gintsts_data_t gintsts = {.d32 = 0 };
 192
 193         hfnum.d32 =
 194             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
 195
 196 #ifdef DEBUG_SOF
 197         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
 198 #endif
 199         hcd->frame_number = hfnum.b.frnum;
 200
 201 #ifdef DEBUG
 202         hcd->frrem_accum += hfnum.b.frrem;
 203         hcd->frrem_samples++;
 204 #endif
 205
 206 #ifdef DWC_TRACK_MISSED_SOFS
 207         track_missed_sofs(hcd->frame_number);
 208 #endif
 209         /* Determine whether any periodic QHs should be executed. */
 210         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
 211         while (qh_entry != &hcd->periodic_sched_inactive) {
 212                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
 213                 qh_entry = qh_entry->next;
 214                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
 215                         /*
 216                          * Move QH to the ready list to be executed next
 217                          * (micro)frame.
 218                          */
 219                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
 220                                            &qh->qh_list_entry);
 221                 }
 222         }
 223         tr_type = dwc_otg_hcd_select_transactions(hcd);
 224         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 225                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 226         }
 227
 228         /* Clear interrupt */
 229         gintsts.b.sofintr = 1;
 230         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
 231
 232         return 1;
 233 }
 234
 235 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
 236  * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
 237  * memory if the DWC_otg controller is operating in Slave mode. */
 238 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 239 {
 240         host_grxsts_data_t grxsts;
 241         dwc_hc_t *hc = NULL;
 242
 243         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
 244
 245         grxsts.d32 =
 246             DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
 247
 248         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
 249         if (!hc) {
 250                 DWC_ERROR("Unable to get corresponding channel\n");
 251                 return 0;
 252         }
 253
 254         /* Packet Status */
 255         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
 256         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
 257         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
 258                     hc->data_pid_start);
 259         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
 260
 261         switch (grxsts.b.pktsts) {
 262         case DWC_GRXSTS_PKTSTS_IN:
 263                 /* Read the data into the host buffer. */
 264                 if (grxsts.b.bcnt > 0) {
 265                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
 266                                             hc->xfer_buff, grxsts.b.bcnt);
 267
 268                         /* Update the HC fields for the next packet received. */
 269                         hc->xfer_count += grxsts.b.bcnt;
 270                         hc->xfer_buff += grxsts.b.bcnt;
 271                 }
 272
 273         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
 274         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
 275         case DWC_GRXSTS_PKTSTS_CH_HALTED:
 276                 /* Handled in interrupt, just ignore data */
 277                 break;
 278         default:
 279                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
 280                           grxsts.b.pktsts);
 281                 break;
 282         }
 283
 284         return 1;
 285 }
 286
 287 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 288  * data packets may be written to the FIFO for OUT transfers. More requests
 289  * may be written to the non-periodic request queue for IN transfers. This
 290  * interrupt is enabled only in Slave mode. */
 291 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 292 {
 293         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 294         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 295                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
 296         return 1;
 297 }
 298
 299 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 300  * packets may be written to the FIFO for OUT transfers. More requests may be
 301  * written to the periodic request queue for IN transfers. This interrupt is
 302  * enabled only in Slave mode. */
 303 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 304 {
 305         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
 306         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 307                                        DWC_OTG_TRANSACTION_PERIODIC);
 308         return 1;
 309 }
 310
 311 extern inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd);
 312 /** There are multiple conditions that can cause a port interrupt. This function
 313  * determines which interrupt conditions have occurred and handles them
 314  * appropriately. */
 315 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 316 {
 317         int retval = 0;
 318         hprt0_data_t hprt0;
 319         hprt0_data_t hprt0_modify;
 320         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 321         struct usb_bus *bus = hcd_to_bus(hcd);
 322
 323         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 324         hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 325
 326         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
 327          * GINTSTS */
 328
 329         hprt0_modify.b.prtena = 0;
 330         hprt0_modify.b.prtconndet = 0;
 331         hprt0_modify.b.prtenchng = 0;
 332         hprt0_modify.b.prtovrcurrchng = 0;
 333
 334         /* Port Connect Detected
 335          * Set flag and clear if detected */
 336         if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
 337                 // Dont modify port status if we are in hibernation state
 338                 hprt0_modify.b.prtconndet = 1;
 339                 hprt0_modify.b.prtenchng = 1;
 340                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 341                 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 342                 return retval;
 343         }
 344
 345         if (hprt0.b.prtconndet) {
 346                 /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
 347                 if (dwc_otg_hcd->core_if->adp_enable &&
 348                                 dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
 349                         DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
 350                         DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
 351                         dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 352                         /* TODO - check if this is required, as
 353                          * host initialization was already performed
 354                          * after initial ADP probing
 355                          */
 356                         /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 357                         dwc_otg_core_init(dwc_otg_hcd->core_if);
 358                         dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
 359                         cil_hcd_start(dwc_otg_hcd->core_if);*/
 360                 } else {
 361                         hprt0_data_t hprt0_local;
 362                         /* check if root hub is in suspend state
 363                          * if root hub in suspend, resume it.
 364                          */
 365                         if ((bus->root_hub) && (hcd->state == HC_STATE_SUSPENDED) ) {
 366                                 DWC_PRINTF("%s: hcd->state = %d, hcd->flags = %ld\n",
 367                                                 __func__, hcd->state, hcd->flags);
 368                                 usb_hcd_resume_root_hub(hcd);
 369                         }
 370                         DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
 371                                     "Port Connect Detected--\n", hprt0.d32);
 372                         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 373                         dwc_otg_hcd->flags.b.port_connect_status = 1;
 374                         hprt0_modify.b.prtconndet = 1;
 375                         /* PET testing */
 376                         if (dwc_otg_hcd->core_if->otg_ver && (dwc_otg_hcd->core_if->test_mode == 7)) {
 377                                 hprt0_local.d32 = dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 378                                 hprt0_local.b.prtrst = 1;
 379                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_local.d32);
 380                                 dwc_mdelay(60);
 381                                 hprt0.d32 = dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 382                                 hprt0.b.prtrst = 0;
 383                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
 384                         }
 385
 386                         /* B-Device has connected, Delete the connection timer. */
 387                         DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
 388                 }
 389                 /* The Hub driver asserts a reset when it sees port connect
 390                  * status change flag */
 391                 retval |= 1;
 392         }
 393
 394         /* Port Enable Changed
 395          * Clear if detected - Set internal flag if disabled */
 396         if (hprt0.b.prtenchng) {
 397                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 398                             "Port Enable Changed--\n", hprt0.d32);
 399                 hprt0_modify.b.prtenchng = 1;
 400                 if (hprt0.b.prtena == 1) {
 401                         hfir_data_t hfir;
 402                         int do_reset = 0;
 403                         dwc_otg_core_params_t *params =
 404                             dwc_otg_hcd->core_if->core_params;
 405                         dwc_otg_core_global_regs_t *global_regs =
 406                             dwc_otg_hcd->core_if->core_global_regs;
 407                         dwc_otg_host_if_t *host_if =
 408                             dwc_otg_hcd->core_if->host_if;
 409
 410                         /* Every time when port enables calculate
 411                          * HFIR.FrInterval
 412                          */
 413                         hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
 414                         hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
 415                         DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
 416
 417                         /* Check if we need to adjust the PHY clock speed for
 418                          * low power and adjust it */
 419                         if (params->host_support_fs_ls_low_power) {
 420                                 gusbcfg_data_t usbcfg;
 421
 422                                 usbcfg.d32 =
 423                                     DWC_READ_REG32(&global_regs->gusbcfg);
 424
 425                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
 426                                     || hprt0.b.prtspd ==
 427                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
 428                                         /*
 429                                          * Low power
 430                                          */
 431                                         hcfg_data_t hcfg;
 432                                         if (usbcfg.b.phylpwrclksel == 0) {
 433                                                 /* Set PHY low power clock select for FS/LS devices */
 434                                                 usbcfg.b.phylpwrclksel = 1;
 435                                                 DWC_WRITE_REG32
 436                                                     (&global_regs->gusbcfg,
 437                                                      usbcfg.d32);
 438                                                 do_reset = 1;
 439                                         }
 440
 441                                         hcfg.d32 =
 442                                             DWC_READ_REG32
 443                                             (&host_if->host_global_regs->hcfg);
 444
 445                                         if (hprt0.b.prtspd ==
 446                                             DWC_HPRT0_PRTSPD_LOW_SPEED
 447                                             && params->host_ls_low_power_phy_clk
 448                                             ==
 449                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
 450                                         {
 451                                                 /* 6 MHZ */
 452                                                 DWC_DEBUGPL(DBG_CIL,
 453                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
 454                                                 if (hcfg.b.fslspclksel !=
 455                                                     DWC_HCFG_6_MHZ) {
 456                                                         hcfg.b.fslspclksel =
 457                                                             DWC_HCFG_6_MHZ;
 458                                                         DWC_WRITE_REG32
 459                                                             (&host_if->host_global_regs->hcfg,
 460                                                              hcfg.d32);
 461                                                         do_reset = 1;
 462                                                 }
 463                                         } else {
 464                                                 /* 48 MHZ */
 465                                                 DWC_DEBUGPL(DBG_CIL,
 466                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
 467                                                 if (hcfg.b.fslspclksel !=
 468                                                     DWC_HCFG_48_MHZ) {
 469                                                         hcfg.b.fslspclksel =
 470                                                             DWC_HCFG_48_MHZ;
 471                                                         DWC_WRITE_REG32
 472                                                             (&host_if->host_global_regs->hcfg,
 473                                                              hcfg.d32);
 474                                                         do_reset = 1;
 475                                                 }
 476                                         }
 477                                 } else {
 478                                         /*
 479                                          * Not low power
 480                                          */
 481                                         if (usbcfg.b.phylpwrclksel == 1) {
 482                                                 usbcfg.b.phylpwrclksel = 0;
 483                                                 DWC_WRITE_REG32
 484                                                     (&global_regs->gusbcfg,
 485                                                      usbcfg.d32);
 486                                                 do_reset = 1;
 487                                         }
 488                                 }
 489
 490                                 if (do_reset) {
 491                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
 492                                 }
 493                         }
 494
 495                         if (!do_reset) {
 496                                 /* Port has been enabled set the reset change flag */
 497                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
 498                         }
 499                 } else {
 500                         dwc_otg_hcd->flags.b.port_enable_change = 1;
 501                 }
 502                 retval |= 1;
 503         }
 504
 505         /** Overcurrent Change Interrupt */
 506         if (hprt0.b.prtovrcurrchng) {
 507                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 508                             "Port Overcurrent Changed--\n", hprt0.d32);
 509                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
 510                 hprt0_modify.b.prtovrcurrchng = 1;
 511                 retval |= 1;
 512         }
 513
 514         /* Clear Port Interrupts */
 515         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 516
 517         return retval;
 518 }
 519
 520 /** This interrupt indicates that one or more host channels has a pending
 521  * interrupt. There are multiple conditions that can cause each host channel
 522  * interrupt. This function determines which conditions have occurred for each
 523  * host channel interrupt and handles them appropriately. */
 524 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
 525 {
 526         int i;
 527         int retval = 0;
 528         haint_data_t haint;
 529
 530         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
 531          * GINTSTS */
 532
 533         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
 534
 535         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
 536                 if (haint.b2.chint & (1 << i)) {
 537                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
 538                 }
 539         }
 540
 541         return retval;
 542 }
 543
 544 /**
 545  * Gets the actual length of a transfer after the transfer halts. _halt_status
 546  * holds the reason for the halt.
 547  *
 548  * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
 549  * *short_read is set to 1 upon return if less than the requested
 550  * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
 551  * return. short_read may also be NULL on entry, in which case it remains
 552  * unchanged.
 553  */
 554 static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
 555                                        dwc_otg_hc_regs_t * hc_regs,
 556                                        dwc_otg_qtd_t * qtd,
 557                                        dwc_otg_halt_status_e halt_status,
 558                                        int *short_read)
 559 {
 560         hctsiz_data_t hctsiz;
 561         uint32_t length;
 562
 563         if (short_read != NULL) {
 564                 *short_read = 0;
 565         }
 566         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 567
 568         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
 569                 if (hc->ep_is_in) {
 570                         length = hc->xfer_len - hctsiz.b.xfersize;
 571                         if (short_read != NULL) {
 572                                 *short_read = (hctsiz.b.xfersize != 0);
 573                         }
 574                 } else if (hc->qh->do_split) {
 575                         length = qtd->ssplit_out_xfer_count;
 576                 } else {
 577                         length = hc->xfer_len;
 578                 }
 579         } else {
 580                 /*
 581                  * Must use the hctsiz.pktcnt field to determine how much data
 582                  * has been transferred. This field reflects the number of
 583                  * packets that have been transferred via the USB. This is
 584                  * always an integral number of packets if the transfer was
 585                  * halted before its normal completion. (Can't use the
 586                  * hctsiz.xfersize field because that reflects the number of
 587                  * bytes transferred via the AHB, not the USB).
 588                  */
 589                 length =
 590                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
 591         }
 592
 593         return length;
 594 }
 595
 596 /**
 597  * Updates the state of the URB after a Transfer Complete interrupt on the
 598  * host channel. Updates the actual_length field of the URB based on the
 599  * number of bytes transferred via the host channel. Sets the URB status
 600  * if the data transfer is finished.
 601  *
 602  * @return 1 if the data transfer specified by the URB is completely finished,
 603  * 0 otherwise.
 604  */
 605 static int update_urb_state_xfer_comp(dwc_hc_t * hc,
 606                                       dwc_otg_hc_regs_t * hc_regs,
 607                                       dwc_otg_hcd_urb_t * urb,
 608                                       dwc_otg_qtd_t * qtd)
 609 {
 610         int xfer_done = 0;
 611         int short_read = 0;
 612
 613         int xfer_length;
 614
 615         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
 616                                              DWC_OTG_HC_XFER_COMPLETE,
 617                                              &short_read);
 618
 619
 620         /* non DWORD-aligned buffer case handling. */
 621         if (hc->align_buff && xfer_length && hc->ep_is_in) {
 622                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
 623                            xfer_length);
 624         }
 625
 626         urb->actual_length += xfer_length;
 627
 628         if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
 629             (urb->flags & URB_SEND_ZERO_PACKET)
 630             && (urb->actual_length == urb->length)
 631             && !(urb->length % hc->max_packet)) {
 632                 xfer_done = 0;
 633         } else if (short_read || urb->actual_length >= urb->length) {
 634                 xfer_done = 1;
 635                 urb->status = 0;
 636         }
 637
 638 #ifdef DEBUG
 639         {
 640                 hctsiz_data_t hctsiz;
 641                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 642                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
 643                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
 644                             hc->hc_num);
 645                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
 646                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
 647                             hctsiz.b.xfersize);
 648                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
 649                             urb->length);
 650                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
 651                             urb->actual_length);
 652                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
 653                             short_read, xfer_done);
 654         }
 655 #endif
 656
 657         return xfer_done;
 658 }
 659
 660 /*
 661  * Save the starting data toggle for the next transfer. The data toggle is
 662  * saved in the QH for non-control transfers and it's saved in the QTD for
 663  * control transfers.
 664  */
 665 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
 666                              dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
 667 {
 668         hctsiz_data_t hctsiz;
 669         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 670
 671         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
 672                 dwc_otg_qh_t *qh = hc->qh;
 673                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 674                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 675                 } else {
 676                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
 677                 }
 678         } else {
 679                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 680                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
 681                 } else {
 682                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
 683                 }
 684         }
 685 }
 686
 687 /**
 688  * Updates the state of an Isochronous URB when the transfer is stopped for
 689  * any reason. The fields of the current entry in the frame descriptor array
 690  * are set based on the transfer state and the input _halt_status. Completes
 691  * the Isochronous URB if all the URB frames have been completed.
 692  *
 693  * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
 694  * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
 695  */
 696 static dwc_otg_halt_status_e
 697 update_isoc_urb_state(dwc_otg_hcd_t * hcd,
 698                       dwc_hc_t * hc,
 699                       dwc_otg_hc_regs_t * hc_regs,
 700                       dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
 701 {
 702         dwc_otg_hcd_urb_t *urb = qtd->urb;
 703         dwc_otg_halt_status_e ret_val = halt_status;
 704         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
 705
 706         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 707         switch (halt_status) {
 708         case DWC_OTG_HC_XFER_COMPLETE:
 709                 frame_desc->status = 0;
 710                 frame_desc->actual_length =
 711                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 712
 713                 /* non DWORD-aligned buffer case handling. */
 714                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 715                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
 716                                    hc->qh->dw_align_buf, frame_desc->actual_length);
 717                 }
 718
 719                 break;
 720         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
 721                 urb->error_count++;
 722                 if (hc->ep_is_in) {
 723                         frame_desc->status = -DWC_E_NO_STREAM_RES;
 724                 } else {
 725                         frame_desc->status = -DWC_E_COMMUNICATION;
 726                 }
 727                 frame_desc->actual_length = 0;
 728                 break;
 729         case DWC_OTG_HC_XFER_BABBLE_ERR:
 730                 urb->error_count++;
 731                 frame_desc->status = -DWC_E_OVERFLOW;
 732                 /* Don't need to update actual_length in this case. */
 733                 break;
 734         case DWC_OTG_HC_XFER_XACT_ERR:
 735                 urb->error_count++;
 736                 frame_desc->status = -DWC_E_PROTOCOL;
 737                 frame_desc->actual_length =
 738                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 739
 740                 /* non DWORD-aligned buffer case handling. */
 741                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 742                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
 743                                    hc->qh->dw_align_buf, frame_desc->actual_length);
 744                 }
 745                 /* Skip whole frame */
 746                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
 747                     hc->ep_is_in && hcd->core_if->dma_enable) {
 748                         qtd->complete_split = 0;
 749                         qtd->isoc_split_offset = 0;
 750                 }
 751
 752                 break;
 753         default:
 754                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
 755                 break;
 756         }
 757         if (++qtd->isoc_frame_index == urb->packet_count) {
 758                 /*
 759                  * urb->status is not used for isoc transfers.
 760                  * The individual frame_desc statuses are used instead.
 761                  */
 762                 hcd->fops->complete(hcd, urb->priv, urb, 0);
 763                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
 764         } else {
 765                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
 766         }
 767         return ret_val;
 768 }
 769
 770 /**
 771  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 772  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 773  * still linked to the QH, the QH is added to the end of the inactive
 774  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 775  * schedule if no more QTDs are linked to the QH.
 776  */
 777 static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
 778 {
 779         int continue_split = 0;
 780         dwc_otg_qtd_t *qtd;
 781
 782         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
 783
 784         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 785
 786         if (qtd->complete_split) {
 787                 continue_split = 1;
 788         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
 789                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
 790                 continue_split = 1;
 791         }
 792
 793         if (free_qtd) {
 794                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 795                 continue_split = 0;
 796         }
 797
 798         qh->channel = NULL;
 799         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
 800 }
 801
 802 /**
 803  * Releases a host channel for use by other transfers. Attempts to select and
 804  * queue more transactions since at least one host channel is available.
 805  *
 806  * @param hcd The HCD state structure.
 807  * @param hc The host channel to release.
 808  * @param qtd The QTD associated with the host channel. This QTD may be freed
 809  * if the transfer is complete or an error has occurred.
 810  * @param halt_status Reason the channel is being released. This status
 811  * determines the actions taken by this function.
 812  */
 813 static void release_channel(dwc_otg_hcd_t * hcd,
 814                             dwc_hc_t * hc,
 815                             dwc_otg_qtd_t * qtd,
 816                             dwc_otg_halt_status_e halt_status)
 817 {
 818         dwc_otg_transaction_type_e tr_type;
 819         int free_qtd;
 820
 821         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
 822                     __func__, hc->hc_num, halt_status);
 823
 824         if(halt_status != DWC_OTG_HC_XFER_URB_DEQUEUE){
 825                 if(((uint32_t) qtd & 0xf0000000)==0){
 826                         DWC_PRINTF("%s error: qtd %p, status %d 0!!!\n", __func__, qtd, halt_status);
 827                         goto cleanup;
 828                 }
 829
 830                 if(((uint32_t) qtd & 0x80000000)==0){
 831                         DWC_PRINTF("%s error: qtd %p, status %d 1!!!\n", __func__, qtd, halt_status);
 832                         goto cleanup;
 833                 }
 834
 835                 if(((uint32_t) qtd->urb & 0xf0000000)==0){
 836                         DWC_PRINTF("%s qtd %p urb %p, status %d\n", __func__, qtd, qtd->urb, halt_status);
 837                         goto cleanup;
 838                 }
 839         }
 840
 841         switch (halt_status) {
 842         case DWC_OTG_HC_XFER_URB_COMPLETE:
 843                 free_qtd = 1;
 844                 break;
 845         case DWC_OTG_HC_XFER_AHB_ERR:
 846         case DWC_OTG_HC_XFER_STALL:
 847         case DWC_OTG_HC_XFER_BABBLE_ERR:
 848                 free_qtd = 1;
 849                 break;
 850         case DWC_OTG_HC_XFER_XACT_ERR:
 851                 if (qtd->error_count >= 3) {
 852                         DWC_DEBUGPL(DBG_HCDV,
 853                                     "  Complete URB with transaction error\n");
 854                         free_qtd = 1;
 855                         qtd->urb->status = -DWC_E_PROTOCOL;
 856                         hcd->fops->complete(hcd, qtd->urb->priv,
 857                                             qtd->urb, -DWC_E_PROTOCOL);
 858                 } else {
 859                         free_qtd = 0;
 860                 }
 861                 break;
 862         case DWC_OTG_HC_XFER_URB_DEQUEUE:
 863                 /*
 864                  * The QTD has already been removed and the QH has been
 865                  * deactivated. Don't want to do anything except release the
 866                  * host channel and try to queue more transfers.
 867                  */
 868                 goto cleanup;
 869         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
 870                 free_qtd = 0;
 871                 break;
 872         case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
 873                 DWC_DEBUGPL(DBG_HCDV,
 874                         "  Complete URB with I/O error\n");
 875                 free_qtd = 1;
 876                 qtd->urb->status = -DWC_E_IO;
 877                 hcd->fops->complete(hcd, qtd->urb->priv,
 878                         qtd->urb, -DWC_E_IO);
 879                 break;
 880         default:
 881                 free_qtd = 0;
 882                 break;
 883         }
 884
 885         deactivate_qh(hcd, hc->qh, free_qtd);
 886
 887 cleanup:
 888         /*
 889          * Release the host channel for use by other transfers. The cleanup
 890          * function clears the channel interrupt enables and conditions, so
 891          * there's no need to clear the Channel Halted interrupt separately.
 892          */
 893         dwc_otg_hc_cleanup(hcd->core_if, hc);
 894         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
 895
 896         switch (hc->ep_type) {
 897         case DWC_OTG_EP_TYPE_CONTROL:
 898         case DWC_OTG_EP_TYPE_BULK:
 899                 hcd->non_periodic_channels--;
 900                 break;
 901
 902         default:
 903                 /*
 904                  * Don't release reservations for periodic channels here.
 905                  * That's done when a periodic transfer is descheduled (i.e.
 906                  * when the QH is removed from the periodic schedule).
 907                  */
 908                 break;
 909         }
 910
 911         /* Try to queue more transfers now that there's a free channel. */
 912         tr_type = dwc_otg_hcd_select_transactions(hcd);
 913         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 914                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 915         }
 916 }
 917
 918 /**
 919  * Halts a host channel. If the channel cannot be halted immediately because
 920  * the request queue is full, this function ensures that the FIFO empty
 921  * interrupt for the appropriate queue is enabled so that the halt request can
 922  * be queued when there is space in the request queue.
 923  *
 924  * This function may also be called in DMA mode. In that case, the channel is
 925  * simply released since the core always halts the channel automatically in
 926  * DMA mode.
 927  */
 928 static void halt_channel(dwc_otg_hcd_t * hcd,
 929                          dwc_hc_t * hc,
 930                          dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
 931 {
 932         if (hcd->core_if->dma_enable) {
 933                 release_channel(hcd, hc, qtd, halt_status);
 934                 return;
 935         }
 936
 937         /* Slave mode processing... */
 938         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
 939
 940         if (hc->halt_on_queue) {
 941                 gintmsk_data_t gintmsk = {.d32 = 0 };
 942                 dwc_otg_core_global_regs_t *global_regs;
 943                 global_regs = hcd->core_if->core_global_regs;
 944
 945                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
 946                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
 947                         /*
 948                          * Make sure the Non-periodic Tx FIFO empty interrupt
 949                          * is enabled so that the non-periodic schedule will
 950                          * be processed.
 951                          */
 952                         gintmsk.b.nptxfempty = 1;
 953                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 954                 } else {
 955                         /*
 956                          * Move the QH from the periodic queued schedule to
 957                          * the periodic assigned schedule. This allows the
 958                          * halt to be queued when the periodic schedule is
 959                          * processed.
 960                          */
 961                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
 962                                            &hc->qh->qh_list_entry);
 963
 964                         /*
 965                          * Make sure the Periodic Tx FIFO Empty interrupt is
 966                          * enabled so that the periodic schedule will be
 967                          * processed.
 968                          */
 969                         gintmsk.b.ptxfempty = 1;
 970                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 971                 }
 972         }
 973 }
 974
 975 /**
 976  * Performs common cleanup for non-periodic transfers after a Transfer
 977  * Complete interrupt. This function should be called after any endpoint type
 978  * specific handling is finished to release the host channel.
 979  */
 980 static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
 981                                        dwc_hc_t * hc,
 982                                        dwc_otg_hc_regs_t * hc_regs,
 983                                        dwc_otg_qtd_t * qtd,
 984                                        dwc_otg_halt_status_e halt_status)
 985 {
 986         hcint_data_t hcint;
 987
 988         qtd->error_count = 0;
 989
 990         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
 991         if (hcint.b.nyet) {
 992                 /*
 993                  * Got a NYET on the last transaction of the transfer. This
 994                  * means that the endpoint should be in the PING state at the
 995                  * beginning of the next transfer.
 996                  */
 997                 hc->qh->ping_state = 1;
 998                 clear_hc_int(hc_regs, nyet);
 999         }
1000
1001         /*
1002          * Always halt and release the host channel to make it available for
1003          * more transfers. There may still be more phases for a control
1004          * transfer or more data packets for a bulk transfer at this point,
1005          * but the host channel is still halted. A channel will be reassigned
1006          * to the transfer when the non-periodic schedule is processed after
1007          * the channel is released. This allows transactions to be queued
1008          * properly via dwc_otg_hcd_queue_transactions, which also enables the
1009          * Tx FIFO Empty interrupt if necessary.
1010          */
1011         if (hc->ep_is_in) {
1012                 /*
1013                  * IN transfers in Slave mode require an explicit disable to
1014                  * halt the channel. (In DMA mode, this call simply releases
1015                  * the channel.)
1016                  */
1017                 halt_channel(hcd, hc, qtd, halt_status);
1018         } else {
1019                 /*
1020                  * The channel is automatically disabled by the core for OUT
1021                  * transfers in Slave mode.
1022                  */
1023                 release_channel(hcd, hc, qtd, halt_status);
1024         }
1025 }
1026
1027 /**
1028  * Performs common cleanup for periodic transfers after a Transfer Complete
1029  * interrupt. This function should be called after any endpoint type specific
1030  * handling is finished to release the host channel.
1031  */
1032 static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
1033                                    dwc_hc_t * hc,
1034                                    dwc_otg_hc_regs_t * hc_regs,
1035                                    dwc_otg_qtd_t * qtd,
1036                                    dwc_otg_halt_status_e halt_status)
1037 {
1038         hctsiz_data_t hctsiz;
1039         qtd->error_count = 0;
1040
1041         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1042         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
1043                 /* Core halts channel in these cases. */
1044                 release_channel(hcd, hc, qtd, halt_status);
1045         } else {
1046                 /* Flush any outstanding requests from the Tx queue. */
1047                 halt_channel(hcd, hc, qtd, halt_status);
1048         }
1049 }
1050
1051 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
1052                                              dwc_hc_t * hc,
1053                                              dwc_otg_hc_regs_t * hc_regs,
1054                                              dwc_otg_qtd_t * qtd)
1055 {
1056         uint32_t len;
1057         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1058         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
1059
1060         len = get_actual_xfer_length(hc, hc_regs, qtd,
1061                                      DWC_OTG_HC_XFER_COMPLETE, NULL);
1062
1063         if (!len) {
1064                 qtd->complete_split = 0;
1065                 qtd->isoc_split_offset = 0;
1066                 return 0;
1067         }
1068         frame_desc->actual_length += len;
1069
1070         if (hc->align_buff && len)
1071                 dwc_memcpy(qtd->urb->buf + frame_desc->offset +
1072                            qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
1073         qtd->isoc_split_offset += len;
1074
1075         if (frame_desc->length == frame_desc->actual_length) {
1076                 frame_desc->status = 0;
1077                 qtd->isoc_frame_index++;
1078                 qtd->complete_split = 0;
1079                 qtd->isoc_split_offset = 0;
1080         }
1081
1082         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
1083                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1084                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1085         } else {
1086                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1087         }
1088
1089         return 1;               /* Indicates that channel released */
1090 }
1091
1092 /**
1093  * Handles a host channel Transfer Complete interrupt. This handler may be
1094  * called in either DMA mode or Slave mode.
1095  */
1096 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
1097                                        dwc_hc_t * hc,
1098                                        dwc_otg_hc_regs_t * hc_regs,
1099                                        dwc_otg_qtd_t * qtd)
1100 {
1101         int urb_xfer_done;
1102         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
1103         dwc_otg_hcd_urb_t *urb;
1104         int pipe_type;
1105
1106         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1107                     "Transfer Complete--\n", hc->hc_num);
1108
1109         if(((uint32_t) qtd & 0xf0000000)==0){
1110                 DWC_PRINTF("%s qtd %p\n", __func__, qtd);
1111                 release_channel(hcd, hc, qtd, hc->halt_status);
1112                 return 1;
1113         }
1114
1115         urb = qtd->urb;
1116         if(((uint32_t)urb & 0xf0000000)==0){
1117                 DWC_PRINTF("%s qtd %p, urb %p\n", __func__, qtd, urb);
1118                 release_channel(hcd, hc, qtd, hc->halt_status);
1119                 return 1;
1120         }
1121
1122         pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1123
1124         if (hcd->core_if->dma_desc_enable) {
1125                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
1126                 if (pipe_type == UE_ISOCHRONOUS) {
1127                         /* Do not disable the interrupt, just clear it */
1128                         clear_hc_int(hc_regs, xfercomp);
1129                         return 1;
1130                 }
1131                 goto handle_xfercomp_done;
1132         }
1133
1134         /*
1135          * Handle xfer complete on CSPLIT.
1136          */
1137
1138         if (hc->qh->do_split) {
1139                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
1140                     && hcd->core_if->dma_enable) {
1141                         if (qtd->complete_split
1142                             && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
1143                                                              qtd))
1144                                 goto handle_xfercomp_done;
1145                 } else {
1146                         qtd->complete_split = 0;
1147                 }
1148         }
1149
1150         /* Update the QTD and URB states. */
1151         switch (pipe_type) {
1152         case UE_CONTROL:
1153                 switch (qtd->control_phase) {
1154                 case DWC_OTG_CONTROL_SETUP:
1155                         if (urb->length > 0) {
1156                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
1157                         } else {
1158                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1159                         }
1160                         DWC_DEBUGPL(DBG_HCDV,
1161                                     "  Control setup transaction done\n");
1162                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1163                         break;
1164                 case DWC_OTG_CONTROL_DATA:{
1165                                 urb_xfer_done =
1166                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
1167                                                                qtd);
1168                                 if (urb_xfer_done) {
1169                                         qtd->control_phase =
1170                                             DWC_OTG_CONTROL_STATUS;
1171                                         DWC_DEBUGPL(DBG_HCDV,
1172                                                     "  Control data transfer done\n");
1173                                 } else {
1174                                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1175                                 }
1176                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1177                                 break;
1178                         }
1179                 case DWC_OTG_CONTROL_STATUS:
1180                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
1181                         if (urb->status == -DWC_E_IN_PROGRESS) {
1182                                 urb->status = 0;
1183                         }
1184                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1185                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1186                         break;
1187                 }
1188
1189                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1190                 break;
1191         case UE_BULK:
1192                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
1193                 urb_xfer_done =
1194                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1195                 if (urb_xfer_done) {
1196                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1197                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1198                 } else {
1199                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1200                 }
1201
1202                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1203                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1204                 break;
1205         case UE_INTERRUPT:
1206                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
1207                 urb_xfer_done =
1208                         update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1209
1210                 /*
1211                  * Interrupt URB is done on the first transfer complete
1212                  * interrupt.
1213                  */
1214                 if (urb_xfer_done) {
1215                                 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1216                                 halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1217                 } else {
1218                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1219                 }
1220
1221                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1222                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1223                 break;
1224         case UE_ISOCHRONOUS:
1225                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
1226                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1227                         halt_status =
1228                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1229                                                   DWC_OTG_HC_XFER_COMPLETE);
1230                 }
1231                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1232                 break;
1233         }
1234
1235 handle_xfercomp_done:
1236         disable_hc_int(hc_regs, xfercompl);
1237
1238         return 1;
1239 }
1240
1241 /**
1242  * Handles a host channel STALL interrupt. This handler may be called in
1243  * either DMA mode or Slave mode.
1244  */
1245 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
1246                                     dwc_hc_t * hc,
1247                                     dwc_otg_hc_regs_t * hc_regs,
1248                                     dwc_otg_qtd_t * qtd)
1249 {
1250         dwc_otg_hcd_urb_t *urb = qtd->urb;
1251         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1252
1253         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1254                     "STALL Received--\n", hc->hc_num);
1255
1256         if (hcd->core_if->dma_desc_enable) {
1257                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
1258                 goto handle_stall_done;
1259         }
1260
1261         if (pipe_type == UE_CONTROL) {
1262                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1263         }
1264
1265         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
1266                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1267                 /*
1268                  * USB protocol requires resetting the data toggle for bulk
1269                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1270                  * setup command is issued to the endpoint. Anticipate the
1271                  * CLEAR_FEATURE command since a STALL has occurred and reset
1272                  * the data toggle now.
1273                  */
1274                 hc->qh->data_toggle = 0;
1275         }
1276
1277         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
1278
1279 handle_stall_done:
1280         disable_hc_int(hc_regs, stall);
1281
1282         return 1;
1283 }
1284
1285 /*
1286  * Updates the state of the URB when a transfer has been stopped due to an
1287  * abnormal condition before the transfer completes. Modifies the
1288  * actual_length field of the URB to reflect the number of bytes that have
1289  * actually been transferred via the host channel.
1290  */
1291 static void update_urb_state_xfer_intr(dwc_hc_t * hc,
1292                                        dwc_otg_hc_regs_t * hc_regs,
1293                                        dwc_otg_hcd_urb_t * urb,
1294                                        dwc_otg_qtd_t * qtd,
1295                                        dwc_otg_halt_status_e halt_status)
1296 {
1297         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
1298                                                             halt_status, NULL);
1299         /* non DWORD-aligned buffer case handling. */
1300         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
1301                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
1302                            bytes_transferred);
1303         }
1304
1305         urb->actual_length += bytes_transferred;
1306
1307 #ifdef DEBUG
1308         {
1309                 hctsiz_data_t hctsiz;
1310                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1311                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
1312                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
1313                             hc->hc_num);
1314                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
1315                             hc->start_pkt_count);
1316                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
1317                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
1318                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
1319                             bytes_transferred);
1320                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
1321                             urb->actual_length);
1322                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
1323                             urb->length);
1324         }
1325 #endif
1326 }
1327
1328 /**
1329  * Handles a host channel NAK interrupt. This handler may be called in either
1330  * DMA mode or Slave mode.
1331  */
1332 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
1333                                   dwc_hc_t * hc,
1334                                   dwc_otg_hc_regs_t * hc_regs,
1335                                   dwc_otg_qtd_t * qtd)
1336 {
1337         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1338                     "NAK Received--\n", hc->hc_num);
1339
1340         /*
1341          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1342          * interrupt.  Re-start the SSPLIT transfer.
1343          */
1344         if (hc->do_split) {
1345                 if (hc->complete_split) {
1346                         qtd->error_count = 0;
1347                 }
1348                 qtd->complete_split = 0;
1349                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1350                 goto handle_nak_done;
1351         }
1352
1353         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1354         case UE_CONTROL:
1355         case UE_BULK:
1356                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
1357                         /*
1358                          * NAK interrupts are enabled on bulk/control IN
1359                          * transfers in DMA mode for the sole purpose of
1360                          * resetting the error count after a transaction error
1361                          * occurs. The core will continue transferring data.
1362                          */
1363                         qtd->error_count = 0;
1364                         goto handle_nak_done;
1365                 }
1366
1367                 /*
1368                  * NAK interrupts normally occur during OUT transfers in DMA
1369                  * or Slave mode. For IN transfers, more requests will be
1370                  * queued as request queue space is available.
1371                  */
1372                 qtd->error_count = 0;
1373
1374                 if (!hc->qh->ping_state) {
1375                         update_urb_state_xfer_intr(hc, hc_regs,
1376                                                    qtd->urb, qtd,
1377                                                    DWC_OTG_HC_XFER_NAK);
1378                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1379
1380                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
1381                                 hc->qh->ping_state = 1;
1382                 }
1383
1384                 /*
1385                  * Halt the channel so the transfer can be re-started from
1386                  * the appropriate point or the PING protocol will
1387                  * start/continue.
1388                  */
1389                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1390                 break;
1391         case UE_INTERRUPT:
1392                 qtd->error_count = 0;
1393                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1394                 break;
1395         case UE_ISOCHRONOUS:
1396                 /* Should never get called for isochronous transfers. */
1397                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
1398                 break;
1399         }
1400
1401 handle_nak_done:
1402         disable_hc_int(hc_regs, nak);
1403
1404         return 1;
1405 }
1406
1407 /**
1408  * Handles a host channel ACK interrupt. This interrupt is enabled when
1409  * performing the PING protocol in Slave mode, when errors occur during
1410  * either Slave mode or DMA mode, and during Start Split transactions.
1411  */
1412 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
1413                                   dwc_hc_t * hc,
1414                                   dwc_otg_hc_regs_t * hc_regs,
1415                                   dwc_otg_qtd_t * qtd)
1416 {
1417         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1418                     "ACK Received--\n", hc->hc_num);
1419
1420         if (hc->do_split) {
1421                 /*
1422                  * Handle ACK on SSPLIT.
1423                  * ACK should not occur in CSPLIT.
1424                  */
1425                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
1426                         qtd->ssplit_out_xfer_count = hc->xfer_len;
1427                 }
1428                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
1429                         /* Don't need complete for isochronous out transfers. */
1430                         qtd->complete_split = 1;
1431                 }
1432
1433                 /* ISOC OUT */
1434                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1435                         switch (hc->xact_pos) {
1436                         case DWC_HCSPLIT_XACTPOS_ALL:
1437                                 break;
1438                         case DWC_HCSPLIT_XACTPOS_END:
1439                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
1440                                 qtd->isoc_split_offset = 0;
1441                                 break;
1442                         case DWC_HCSPLIT_XACTPOS_BEGIN:
1443                         case DWC_HCSPLIT_XACTPOS_MID:
1444                                 /*
1445                                  * For BEGIN or MID, calculate the length for
1446                                  * the next microframe to determine the correct
1447                                  * SSPLIT token, either MID or END.
1448                                  */
1449                                 {
1450                                         struct dwc_otg_hcd_iso_packet_desc
1451                                         *frame_desc;
1452
1453                                         frame_desc =
1454                                             &qtd->urb->
1455                                             iso_descs[qtd->isoc_frame_index];
1456                                         qtd->isoc_split_offset += 188;
1457
1458                                         if ((frame_desc->length -
1459                                              qtd->isoc_split_offset) <= 188) {
1460                                                 qtd->isoc_split_pos =
1461                                                     DWC_HCSPLIT_XACTPOS_END;
1462                                         } else {
1463                                                 qtd->isoc_split_pos =
1464                                                     DWC_HCSPLIT_XACTPOS_MID;
1465                                         }
1466
1467                                 }
1468                                 break;
1469                         }
1470                 } else {
1471                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1472                 }
1473         } else {
1474                 qtd->error_count = 0;
1475
1476                 if (hc->qh->ping_state) {
1477                         hc->qh->ping_state = 0;
1478                         /*
1479                          * Halt the channel so the transfer can be re-started
1480                          * from the appropriate point. This only happens in
1481                          * Slave mode. In DMA mode, the ping_state is cleared
1482                          * when the transfer is started because the core
1483                          * automatically executes the PING, then the transfer.
1484                          */
1485                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1486                 }
1487         }
1488
1489         /*
1490          * If the ACK occurred when _not_ in the PING state, let the channel
1491          * continue transferring data after clearing the error count.
1492          */
1493
1494         disable_hc_int(hc_regs, ack);
1495
1496         return 1;
1497 }
1498
1499 /**
1500  * Handles a host channel NYET interrupt. This interrupt should only occur on
1501  * Bulk and Control OUT endpoints and for complete split transactions. If a
1502  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1503  * handled in the xfercomp interrupt handler, not here. This handler may be
1504  * called in either DMA mode or Slave mode.
1505  */
1506 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
1507                                    dwc_hc_t * hc,
1508                                    dwc_otg_hc_regs_t * hc_regs,
1509                                    dwc_otg_qtd_t * qtd)
1510 {
1511         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1512                     "NYET Received--\n", hc->hc_num);
1513
1514         /*
1515          * NYET on CSPLIT
1516          * re-do the CSPLIT immediately on non-periodic
1517          */
1518         if (hc->do_split && hc->complete_split) {
1519                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
1520                     && hcd->core_if->dma_enable) {
1521                         qtd->complete_split = 0;
1522                         qtd->isoc_split_offset = 0;
1523                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
1524                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1525                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1526                         }
1527                         else
1528                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1529                         goto handle_nyet_done;
1530                 }
1531
1532                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1533                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1534                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
1535
1536                         if (dwc_full_frame_num(frnum) !=
1537                             dwc_full_frame_num(hc->qh->sched_frame)) {
1538                                 /*
1539                                  * No longer in the same full speed frame.
1540                                  * Treat this as a transaction error.
1541                                  */
1542 #if 0
1543                                 /** @todo Fix system performance so this can
1544                                  * be treated as an error. Right now complete
1545                                  * splits cannot be scheduled precisely enough
1546                                  * due to other system activity, so this error
1547                                  * occurs regularly in Slave mode.
1548                                  */
1549                                 qtd->error_count++;
1550 #endif
1551                                 qtd->complete_split = 0;
1552                                 halt_channel(hcd, hc, qtd,
1553                                              DWC_OTG_HC_XFER_XACT_ERR);
1554                                 /** @todo add support for isoc release */
1555                                 goto handle_nyet_done;
1556                         }
1557                 }
1558
1559                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1560                 goto handle_nyet_done;
1561         }
1562
1563         hc->qh->ping_state = 1;
1564         qtd->error_count = 0;
1565
1566         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
1567                                    DWC_OTG_HC_XFER_NYET);
1568         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1569
1570         /*
1571          * Halt the channel and re-start the transfer so the PING
1572          * protocol will start.
1573          */
1574         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1575
1576 handle_nyet_done:
1577         disable_hc_int(hc_regs, nyet);
1578         return 1;
1579 }
1580
1581 /**
1582  * Handles a host channel babble interrupt. This handler may be called in
1583  * either DMA mode or Slave mode.
1584  */
1585 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
1586                                      dwc_hc_t * hc,
1587                                      dwc_otg_hc_regs_t * hc_regs,
1588                                      dwc_otg_qtd_t * qtd)
1589 {
1590         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1591                     "Babble Error--\n", hc->hc_num);
1592
1593         if (hcd->core_if->dma_desc_enable) {
1594                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1595                                                DWC_OTG_HC_XFER_BABBLE_ERR);
1596                 goto handle_babble_done;
1597         }
1598
1599         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1600                 hcd->fops->complete(hcd, qtd->urb->priv,
1601                                     qtd->urb, -DWC_E_OVERFLOW);
1602                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
1603         } else {
1604                 dwc_otg_halt_status_e halt_status;
1605                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1606                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
1607                 halt_channel(hcd, hc, qtd, halt_status);
1608         }
1609
1610 handle_babble_done:
1611         disable_hc_int(hc_regs, bblerr);
1612         return 1;
1613 }
1614
1615 /**
1616  * Handles a host channel AHB error interrupt. This handler is only called in
1617  * DMA mode.
1618  */
1619 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
1620                                      dwc_hc_t * hc,
1621                                      dwc_otg_hc_regs_t * hc_regs,
1622                                      dwc_otg_qtd_t * qtd)
1623 {
1624         hcchar_data_t hcchar;
1625         hcsplt_data_t hcsplt;
1626         hctsiz_data_t hctsiz;
1627         uint32_t hcdma;
1628         char *pipetype, *speed;
1629
1630         dwc_otg_hcd_urb_t *urb = qtd->urb;
1631
1632         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1633                     "AHB Error--\n", hc->hc_num);
1634
1635         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1636         hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1637         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1638         hcdma = DWC_READ_REG32(&hc_regs->hcdma);
1639
1640         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
1641         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1642         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1643         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
1644         DWC_ERROR("  Device address: %d\n",
1645                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
1646         DWC_ERROR("  Endpoint: %d, %s\n",
1647                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
1648                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
1649
1650         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1651         case UE_CONTROL:
1652                 pipetype = "CONTROL";
1653                 break;
1654         case UE_BULK:
1655                 pipetype = "BULK";
1656                 break;
1657         case UE_INTERRUPT:
1658                 pipetype = "INTERRUPT";
1659                 break;
1660         case UE_ISOCHRONOUS:
1661                 pipetype = "ISOCHRONOUS";
1662                 break;
1663         default:
1664                 pipetype = "UNKNOWN";
1665                 break;
1666         }
1667
1668         DWC_ERROR("  Endpoint type: %s\n", pipetype);
1669
1670         switch (hc->speed) {
1671         case DWC_OTG_EP_SPEED_HIGH:
1672                 speed = "HIGH";
1673                 break;
1674         case DWC_OTG_EP_SPEED_FULL:
1675                 speed = "FULL";
1676                 break;
1677         case DWC_OTG_EP_SPEED_LOW:
1678                 speed = "LOW";
1679                 break;
1680         default:
1681                 speed = "UNKNOWN";
1682                 break;
1683         };
1684
1685         DWC_ERROR("  Speed: %s\n", speed);
1686
1687         DWC_ERROR("  Max packet size: %d\n",
1688                   dwc_otg_hcd_get_mps(&urb->pipe_info));
1689         DWC_ERROR("  Data buffer length: %d\n", urb->length);
1690         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
1691                   urb->buf, (void *)urb->dma);
1692         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
1693                   urb->setup_packet, (void *)urb->setup_dma);
1694         DWC_ERROR("  Interval: %d\n", urb->interval);
1695
1696         /* Core haltes the channel for Descriptor DMA mode */
1697         if (hcd->core_if->dma_desc_enable) {
1698                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1699                                                DWC_OTG_HC_XFER_AHB_ERR);
1700                 goto handle_ahberr_done;
1701         }
1702
1703         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
1704
1705         /*
1706          * Force a channel halt. Don't call halt_channel because that won't
1707          * write to the HCCHARn register in DMA mode to force the halt.
1708          */
1709         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
1710 handle_ahberr_done:
1711         disable_hc_int(hc_regs, ahberr);
1712         return 1;
1713 }
1714
1715 /**
1716  * Handles a host channel transaction error interrupt. This handler may be
1717  * called in either DMA mode or Slave mode.
1718  */
1719 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
1720                                       dwc_hc_t * hc,
1721                                       dwc_otg_hc_regs_t * hc_regs,
1722                                       dwc_otg_qtd_t * qtd)
1723 {
1724         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1725                     "Transaction Error--\n", hc->hc_num);
1726
1727         if (hcd->core_if->dma_desc_enable) {
1728                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1729                                                DWC_OTG_HC_XFER_XACT_ERR);
1730                 goto handle_xacterr_done;
1731         }
1732
1733         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1734         case UE_CONTROL:
1735         case UE_BULK:
1736                 qtd->error_count++;
1737                 if (!hc->qh->ping_state) {
1738
1739                         update_urb_state_xfer_intr(hc, hc_regs,
1740                                                    qtd->urb, qtd,
1741                                                    DWC_OTG_HC_XFER_XACT_ERR);
1742                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1743                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
1744                                 hc->qh->ping_state = 1;
1745                         }
1746                 }
1747
1748                 /*
1749                  * Halt the channel so the transfer can be re-started from
1750                  * the appropriate point or the PING protocol will start.
1751                  */
1752                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1753                 break;
1754         case UE_INTERRUPT:
1755                 qtd->error_count++;
1756                 if (hc->do_split && hc->complete_split) {
1757                         qtd->complete_split = 0;
1758                 }
1759                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1760                 break;
1761         case UE_ISOCHRONOUS:
1762                 {
1763                         dwc_otg_halt_status_e halt_status;
1764                         halt_status =
1765                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1766                                                   DWC_OTG_HC_XFER_XACT_ERR);
1767
1768                         halt_channel(hcd, hc, qtd, halt_status);
1769                 }
1770                 break;
1771         }
1772 handle_xacterr_done:
1773         disable_hc_int(hc_regs, xacterr);
1774
1775         return 1;
1776 }
1777
1778 /**
1779  * Handles a host channel frame overrun interrupt. This handler may be called
1780  * in either DMA mode or Slave mode.
1781  */
1782 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
1783                                        dwc_hc_t * hc,
1784                                        dwc_otg_hc_regs_t * hc_regs,
1785                                        dwc_otg_qtd_t * qtd)
1786 {
1787         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1788                     "Frame Overrun--\n", hc->hc_num);
1789
1790         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1791         case UE_CONTROL:
1792         case UE_BULK:
1793                 break;
1794         case UE_INTERRUPT:
1795                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
1796                 break;
1797         case UE_ISOCHRONOUS:
1798                 {
1799                         dwc_otg_halt_status_e halt_status;
1800                         halt_status =
1801                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1802                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
1803
1804                         halt_channel(hcd, hc, qtd, halt_status);
1805                 }
1806                 break;
1807         }
1808
1809         disable_hc_int(hc_regs, frmovrun);
1810
1811         return 1;
1812 }
1813
1814 /**
1815  * Handles a host channel data toggle error interrupt. This handler may be
1816  * called in either DMA mode or Slave mode.
1817  */
1818 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
1819                                          dwc_hc_t * hc,
1820                                          dwc_otg_hc_regs_t * hc_regs,
1821                                          dwc_otg_qtd_t * qtd)
1822 {
1823         DWC_ERROR("--Host Channel %d Interrupt: "
1824                   "Data Toggle Error--\n", hc->hc_num);
1825         if (hc->ep_is_in) {
1826                 qtd->error_count += 3;//Complete the error URB immediately
1827         } else {
1828                 DWC_ERROR("Data Toggle Error on OUT transfer,"
1829                           "channel %d\n", hc->hc_num);
1830         }
1831         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1832         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1833         clear_hc_int(hc_regs,chhltd);
1834
1835         return 1;
1836 }
1837
1838 #ifdef DEBUG
1839 /**
1840  * This function is for debug only. It checks that a valid halt status is set
1841  * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1842  * taken and a warning is issued.
1843  * @return 1 if halt status is ok, 0 otherwise.
1844  */
1845 static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
1846                                  dwc_hc_t * hc,
1847                                  dwc_otg_hc_regs_t * hc_regs,
1848                                  dwc_otg_qtd_t * qtd)
1849 {
1850         hcchar_data_t hcchar;
1851         hctsiz_data_t hctsiz;
1852         hcint_data_t hcint;
1853         hcintmsk_data_t hcintmsk;
1854         hcsplt_data_t hcsplt;
1855
1856         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
1857                 /*
1858                  * This code is here only as a check. This condition should
1859                  * never happen. Ignore the halt if it does occur.
1860                  */
1861                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1862                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1863                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1864                 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1865                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1866                 DWC_WARN
1867                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
1868                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1869                      "hcint 0x%08x, hcintmsk 0x%08x, "
1870                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
1871                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
1872                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
1873
1874                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1875                          __func__, hc->hc_num);
1876                 DWC_WARN("\n");
1877                 clear_hc_int(hc_regs, chhltd);
1878                 return 0;
1879         }
1880
1881         /*
1882          * This code is here only as a check. hcchar.chdis should
1883          * never be set when the halt interrupt occurs. Halt the
1884          * channel again if it does occur.
1885          */
1886         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1887         if (hcchar.b.chdis) {
1888                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1889                          "hcchar 0x%08x, trying to halt again\n",
1890                          __func__, hcchar.d32);
1891                 clear_hc_int(hc_regs, chhltd);
1892                 hc->halt_pending = 0;
1893                 halt_channel(hcd, hc, qtd, hc->halt_status);
1894                 return 0;
1895         }
1896
1897         return 1;
1898 }
1899 #endif
1900
1901 /**
1902  * Handles a host Channel Halted interrupt in DMA mode. This handler
1903  * determines the reason the channel halted and proceeds accordingly.
1904  */
1905 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
1906                                       dwc_hc_t * hc,
1907                                       dwc_otg_hc_regs_t * hc_regs,
1908                                       dwc_otg_qtd_t * qtd)
1909 {
1910         hcint_data_t hcint;
1911         hcintmsk_data_t hcintmsk;
1912         int out_nak_enh = 0;
1913
1914         /* For core with OUT NAK enhancement, the flow for high-
1915          * speed CONTROL/BULK OUT is handled a little differently.
1916          */
1917         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
1918                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1919                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1920                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1921                         out_nak_enh = 1;
1922                 }
1923         }
1924
1925         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1926             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
1927              && !hcd->core_if->dma_desc_enable)) {
1928                 /*
1929                  * Just release the channel. A dequeue can happen on a
1930                  * transfer timeout. In the case of an AHB Error, the channel
1931                  * was forced to halt because there's no way to gracefully
1932                  * recover.
1933                  */
1934                 if (hcd->core_if->dma_desc_enable)
1935                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1936                                                        hc->halt_status);
1937                 else
1938                         release_channel(hcd, hc, qtd, hc->halt_status);
1939                 return;
1940         }
1941
1942         /* Read the HCINTn register to determine the cause for the halt. */
1943         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1944         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1945
1946         if (hcint.b.xfercomp) {
1947                 /** @todo This is here because of a possible hardware bug.  Spec
1948                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1949                  * interrupt w/ACK bit set should occur, but I only see the
1950                  * XFERCOMP bit, even with it masked out.  This is a workaround
1951                  * for that behavior.  Should fix this when hardware is fixed.
1952                  */
1953                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1954                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1955                 }
1956                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1957         } else if (hcint.b.stall) {
1958                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1959         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
1960                 if (out_nak_enh) {
1961                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1962                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
1963                                 qtd->error_count = 0;
1964                         } else {
1965                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
1966                         }
1967                 }
1968
1969                 /*
1970                  * Must handle xacterr before nak or ack. Could get a xacterr
1971                  * at the same time as either of these on a BULK/CONTROL OUT
1972                  * that started with a PING. The xacterr takes precedence.
1973                  */
1974                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1975         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
1976                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1977         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
1978                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
1979         } else if (hcint.b.bblerr) {
1980                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1981         } else if (hcint.b.frmovrun) {
1982                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1983         } else if(hcint.b.datatglerr){
1984         handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
1985         }
1986         else if (!out_nak_enh) {
1987                 if (hcint.b.nyet) {
1988                         /*
1989                          * Must handle nyet before nak or ack. Could get a nyet at the
1990                          * same time as either of those on a BULK/CONTROL OUT that
1991                          * started with a PING. The nyet takes precedence.
1992                          */
1993                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
1994                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
1995                         /*
1996                          * If nak is not masked, it's because a non-split IN transfer
1997                          * is in an error state. In that case, the nak is handled by
1998                          * the nak interrupt handler, not here. Handle nak here for
1999                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
2000                          * rewinding the buffer pointer.
2001                          */
2002                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
2003                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
2004                         /*
2005                          * If ack is not masked, it's because a non-split IN transfer
2006                          * is in an error state. In that case, the ack is handled by
2007                          * the ack interrupt handler, not here. Handle ack here for
2008                          * split transfers. Start splits halt on ACK.
2009                          */
2010                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
2011                 } else {
2012                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2013                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2014                                 /*
2015                                  * A periodic transfer halted with no other channel
2016                                  * interrupts set. Assume it was halted by the core
2017                                  * because it could not be completed in its scheduled
2018                                  * (micro)frame.
2019                                  */
2020 #ifdef DEBUG
2021                                 DWC_PRINTF
2022                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
2023                                      __func__, hc->hc_num);
2024 #endif
2025                                 halt_channel(hcd, hc, qtd,
2026                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
2027                         } else {
2028                                 DWC_ERROR
2029                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
2030                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
2031                                      __func__, hc->hc_num, hcint.d32,
2032                                      DWC_READ_REG32(&hcd->
2033                                                     core_if->core_global_regs->
2034                                                     gintsts));
2035                                          clear_hc_int(hc_regs,chhltd);
2036                         }
2037
2038                 }
2039         } else {
2040                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
2041                            hcint.d32);
2042         }
2043 }
2044
2045 /**
2046  * Handles a host channel Channel Halted interrupt.
2047  *
2048  * In slave mode, this handler is called only when the driver specifically
2049  * requests a halt. This occurs during handling other host channel interrupts
2050  * (e.g. nak, xacterr, stall, nyet, etc.).
2051  *
2052  * In DMA mode, this is the interrupt that occurs when the core has finished
2053  * processing a transfer on a channel. Other host channel interrupts (except
2054  * ahberr) are disabled in DMA mode.
2055  */
2056 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
2057                                      dwc_hc_t * hc,
2058                                      dwc_otg_hc_regs_t * hc_regs,
2059                                      dwc_otg_qtd_t * qtd)
2060 {
2061         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
2062                     "Channel Halted--\n", hc->hc_num);
2063
2064         if (hcd->core_if->dma_enable) {
2065                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
2066         } else {
2067 #ifdef DEBUG
2068                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
2069                         return 1;
2070                 }
2071 #endif
2072                 release_channel(hcd, hc, qtd, hc->halt_status);
2073         }
2074
2075         return 1;
2076 }
2077
2078 /** Handles interrupt for a specific Host Channel */
2079 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
2080 {
2081         int retval = 0;
2082         hcint_data_t hcint;
2083         hcintmsk_data_t hcintmsk;
2084         dwc_hc_t *hc;
2085         dwc_otg_hc_regs_t *hc_regs;
2086         dwc_otg_qtd_t *qtd;
2087
2088         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
2089
2090         hc = dwc_otg_hcd->hc_ptr_array[num];
2091         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
2092         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
2093
2094         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2095         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
2096         DWC_DEBUGPL(DBG_HCDV,
2097                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2098                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
2099         hcint.d32 = hcint.d32 & hcintmsk.d32;
2100
2101         if (!dwc_otg_hcd->core_if->dma_enable) {
2102                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
2103                         hcint.b.chhltd = 0;
2104                 }
2105         }
2106
2107         if (hcint.b.chhltd) {
2108                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2109         }
2110         if (hcint.b.xfercomp) {
2111                 retval |=
2112                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2113                 /*
2114                  * If NYET occurred at same time as Xfer Complete, the NYET is
2115                  * handled by the Xfer Complete interrupt handler. Don't want
2116                  * to call the NYET interrupt handler in this case.
2117                  */
2118                 hcint.b.nyet = 0;
2119         }
2120         if (hcint.b.ahberr) {
2121                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2122         }
2123         if (hcint.b.stall) {
2124                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2125         }
2126         if (hcint.b.nak) {
2127                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2128         }
2129         if (hcint.b.ack) {
2130                 if(!hcint.b.chhltd)
2131                         retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2132         }
2133         if (hcint.b.nyet) {
2134                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2135         }
2136         if (hcint.b.xacterr) {
2137                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2138         }
2139         if (hcint.b.bblerr) {
2140                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2141         }
2142         if (hcint.b.frmovrun) {
2143                 retval |=
2144                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2145         }
2146         if (hcint.b.datatglerr) {
2147                 retval |=
2148                     handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2149         }
2150
2151         return retval;
2152 }
2153
2154 #endif /* DWC_DEVICE_ONLY */