drivers/usb/dwc_otg_310/dwc_otg_hcd_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
   3  * $Revision: #92 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 #include "dwc_otg_hcd.h"
  36 #include "dwc_otg_regs.h"
  37 #include <linux/usb.h>
  38 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
  39 #include <../drivers/usb/core/hcd.h>
  40 #else
  41 #include <linux/usb/hcd.h>
  42 #endif
  43 /** @file
  44  * This file contains the implementation of the HCD Interrupt handlers.
  45  */
  46
  47 /** This function handles interrupts for the HCD. */
  48 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd)
  49 {
  50         int retval = 0;
  51         dwc_irqflags_t flags;
  52
  53         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  54         gintsts_data_t gintsts;
  55 #ifdef DEBUG
  56         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
  57 #endif
  58
  59         if (dwc_otg_check_haps_status(core_if) == -1) {
  60                 DWC_WARN("HAPS is disconnected");
  61                 return retval;
  62         }
  63
  64         /* Exit from ISR if core is hibernated */
  65         if (core_if->hibernation_suspend == 1) {
  66                 return retval;
  67         }
  68         DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
  69         /* Check if HOST Mode */
  70         if (dwc_otg_is_host_mode(core_if)) {
  71                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
  72                 if (!gintsts.d32) {
  73                         DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
  74                         return 0;
  75                 }
  76 #ifdef DEBUG
  77                 /* Don't print debug message in the interrupt handler on SOF */
  78 #ifndef DEBUG_SOF
  79                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  80 #endif
  81                         DWC_DEBUGPL(DBG_HCD, "\n");
  82 #endif
  83
  84 #ifdef DEBUG
  85 #ifndef DEBUG_SOF
  86                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  87 #endif
  88                         DWC_DEBUGPL(DBG_HCD,
  89                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
  90                                     gintsts.d32);
  91 #endif
  92
  93                 if (gintsts.b.sofintr) {
  94                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
  95                 }
  96                 if (gintsts.b.rxstsqlvl) {
  97                         retval |=
  98                             dwc_otg_hcd_handle_rx_status_q_level_intr
  99                             (dwc_otg_hcd);
 100                 }
 101                 if (gintsts.b.nptxfempty) {
 102                         retval |=
 103                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
 104                             (dwc_otg_hcd);
 105                 }
 106                 if (gintsts.b.i2cintr) {
 107                         /** @todo Implement i2cintr handler. */
 108                 }
 109                 if (gintsts.b.portintr) {
 110                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
 111                 }
 112                 if (gintsts.b.hcintr) {
 113                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
 114                 }
 115                 if (gintsts.b.ptxfempty) {
 116                         retval |=
 117                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
 118                             (dwc_otg_hcd);
 119                 }
 120 #ifdef DEBUG
 121 #ifndef DEBUG_SOF
 122                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 123 #endif
 124                 {
 125                         DWC_DEBUGPL(DBG_HCD,
 126                                     "DWC OTG HCD Finished Servicing Interrupts\n");
 127                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
 128                                     DWC_READ_REG32(&global_regs->gintsts));
 129                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
 130                                     DWC_READ_REG32(&global_regs->gintmsk));
 131                 }
 132 #endif
 133
 134 #ifdef DEBUG
 135 #ifndef DEBUG_SOF
 136                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 137 #endif
 138                         DWC_DEBUGPL(DBG_HCD, "\n");
 139 #endif
 140
 141         }
 142         DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
 143         return retval;
 144 }
 145
 146 #ifdef DWC_TRACK_MISSED_SOFS
 147 #warning Compiling code to track missed SOFs
 148 #define FRAME_NUM_ARRAY_SIZE 1000
 149 /**
 150  * This function is for debug only.
 151  */
 152 static inline void track_missed_sofs(uint16_t curr_frame_number)
 153 {
 154         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
 155         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
 156         static int frame_num_idx;
 157         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
 158         static int dumped_frame_num_array;
 159
 160         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
 161                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
 162                     curr_frame_number) {
 163                         frame_num_array[frame_num_idx] = curr_frame_number;
 164                         last_frame_num_array[frame_num_idx++] = last_frame_num;
 165                 }
 166         } else if (!dumped_frame_num_array) {
 167                 int i;
 168                 DWC_PRINTF("Frame     Last Frame\n");
 169                 DWC_PRINTF("-----     ----------\n");
 170                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
 171                         DWC_PRINTF("0x%04x    0x%04x\n",
 172                                    frame_num_array[i], last_frame_num_array[i]);
 173                 }
 174                 dumped_frame_num_array = 1;
 175         }
 176         last_frame_num = curr_frame_number;
 177 }
 178 #endif
 179
 180 /**
 181  * Handles the start-of-frame interrupt in host mode. Non-periodic
 182  * transactions may be queued to the DWC_otg controller for the current
 183  * (micro)frame. Periodic transactions may be queued to the controller for the
 184  * next (micro)frame.
 185  */
 186 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd)
 187 {
 188         hfnum_data_t hfnum;
 189         dwc_list_link_t *qh_entry;
 190         dwc_otg_qh_t *qh;
 191         dwc_otg_transaction_type_e tr_type;
 192         gintsts_data_t gintsts = {.d32 = 0 };
 193
 194         hfnum.d32 =
 195             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
 196
 197 #ifdef DEBUG_SOF
 198         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
 199 #endif
 200         hcd->frame_number = hfnum.b.frnum;
 201
 202 #ifdef DEBUG
 203         hcd->frrem_accum += hfnum.b.frrem;
 204         hcd->frrem_samples++;
 205 #endif
 206
 207 #ifdef DWC_TRACK_MISSED_SOFS
 208         track_missed_sofs(hcd->frame_number);
 209 #endif
 210         /* Determine whether any periodic QHs should be executed. */
 211         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
 212         while (qh_entry != &hcd->periodic_sched_inactive) {
 213                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
 214                 qh_entry = qh_entry->next;
 215                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
 216                         /*
 217                          * Move QH to the ready list to be executed next
 218                          * (micro)frame.
 219                          */
 220                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
 221                                            &qh->qh_list_entry);
 222                 }
 223         }
 224         tr_type = dwc_otg_hcd_select_transactions(hcd);
 225         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 226                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 227         }
 228
 229         /* Clear interrupt */
 230         gintsts.b.sofintr = 1;
 231         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
 232
 233         return 1;
 234 }
 235
 236 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
 237  * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
 238  * memory if the DWC_otg controller is operating in Slave mode. */
 239 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 240 {
 241         host_grxsts_data_t grxsts;
 242         dwc_hc_t *hc = NULL;
 243
 244         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
 245
 246         grxsts.d32 =
 247             DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
 248
 249         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
 250         if (!hc) {
 251                 DWC_ERROR("Unable to get corresponding channel\n");
 252                 return 0;
 253         }
 254
 255         /* Packet Status */
 256         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
 257         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
 258         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
 259                     hc->data_pid_start);
 260         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
 261
 262         switch (grxsts.b.pktsts) {
 263         case DWC_GRXSTS_PKTSTS_IN:
 264                 /* Read the data into the host buffer. */
 265                 if (grxsts.b.bcnt > 0) {
 266                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
 267                                             hc->xfer_buff, grxsts.b.bcnt);
 268
 269                         /* Update the HC fields for the next packet received. */
 270                         hc->xfer_count += grxsts.b.bcnt;
 271                         hc->xfer_buff += grxsts.b.bcnt;
 272                 }
 273
 274         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
 275         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
 276         case DWC_GRXSTS_PKTSTS_CH_HALTED:
 277                 /* Handled in interrupt, just ignore data */
 278                 break;
 279         default:
 280                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
 281                           grxsts.b.pktsts);
 282                 break;
 283         }
 284
 285         return 1;
 286 }
 287
 288 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 289  * data packets may be written to the FIFO for OUT transfers. More requests
 290  * may be written to the non-periodic request queue for IN transfers. This
 291  * interrupt is enabled only in Slave mode. */
 292 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 293 {
 294         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 295         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 296                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
 297         return 1;
 298 }
 299
 300 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 301  * packets may be written to the FIFO for OUT transfers. More requests may be
 302  * written to the periodic request queue for IN transfers. This interrupt is
 303  * enabled only in Slave mode. */
 304 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 305 {
 306         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
 307         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
 308                                        DWC_OTG_TRANSACTION_PERIODIC);
 309         return 1;
 310 }
 311
 312 extern inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd);
 313 /** There are multiple conditions that can cause a port interrupt. This function
 314  * determines which interrupt conditions have occurred and handles them
 315  * appropriately. */
 316 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 317 {
 318         int retval = 0;
 319         hprt0_data_t hprt0;
 320         hprt0_data_t hprt0_modify;
 321         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 322         struct usb_bus *bus = hcd_to_bus(hcd);
 323
 324         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 325         hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 326
 327         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
 328          * GINTSTS */
 329
 330         hprt0_modify.b.prtena = 0;
 331         hprt0_modify.b.prtconndet = 0;
 332         hprt0_modify.b.prtenchng = 0;
 333         hprt0_modify.b.prtovrcurrchng = 0;
 334
 335         /* Port Connect Detected
 336          * Set flag and clear if detected */
 337         if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
 338                 /* Dont modify port status if we are in hibernation state */
 339                 hprt0_modify.b.prtconndet = 1;
 340                 hprt0_modify.b.prtenchng = 1;
 341                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
 342                                 hprt0_modify.d32);
 343                 hprt0.d32 =
 344                     DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
 345                 return retval;
 346         }
 347
 348         if (hprt0.b.prtconndet) {
 349                 /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
 350                 if (dwc_otg_hcd->core_if->adp_enable &&
 351                     dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
 352                         DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
 353                         DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.
 354                                          vbuson_timer);
 355                         dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 356                         /* TODO - check if this is required, as
 357                          * host initialization was already performed
 358                          * after initial ADP probing
 359                          */
 360                         /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
 361                            dwc_otg_core_init(dwc_otg_hcd->core_if);
 362                            dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
 363                            cil_hcd_start(dwc_otg_hcd->core_if); */
 364                 } else {
 365                         hprt0_data_t hprt0_local;
 366                         /* check if root hub is in suspend state
 367                          * if root hub in suspend, resume it.
 368                          */
 369                         if ((bus->root_hub)
 370                             && (hcd->state == HC_STATE_SUSPENDED)) {
 371                                 DWC_PRINTF
 372                                     ("%s: hcd->state = %d, hcd->flags = %ld\n",
 373                                      __func__, hcd->state, hcd->flags);
 374                                 usb_hcd_resume_root_hub(hcd);
 375                         }
 376                         DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
 377                                     "Port Connect Detected--\n", hprt0.d32);
 378                         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 379                         dwc_otg_hcd->flags.b.port_connect_status = 1;
 380                         hprt0_modify.b.prtconndet = 1;
 381                         /* PET testing */
 382                         if (dwc_otg_hcd->core_if->otg_ver
 383                             && (dwc_otg_hcd->core_if->test_mode == 7)) {
 384                                 hprt0_local.d32 =
 385                                     dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 386                                 hprt0_local.b.prtrst = 1;
 387                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->
 388                                                 hprt0, hprt0_local.d32);
 389                                 dwc_mdelay(60);
 390                                 hprt0.d32 =
 391                                     dwc_otg_read_hprt0(dwc_otg_hcd->core_if);
 392                                 hprt0.b.prtrst = 0;
 393                                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->
 394                                                 hprt0, hprt0.d32);
 395                         }
 396
 397                         /* B-Device has connected, Delete the connection timer. */
 398                         DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
 399                 }
 400                 /* The Hub driver asserts a reset when it sees port connect
 401                  * status change flag */
 402                 retval |= 1;
 403         }
 404
 405         /* Port Enable Changed
 406          * Clear if detected - Set internal flag if disabled */
 407         if (hprt0.b.prtenchng) {
 408                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 409                             "Port Enable Changed--\n", hprt0.d32);
 410                 hprt0_modify.b.prtenchng = 1;
 411                 if (hprt0.b.prtena == 1) {
 412                         hfir_data_t hfir;
 413                         int do_reset = 0;
 414                         dwc_otg_core_params_t *params =
 415                             dwc_otg_hcd->core_if->core_params;
 416                         dwc_otg_core_global_regs_t *global_regs =
 417                             dwc_otg_hcd->core_if->core_global_regs;
 418                         dwc_otg_host_if_t *host_if =
 419                             dwc_otg_hcd->core_if->host_if;
 420
 421                         /* Every time when port enables calculate
 422                          * HFIR.FrInterval
 423                          */
 424                         hfir.d32 =
 425                             DWC_READ_REG32(&host_if->host_global_regs->hfir);
 426                         hfir.b.frint =
 427                             calc_frame_interval(dwc_otg_hcd->core_if);
 428                         DWC_WRITE_REG32(&host_if->host_global_regs->hfir,
 429                                         hfir.d32);
 430
 431                         /* Check if we need to adjust the PHY clock speed for
 432                          * low power and adjust it */
 433                         if (params->host_support_fs_ls_low_power) {
 434                                 gusbcfg_data_t usbcfg;
 435
 436                                 usbcfg.d32 =
 437                                     DWC_READ_REG32(&global_regs->gusbcfg);
 438
 439                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
 440                                     || hprt0.b.prtspd ==
 441                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
 442                                         /*
 443                                          * Low power
 444                                          */
 445                                         hcfg_data_t hcfg;
 446                                         if (usbcfg.b.phylpwrclksel == 0) {
 447                                                 /* Set PHY low power clock select for FS/LS devices */
 448                                                 usbcfg.b.phylpwrclksel = 1;
 449                                                 DWC_WRITE_REG32
 450                                                     (&global_regs->gusbcfg,
 451                                                      usbcfg.d32);
 452                                                 do_reset = 1;
 453                                         }
 454
 455                                         hcfg.d32 =
 456                                             DWC_READ_REG32
 457                                             (&host_if->host_global_regs->hcfg);
 458
 459                                         if (hprt0.b.prtspd ==
 460                                             DWC_HPRT0_PRTSPD_LOW_SPEED
 461                                             && params->host_ls_low_power_phy_clk
 462                                             ==
 463                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 464                                                 /* 6 MHZ */
 465                                                 DWC_DEBUGPL(DBG_CIL,
 466                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
 467                                                 if (hcfg.b.fslspclksel !=
 468                                                     DWC_HCFG_6_MHZ) {
 469                                                         hcfg.b.fslspclksel =
 470                                                             DWC_HCFG_6_MHZ;
 471                                                         DWC_WRITE_REG32
 472                                                             (&host_if->
 473                                                              host_global_regs->
 474                                                              hcfg, hcfg.d32);
 475                                                         do_reset = 1;
 476                                                 }
 477                                         } else {
 478                                                 /* 48 MHZ */
 479                                                 DWC_DEBUGPL(DBG_CIL,
 480                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
 481                                                 if (hcfg.b.fslspclksel !=
 482                                                     DWC_HCFG_48_MHZ) {
 483                                                         hcfg.b.fslspclksel =
 484                                                             DWC_HCFG_48_MHZ;
 485                                                         DWC_WRITE_REG32
 486                                                             (&host_if->
 487                                                              host_global_regs->
 488                                                              hcfg, hcfg.d32);
 489                                                         do_reset = 1;
 490                                                 }
 491                                         }
 492                                 } else {
 493                                         /*
 494                                          * Not low power
 495                                          */
 496                                         if (usbcfg.b.phylpwrclksel == 1) {
 497                                                 usbcfg.b.phylpwrclksel = 0;
 498                                                 DWC_WRITE_REG32
 499                                                     (&global_regs->gusbcfg,
 500                                                      usbcfg.d32);
 501                                                 do_reset = 1;
 502                                         }
 503                                 }
 504
 505                                 if (do_reset) {
 506                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->
 507                                                           reset_tasklet);
 508                                 }
 509                         }
 510
 511                         if (!do_reset) {
 512                                 /* Port has been enabled set the reset change flag */
 513                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
 514                         }
 515                 } else {
 516                         dwc_otg_hcd->flags.b.port_enable_change = 1;
 517                 }
 518                 retval |= 1;
 519         }
 520
 521         /** Overcurrent Change Interrupt */
 522         if (hprt0.b.prtovrcurrchng) {
 523                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 524                             "Port Overcurrent Changed--\n", hprt0.d32);
 525                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
 526                 hprt0_modify.b.prtovrcurrchng = 1;
 527                 retval |= 1;
 528         }
 529
 530         /* Clear Port Interrupts */
 531         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 532
 533         return retval;
 534 }
 535
 536 /** This interrupt indicates that one or more host channels has a pending
 537  * interrupt. There are multiple conditions that can cause each host channel
 538  * interrupt. This function determines which conditions have occurred for each
 539  * host channel interrupt and handles them appropriately. */
 540 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd)
 541 {
 542         int i;
 543         int retval = 0;
 544         haint_data_t haint;
 545
 546         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
 547          * GINTSTS */
 548
 549         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
 550
 551         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
 552                 if (haint.b2.chint & (1 << i)) {
 553                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
 554                 }
 555         }
 556
 557         return retval;
 558 }
 559
 560 /**
 561  * Gets the actual length of a transfer after the transfer halts. _halt_status
 562  * holds the reason for the halt.
 563  *
 564  * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
 565  * *short_read is set to 1 upon return if less than the requested
 566  * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
 567  * return. short_read may also be NULL on entry, in which case it remains
 568  * unchanged.
 569  */
 570 static uint32_t get_actual_xfer_length(dwc_hc_t *hc,
 571                                        dwc_otg_hc_regs_t *hc_regs,
 572                                        dwc_otg_qtd_t *qtd,
 573                                        dwc_otg_halt_status_e halt_status,
 574                                        int *short_read)
 575 {
 576         hctsiz_data_t hctsiz;
 577         uint32_t length;
 578
 579         if (short_read != NULL) {
 580                 *short_read = 0;
 581         }
 582         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 583
 584         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
 585                 if (hc->ep_is_in) {
 586                         length = hc->xfer_len - hctsiz.b.xfersize;
 587                         if (short_read != NULL) {
 588                                 *short_read = (hctsiz.b.xfersize != 0);
 589                         }
 590                 } else if (hc->qh->do_split) {
 591                         length = qtd->ssplit_out_xfer_count;
 592                 } else {
 593                         length = hc->xfer_len;
 594                 }
 595         } else {
 596                 /*
 597                  * Must use the hctsiz.pktcnt field to determine how much data
 598                  * has been transferred. This field reflects the number of
 599                  * packets that have been transferred via the USB. This is
 600                  * always an integral number of packets if the transfer was
 601                  * halted before its normal completion. (Can't use the
 602                  * hctsiz.xfersize field because that reflects the number of
 603                  * bytes transferred via the AHB, not the USB).
 604                  */
 605                 length =
 606                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
 607         }
 608
 609         return length;
 610 }
 611
 612 /**
 613  * Updates the state of the URB after a Transfer Complete interrupt on the
 614  * host channel. Updates the actual_length field of the URB based on the
 615  * number of bytes transferred via the host channel. Sets the URB status
 616  * if the data transfer is finished.
 617  *
 618  * @return 1 if the data transfer specified by the URB is completely finished,
 619  * 0 otherwise.
 620  */
 621 static int update_urb_state_xfer_comp(dwc_hc_t *hc,
 622                                       dwc_otg_hc_regs_t *hc_regs,
 623                                       dwc_otg_hcd_urb_t *urb,
 624                                       dwc_otg_qtd_t *qtd)
 625 {
 626         int xfer_done = 0;
 627         int short_read = 0;
 628
 629         int xfer_length;
 630
 631         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
 632                                              DWC_OTG_HC_XFER_COMPLETE,
 633                                              &short_read);
 634
 635         /* non DWORD-aligned buffer case handling. */
 636         if (hc->align_buff && xfer_length && hc->ep_is_in) {
 637                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
 638                            xfer_length);
 639         }
 640
 641         urb->actual_length += xfer_length;
 642
 643         if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
 644             (urb->flags & URB_SEND_ZERO_PACKET)
 645             && (urb->actual_length == urb->length)
 646             && !(urb->length % hc->max_packet)) {
 647                 xfer_done = 0;
 648         } else if (short_read || urb->actual_length >= urb->length) {
 649                 xfer_done = 1;
 650                 urb->status = 0;
 651         }
 652 #ifdef DEBUG
 653         {
 654                 hctsiz_data_t hctsiz;
 655                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 656                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
 657                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
 658                             hc->hc_num);
 659                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
 660                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
 661                             hctsiz.b.xfersize);
 662                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
 663                             urb->length);
 664                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
 665                             urb->actual_length);
 666                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
 667                             short_read, xfer_done);
 668         }
 669 #endif
 670
 671         return xfer_done;
 672 }
 673
 674 /*
 675  * Save the starting data toggle for the next transfer. The data toggle is
 676  * saved in the QH for non-control transfers and it's saved in the QTD for
 677  * control transfers.
 678  */
 679 void dwc_otg_hcd_save_data_toggle(dwc_hc_t *hc,
 680                                   dwc_otg_hc_regs_t *hc_regs,
 681                                   dwc_otg_qtd_t *qtd)
 682 {
 683         hctsiz_data_t hctsiz;
 684         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
 685
 686         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
 687                 dwc_otg_qh_t *qh = hc->qh;
 688                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 689                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 690                 } else {
 691                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
 692                 }
 693         } else {
 694                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 695                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
 696                 } else {
 697                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
 698                 }
 699         }
 700 }
 701
 702 /**
 703  * Updates the state of an Isochronous URB when the transfer is stopped for
 704  * any reason. The fields of the current entry in the frame descriptor array
 705  * are set based on the transfer state and the input _halt_status. Completes
 706  * the Isochronous URB if all the URB frames have been completed.
 707  *
 708  * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
 709  * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
 710  */
 711 static dwc_otg_halt_status_e
 712 update_isoc_urb_state(dwc_otg_hcd_t *hcd,
 713                       dwc_hc_t *hc,
 714                       dwc_otg_hc_regs_t *hc_regs,
 715                       dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 716 {
 717         dwc_otg_hcd_urb_t *urb = qtd->urb;
 718         dwc_otg_halt_status_e ret_val = halt_status;
 719         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
 720
 721         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 722         switch (halt_status) {
 723         case DWC_OTG_HC_XFER_COMPLETE:
 724                 frame_desc->status = 0;
 725                 frame_desc->actual_length =
 726                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 727
 728                 /* non DWORD-aligned buffer case handling. */
 729                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 730                         dwc_memcpy(urb->buf + frame_desc->offset +
 731                                    qtd->isoc_split_offset, hc->qh->dw_align_buf,
 732                                    frame_desc->actual_length);
 733                 }
 734
 735                 break;
 736         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
 737                 urb->error_count++;
 738                 if (hc->ep_is_in) {
 739                         frame_desc->status = -DWC_E_NO_STREAM_RES;
 740                 } else {
 741                         frame_desc->status = -DWC_E_COMMUNICATION;
 742                 }
 743                 frame_desc->actual_length = 0;
 744                 break;
 745         case DWC_OTG_HC_XFER_BABBLE_ERR:
 746                 urb->error_count++;
 747                 frame_desc->status = -DWC_E_OVERFLOW;
 748                 /* Don't need to update actual_length in this case. */
 749                 break;
 750         case DWC_OTG_HC_XFER_XACT_ERR:
 751                 urb->error_count++;
 752                 frame_desc->status = -DWC_E_PROTOCOL;
 753                 frame_desc->actual_length =
 754                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
 755
 756                 /* non DWORD-aligned buffer case handling. */
 757                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
 758                         dwc_memcpy(urb->buf + frame_desc->offset +
 759                                    qtd->isoc_split_offset, hc->qh->dw_align_buf,
 760                                    frame_desc->actual_length);
 761                 }
 762                 /* Skip whole frame */
 763                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
 764                     hc->ep_is_in && hcd->core_if->dma_enable) {
 765                         qtd->complete_split = 0;
 766                         qtd->isoc_split_offset = 0;
 767                 }
 768
 769                 break;
 770         default:
 771                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
 772                 break;
 773         }
 774         if (++qtd->isoc_frame_index == urb->packet_count) {
 775                 /*
 776                  * urb->status is not used for isoc transfers.
 777                  * The individual frame_desc statuses are used instead.
 778                  */
 779                 hcd->fops->complete(hcd, urb->priv, urb, 0);
 780                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
 781         } else {
 782                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
 783         }
 784         return ret_val;
 785 }
 786
 787 /**
 788  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 789  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 790  * still linked to the QH, the QH is added to the end of the inactive
 791  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 792  * schedule if no more QTDs are linked to the QH.
 793  */
 794 static void deactivate_qh(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int free_qtd)
 795 {
 796         int continue_split = 0;
 797         dwc_otg_qtd_t *qtd;
 798
 799         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
 800
 801         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
 802
 803         if (qtd->complete_split) {
 804                 continue_split = 1;
 805         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
 806                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
 807                 continue_split = 1;
 808         }
 809
 810         if (free_qtd) {
 811                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
 812                 continue_split = 0;
 813         }
 814
 815         qh->channel = NULL;
 816         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
 817 }
 818
 819 /**
 820  * Releases a host channel for use by other transfers. Attempts to select and
 821  * queue more transactions since at least one host channel is available.
 822  *
 823  * @param hcd The HCD state structure.
 824  * @param hc The host channel to release.
 825  * @param qtd The QTD associated with the host channel. This QTD may be freed
 826  * if the transfer is complete or an error has occurred.
 827  * @param halt_status Reason the channel is being released. This status
 828  * determines the actions taken by this function.
 829  */
 830 static void release_channel(dwc_otg_hcd_t *hcd,
 831                             dwc_hc_t *hc,
 832                             dwc_otg_qtd_t *qtd,
 833                             dwc_otg_halt_status_e halt_status)
 834 {
 835         dwc_otg_transaction_type_e tr_type;
 836         int free_qtd;
 837
 838         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
 839                     __func__, hc->hc_num, halt_status);
 840
 841         if (halt_status != DWC_OTG_HC_XFER_URB_DEQUEUE) {
 842                 if (((uint32_t) qtd & 0xf0000000) == 0) {
 843                         DWC_PRINTF("%s error: qtd %p, status %d 0!!!\n",
 844                                    __func__, qtd, halt_status);
 845                         goto cleanup;
 846                 }
 847
 848                 if (((uint32_t) qtd & 0x80000000) == 0) {
 849                         DWC_PRINTF("%s error: qtd %p, status %d 1!!!\n",
 850                                    __func__, qtd, halt_status);
 851                         goto cleanup;
 852                 }
 853
 854                 if (((uint32_t) qtd->urb & 0xf0000000) == 0) {
 855                         DWC_PRINTF("%s qtd %p urb %p, status %d\n", __func__,
 856                                    qtd, qtd->urb, halt_status);
 857                         goto cleanup;
 858                 }
 859         }
 860
 861         switch (halt_status) {
 862         case DWC_OTG_HC_XFER_URB_COMPLETE:
 863                 free_qtd = 1;
 864                 break;
 865         case DWC_OTG_HC_XFER_AHB_ERR:
 866         case DWC_OTG_HC_XFER_STALL:
 867         case DWC_OTG_HC_XFER_BABBLE_ERR:
 868                 free_qtd = 1;
 869                 break;
 870         case DWC_OTG_HC_XFER_XACT_ERR:
 871                 if (qtd->error_count >= 3) {
 872                         DWC_DEBUGPL(DBG_HCDV,
 873                                     "  Complete URB with transaction error\n");
 874                         free_qtd = 1;
 875                         qtd->urb->status = -DWC_E_PROTOCOL;
 876                         hcd->fops->complete(hcd, qtd->urb->priv,
 877                                             qtd->urb, -DWC_E_PROTOCOL);
 878                 } else {
 879                         free_qtd = 0;
 880                 }
 881                 break;
 882         case DWC_OTG_HC_XFER_URB_DEQUEUE:
 883                 /*
 884                  * The QTD has already been removed and the QH has been
 885                  * deactivated. Don't want to do anything except release the
 886                  * host channel and try to queue more transfers.
 887                  */
 888                 goto cleanup;
 889         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
 890                 free_qtd = 0;
 891                 break;
 892         case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
 893                 DWC_DEBUGPL(DBG_HCDV, "  Complete URB with I/O error\n");
 894                 free_qtd = 1;
 895                 qtd->urb->status = -DWC_E_IO;
 896                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, -DWC_E_IO);
 897                 break;
 898         default:
 899                 free_qtd = 0;
 900                 break;
 901         }
 902
 903         deactivate_qh(hcd, hc->qh, free_qtd);
 904
 905 cleanup:
 906         /*
 907          * Release the host channel for use by other transfers. The cleanup
 908          * function clears the channel interrupt enables and conditions, so
 909          * there's no need to clear the Channel Halted interrupt separately.
 910          */
 911         dwc_otg_hc_cleanup(hcd->core_if, hc);
 912         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
 913
 914         switch (hc->ep_type) {
 915         case DWC_OTG_EP_TYPE_CONTROL:
 916         case DWC_OTG_EP_TYPE_BULK:
 917                 hcd->non_periodic_channels--;
 918                 break;
 919
 920         default:
 921                 /*
 922                  * Don't release reservations for periodic channels here.
 923                  * That's done when a periodic transfer is descheduled (i.e.
 924                  * when the QH is removed from the periodic schedule).
 925                  */
 926                 break;
 927         }
 928
 929         /* Try to queue more transfers now that there's a free channel. */
 930         tr_type = dwc_otg_hcd_select_transactions(hcd);
 931         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 932                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
 933         }
 934 }
 935
 936 /**
 937  * Halts a host channel. If the channel cannot be halted immediately because
 938  * the request queue is full, this function ensures that the FIFO empty
 939  * interrupt for the appropriate queue is enabled so that the halt request can
 940  * be queued when there is space in the request queue.
 941  *
 942  * This function may also be called in DMA mode. In that case, the channel is
 943  * simply released since the core always halts the channel automatically in
 944  * DMA mode.
 945  */
 946 static void halt_channel(dwc_otg_hcd_t *hcd,
 947                          dwc_hc_t *hc,
 948                          dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 949 {
 950         if (hcd->core_if->dma_enable) {
 951                 release_channel(hcd, hc, qtd, halt_status);
 952                 return;
 953         }
 954
 955         /* Slave mode processing... */
 956         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
 957
 958         if (hc->halt_on_queue) {
 959                 gintmsk_data_t gintmsk = {.d32 = 0 };
 960                 dwc_otg_core_global_regs_t *global_regs;
 961                 global_regs = hcd->core_if->core_global_regs;
 962
 963                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
 964                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
 965                         /*
 966                          * Make sure the Non-periodic Tx FIFO empty interrupt
 967                          * is enabled so that the non-periodic schedule will
 968                          * be processed.
 969                          */
 970                         gintmsk.b.nptxfempty = 1;
 971                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 972                 } else {
 973                         /*
 974                          * Move the QH from the periodic queued schedule to
 975                          * the periodic assigned schedule. This allows the
 976                          * halt to be queued when the periodic schedule is
 977                          * processed.
 978                          */
 979                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
 980                                            &hc->qh->qh_list_entry);
 981
 982                         /*
 983                          * Make sure the Periodic Tx FIFO Empty interrupt is
 984                          * enabled so that the periodic schedule will be
 985                          * processed.
 986                          */
 987                         gintmsk.b.ptxfempty = 1;
 988                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
 989                 }
 990         }
 991 }
 992
 993 /**
 994  * Performs common cleanup for non-periodic transfers after a Transfer
 995  * Complete interrupt. This function should be called after any endpoint type
 996  * specific handling is finished to release the host channel.
 997  */
 998 static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd,
 999                                        dwc_hc_t *hc,
1000                                        dwc_otg_hc_regs_t *hc_regs,
1001                                        dwc_otg_qtd_t *qtd,
1002                                        dwc_otg_halt_status_e halt_status)
1003 {
1004         hcint_data_t hcint;
1005
1006         qtd->error_count = 0;
1007
1008         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1009         if (hcint.b.nyet) {
1010                 /*
1011                  * Got a NYET on the last transaction of the transfer. This
1012                  * means that the endpoint should be in the PING state at the
1013                  * beginning of the next transfer.
1014                  */
1015                 hc->qh->ping_state = 1;
1016                 clear_hc_int(hc_regs, nyet);
1017         }
1018
1019         /*
1020          * Always halt and release the host channel to make it available for
1021          * more transfers. There may still be more phases for a control
1022          * transfer or more data packets for a bulk transfer at this point,
1023          * but the host channel is still halted. A channel will be reassigned
1024          * to the transfer when the non-periodic schedule is processed after
1025          * the channel is released. This allows transactions to be queued
1026          * properly via dwc_otg_hcd_queue_transactions, which also enables the
1027          * Tx FIFO Empty interrupt if necessary.
1028          */
1029         if (hc->ep_is_in) {
1030                 /*
1031                  * IN transfers in Slave mode require an explicit disable to
1032                  * halt the channel. (In DMA mode, this call simply releases
1033                  * the channel.)
1034                  */
1035                 halt_channel(hcd, hc, qtd, halt_status);
1036         } else {
1037                 /*
1038                  * The channel is automatically disabled by the core for OUT
1039                  * transfers in Slave mode.
1040                  */
1041                 release_channel(hcd, hc, qtd, halt_status);
1042         }
1043 }
1044
1045 /**
1046  * Performs common cleanup for periodic transfers after a Transfer Complete
1047  * interrupt. This function should be called after any endpoint type specific
1048  * handling is finished to release the host channel.
1049  */
1050 static void complete_periodic_xfer(dwc_otg_hcd_t *hcd,
1051                                    dwc_hc_t *hc,
1052                                    dwc_otg_hc_regs_t *hc_regs,
1053                                    dwc_otg_qtd_t *qtd,
1054                                    dwc_otg_halt_status_e halt_status)
1055 {
1056         hctsiz_data_t hctsiz;
1057         qtd->error_count = 0;
1058
1059         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1060         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
1061                 /* Core halts channel in these cases. */
1062                 release_channel(hcd, hc, qtd, halt_status);
1063         } else {
1064                 /* Flush any outstanding requests from the Tx queue. */
1065                 halt_channel(hcd, hc, qtd, halt_status);
1066         }
1067 }
1068
1069 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t *hcd,
1070                                              dwc_hc_t *hc,
1071                                              dwc_otg_hc_regs_t *hc_regs,
1072                                              dwc_otg_qtd_t *qtd)
1073 {
1074         uint32_t len;
1075         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1076         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
1077
1078         len = get_actual_xfer_length(hc, hc_regs, qtd,
1079                                      DWC_OTG_HC_XFER_COMPLETE, NULL);
1080
1081         if (!len) {
1082                 qtd->complete_split = 0;
1083                 qtd->isoc_split_offset = 0;
1084                 return 0;
1085         }
1086         frame_desc->actual_length += len;
1087
1088         if (hc->align_buff && len)
1089                 dwc_memcpy(qtd->urb->buf + frame_desc->offset +
1090                            qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
1091         qtd->isoc_split_offset += len;
1092
1093         if (frame_desc->length == frame_desc->actual_length) {
1094                 frame_desc->status = 0;
1095                 qtd->isoc_frame_index++;
1096                 qtd->complete_split = 0;
1097                 qtd->isoc_split_offset = 0;
1098         }
1099
1100         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
1101                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
1102                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
1103         } else {
1104                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
1105         }
1106
1107         return 1;               /* Indicates that channel released */
1108 }
1109
1110 /**
1111  * Handles a host channel Transfer Complete interrupt. This handler may be
1112  * called in either DMA mode or Slave mode.
1113  */
1114 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd,
1115                                        dwc_hc_t *hc,
1116                                        dwc_otg_hc_regs_t *hc_regs,
1117                                        dwc_otg_qtd_t *qtd)
1118 {
1119         int urb_xfer_done;
1120         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
1121         dwc_otg_hcd_urb_t *urb;
1122         int pipe_type;
1123
1124         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1125                     "Transfer Complete--\n", hc->hc_num);
1126
1127         if (((uint32_t) qtd & 0xf0000000) == 0) {
1128                 DWC_PRINTF("%s qtd %p\n", __func__, qtd);
1129                 release_channel(hcd, hc, qtd, hc->halt_status);
1130                 return 1;
1131         }
1132
1133         urb = qtd->urb;
1134         if (((uint32_t) urb & 0xf0000000) == 0) {
1135                 DWC_PRINTF("%s qtd %p, urb %p\n", __func__, qtd, urb);
1136                 release_channel(hcd, hc, qtd, hc->halt_status);
1137                 return 1;
1138         }
1139
1140         pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1141
1142         if (hcd->core_if->dma_desc_enable) {
1143                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
1144                 if (pipe_type == UE_ISOCHRONOUS) {
1145                         /* Do not disable the interrupt, just clear it */
1146                         clear_hc_int(hc_regs, xfercomp);
1147                         return 1;
1148                 }
1149                 goto handle_xfercomp_done;
1150         }
1151
1152         /*
1153          * Handle xfer complete on CSPLIT.
1154          */
1155
1156         if (hc->qh->do_split) {
1157                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
1158                     && hcd->core_if->dma_enable) {
1159                         if (qtd->complete_split
1160                             && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
1161                                                              qtd))
1162                                 goto handle_xfercomp_done;
1163                 } else {
1164                         qtd->complete_split = 0;
1165                 }
1166         }
1167
1168         /* Update the QTD and URB states. */
1169         switch (pipe_type) {
1170         case UE_CONTROL:
1171                 switch (qtd->control_phase) {
1172                 case DWC_OTG_CONTROL_SETUP:
1173                         if (urb->length > 0) {
1174                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
1175                         } else {
1176                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1177                         }
1178                         DWC_DEBUGPL(DBG_HCDV,
1179                                     "  Control setup transaction done\n");
1180                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1181                         break;
1182                 case DWC_OTG_CONTROL_DATA:{
1183                                 urb_xfer_done =
1184                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
1185                                                                qtd);
1186                                 if (urb_xfer_done) {
1187                                         qtd->control_phase =
1188                                             DWC_OTG_CONTROL_STATUS;
1189                                         DWC_DEBUGPL(DBG_HCDV,
1190                                                     "  Control data transfer done\n");
1191                                 } else {
1192                                         dwc_otg_hcd_save_data_toggle(hc,
1193                                                                      hc_regs,
1194                                                                      qtd);
1195                                 }
1196                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1197                                 break;
1198                         }
1199                 case DWC_OTG_CONTROL_STATUS:
1200                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
1201                         if (urb->status == -DWC_E_IN_PROGRESS) {
1202                                 urb->status = 0;
1203                         }
1204                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1205                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1206                         break;
1207                 }
1208
1209                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1210                 break;
1211         case UE_BULK:
1212                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
1213                 urb_xfer_done =
1214                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1215                 if (urb_xfer_done) {
1216                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1217                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1218                 } else {
1219                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1220                 }
1221
1222                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1223                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1224                 break;
1225         case UE_INTERRUPT:
1226                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
1227                 urb_xfer_done =
1228                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1229
1230                 /*
1231                  * Interrupt URB is done on the first transfer complete
1232                  * interrupt.
1233                  */
1234                 if (urb_xfer_done) {
1235                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
1236                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1237                 } else {
1238                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1239                 }
1240
1241                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1242                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1243                 break;
1244         case UE_ISOCHRONOUS:
1245                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
1246                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1247                         halt_status =
1248                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1249                                                   DWC_OTG_HC_XFER_COMPLETE);
1250                 }
1251                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1252                 break;
1253         }
1254
1255 handle_xfercomp_done:
1256         disable_hc_int(hc_regs, xfercompl);
1257
1258         return 1;
1259 }
1260
1261 /**
1262  * Handles a host channel STALL interrupt. This handler may be called in
1263  * either DMA mode or Slave mode.
1264  */
1265 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd,
1266                                     dwc_hc_t *hc,
1267                                     dwc_otg_hc_regs_t *hc_regs,
1268                                     dwc_otg_qtd_t *qtd)
1269 {
1270         dwc_otg_hcd_urb_t *urb = qtd->urb;
1271         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
1272
1273         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1274                     "STALL Received--\n", hc->hc_num);
1275
1276         if (hcd->core_if->dma_desc_enable) {
1277                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1278                                                DWC_OTG_HC_XFER_STALL);
1279                 goto handle_stall_done;
1280         }
1281
1282         if (pipe_type == UE_CONTROL) {
1283                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1284         }
1285
1286         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
1287                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
1288                 /*
1289                  * USB protocol requires resetting the data toggle for bulk
1290                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1291                  * setup command is issued to the endpoint. Anticipate the
1292                  * CLEAR_FEATURE command since a STALL has occurred and reset
1293                  * the data toggle now.
1294                  */
1295                 hc->qh->data_toggle = 0;
1296         }
1297
1298         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
1299
1300 handle_stall_done:
1301         disable_hc_int(hc_regs, stall);
1302
1303         return 1;
1304 }
1305
1306 /*
1307  * Updates the state of the URB when a transfer has been stopped due to an
1308  * abnormal condition before the transfer completes. Modifies the
1309  * actual_length field of the URB to reflect the number of bytes that have
1310  * actually been transferred via the host channel.
1311  */
1312 static void update_urb_state_xfer_intr(dwc_hc_t *hc,
1313                                        dwc_otg_hc_regs_t *hc_regs,
1314                                        dwc_otg_hcd_urb_t *urb,
1315                                        dwc_otg_qtd_t *qtd,
1316                                        dwc_otg_halt_status_e halt_status)
1317 {
1318         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
1319                                                             halt_status, NULL);
1320         /* non DWORD-aligned buffer case handling. */
1321         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
1322                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
1323                            bytes_transferred);
1324         }
1325
1326         urb->actual_length += bytes_transferred;
1327
1328 #ifdef DEBUG
1329         {
1330                 hctsiz_data_t hctsiz;
1331                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1332                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
1333                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
1334                             hc->hc_num);
1335                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
1336                             hc->start_pkt_count);
1337                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
1338                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
1339                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
1340                             bytes_transferred);
1341                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
1342                             urb->actual_length);
1343                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
1344                             urb->length);
1345         }
1346 #endif
1347 }
1348
1349 /**
1350  * Handles a host channel NAK interrupt. This handler may be called in either
1351  * DMA mode or Slave mode.
1352  */
1353 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd,
1354                                   dwc_hc_t *hc,
1355                                   dwc_otg_hc_regs_t *hc_regs,
1356                                   dwc_otg_qtd_t *qtd)
1357 {
1358         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1359                     "NAK Received--\n", hc->hc_num);
1360
1361         /*
1362          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1363          * interrupt.  Re-start the SSPLIT transfer.
1364          */
1365         if (hc->do_split) {
1366                 if (hc->complete_split) {
1367                         qtd->error_count = 0;
1368                 }
1369                 qtd->complete_split = 0;
1370                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1371                 goto handle_nak_done;
1372         }
1373
1374         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1375         case UE_CONTROL:
1376         case UE_BULK:
1377                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
1378                         /*
1379                          * NAK interrupts are enabled on bulk/control IN
1380                          * transfers in DMA mode for the sole purpose of
1381                          * resetting the error count after a transaction error
1382                          * occurs. The core will continue transferring data.
1383                          */
1384                         qtd->error_count = 0;
1385                         goto handle_nak_done;
1386                 }
1387
1388                 /*
1389                  * NAK interrupts normally occur during OUT transfers in DMA
1390                  * or Slave mode. For IN transfers, more requests will be
1391                  * queued as request queue space is available.
1392                  */
1393                 qtd->error_count = 0;
1394
1395                 if (!hc->qh->ping_state) {
1396                         update_urb_state_xfer_intr(hc, hc_regs,
1397                                                    qtd->urb, qtd,
1398                                                    DWC_OTG_HC_XFER_NAK);
1399                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1400
1401                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
1402                                 hc->qh->ping_state = 1;
1403                 }
1404
1405                 /*
1406                  * Halt the channel so the transfer can be re-started from
1407                  * the appropriate point or the PING protocol will
1408                  * start/continue.
1409                  */
1410                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1411                 break;
1412         case UE_INTERRUPT:
1413                 qtd->error_count = 0;
1414                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1415                 break;
1416         case UE_ISOCHRONOUS:
1417                 /* Should never get called for isochronous transfers. */
1418                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
1419                 break;
1420         }
1421
1422 handle_nak_done:
1423         disable_hc_int(hc_regs, nak);
1424
1425         return 1;
1426 }
1427
1428 /**
1429  * Handles a host channel ACK interrupt. This interrupt is enabled when
1430  * performing the PING protocol in Slave mode, when errors occur during
1431  * either Slave mode or DMA mode, and during Start Split transactions.
1432  */
1433 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd,
1434                                   dwc_hc_t *hc,
1435                                   dwc_otg_hc_regs_t *hc_regs,
1436                                   dwc_otg_qtd_t *qtd)
1437 {
1438         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1439                     "ACK Received--\n", hc->hc_num);
1440
1441         if (hc->do_split) {
1442                 /*
1443                  * Handle ACK on SSPLIT.
1444                  * ACK should not occur in CSPLIT.
1445                  */
1446                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
1447                         qtd->ssplit_out_xfer_count = hc->xfer_len;
1448                 }
1449                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
1450                         /* Don't need complete for isochronous out transfers. */
1451                         qtd->complete_split = 1;
1452                 }
1453
1454                 /* ISOC OUT */
1455                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1456                         switch (hc->xact_pos) {
1457                         case DWC_HCSPLIT_XACTPOS_ALL:
1458                                 break;
1459                         case DWC_HCSPLIT_XACTPOS_END:
1460                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
1461                                 qtd->isoc_split_offset = 0;
1462                                 break;
1463                         case DWC_HCSPLIT_XACTPOS_BEGIN:
1464                         case DWC_HCSPLIT_XACTPOS_MID:
1465                                 /*
1466                                  * For BEGIN or MID, calculate the length for
1467                                  * the next microframe to determine the correct
1468                                  * SSPLIT token, either MID or END.
1469                                  */
1470                                 {
1471                                         struct dwc_otg_hcd_iso_packet_desc
1472                                         *frame_desc;
1473
1474                                         frame_desc =
1475                                             &qtd->urb->iso_descs[qtd->
1476                                                                  isoc_frame_index];
1477                                         qtd->isoc_split_offset += 188;
1478
1479                                         if ((frame_desc->length -
1480                                              qtd->isoc_split_offset) <= 188) {
1481                                                 qtd->isoc_split_pos =
1482                                                     DWC_HCSPLIT_XACTPOS_END;
1483                                         } else {
1484                                                 qtd->isoc_split_pos =
1485                                                     DWC_HCSPLIT_XACTPOS_MID;
1486                                         }
1487
1488                                 }
1489                                 break;
1490                         }
1491                 } else {
1492                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1493                 }
1494         } else {
1495                 qtd->error_count = 0;
1496
1497                 if (hc->qh->ping_state) {
1498                         hc->qh->ping_state = 0;
1499                         /*
1500                          * Halt the channel so the transfer can be re-started
1501                          * from the appropriate point. This only happens in
1502                          * Slave mode. In DMA mode, the ping_state is cleared
1503                          * when the transfer is started because the core
1504                          * automatically executes the PING, then the transfer.
1505                          */
1506                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1507                 }
1508         }
1509
1510         /*
1511          * If the ACK occurred when _not_ in the PING state, let the channel
1512          * continue transferring data after clearing the error count.
1513          */
1514
1515         disable_hc_int(hc_regs, ack);
1516
1517         return 1;
1518 }
1519
1520 /**
1521  * Handles a host channel NYET interrupt. This interrupt should only occur on
1522  * Bulk and Control OUT endpoints and for complete split transactions. If a
1523  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1524  * handled in the xfercomp interrupt handler, not here. This handler may be
1525  * called in either DMA mode or Slave mode.
1526  */
1527 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd,
1528                                    dwc_hc_t *hc,
1529                                    dwc_otg_hc_regs_t *hc_regs,
1530                                    dwc_otg_qtd_t *qtd)
1531 {
1532         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1533                     "NYET Received--\n", hc->hc_num);
1534
1535         /*
1536          * NYET on CSPLIT
1537          * re-do the CSPLIT immediately on non-periodic
1538          */
1539         if (hc->do_split && hc->complete_split) {
1540                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
1541                     && hcd->core_if->dma_enable) {
1542                         qtd->complete_split = 0;
1543                         qtd->isoc_split_offset = 0;
1544                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
1545                                 hcd->fops->complete(hcd, qtd->urb->priv,
1546                                                     qtd->urb, 0);
1547                                 release_channel(hcd, hc, qtd,
1548                                                 DWC_OTG_HC_XFER_URB_COMPLETE);
1549                         } else
1550                                 release_channel(hcd, hc, qtd,
1551                                                 DWC_OTG_HC_XFER_NO_HALT_STATUS);
1552                         goto handle_nyet_done;
1553                 }
1554
1555                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1556                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1557                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
1558
1559                         if (dwc_full_frame_num(frnum) !=
1560                             dwc_full_frame_num(hc->qh->sched_frame)) {
1561                                 /*
1562                                  * No longer in the same full speed frame.
1563                                  * Treat this as a transaction error.
1564                                  */
1565 #if 0
1566                                 /** @todo Fix system performance so this can
1567                                  * be treated as an error. Right now complete
1568                                  * splits cannot be scheduled precisely enough
1569                                  * due to other system activity, so this error
1570                                  * occurs regularly in Slave mode.
1571                                  */
1572                                 qtd->error_count++;
1573 #endif
1574                                 qtd->complete_split = 0;
1575                                 halt_channel(hcd, hc, qtd,
1576                                              DWC_OTG_HC_XFER_XACT_ERR);
1577                                 /** @todo add support for isoc release */
1578                                 goto handle_nyet_done;
1579                         }
1580                 }
1581
1582                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1583                 goto handle_nyet_done;
1584         }
1585
1586         hc->qh->ping_state = 1;
1587         qtd->error_count = 0;
1588
1589         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
1590                                    DWC_OTG_HC_XFER_NYET);
1591         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1592
1593         /*
1594          * Halt the channel and re-start the transfer so the PING
1595          * protocol will start.
1596          */
1597         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1598
1599 handle_nyet_done:
1600         disable_hc_int(hc_regs, nyet);
1601         return 1;
1602 }
1603
1604 /**
1605  * Handles a host channel babble interrupt. This handler may be called in
1606  * either DMA mode or Slave mode.
1607  */
1608 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd,
1609                                      dwc_hc_t *hc,
1610                                      dwc_otg_hc_regs_t *hc_regs,
1611                                      dwc_otg_qtd_t *qtd)
1612 {
1613         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1614                     "Babble Error--\n", hc->hc_num);
1615
1616         if (hcd->core_if->dma_desc_enable) {
1617                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1618                                                DWC_OTG_HC_XFER_BABBLE_ERR);
1619                 goto handle_babble_done;
1620         }
1621
1622         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1623                 hcd->fops->complete(hcd, qtd->urb->priv,
1624                                     qtd->urb, -DWC_E_OVERFLOW);
1625                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
1626         } else {
1627                 dwc_otg_halt_status_e halt_status;
1628                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1629                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
1630                 halt_channel(hcd, hc, qtd, halt_status);
1631         }
1632
1633 handle_babble_done:
1634         disable_hc_int(hc_regs, bblerr);
1635         return 1;
1636 }
1637
1638 /**
1639  * Handles a host channel AHB error interrupt. This handler is only called in
1640  * DMA mode.
1641  */
1642 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd,
1643                                      dwc_hc_t *hc,
1644                                      dwc_otg_hc_regs_t *hc_regs,
1645                                      dwc_otg_qtd_t *qtd)
1646 {
1647         hcchar_data_t hcchar;
1648         hcsplt_data_t hcsplt;
1649         hctsiz_data_t hctsiz;
1650         uint32_t hcdma;
1651         char *pipetype, *speed;
1652
1653         dwc_otg_hcd_urb_t *urb = qtd->urb;
1654
1655         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1656                     "AHB Error--\n", hc->hc_num);
1657
1658         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1659         hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1660         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1661         hcdma = DWC_READ_REG32(&hc_regs->hcdma);
1662
1663         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
1664         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1665         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1666         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
1667         DWC_ERROR("  Device address: %d\n",
1668                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
1669         DWC_ERROR("  Endpoint: %d, %s\n",
1670                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
1671                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
1672
1673         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1674         case UE_CONTROL:
1675                 pipetype = "CONTROL";
1676                 break;
1677         case UE_BULK:
1678                 pipetype = "BULK";
1679                 break;
1680         case UE_INTERRUPT:
1681                 pipetype = "INTERRUPT";
1682                 break;
1683         case UE_ISOCHRONOUS:
1684                 pipetype = "ISOCHRONOUS";
1685                 break;
1686         default:
1687                 pipetype = "UNKNOWN";
1688                 break;
1689         }
1690
1691         DWC_ERROR("  Endpoint type: %s\n", pipetype);
1692
1693         switch (hc->speed) {
1694         case DWC_OTG_EP_SPEED_HIGH:
1695                 speed = "HIGH";
1696                 break;
1697         case DWC_OTG_EP_SPEED_FULL:
1698                 speed = "FULL";
1699                 break;
1700         case DWC_OTG_EP_SPEED_LOW:
1701                 speed = "LOW";
1702                 break;
1703         default:
1704                 speed = "UNKNOWN";
1705                 break;
1706         };
1707
1708         DWC_ERROR("  Speed: %s\n", speed);
1709
1710         DWC_ERROR("  Max packet size: %d\n",
1711                   dwc_otg_hcd_get_mps(&urb->pipe_info));
1712         DWC_ERROR("  Data buffer length: %d\n", urb->length);
1713         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
1714                   urb->buf, (void *)urb->dma);
1715         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
1716                   urb->setup_packet, (void *)urb->setup_dma);
1717         DWC_ERROR("  Interval: %d\n", urb->interval);
1718
1719         /* Core haltes the channel for Descriptor DMA mode */
1720         if (hcd->core_if->dma_desc_enable) {
1721                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1722                                                DWC_OTG_HC_XFER_AHB_ERR);
1723                 goto handle_ahberr_done;
1724         }
1725
1726         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
1727
1728         /*
1729          * Force a channel halt. Don't call halt_channel because that won't
1730          * write to the HCCHARn register in DMA mode to force the halt.
1731          */
1732         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
1733 handle_ahberr_done:
1734         disable_hc_int(hc_regs, ahberr);
1735         return 1;
1736 }
1737
1738 /**
1739  * Handles a host channel transaction error interrupt. This handler may be
1740  * called in either DMA mode or Slave mode.
1741  */
1742 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd,
1743                                       dwc_hc_t *hc,
1744                                       dwc_otg_hc_regs_t *hc_regs,
1745                                       dwc_otg_qtd_t *qtd)
1746 {
1747         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1748                     "Transaction Error--\n", hc->hc_num);
1749
1750         if (hcd->core_if->dma_desc_enable) {
1751                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1752                                                DWC_OTG_HC_XFER_XACT_ERR);
1753                 goto handle_xacterr_done;
1754         }
1755
1756         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1757         case UE_CONTROL:
1758         case UE_BULK:
1759                 qtd->error_count++;
1760                 if (!hc->qh->ping_state) {
1761
1762                         update_urb_state_xfer_intr(hc, hc_regs,
1763                                                    qtd->urb, qtd,
1764                                                    DWC_OTG_HC_XFER_XACT_ERR);
1765                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1766                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
1767                                 hc->qh->ping_state = 1;
1768                         }
1769                 }
1770
1771                 /*
1772                  * Halt the channel so the transfer can be re-started from
1773                  * the appropriate point or the PING protocol will start.
1774                  */
1775                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1776                 break;
1777         case UE_INTERRUPT:
1778                 qtd->error_count++;
1779                 if (hc->do_split && hc->complete_split) {
1780                         qtd->complete_split = 0;
1781                 }
1782                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1783                 break;
1784         case UE_ISOCHRONOUS:
1785                 {
1786                         dwc_otg_halt_status_e halt_status;
1787                         halt_status =
1788                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1789                                                   DWC_OTG_HC_XFER_XACT_ERR);
1790
1791                         halt_channel(hcd, hc, qtd, halt_status);
1792                 }
1793                 break;
1794         }
1795 handle_xacterr_done:
1796         disable_hc_int(hc_regs, xacterr);
1797
1798         return 1;
1799 }
1800
1801 /**
1802  * Handles a host channel frame overrun interrupt. This handler may be called
1803  * in either DMA mode or Slave mode.
1804  */
1805 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd,
1806                                        dwc_hc_t *hc,
1807                                        dwc_otg_hc_regs_t *hc_regs,
1808                                        dwc_otg_qtd_t *qtd)
1809 {
1810         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1811                     "Frame Overrun--\n", hc->hc_num);
1812
1813         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1814         case UE_CONTROL:
1815         case UE_BULK:
1816                 break;
1817         case UE_INTERRUPT:
1818                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
1819                 break;
1820         case UE_ISOCHRONOUS:
1821                 {
1822                         dwc_otg_halt_status_e halt_status;
1823                         halt_status =
1824                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1825                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
1826
1827                         halt_channel(hcd, hc, qtd, halt_status);
1828                 }
1829                 break;
1830         }
1831
1832         disable_hc_int(hc_regs, frmovrun);
1833
1834         return 1;
1835 }
1836
1837 /**
1838  * Handles a host channel data toggle error interrupt. This handler may be
1839  * called in either DMA mode or Slave mode.
1840  */
1841 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd,
1842                                          dwc_hc_t *hc,
1843                                          dwc_otg_hc_regs_t *hc_regs,
1844                                          dwc_otg_qtd_t *qtd)
1845 {
1846         DWC_ERROR("--Host Channel %d Interrupt: "
1847                   "Data Toggle Error--\n", hc->hc_num);
1848         if (!hcd->flags.b.port_connect_status) {
1849                 /* No longer connected. */
1850                 DWC_ERROR("Not connected\n");
1851                 return 1;
1852         }
1853         if (hc->ep_is_in) {
1854                 qtd->error_count += 3;  /* Complete the error URB immediately */
1855         } else {
1856                 DWC_ERROR("Data Toggle Error on OUT transfer,"
1857                           "channel %d\n", hc->hc_num);
1858         }
1859         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
1860         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1861         clear_hc_int(hc_regs, chhltd);
1862
1863         return 1;
1864 }
1865
1866 #ifdef DEBUG
1867 /**
1868  * This function is for debug only. It checks that a valid halt status is set
1869  * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1870  * taken and a warning is issued.
1871  * @return 1 if halt status is ok, 0 otherwise.
1872  */
1873 static inline int halt_status_ok(dwc_otg_hcd_t *hcd,
1874                                  dwc_hc_t *hc,
1875                                  dwc_otg_hc_regs_t *hc_regs,
1876                                  dwc_otg_qtd_t *qtd)
1877 {
1878         hcchar_data_t hcchar;
1879         hctsiz_data_t hctsiz;
1880         hcint_data_t hcint;
1881         hcintmsk_data_t hcintmsk;
1882         hcsplt_data_t hcsplt;
1883
1884         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
1885                 /*
1886                  * This code is here only as a check. This condition should
1887                  * never happen. Ignore the halt if it does occur.
1888                  */
1889                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1890                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
1891                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1892                 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1893                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
1894                 DWC_WARN
1895                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
1896                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1897                      "hcint 0x%08x, hcintmsk 0x%08x, "
1898                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
1899                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
1900                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
1901
1902                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1903                          __func__, hc->hc_num);
1904                 DWC_WARN("\n");
1905                 clear_hc_int(hc_regs, chhltd);
1906                 return 0;
1907         }
1908
1909         /*
1910          * This code is here only as a check. hcchar.chdis should
1911          * never be set when the halt interrupt occurs. Halt the
1912          * channel again if it does occur.
1913          */
1914         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1915         if (hcchar.b.chdis) {
1916                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1917                          "hcchar 0x%08x, trying to halt again\n",
1918                          __func__, hcchar.d32);
1919                 clear_hc_int(hc_regs, chhltd);
1920                 hc->halt_pending = 0;
1921                 halt_channel(hcd, hc, qtd, hc->halt_status);
1922                 return 0;
1923         }
1924
1925         return 1;
1926 }
1927 #endif
1928
1929 /**
1930  * Handles a host Channel Halted interrupt in DMA mode. This handler
1931  * determines the reason the channel halted and proceeds accordingly.
1932  */
1933 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
1934                                       dwc_hc_t *hc,
1935                                       dwc_otg_hc_regs_t *hc_regs,
1936                                       dwc_otg_qtd_t *qtd)
1937 {
1938         hcint_data_t hcint;
1939         hcintmsk_data_t hcintmsk;
1940         int out_nak_enh = 0;
1941
1942         /* For core with OUT NAK enhancement, the flow for high-
1943          * speed CONTROL/BULK OUT is handled a little differently.
1944          */
1945         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
1946                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1947                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1948                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1949                         out_nak_enh = 1;
1950                 }
1951         }
1952
1953         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1954             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
1955              && !hcd->core_if->dma_desc_enable)) {
1956                 /*
1957                  * Just release the channel. A dequeue can happen on a
1958                  * transfer timeout. In the case of an AHB Error, the channel
1959                  * was forced to halt because there's no way to gracefully
1960                  * recover.
1961                  */
1962                 if (hcd->core_if->dma_desc_enable)
1963                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
1964                                                        hc->halt_status);
1965                 else
1966                         release_channel(hcd, hc, qtd, hc->halt_status);
1967                 return;
1968         }
1969
1970         /* Read the HCINTn register to determine the cause for the halt. */
1971         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1972         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
1973
1974         if (hcint.b.xfercomp) {
1975                 /** @todo This is here because of a possible hardware bug.  Spec
1976                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1977                  * interrupt w/ACK bit set should occur, but I only see the
1978                  * XFERCOMP bit, even with it masked out.  This is a workaround
1979                  * for that behavior.  Should fix this when hardware is fixed.
1980                  */
1981                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1982                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1983                 }
1984                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1985         } else if (hcint.b.stall) {
1986                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1987         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
1988                 if (out_nak_enh) {
1989                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1990                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
1991                                 qtd->error_count = 0;
1992                         } else {
1993                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
1994                         }
1995                 }
1996
1997                 /*
1998                  * Must handle xacterr before nak or ack. Could get a xacterr
1999                  * at the same time as either of these on a BULK/CONTROL OUT
2000                  * that started with a PING. The xacterr takes precedence.
2001                  */
2002                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
2003         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
2004                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
2005         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
2006                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
2007         } else if (hcint.b.bblerr) {
2008                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
2009         } else if (hcint.b.frmovrun) {
2010                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
2011         } else if (hcint.b.datatglerr) {
2012                 handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
2013         } else if (!out_nak_enh) {
2014                 if (hcint.b.nyet) {
2015                         /*
2016                          * Must handle nyet before nak or ack. Could get a nyet at the
2017                          * same time as either of those on a BULK/CONTROL OUT that
2018                          * started with a PING. The nyet takes precedence.
2019                          */
2020                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
2021                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
2022                         /*
2023                          * If nak is not masked, it's because a non-split IN transfer
2024                          * is in an error state. In that case, the nak is handled by
2025                          * the nak interrupt handler, not here. Handle nak here for
2026                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
2027                          * rewinding the buffer pointer.
2028                          */
2029                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
2030                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
2031                         /*
2032                          * If ack is not masked, it's because a non-split IN transfer
2033                          * is in an error state. In that case, the ack is handled by
2034                          * the ack interrupt handler, not here. Handle ack here for
2035                          * split transfers. Start splits halt on ACK.
2036                          */
2037                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
2038                 } else {
2039                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2040                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2041                                 /*
2042                                  * A periodic transfer halted with no other channel
2043                                  * interrupts set. Assume it was halted by the core
2044                                  * because it could not be completed in its scheduled
2045                                  * (micro)frame.
2046                                  */
2047 #ifdef DEBUG
2048                                 DWC_PRINTF
2049                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
2050                                      __func__, hc->hc_num);
2051 #endif
2052                                 halt_channel(hcd, hc, qtd,
2053                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
2054                         } else {
2055                                 DWC_ERROR
2056                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
2057                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
2058                                      __func__, hc->hc_num, hcint.d32,
2059                                      DWC_READ_REG32(&hcd->core_if->
2060                                                     core_global_regs->gintsts));
2061                                 clear_hc_int(hc_regs, chhltd);
2062                         }
2063
2064                 }
2065         } else {
2066                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
2067                            hcint.d32);
2068                 if (!hcint.b.nyet && !hcint.b.nak && !hcint.b.ack)
2069                         clear_hc_int(hc_regs, chhltd);
2070         }
2071 }
2072
2073 /**
2074  * Handles a host channel Channel Halted interrupt.
2075  *
2076  * In slave mode, this handler is called only when the driver specifically
2077  * requests a halt. This occurs during handling other host channel interrupts
2078  * (e.g. nak, xacterr, stall, nyet, etc.).
2079  *
2080  * In DMA mode, this is the interrupt that occurs when the core has finished
2081  * processing a transfer on a channel. Other host channel interrupts (except
2082  * ahberr) are disabled in DMA mode.
2083  */
2084 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd,
2085                                      dwc_hc_t *hc,
2086                                      dwc_otg_hc_regs_t *hc_regs,
2087                                      dwc_otg_qtd_t *qtd)
2088 {
2089         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
2090                     "Channel Halted--\n", hc->hc_num);
2091
2092         if (hcd->core_if->dma_enable) {
2093                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
2094         } else {
2095 #ifdef DEBUG
2096                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
2097                         return 1;
2098                 }
2099 #endif
2100                 release_channel(hcd, hc, qtd, hc->halt_status);
2101         }
2102
2103         return 1;
2104 }
2105
2106 /** Handles interrupt for a specific Host Channel */
2107 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
2108 {
2109         int retval = 0;
2110         hcint_data_t hcint;
2111         hcintmsk_data_t hcintmsk;
2112         dwc_hc_t *hc;
2113         dwc_otg_hc_regs_t *hc_regs;
2114         dwc_otg_qtd_t *qtd;
2115
2116         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
2117
2118         hc = dwc_otg_hcd->hc_ptr_array[num];
2119         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
2120         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
2121
2122         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2123         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
2124         DWC_DEBUGPL(DBG_HCDV,
2125                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2126                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
2127         hcint.d32 = hcint.d32 & hcintmsk.d32;
2128
2129         if (!dwc_otg_hcd->core_if->dma_enable) {
2130                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
2131                         hcint.b.chhltd = 0;
2132                 }
2133         }
2134
2135         if (hcint.b.chhltd) {
2136                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2137         }
2138         if (hcint.b.xfercomp) {
2139                 retval |=
2140                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2141                 /*
2142                  * If NYET occurred at same time as Xfer Complete, the NYET is
2143                  * handled by the Xfer Complete interrupt handler. Don't want
2144                  * to call the NYET interrupt handler in this case.
2145                  */
2146                 hcint.b.nyet = 0;
2147         }
2148         if (hcint.b.ahberr) {
2149                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2150         }
2151         if (hcint.b.stall) {
2152                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2153         }
2154         if (hcint.b.nak) {
2155                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2156         }
2157         if (hcint.b.ack) {
2158                 if (!hcint.b.chhltd)
2159                         retval |=
2160                             handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2161         }
2162         if (hcint.b.nyet) {
2163                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2164         }
2165         if (hcint.b.xacterr) {
2166                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2167         }
2168         if (hcint.b.bblerr) {
2169                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2170         }
2171         if (hcint.b.frmovrun) {
2172                 retval |=
2173                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2174         }
2175         if (hcint.b.datatglerr) {
2176                 retval |=
2177                     handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
2178         }
2179
2180         return retval;
2181 }
2182
2183 #endif /* DWC_DEVICE_ONLY */