1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
34 #if !defined(__DWC_CIL_H__)
37 #include "common_port/dwc_list.h"
38 #include "dwc_otg_dbg.h"
39 #include "dwc_otg_regs.h"
41 #include "dwc_otg_core_if.h"
42 #include "dwc_otg_adp.h"
46 * This file contains the interface to the Core Interface Layer.
51 #define MAX_DMA_DESCS_PER_EP 256
54 * Enumeration for the data buffer mode
56 typedef enum _data_buffer_mode {
57 BM_STANDARD = 0, /* data buffer is in normal mode */
58 BM_SG = 1, /* data buffer uses the scatter/gather mode */
59 BM_CONCAT = 2, /* data buffer uses the concatenation mode */
60 BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */
61 BM_ALIGN = 4 /* data buffer is in buffer alignment mode */
65 /** Macros defined for DWC OTG HW Release version */
67 #define OTG_CORE_REV_2_60a 0x4F54260A
68 #define OTG_CORE_REV_2_71a 0x4F54271A
69 #define OTG_CORE_REV_2_72a 0x4F54272A
70 #define OTG_CORE_REV_2_80a 0x4F54280A
71 #define OTG_CORE_REV_2_81a 0x4F54281A
72 #define OTG_CORE_REV_2_90a 0x4F54290A
73 #define OTG_CORE_REV_2_91a 0x4F54291A
74 #define OTG_CORE_REV_2_92a 0x4F54292A
75 #define OTG_CORE_REV_2_93a 0x4F54293A
76 #define OTG_CORE_REV_2_94a 0x4F54294A
77 #define OTG_CORE_REV_3_00a 0x4F54300A
78 #define OTG_CORE_REV_3_10a 0x4F54310A
81 * Information for each ISOC packet.
83 typedef struct iso_pkt_info {
90 * The <code>dwc_ep</code> structure represents the state of a single
91 * endpoint when acting in device mode. It contains the data items
92 * needed for an endpoint to be activated and transfer packets.
94 typedef struct dwc_ep {
95 /** EP number used for register address lookup */
97 /** EP direction 0 = OUT */
103 * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
104 * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
105 unsigned tx_fifo_num:4;
106 /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */
108 #define DWC_OTG_EP_TYPE_CONTROL 0
109 #define DWC_OTG_EP_TYPE_ISOC 1
110 #define DWC_OTG_EP_TYPE_BULK 2
111 #define DWC_OTG_EP_TYPE_INTR 3
113 /** DATA start PID for INTR and BULK EP */
114 unsigned data_pid_start:1;
115 /** Frame (even/odd) for ISOC EP */
116 unsigned even_odd_frame:1;
117 /** Max Packet bytes */
118 unsigned maxpacket:11;
120 /** Max Transfer size */
123 /** @name Transfer state */
127 * Pointer to the beginning of the transfer buffer -- do not modify
133 dwc_dma_t dma_desc_addr;
134 dwc_otg_dev_dma_desc_t *desc_addr;
136 uint8_t *start_xfer_buff;
137 /** pointer to the transfer buffer */
139 /** Number of bytes to transfer */
140 unsigned xfer_len:19;
141 /** Number of bytes transferred. */
142 unsigned xfer_count:19;
145 /** Total len for control transfer */
146 unsigned total_len:19;
148 /** stall clear flag */
149 unsigned stall_clear_flag:1;
151 /** SETUP pkt cnt rollover flag for EP0 out*/
152 unsigned stp_rollover;
155 /* The buffer mode */
156 data_buffer_mode_e buff_mode;
158 /* The chain of DMA descriptors.
159 * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
161 dwc_otg_dma_desc_t *descs;
163 /* The DMA address of the descriptors chain start */
164 dma_addr_t descs_dma_addr;
165 /** This variable stores the length of the last enqueued request */
166 uint32_t cfi_req_len;
169 /** Max DMA Descriptor count for any EP */
170 #define MAX_DMA_DESC_CNT 256
171 /** Allocated DMA Desc count */
176 /** Next frame num to setup next ISOC transfer */
178 /** Indicates SOF number overrun in DSTS */
181 #ifdef DWC_UTE_PER_IO
182 /** Next frame num for which will be setup DMA Desc */
183 uint32_t xiso_frame_num;
185 uint32_t xiso_bInterval;
186 /** Count of currently active transfers - shall be either 0 or 1 */
187 int xiso_active_xfers;
188 int xiso_queued_xfers;
192 * Variables specific for ISOC EPs
195 /** DMA addresses of ISOC buffers */
199 dwc_dma_t iso_dma_desc_addr;
200 dwc_otg_dev_dma_desc_t *iso_desc_addr;
202 /** pointer to the transfer buffers */
206 /** number of ISOC Buffer is processing */
207 uint32_t proc_buf_num;
208 /** Interval of ISOC Buffer processing */
209 uint32_t buf_proc_intrvl;
210 /** Data size for regular frame */
211 uint32_t data_per_frame;
213 /* todo - pattern data support is to be implemented in the future */
214 /** Data size for pattern frame */
215 uint32_t data_pattern_frame;
216 /** Frame number of pattern data */
221 /** ISO Packet number per frame */
222 uint32_t pkt_per_frm;
223 /** Next frame num for which will be setup DMA Desc */
225 /** Number of packets per buffer processing */
227 /** Info for all isoc packets */
228 iso_pkt_info_t *pkt_info;
229 /** current pkt number */
231 /** current pkt number */
232 uint8_t *cur_pkt_addr;
233 /** current pkt number */
234 uint32_t cur_pkt_dma_addr;
235 #endif /* DWC_EN_ISOC */
241 * Reasons for halting a host channel.
243 typedef enum dwc_otg_halt_status {
244 DWC_OTG_HC_XFER_NO_HALT_STATUS,
245 DWC_OTG_HC_XFER_COMPLETE,
246 DWC_OTG_HC_XFER_URB_COMPLETE,
249 DWC_OTG_HC_XFER_NYET,
250 DWC_OTG_HC_XFER_STALL,
251 DWC_OTG_HC_XFER_XACT_ERR,
252 DWC_OTG_HC_XFER_FRAME_OVERRUN,
253 DWC_OTG_HC_XFER_BABBLE_ERR,
254 DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
255 DWC_OTG_HC_XFER_AHB_ERR,
256 DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
257 DWC_OTG_HC_XFER_URB_DEQUEUE
258 } dwc_otg_halt_status_e;
261 * Host channel descriptor. This structure represents the state of a single
262 * host channel when acting in host mode. It contains the data items needed to
263 * transfer packets to an endpoint via a host channel.
265 typedef struct dwc_hc {
266 /** Host channel number used for register address lookup */
269 /** Device to access */
275 /** EP direction. 0: OUT, 1: IN */
280 * One of the following values:
281 * - DWC_OTG_EP_SPEED_LOW
282 * - DWC_OTG_EP_SPEED_FULL
283 * - DWC_OTG_EP_SPEED_HIGH
286 #define DWC_OTG_EP_SPEED_LOW 0
287 #define DWC_OTG_EP_SPEED_FULL 1
288 #define DWC_OTG_EP_SPEED_HIGH 2
292 * One of the following values:
293 * - DWC_OTG_EP_TYPE_CONTROL: 0
294 * - DWC_OTG_EP_TYPE_ISOC: 1
295 * - DWC_OTG_EP_TYPE_BULK: 2
296 * - DWC_OTG_EP_TYPE_INTR: 3
300 /** Max packet size in bytes */
301 unsigned max_packet:11;
304 * PID for initial transaction.
308 * 3: MDATA (non-Control EP),
311 unsigned data_pid_start:2;
312 #define DWC_OTG_HC_PID_DATA0 0
313 #define DWC_OTG_HC_PID_DATA2 1
314 #define DWC_OTG_HC_PID_DATA1 2
315 #define DWC_OTG_HC_PID_MDATA 3
316 #define DWC_OTG_HC_PID_SETUP 3
318 /** Number of periodic transactions per (micro)frame */
319 unsigned multi_count:2;
321 /** @name Transfer State */
324 /** Pointer to the current transfer buffer position. */
327 * In Buffer DMA mode this buffer will be used
328 * if xfer_buff is not DWORD aligned.
330 dwc_dma_t align_buff;
331 /** Total number of bytes to transfer. */
333 /** Number of bytes transferred so far. */
335 /** Packet count at start of transfer.*/
336 uint16_t start_pkt_count;
339 * Flag to indicate whether the transfer has been started. Set to 1 if
340 * it has been started, 0 otherwise.
342 uint8_t xfer_started;
345 * Set to 1 to indicate that a PING request should be issued on this
346 * channel. If 0, process normally.
351 * Set to 1 to indicate that the error count for this transaction is
352 * non-zero. Set to 0 if the error count is 0.
357 * Set to 1 to indicate that this channel should be halted the next
358 * time a request is queued for the channel. This is necessary in
359 * slave mode if no request queue space is available when an attempt
360 * is made to halt the channel.
362 uint8_t halt_on_queue;
365 * Set to 1 if the host channel has been halted, but the core is not
366 * finished flushing queued requests. Otherwise 0.
368 uint8_t halt_pending;
371 * Reason for halting the host channel.
373 dwc_otg_halt_status_e halt_status;
376 * Split settings for the host channel
378 uint8_t do_split; /**< Enable split for the channel */
379 uint8_t complete_split; /**< Enable complete split */
380 uint8_t hub_addr; /**< Address of high speed hub */
382 uint8_t port_addr; /**< Port of the low/full speed device */
383 /** Split transaction position
384 * One of the following values:
385 * - DWC_HCSPLIT_XACTPOS_MID
386 * - DWC_HCSPLIT_XACTPOS_BEGIN
387 * - DWC_HCSPLIT_XACTPOS_END
388 * - DWC_HCSPLIT_XACTPOS_ALL */
391 /** Set when the host channel does a short read. */
395 * Number of requests issued for this channel since it was assigned to
396 * the current transfer (not counting PINGs).
401 * Queue Head for the transfer being processed by this channel.
403 struct dwc_otg_qh *qh;
407 /** Entry in list of host channels. */
408 DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
410 /** @name Descriptor DMA support */
413 /** Number of Transfer Descriptors */
416 /** Descriptor List DMA address */
417 dwc_dma_t desc_list_addr;
419 /** Scheduling micro-frame bitmap. */
426 * The following parameters may be specified when starting the module. These
427 * parameters define how the DWC_otg controller should be configured.
429 typedef struct dwc_otg_core_params {
433 * Specifies the OTG capabilities. The driver will automatically
434 * detect the value for this parameter if none is specified.
435 * 0 - HNP and SRP capable (default)
436 * 1 - SRP Only capable
437 * 2 - No HNP/SRP capable
442 * Specifies whether to use slave or DMA mode for accessing the data
443 * FIFOs. The driver will automatically detect the value for this
444 * parameter if none is specified.
446 * 1 - DMA (default, if available)
451 * When DMA mode is enabled specifies whether to use address DMA or DMA
452 * Descriptor mode for accessing the data FIFOs in device mode. The driver
453 * will automatically detect the value for this if none is specified.
455 * 1 - DMA Descriptor(default, if available)
457 int32_t dma_desc_enable;
458 /** The DMA Burst size (applicable only for External DMA
459 * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
461 int32_t dma_burst_size; /* Translate this to GAHBCFG values */
464 * Specifies the maximum speed of operation in host and device mode.
465 * The actual speed depends on the speed of the attached device and
466 * the value of phy_type. The actual speed depends on the speed of the
468 * 0 - High Speed (default)
472 /** Specifies whether low power mode is supported when attached
473 * to a Full Speed or Low Speed device in host mode.
474 * 0 - Don't support low power mode (default)
475 * 1 - Support low power mode
477 int32_t host_support_fs_ls_low_power;
479 /** Specifies the PHY clock rate in low power mode when connected to a
480 * Low Speed device in host mode. This parameter is applicable only if
481 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
482 * then defaults to 6 MHZ otherwise 48 MHZ.
487 int32_t host_ls_low_power_phy_clk;
490 * 0 - Use cC FIFO size parameters
491 * 1 - Allow dynamic FIFO sizing (default)
493 int32_t enable_dynamic_fifo;
495 /** Total number of 4-byte words in the data FIFO memory. This
496 * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
498 * 32 to 32768 (default 8192)
499 * Note: The total FIFO memory depth in the FPGA configuration is 8192.
501 int32_t data_fifo_size;
503 /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
504 * FIFO sizing is enabled.
505 * 16 to 32768 (default 1064)
507 int32_t dev_rx_fifo_size;
509 /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
510 * when dynamic FIFO sizing is enabled.
511 * 16 to 32768 (default 1024)
513 int32_t dev_nperio_tx_fifo_size;
515 /** Number of 4-byte words in each of the periodic Tx FIFOs in device
516 * mode when dynamic FIFO sizing is enabled.
517 * 4 to 768 (default 256)
519 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
521 /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
522 * FIFO sizing is enabled.
523 * 16 to 32768 (default 1024)
525 int32_t host_rx_fifo_size;
527 /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
528 * when Dynamic FIFO sizing is enabled in the core.
529 * 16 to 32768 (default 1024)
531 int32_t host_nperio_tx_fifo_size;
533 /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
534 * FIFO sizing is enabled.
535 * 16 to 32768 (default 1024)
537 int32_t host_perio_tx_fifo_size;
539 /** The maximum transfer size supported in bytes.
540 * 2047 to 65,535 (default 65,535)
542 int32_t max_transfer_size;
544 /** The maximum number of packets in a transfer.
545 * 15 to 511 (default 511)
547 int32_t max_packet_count;
549 /** The number of host channel registers to use.
550 * 1 to 16 (default 12)
551 * Note: The FPGA configuration supports a maximum of 12 host channels.
553 int32_t host_channels;
555 /** The number of endpoints in addition to EP0 available for device
557 * 1 to 15 (default 6 IN and OUT)
558 * Note: The FPGA configuration supports a maximum of 6 IN and OUT
559 * endpoints in addition to EP0.
561 int32_t dev_endpoints;
564 * Specifies the type of PHY interface to use. By default, the driver
565 * will automatically detect the phy_type.
568 * 1 - UTMI+ (default)
574 * Specifies the UTMI+ Data Width. This parameter is
575 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
576 * PHY_TYPE, this parameter indicates the data width between
577 * the MAC and the ULPI Wrapper.) Also, this parameter is
578 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
579 * to "8 and 16 bits", meaning that the core has been
580 * configured to work at either data path width.
582 * 8 or 16 bits (default 16)
584 int32_t phy_utmi_width;
587 * Specifies whether the ULPI operates at double or single
588 * data rate. This parameter is only applicable if PHY_TYPE is
591 * 0 - single data rate ULPI interface with 8 bit wide data
593 * 1 - double data rate ULPI interface with 4 bit wide data
596 int32_t phy_ulpi_ddr;
599 * Specifies whether to use the internal or external supply to
600 * drive the vbus with a ULPI phy.
602 int32_t phy_ulpi_ext_vbus;
605 * Specifies whether to use the I2Cinterface for full speed PHY. This
606 * parameter is only applicable if PHY_TYPE is FS.
617 * Specifies whether dedicated transmit FIFOs are
618 * enabled for non periodic IN endpoints in device mode
622 int32_t en_multiple_tx_fifo;
624 /** Number of 4-byte words in each of the Tx FIFOs in device
625 * mode when dynamic FIFO sizing is enabled.
626 * 4 to 768 (default 256)
628 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
630 /** Thresholding enable flag-
631 * bit 0 - enable non-ISO Tx thresholding
632 * bit 1 - enable ISO Tx thresholding
633 * bit 2 - enable Rx thresholding
637 /** Thresholding length for Tx
638 * FIFOs in 32 bit DWORDs
640 uint32_t tx_thr_length;
642 /** Thresholding length for Rx
643 * FIFOs in 32 bit DWORDs
645 uint32_t rx_thr_length;
648 * Specifies whether LPM (Link Power Management) support is enabled
653 * Specifies whether LPM Errata (Link Power Management) support is enabled
658 * Specifies the baseline besl value
660 int32_t baseline_besl;
663 * Specifies the deep besl value
666 /** Per Transfer Interrupt
673 /** Multi Processor Interrupt
680 /** IS_USB Capability
686 /** AHB Threshold Ratio
687 * 2'b00 AHB Threshold = MAC Threshold
688 * 2'b01 AHB Threshold = 1/2 MAC Threshold
689 * 2'b10 AHB Threshold = 1/4 MAC Threshold
690 * 2'b11 AHB Threshold = 1/8 MAC Threshold
692 int32_t ahb_thr_ratio;
698 int32_t adp_supp_enable;
700 /** HFIR Reload Control
701 * 0 - The HFIR cannot be reloaded dynamically.
702 * 1 - Allow dynamic reloading of the HFIR register during runtime.
706 /** DCFG: Enable device Out NAK
707 * 0 - The core does not set NAK after Bulk Out transfer complete.
708 * 1 - The core sets NAK after Bulk OUT transfer complete.
712 /** DCFG: Enable Continue on BNA
713 * After receiving BNA interrupt the core disables the endpoint,when the
714 * endpoint is re-enabled by the application the core starts processing
715 * 0 - from the DOEPDMA descriptor
716 * 1 - from the descriptor which received the BNA.
720 /** GAHBCFG: AHB Single Support
721 * This bit when programmed supports SINGLE transfers for remainder
722 * data in a transfer for DMA mode of operation.
723 * 0 - in this case the remainder data will be sent using INCR burst size.
724 * 1 - in this case the remainder data will be sent using SINGLE burst size.
728 /** Core Power down mode
729 * 0 - No Power Down is enabled
731 * 2 - Complete Power Down (Hibernation)
735 /** OTG revision supported
736 * 0 - OTG 1.3 revision
737 * 1 - OTG 2.0 revision
741 } dwc_otg_core_params_t;
744 struct dwc_otg_core_if;
745 typedef struct hc_xfer_info {
746 struct dwc_otg_core_if *core_if;
751 typedef struct ep_xfer_info {
752 struct dwc_otg_core_if *core_if;
759 typedef enum dwc_otg_lx_state {
762 /** LPM sleep state*/
764 /** USB suspend state*/
768 } dwc_otg_lx_state_e;
770 struct dwc_otg_global_regs_backup {
771 uint32_t gotgctl_local;
772 uint32_t gintmsk_local;
773 uint32_t gahbcfg_local;
774 uint32_t gusbcfg_local;
775 uint32_t grxfsiz_local;
776 uint32_t gnptxfsiz_local;
777 #ifdef CONFIG_USB_DWC_OTG_LPM
778 uint32_t glpmcfg_local;
780 uint32_t gi2cctl_local;
781 uint32_t hptxfsiz_local;
782 uint32_t pcgcctl_local;
783 uint32_t gdfifocfg_local;
784 uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
785 uint32_t gpwrdn_local;
786 uint32_t xhib_pcgcctl;
787 uint32_t xhib_gpwrdn;
790 struct dwc_otg_host_regs_backup {
792 uint32_t haintmsk_local;
793 uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
794 uint32_t hprt0_local;
798 struct dwc_otg_dev_regs_backup {
804 uint32_t diepctl[MAX_EPS_CHANNELS];
805 uint32_t dieptsiz[MAX_EPS_CHANNELS];
806 uint32_t diepdma[MAX_EPS_CHANNELS];
809 * The <code>dwc_otg_core_if</code> structure contains information needed to manage
810 * the DWC_otg controller acting in either host or device mode. It
811 * represents the programming view of the controller as a whole.
813 struct dwc_otg_core_if {
814 /** Parameters that define how the core should be configured.*/
815 dwc_otg_core_params_t *core_params;
817 /** Core Global registers starting at offset 000h. */
818 dwc_otg_core_global_regs_t *core_global_regs;
820 /** Device-specific information */
821 dwc_otg_dev_if_t *dev_if;
822 /** Host-specific information */
823 dwc_otg_host_if_t *host_if;
825 /** Value from SNPSID register */
828 /** The DWC otg device pointer. */
829 struct dwc_otg_device *otg_dev;
832 * Set to 1 if the core PHY interface bits in USBCFG have been
835 uint8_t phy_init_done;
838 * SRP Success flag, set by srp success interrupt in FS I2C mode
841 uint8_t srp_timer_started;
842 /** Timer for SRP. If it expires before SRP is successful
844 dwc_timer_t *srp_timer;
847 #define USB_MODE_NORMAL (0)
848 #define USB_MODE_FORCE_HOST (1)
849 #define USB_MODE_FORCE_DEVICE (2)
851 #ifdef DWC_DEV_SRPCAP
852 /* This timer is needed to power on the hibernated host core if SRP is not
853 * initiated on connected SRP capable device for limited period of time
855 uint8_t pwron_timer_started;
856 dwc_timer_t *pwron_timer;
858 /* Common configuration information */
859 /** Power and Clock Gating Control Register */
860 volatile uint32_t *pcgcctl;
861 #define DWC_OTG_PCGCCTL_OFFSET 0xE00
863 /** Push/pop addresses for endpoints or host channels.*/
864 uint32_t *data_fifo[MAX_EPS_CHANNELS];
865 #define DWC_OTG_DATA_FIFO_OFFSET 0x1000
866 #define DWC_OTG_DATA_FIFO_SIZE 0x1000
868 /** Total RAM for FIFOs (Bytes) */
869 uint16_t total_fifo_size;
870 /** Size of Rx FIFO (Bytes) */
871 uint16_t rx_fifo_size;
872 /** Size of Non-periodic Tx FIFO (Bytes) */
873 uint16_t nperio_tx_fifo_size;
875 /** 1 if DMA is enabled, 0 otherwise. */
878 /** 1 if DMA descriptor is enabled, 0 otherwise. */
879 uint8_t dma_desc_enable;
881 /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
882 uint8_t pti_enh_enable;
884 /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
885 uint8_t multiproc_int_enable;
887 /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
888 uint8_t en_multiple_tx_fifo;
890 /** Set to 1 if multiple packets of a high-bandwidth transfer is in
891 * process of being queued */
892 uint8_t queuing_high_bandwidth;
894 /** Hardware Configuration -- stored here for convenience.*/
895 hwcfg1_data_t hwcfg1;
896 hwcfg2_data_t hwcfg2;
897 hwcfg3_data_t hwcfg3;
898 hwcfg4_data_t hwcfg4;
899 fifosize_data_t hptxfsiz;
901 /** Host and Device Configuration -- stored here for convenience.*/
905 /** The operational State, during transations
906 * (a_host>>a_peripherial and b_device=>b_host) this may not
907 * match the core but allows the software to determine
912 /** Test mode for PET testing */
916 * Set to 1 if the HCD needs to be restarted on a session request
917 * interrupt. This is required if no connector ID status change has
918 * occurred since the HCD was last disconnected.
920 uint8_t restart_hcd_on_session_req;
923 /** A-Device is a_host */
925 /** A-Device is a_suspend */
926 #define A_SUSPEND (2)
927 /** A-Device is a_peripherial */
928 #define A_PERIPHERAL (3)
929 /** B-Device is operating as a Peripheral. */
930 #define B_PERIPHERAL (4)
931 /** B-Device is operating as a Host. */
935 struct dwc_otg_cil_callbacks *hcd_cb;
938 struct dwc_otg_cil_callbacks *pcd_cb;
940 /** Device mode Periodic Tx FIFO Mask */
942 /** Device mode Periodic Tx FIFO Mask */
945 /** Workqueue object used for handling several interrupts */
948 /** Tasklet used for handling "Wakeup Detected" Interrupt*/
949 dwc_tasklet_t *wkp_tasklet;
950 /** This arrays used for debug purposes for DEV OUT NAK enhancement */
951 uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
952 ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
953 dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
955 uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
957 hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
958 dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
960 uint32_t hfnum_7_samples;
961 uint64_t hfnum_7_frrem_accum;
962 uint32_t hfnum_0_samples;
963 uint64_t hfnum_0_frrem_accum;
964 uint32_t hfnum_other_samples;
965 uint64_t hfnum_other_frrem_accum;
969 uint16_t pwron_rxfsiz;
970 uint16_t pwron_gnptxfsiz;
971 uint16_t pwron_txfsiz[15];
973 uint16_t init_rxfsiz;
974 uint16_t init_gnptxfsiz;
975 uint16_t init_txfsiz[15];
978 /** Lx state of device */
979 dwc_otg_lx_state_e lx_state;
981 /** Saved Core Global registers */
982 struct dwc_otg_global_regs_backup *gr_backup;
983 /** Saved Host registers */
984 struct dwc_otg_host_regs_backup *hr_backup;
985 /** Saved Device registers */
986 struct dwc_otg_dev_regs_backup *dr_backup;
988 /** Power Down Enable */
991 /** ADP support Enable */
994 /** ADP structure object */
997 /** hibernation/suspend flag */
998 int hibernation_suspend;
1000 /** Device mode extended hibernation flag */
1003 /** OTG revision supported */
1006 /** OTG status flag used for HNP polling */
1009 /** Pointer to either hcd->lock or pcd->lock */
1010 dwc_spinlock_t *lock;
1012 /** Start predict NextEP based on Learning Queue if equal 1,
1013 * also used as counter of disabled NP IN EP's */
1014 uint8_t start_predict;
1016 /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
1017 * active, 0xff otherwise */
1018 uint8_t nextep_seq[MAX_EPS_CHANNELS];
1020 /** Index of fisrt EP in nextep_seq array which should be re-enabled **/
1021 uint8_t first_in_nextep_seq;
1023 /** Frame number while entering to ISR - needed for ISOCs **/
1026 /** Flag to not perform ADP probing if IDSTS event happened */
1027 uint8_t stop_adpprb;
1033 * This function is called when transfer is timed out.
1035 extern void hc_xfer_timeout(void *ptr);
1039 * This function is called when transfer is timed out on endpoint.
1041 extern void ep_xfer_timeout(void *ptr);
1044 * The following functions are functions for works
1045 * using during handling some interrupts
1047 extern void w_conn_id_status_change(void *p);
1049 extern void w_wakeup_detected(void *data);
1051 /** Saves global register values into system memory. */
1052 extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
1053 /** Saves device register values into system memory. */
1054 extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
1055 /** Saves host register values into system memory. */
1056 extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
1057 /** Restore global register values. */
1058 extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
1059 /** Restore host register values. */
1060 extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
1061 /** Restore device register values. */
1062 extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
1064 extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
1065 extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
1068 extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
1069 int restore_mode, int reset);
1070 extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
1071 int rem_wakeup, int reset);
1074 * The following functions support initialization of the CIL driver component
1075 * and the DWC_otg controller.
1077 extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
1078 extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
1080 /** @name Device CIL Functions
1081 * The following functions support managing the DWC_otg controller in device
1085 extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
1086 extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
1088 extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
1089 extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
1090 extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
1091 extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
1092 extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
1094 extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
1096 extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
1098 extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
1100 extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
1101 dwc_ep_t * _ep, int _dma);
1102 extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
1103 extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
1105 extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
1108 extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
1110 extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
1112 #endif /* DWC_EN_ISOC */
1115 /** @name Host CIL Functions
1116 * The following functions support managing the DWC_otg controller in host
1120 extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
1121 extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
1122 dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
1123 extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
1124 extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
1126 extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
1128 extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
1129 extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
1131 extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
1132 extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
1134 extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
1137 extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
1138 extern int dwc_otg_check_haps_status(dwc_otg_core_if_t * core_if);
1140 /* Macro used to clear one channel interrupt */
1141 #define clear_hc_int(_hc_regs_, _intr_) \
1143 hcint_data_t hcint_clear = {.d32 = 0}; \
1144 hcint_clear.b._intr_ = 1; \
1145 DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
1149 * Macro used to disable one channel interrupt. Channel interrupts are
1150 * disabled when the channel is halted or released by the interrupt handler.
1151 * There is no need to handle further interrupts of that type until the
1152 * channel is re-assigned. In fact, subsequent handling may cause crashes
1153 * because the channel structures are cleaned up when the channel is released.
1155 #define disable_hc_int(_hc_regs_, _intr_) \
1157 hcintmsk_data_t hcintmsk = {.d32 = 0}; \
1158 hcintmsk.b._intr_ = 1; \
1159 DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
1163 * This function Reads HPRT0 in preparation to modify. It keeps the
1164 * WC bits 0 so that if they are read as 1, they won't clear when you
1167 static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
1170 hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
1172 hprt0.b.prtconndet = 0;
1173 hprt0.b.prtenchng = 0;
1174 hprt0.b.prtovrcurrchng = 0;
1180 /** @name Common CIL Functions
1181 * The following functions support managing the DWC_otg controller in either
1182 * device or host mode.
1186 extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
1187 uint8_t * dest, uint16_t bytes);
1189 extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
1190 extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
1191 extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
1194 * This function returns the Core Interrupt register.
1196 static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
1198 return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
1199 DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
1203 * This function returns the OTG Interrupt register.
1205 static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
1207 return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
1211 * This function reads the Device All Endpoints Interrupt register and
1212 * returns the IN endpoint interrupt bits.
1214 static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
1220 if (core_if->multiproc_int_enable) {
1221 v = DWC_READ_REG32(&core_if->dev_if->
1222 dev_global_regs->deachint) &
1223 DWC_READ_REG32(&core_if->
1224 dev_if->dev_global_regs->deachintmsk);
1226 v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
1227 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
1229 return (v & 0xffff);
1233 * This function reads the Device All Endpoints Interrupt register and
1234 * returns the OUT endpoint interrupt bits.
1236 static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
1241 if (core_if->multiproc_int_enable) {
1242 v = DWC_READ_REG32(&core_if->dev_if->
1243 dev_global_regs->deachint) &
1244 DWC_READ_REG32(&core_if->
1245 dev_if->dev_global_regs->deachintmsk);
1247 v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
1248 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
1251 return ((v & 0xffff0000) >> 16);
1255 * This function returns the Device IN EP Interrupt register
1257 static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
1260 dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1261 uint32_t v, msk, emp;
1263 if (core_if->multiproc_int_enable) {
1265 DWC_READ_REG32(&dev_if->
1266 dev_global_regs->diepeachintmsk[ep->num]);
1268 DWC_READ_REG32(&dev_if->
1269 dev_global_regs->dtknqr4_fifoemptymsk);
1270 msk |= ((emp >> ep->num) & 0x1) << 7;
1271 v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
1273 msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
1275 DWC_READ_REG32(&dev_if->
1276 dev_global_regs->dtknqr4_fifoemptymsk);
1277 msk |= ((emp >> ep->num) & 0x1) << 7;
1278 v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
1285 * This function returns the Device OUT EP Interrupt register
1287 static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
1288 _core_if, dwc_ep_t * _ep)
1290 dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
1292 doepmsk_data_t msk = {.d32 = 0 };
1294 if (_core_if->multiproc_int_enable) {
1296 DWC_READ_REG32(&dev_if->
1297 dev_global_regs->doepeachintmsk[_ep->num]);
1298 if (_core_if->pti_enh_enable) {
1299 msk.b.pktdrpsts = 1;
1301 v = DWC_READ_REG32(&dev_if->
1302 out_ep_regs[_ep->num]->doepint) & msk.d32;
1304 msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
1305 if (_core_if->pti_enh_enable) {
1306 msk.b.pktdrpsts = 1;
1308 v = DWC_READ_REG32(&dev_if->
1309 out_ep_regs[_ep->num]->doepint) & msk.d32;
1315 * This function returns the Host All Channel Interrupt register
1317 static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
1320 return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
1323 static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
1324 _core_if, dwc_hc_t * _hc)
1326 return (DWC_READ_REG32
1327 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
1331 * This function returns the mode of the operation, host or device.
1333 * @return 0 - Device Mode, 1 - Host Mode
1335 static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
1337 return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
1343 * DWC_otg CIL callback structure. This structure allows the HCD and
1344 * PCD to register functions used for starting and stopping the PCD
1345 * and HCD for role change on for a DRD.
1347 typedef struct dwc_otg_cil_callbacks {
1348 /** Start function for role change */
1349 int (*start) (void *_p);
1350 /** Stop Function for role change */
1351 int (*stop) (void *_p);
1352 /** Disconnect Function for role change */
1353 int (*disconnect) (void *_p);
1354 /** Resume/Remote wakeup Function */
1355 int (*resume_wakeup) (void *_p);
1356 /** Suspend function */
1357 int (*suspend) (void *_p);
1358 /** Session Start (SRP) */
1359 int (*session_start) (void *_p);
1360 #ifdef CONFIG_USB_DWC_OTG_LPM
1361 /** Sleep (switch to L0 state) */
1362 int (*sleep) (void *_p);
1364 /** Pointer passed to start() and stop() */
1366 } dwc_otg_cil_callbacks_t;
1368 extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
1369 dwc_otg_cil_callbacks_t * _cb,
1371 extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
1372 dwc_otg_cil_callbacks_t * _cb,
1375 void dwc_otg_initiate_srp(void * core_if);
1377 //////////////////////////////////////////////////////////////////////
1378 /** Start the HCD. Helper function for using the HCD callbacks.
1380 * @param core_if Programming view of DWC_otg controller.
1382 static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
1384 if (core_if->hcd_cb && core_if->hcd_cb->start) {
1385 core_if->hcd_cb->start(core_if->hcd_cb_p);
1389 /** Stop the HCD. Helper function for using the HCD callbacks.
1391 * @param core_if Programming view of DWC_otg controller.
1393 static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
1395 if (core_if->hcd_cb && core_if->hcd_cb->stop) {
1396 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1400 /** Disconnect the HCD. Helper function for using the HCD callbacks.
1402 * @param core_if Programming view of DWC_otg controller.
1404 static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
1406 if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
1407 core_if->hcd_cb->disconnect(core_if->hcd_cb_p);
1411 /** Inform the HCD the a New Session has begun. Helper function for
1412 * using the HCD callbacks.
1414 * @param core_if Programming view of DWC_otg controller.
1416 static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
1418 if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
1419 core_if->hcd_cb->session_start(core_if->hcd_cb_p);
1423 #ifdef CONFIG_USB_DWC_OTG_LPM
1425 * Inform the HCD about LPM sleep.
1426 * Helper function for using the HCD callbacks.
1428 * @param core_if Programming view of DWC_otg controller.
1430 static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
1432 if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
1433 core_if->hcd_cb->sleep(core_if->hcd_cb_p);
1438 /** Resume the HCD. Helper function for using the HCD callbacks.
1440 * @param core_if Programming view of DWC_otg controller.
1442 static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
1444 if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
1445 core_if->hcd_cb->resume_wakeup(core_if->hcd_cb_p);
1449 /** Start the PCD. Helper function for using the PCD callbacks.
1451 * @param core_if Programming view of DWC_otg controller.
1453 static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
1455 if (core_if->pcd_cb && core_if->pcd_cb->start) {
1456 core_if->pcd_cb->start(core_if->pcd_cb->p);
1460 /** Stop the PCD. Helper function for using the PCD callbacks.
1462 * @param core_if Programming view of DWC_otg controller.
1464 static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
1466 if (core_if->pcd_cb && core_if->pcd_cb->stop) {
1467 core_if->pcd_cb->stop(core_if->pcd_cb->p);
1471 /** Suspend the PCD. Helper function for using the PCD callbacks.
1473 * @param core_if Programming view of DWC_otg controller.
1475 static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
1477 if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
1478 core_if->pcd_cb->suspend(core_if->pcd_cb->p);
1482 /** Resume the PCD. Helper function for using the PCD callbacks.
1484 * @param core_if Programming view of DWC_otg controller.
1486 static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
1488 if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
1489 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
1493 //////////////////////////////////////////////////////////////////////