drivers/usb/dwc_otg_310/dwc_otg_cil.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
   3  * $Revision: #198 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  *
  36  * The Core Interface Layer provides basic services for accessing and
  37  * managing the DWC_otg hardware. These services are used by both the
  38  * Host Controller Driver and the Peripheral Controller Driver.
  39  *
  40  * The CIL manages the memory map for the core so that the HCD and PCD
  41  * don't have to do this separately. It also handles basic tasks like
  42  * reading/writing the registers and data FIFOs in the controller.
  43  * Some of the data access functions provide encapsulation of several
  44  * operations required to perform a task, such as writing multiple
  45  * registers to start a transfer. Finally, the CIL performs basic
  46  * services that are not specific to either the host or device modes
  47  * of operation. These services include management of the OTG Host
  48  * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
  49  * Diagnostic API is also provided to allow testing of the controller
  50  * hardware.
  51  *
  52  * The Core Interface Layer has the following requirements:
  53  * - Provides basic controller operations.
  54  * - Minimal use of OS services.
  55  * - The OS services used will be abstracted by using inline functions
  56  *       or macros.
  57  *
  58  */
  59
  60 #include "common_port/dwc_os.h"
  61 #include "dwc_otg_regs.h"
  62 #include "dwc_otg_cil.h"
  63 #include "dwc_otg_driver.h"
  64 #include "usbdev_rk.h"
  65 #include "dwc_otg_hcd.h"
  66
  67 static int dwc_otg_setup_params(dwc_otg_core_if_t *core_if);
  68
  69 /**
  70  * This function is called to initialize the DWC_otg CSR data
  71  * structures. The register addresses in the device and host
  72  * structures are initialized from the base address supplied by the
  73  * caller. The calling function must make the OS calls to get the
  74  * base address of the DWC_otg controller registers. The core_params
  75  * argument holds the parameters that specify how the core should be
  76  * configured.
  77  *
  78  * @param reg_base_addr Base address of DWC_otg core registers
  79  *
  80  */
  81 dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr)
  82 {
  83         dwc_otg_core_if_t *core_if = 0;
  84         dwc_otg_dev_if_t *dev_if = 0;
  85         dwc_otg_host_if_t *host_if = 0;
  86         uint8_t *reg_base = (uint8_t *) reg_base_addr;
  87         int i = 0;
  88
  89         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
  90
  91         core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
  92
  93         if (core_if == NULL) {
  94                 DWC_DEBUGPL(DBG_CIL,
  95                             "Allocation of dwc_otg_core_if_t failed\n");
  96                 return 0;
  97         }
  98         core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
  99
 100         /*
 101          * Allocate the Device Mode structures.
 102          */
 103         dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
 104
 105         if (dev_if == NULL) {
 106                 DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
 107                 DWC_FREE(core_if);
 108                 return 0;
 109         }
 110
 111         dev_if->dev_global_regs =
 112             (dwc_otg_device_global_regs_t *) (reg_base +
 113                                               DWC_DEV_GLOBAL_REG_OFFSET);
 114
 115         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 116                 dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
 117                     (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
 118                      (i * DWC_EP_REG_OFFSET));
 119
 120                 dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
 121                     (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
 122                      (i * DWC_EP_REG_OFFSET));
 123                 DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
 124                             i, &dev_if->in_ep_regs[i]->diepctl);
 125                 DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
 126                             i, &dev_if->out_ep_regs[i]->doepctl);
 127         }
 128
 129         dev_if->speed = 0;      /* unknown */
 130
 131         core_if->dev_if = dev_if;
 132
 133         /*
 134          * Allocate the Host Mode structures.
 135          */
 136         host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
 137
 138         if (host_if == NULL) {
 139                 DWC_DEBUGPL(DBG_CIL,
 140                             "Allocation of dwc_otg_host_if_t failed\n");
 141                 DWC_FREE(dev_if);
 142                 DWC_FREE(core_if);
 143                 return 0;
 144         }
 145
 146         host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
 147             (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
 148
 149         host_if->hprt0 =
 150             (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
 151
 152         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 153                 host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
 154                     (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
 155                      (i * DWC_OTG_CHAN_REGS_OFFSET));
 156                 DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
 157                             i, &host_if->hc_regs[i]->hcchar);
 158         }
 159
 160         host_if->num_host_channels = MAX_EPS_CHANNELS;
 161         core_if->host_if = host_if;
 162
 163         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 164                 core_if->data_fifo[i] =
 165                     (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
 166                                   (i * DWC_OTG_DATA_FIFO_SIZE));
 167                 DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
 168                             i, (unsigned long)core_if->data_fifo[i]);
 169         }
 170
 171         core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
 172
 173         /* Initiate lx_state to L3 disconnected state */
 174         core_if->lx_state = DWC_OTG_L3;
 175         /*
 176          * Store the contents of the hardware configuration registers here for
 177          * easy access later.
 178          */
 179         core_if->hwcfg1.d32 =
 180             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
 181         core_if->hwcfg2.d32 =
 182             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
 183         core_if->hwcfg3.d32 =
 184             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
 185         core_if->hwcfg4.d32 =
 186             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
 187
 188         /* do not get HPTXFSIZ here, it's unused.
 189          * set global_regs->hptxfsiz in dwc_otg_core_host_init.
 190          * for 3.10a version, host20 FIFO can't be configed,
 191          * because host20 hwcfg2.b.dynamic_fifo = 0.
 192          */
 193 #if 0
 194         /* Force host mode to get HPTXFSIZ exact power on value */
 195         {
 196                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
 197                 gusbcfg.d32 =
 198                     DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
 199                 gusbcfg.b.force_host_mode = 1;
 200                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
 201                                 gusbcfg.d32);
 202                 dwc_mdelay(100);
 203                 core_if->hptxfsiz.d32 =
 204                     DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
 205                 gusbcfg.d32 =
 206                     DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
 207                 gusbcfg.b.force_host_mode = 0;
 208                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
 209                                 gusbcfg.d32);
 210                 dwc_mdelay(100);
 211         }
 212 #endif
 213
 214         DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
 215         DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
 216         DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
 217         DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
 218
 219         core_if->hcfg.d32 =
 220             DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
 221         core_if->dcfg.d32 =
 222             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
 223
 224         DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
 225         DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
 226
 227         DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
 228         DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
 229         DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
 230         DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
 231                     core_if->hwcfg2.b.num_host_chan);
 232         DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
 233                     core_if->hwcfg2.b.nonperio_tx_q_depth);
 234         DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
 235                     core_if->hwcfg2.b.host_perio_tx_q_depth);
 236         DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
 237                     core_if->hwcfg2.b.dev_token_q_depth);
 238
 239         DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
 240                     core_if->hwcfg3.b.dfifo_depth);
 241         DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
 242                     core_if->hwcfg3.b.xfer_size_cntr_width);
 243
 244         /*
 245          * Set the SRP sucess bit for FS-I2c
 246          */
 247         core_if->srp_success = 0;
 248         core_if->srp_timer_started = 0;
 249
 250         /*
 251          * Create new workqueue and init works
 252          */
 253         core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
 254         if (core_if->wq_otg == 0) {
 255                 DWC_WARN("DWC_WORKQ_ALLOC failed\n");
 256                 DWC_FREE(host_if);
 257                 DWC_FREE(dev_if);
 258                 DWC_FREE(core_if);
 259                 return 0;
 260         }
 261
 262         core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
 263         DWC_PRINTF("%p\n", &core_if->core_global_regs->gsnpsid);
 264         DWC_PRINTF("Core Release: %x.%x%x%x\n",
 265                    (core_if->snpsid >> 12 & 0xF),
 266                    (core_if->snpsid >> 8 & 0xF),
 267                    (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
 268
 269         core_if->wkp_tasklet =
 270             DWC_TASK_ALLOC("wkp_tasklet", w_wakeup_detected, core_if);
 271
 272         if (dwc_otg_setup_params(core_if))
 273                 DWC_WARN("Error while setting core params\n");
 274
 275         core_if->hibernation_suspend = 0;
 276         if (core_if->otg_ver)
 277                 core_if->test_mode = 0;
 278
 279         /** ADP initialization */
 280         dwc_otg_adp_init(core_if);
 281
 282         return core_if;
 283 }
 284
 285 /**
 286  * This function frees the structures allocated by dwc_otg_cil_init().
 287  *
 288  * @param core_if The core interface pointer returned from
 289  * dwc_otg_cil_init().
 290  *
 291  */
 292 void dwc_otg_cil_remove(dwc_otg_core_if_t *core_if)
 293 {
 294         dctl_data_t dctl = {.d32 = 0 };
 295         /* Disable all interrupts */
 296         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
 297         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
 298
 299         dctl.b.sftdiscon = 1;
 300         if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
 301                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
 302                                  dctl.d32);
 303         }
 304
 305         if (core_if->wq_otg) {
 306                 DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
 307                 DWC_WORKQ_FREE(core_if->wq_otg);
 308         }
 309         if (core_if->dev_if)
 310                 DWC_FREE(core_if->dev_if);
 311         if (core_if->host_if)
 312                 DWC_FREE(core_if->host_if);
 313
 314         /** Remove ADP Stuff  */
 315         dwc_otg_adp_remove(core_if);
 316         if (core_if->core_params)
 317                 DWC_FREE(core_if->core_params);
 318         if (core_if->wkp_tasklet)
 319                 DWC_TASK_FREE(core_if->wkp_tasklet);
 320         if (core_if->srp_timer)
 321                 DWC_TIMER_FREE(core_if->srp_timer);
 322
 323         DWC_FREE(core_if);
 324 }
 325
 326 /**
 327  * This function enables the controller's Global Interrupt in the AHB Config
 328  * register.
 329  *
 330  * @param core_if Programming view of DWC_otg controller.
 331  */
 332 void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if)
 333 {
 334         gahbcfg_data_t ahbcfg = {.d32 = 0 };
 335         ahbcfg.b.glblintrmsk = 1;       /* Enable interrupts */
 336         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
 337 }
 338
 339 /**
 340  * This function disables the controller's Global Interrupt in the AHB Config
 341  * register.
 342  *
 343  * @param core_if Programming view of DWC_otg controller.
 344  */
 345 void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if)
 346 {
 347         gahbcfg_data_t ahbcfg = {.d32 = 0 };
 348         ahbcfg.b.glblintrmsk = 1;       /* Disable interrupts */
 349         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
 350 }
 351
 352 /**
 353  * This function initializes the commmon interrupts, used in both
 354  * device and host modes.
 355  *
 356  * @param core_if Programming view of the DWC_otg controller
 357  *
 358  */
 359 static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *core_if)
 360 {
 361         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
 362         gintmsk_data_t intr_mask = {.d32 = 0 };
 363
 364         /* Clear any pending OTG Interrupts */
 365         DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
 366
 367         /* Clear any pending interrupts */
 368         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
 369
 370         /*
 371          * Enable the interrupts in the GINTMSK.
 372          */
 373         intr_mask.b.modemismatch = 1;
 374         intr_mask.b.otgintr = 1;
 375
 376         if (!core_if->dma_enable) {
 377                 intr_mask.b.rxstsqlvl = 1;
 378         }
 379
 380         intr_mask.b.conidstschng = 1;
 381         intr_mask.b.wkupintr = 1;
 382         intr_mask.b.disconnect = 0;
 383         intr_mask.b.usbsuspend = 1;
 384         /* intr_mask.b.sessreqintr = 1; */
 385 #ifdef CONFIG_USB_DWC_OTG_LPM
 386         if (core_if->core_params->lpm_enable)
 387                 intr_mask.b.lpmtranrcvd = 1;
 388 #endif
 389         DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
 390 }
 391
 392 /*
 393  * The restore operation is modified to support Synopsys Emulated Powerdown and
 394  * Hibernation. This function is for exiting from Device mode hibernation by
 395  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
 396  * @param core_if Programming view of DWC_otg controller.
 397  * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
 398  * @param reset - indicates whether resume is initiated by Reset.
 399  */
 400 int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t *core_if,
 401                                        int rem_wakeup, int reset)
 402 {
 403         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 404         pcgcctl_data_t pcgcctl = {.d32 = 0 };
 405         dctl_data_t dctl = {.d32 = 0 };
 406
 407         int timeout = 2000;
 408
 409         if (!core_if->hibernation_suspend) {
 410                 DWC_PRINTF("Already exited from Hibernation\n");
 411                 return 1;
 412         }
 413
 414         DWC_DEBUGPL(DBG_PCD, "%s called\n", __func__);
 415         /* Switch-on voltage to the core */
 416         gpwrdn.b.pwrdnswtch = 1;
 417         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 418         dwc_udelay(10);
 419
 420         /* Reset core */
 421         gpwrdn.d32 = 0;
 422         gpwrdn.b.pwrdnrstn = 1;
 423         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 424         dwc_udelay(10);
 425
 426         /* Assert Restore signal */
 427         gpwrdn.d32 = 0;
 428         gpwrdn.b.restore = 1;
 429         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 430         dwc_udelay(10);
 431
 432         /* Disable power clamps */
 433         gpwrdn.d32 = 0;
 434         gpwrdn.b.pwrdnclmp = 1;
 435         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 436
 437         if (rem_wakeup)
 438                 dwc_udelay(70);
 439
 440         /* Deassert Reset core */
 441         gpwrdn.d32 = 0;
 442         gpwrdn.b.pwrdnrstn = 1;
 443         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 444         dwc_udelay(10);
 445
 446         /* Disable PMU interrupt */
 447         gpwrdn.d32 = 0;
 448         gpwrdn.b.pmuintsel = 1;
 449         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 450
 451         /* Mask interrupts from gpwrdn */
 452         gpwrdn.d32 = 0;
 453         gpwrdn.b.connect_det_msk = 1;
 454         gpwrdn.b.srp_det_msk = 1;
 455         gpwrdn.b.disconn_det_msk = 1;
 456         gpwrdn.b.rst_det_msk = 1;
 457         gpwrdn.b.lnstchng_msk = 1;
 458         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 459
 460         /* Indicates that we are going out from hibernation */
 461         core_if->hibernation_suspend = 0;
 462
 463         /*
 464          * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
 465          * indicates restore from remote_wakeup
 466          */
 467         restore_essential_regs(core_if, rem_wakeup, 0);
 468
 469         /*
 470          * Wait a little for seeing new value of variable hibernation_suspend if
 471          * Restore done interrupt received before polling
 472          */
 473         dwc_udelay(10);
 474
 475         if (core_if->hibernation_suspend == 0) {
 476                 /*
 477                  * Wait For Restore_done Interrupt. This mechanism of polling the
 478                  * interrupt is introduced to avoid any possible race conditions
 479                  */
 480                 do {
 481                         gintsts_data_t gintsts;
 482                         gintsts.d32 =
 483                             DWC_READ_REG32(&core_if->core_global_regs->gintsts);
 484                         if (gintsts.b.restoredone) {
 485                                 gintsts.d32 = 0;
 486                                 gintsts.b.restoredone = 1;
 487                                 DWC_WRITE_REG32(&core_if->
 488                                                 core_global_regs->gintsts,
 489                                                 gintsts.d32);
 490                                 DWC_PRINTF("Restore Done Interrupt seen\n");
 491                                 break;
 492                         }
 493                         dwc_udelay(10);
 494                 } while (--timeout);
 495                 if (!timeout) {
 496                         DWC_PRINTF
 497                             ("Restore Done interrupt wasn't generated here\n");
 498                 }
 499         }
 500         /* Clear all pending interupts */
 501         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 502
 503         /* De-assert Restore */
 504         gpwrdn.d32 = 0;
 505         gpwrdn.b.restore = 1;
 506         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 507         dwc_udelay(10);
 508
 509         if (!rem_wakeup) {
 510                 pcgcctl.d32 = 0;
 511                 pcgcctl.b.rstpdwnmodule = 1;
 512                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
 513         }
 514
 515         /* Restore GUSBCFG and DCFG */
 516         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
 517                         core_if->gr_backup->gusbcfg_local);
 518         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
 519                         core_if->dr_backup->dcfg);
 520
 521         /* De-assert Wakeup Logic */
 522         gpwrdn.d32 = 0;
 523         gpwrdn.b.pmuactv = 1;
 524         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 525         dwc_udelay(10);
 526
 527         if (!rem_wakeup) {
 528                 /* Set Device programming done bit */
 529                 dctl.b.pwronprgdone = 1;
 530                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
 531                                  dctl.d32);
 532         } else {
 533                 /* Start Remote Wakeup Signaling */
 534                 dctl.d32 = core_if->dr_backup->dctl;
 535                 dctl.b.rmtwkupsig = 1;
 536                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
 537                                 dctl.d32);
 538         }
 539
 540         dwc_mdelay(2);
 541         /* Clear all pending interupts */
 542         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 543
 544         /* Restore global registers */
 545         dwc_otg_restore_global_regs(core_if);
 546         /* Restore device global registers */
 547         dwc_otg_restore_dev_regs(core_if, rem_wakeup);
 548
 549         if (rem_wakeup) {
 550                 dwc_mdelay(7);
 551                 dctl.d32 = 0;
 552                 dctl.b.rmtwkupsig = 1;
 553                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
 554                                  dctl.d32, 0);
 555         }
 556
 557         core_if->hibernation_suspend = 0;
 558         /* The core will be in ON STATE */
 559         core_if->lx_state = DWC_OTG_L0;
 560         DWC_PRINTF("Hibernation recovery completes here\n");
 561
 562         return 1;
 563 }
 564
 565 /*
 566  * The restore operation is modified to support Synopsys Emulated Powerdown and
 567  * Hibernation. This function is for exiting from Host mode hibernation by
 568  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
 569  * @param core_if Programming view of DWC_otg controller.
 570  * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
 571  * @param reset - indicates whether resume is initiated by Reset.
 572  */
 573 int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t *core_if,
 574                                      int rem_wakeup, int reset)
 575 {
 576         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 577         hprt0_data_t hprt0 = {.d32 = 0 };
 578
 579         int timeout = 2000;
 580
 581         DWC_DEBUGPL(DBG_HCD, "%s called\n", __func__);
 582         /* Switch-on voltage to the core */
 583         gpwrdn.b.pwrdnswtch = 1;
 584         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 585         dwc_udelay(10);
 586
 587         /* Reset core */
 588         gpwrdn.d32 = 0;
 589         gpwrdn.b.pwrdnrstn = 1;
 590         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 591         dwc_udelay(10);
 592
 593         /* Assert Restore signal */
 594         gpwrdn.d32 = 0;
 595         gpwrdn.b.restore = 1;
 596         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 597         dwc_udelay(10);
 598
 599         /* Disable power clamps */
 600         gpwrdn.d32 = 0;
 601         gpwrdn.b.pwrdnclmp = 1;
 602         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 603
 604         if (!rem_wakeup)
 605                 dwc_udelay(50);
 606
 607         /* Deassert Reset core */
 608         gpwrdn.d32 = 0;
 609         gpwrdn.b.pwrdnrstn = 1;
 610         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 611         dwc_udelay(10);
 612
 613         /* Disable PMU interrupt */
 614         gpwrdn.d32 = 0;
 615         gpwrdn.b.pmuintsel = 1;
 616         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 617
 618         gpwrdn.d32 = 0;
 619         gpwrdn.b.connect_det_msk = 1;
 620         gpwrdn.b.srp_det_msk = 1;
 621         gpwrdn.b.disconn_det_msk = 1;
 622         gpwrdn.b.rst_det_msk = 1;
 623         gpwrdn.b.lnstchng_msk = 1;
 624         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 625
 626         /* Indicates that we are going out from hibernation */
 627         core_if->hibernation_suspend = 0;
 628
 629         /* Set Restore Essential Regs bit in PCGCCTL register */
 630         restore_essential_regs(core_if, rem_wakeup, 1);
 631
 632         /* Wait a little for seeing new value of variable hibernation_suspend if
 633          * Restore done interrupt received before polling */
 634         dwc_udelay(10);
 635
 636         if (core_if->hibernation_suspend == 0) {
 637                 /* Wait For Restore_done Interrupt. This mechanism of polling the
 638                  * interrupt is introduced to avoid any possible race conditions
 639                  */
 640                 do {
 641                         gintsts_data_t gintsts;
 642                         gintsts.d32 =
 643                             DWC_READ_REG32(&core_if->core_global_regs->gintsts);
 644                         if (gintsts.b.restoredone) {
 645                                 gintsts.d32 = 0;
 646                                 gintsts.b.restoredone = 1;
 647                                 DWC_WRITE_REG32(&core_if->core_global_regs->
 648                                                 gintsts, gintsts.d32);
 649                                 DWC_DEBUGPL(DBG_HCD,
 650                                             "Restore Done Interrupt seen\n");
 651                                 break;
 652                         }
 653                         dwc_udelay(10);
 654                 } while (--timeout);
 655                 if (!timeout)
 656                         DWC_WARN("Restore Done interrupt wasn't generated\n");
 657         }
 658
 659         /* Set the flag's value to 0 again after
 660          * receiving restore done interrupt */
 661         core_if->hibernation_suspend = 0;
 662
 663         /* This step is not described in functional spec but if not wait for this
 664          * delay, mismatch interrupts occurred because just after restore core is
 665          * in Device mode(gintsts.curmode == 0) */
 666         dwc_mdelay(100);
 667
 668         /* Clear all pending interrupts */
 669         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 670
 671         /* De-assert Restore */
 672         gpwrdn.d32 = 0;
 673         gpwrdn.b.restore = 1;
 674         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 675         dwc_udelay(10);
 676
 677         /* Restore GUSBCFG and HCFG */
 678         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
 679                         core_if->gr_backup->gusbcfg_local);
 680         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
 681                         core_if->hr_backup->hcfg_local);
 682
 683         /* De-assert Wakeup Logic */
 684         gpwrdn.d32 = 0;
 685         gpwrdn.b.pmuactv = 1;
 686         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 687         dwc_udelay(10);
 688
 689         /* Start the Resume operation by programming HPRT0 */
 690         hprt0.d32 = core_if->hr_backup->hprt0_local;
 691         hprt0.b.prtpwr = 1;
 692         hprt0.b.prtena = 0;
 693         hprt0.b.prtsusp = 0;
 694         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 695
 696         DWC_PRINTF("Resume Starts Now\n");
 697         if (!reset) {
 698                 /* Indicates it is Resume Operation */
 699                 hprt0.d32 = core_if->hr_backup->hprt0_local;
 700                 hprt0.b.prtres = 1;
 701                 hprt0.b.prtpwr = 1;
 702                 hprt0.b.prtena = 0;
 703                 hprt0.b.prtsusp = 0;
 704                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 705
 706                 if (!rem_wakeup)
 707                         hprt0.b.prtres = 0;
 708                 /* Wait for Resume time and then program HPRT again */
 709                 dwc_mdelay(100);
 710                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 711
 712         } else {
 713                 /* Indicates it is Reset Operation */
 714                 hprt0.d32 = core_if->hr_backup->hprt0_local;
 715                 hprt0.b.prtrst = 1;
 716                 hprt0.b.prtpwr = 1;
 717                 hprt0.b.prtena = 0;
 718                 hprt0.b.prtsusp = 0;
 719                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 720                 /* Wait for Reset time and then program HPRT again */
 721                 dwc_mdelay(60);
 722                 hprt0.b.prtrst = 0;
 723                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 724         }
 725         /* Clear all interrupt status */
 726         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 727         hprt0.b.prtconndet = 1;
 728         hprt0.b.prtenchng = 1;
 729         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 730
 731         /* Clear all pending interupts */
 732         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 733
 734         /* Restore global registers */
 735         dwc_otg_restore_global_regs(core_if);
 736         /* Restore host global registers */
 737         dwc_otg_restore_host_regs(core_if, reset);
 738
 739         /* The core will be in ON STATE */
 740         core_if->lx_state = DWC_OTG_L0;
 741         DWC_PRINTF("Hibernation recovery is complete here\n");
 742         return 0;
 743 }
 744
 745 /** Saves some register values into system memory. */
 746 int dwc_otg_save_global_regs(dwc_otg_core_if_t *core_if)
 747 {
 748         struct dwc_otg_global_regs_backup *gr;
 749         int i;
 750
 751         gr = core_if->gr_backup;
 752         if (!gr) {
 753                 gr = DWC_ALLOC(sizeof(*gr));
 754                 if (!gr)
 755                         return -DWC_E_NO_MEMORY;
 756                 core_if->gr_backup = gr;
 757         }
 758
 759         gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
 760         gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
 761         gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
 762         gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
 763         gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
 764         gr->gnptxfsiz_local =
 765             DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
 766         gr->hptxfsiz_local =
 767             DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
 768 #ifdef CONFIG_USB_DWC_OTG_LPM
 769         gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
 770 #endif
 771         gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
 772         gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
 773         gr->gdfifocfg_local =
 774             DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
 775         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 776                 gr->dtxfsiz_local[i] =
 777                     DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
 778         }
 779
 780         DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
 781         DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl   = %08x\n", gr->gotgctl_local);
 782         DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
 783         DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg   = %08x\n", gr->gahbcfg_local);
 784         DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg   = %08x\n", gr->gusbcfg_local);
 785         DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz   = %08x\n", gr->grxfsiz_local);
 786         DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
 787                     gr->gnptxfsiz_local);
 788         DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz  = %08x\n",
 789                     gr->hptxfsiz_local);
 790 #ifdef CONFIG_USB_DWC_OTG_LPM
 791         DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg   = %08x\n", gr->glpmcfg_local);
 792 #endif
 793         DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl   = %08x\n", gr->gi2cctl_local);
 794         DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl   = %08x\n", gr->pcgcctl_local);
 795         DWC_DEBUGPL(DBG_ANY, "Backed up gdfifocfg   = %08x\n",
 796                     gr->gdfifocfg_local);
 797
 798         return 0;
 799 }
 800
 801 /** Saves GINTMSK register before setting the msk bits. */
 802 int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t *core_if)
 803 {
 804         struct dwc_otg_global_regs_backup *gr;
 805
 806         gr = core_if->gr_backup;
 807         if (!gr) {
 808                 gr = DWC_ALLOC(sizeof(*gr));
 809                 if (!gr)
 810                         return -DWC_E_NO_MEMORY;
 811                 core_if->gr_backup = gr;
 812         }
 813
 814         gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
 815
 816         DWC_DEBUGPL(DBG_ANY,
 817                     "=============Backing GINTMSK registers============\n");
 818         DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
 819
 820         return 0;
 821 }
 822
 823 int dwc_otg_save_dev_regs(dwc_otg_core_if_t *core_if)
 824 {
 825         struct dwc_otg_dev_regs_backup *dr;
 826         int i;
 827
 828         dr = core_if->dr_backup;
 829         if (!dr) {
 830                 dr = DWC_ALLOC(sizeof(*dr));
 831                 if (!dr)
 832                         return -DWC_E_NO_MEMORY;
 833                 core_if->dr_backup = dr;
 834         }
 835
 836         dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
 837         dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
 838         dr->daintmsk =
 839             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
 840         dr->diepmsk =
 841             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
 842         dr->doepmsk =
 843             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
 844
 845         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
 846                 dr->diepctl[i] =
 847                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
 848                 dr->dieptsiz[i] =
 849                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
 850                 dr->diepdma[i] =
 851                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
 852         }
 853
 854         DWC_DEBUGPL(DBG_ANY,
 855                     "=============Backing Host registers==============\n");
 856         DWC_DEBUGPL(DBG_ANY, "Backed up dcfg            = %08x\n", dr->dcfg);
 857         DWC_DEBUGPL(DBG_ANY, "Backed up dctl        = %08x\n", dr->dctl);
 858         DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk            = %08x\n",
 859                     dr->daintmsk);
 860         DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk        = %08x\n", dr->diepmsk);
 861         DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk        = %08x\n", dr->doepmsk);
 862         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
 863                 DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d]        = %08x\n", i,
 864                             dr->diepctl[i]);
 865                 DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d]        = %08x\n",
 866                             i, dr->dieptsiz[i]);
 867                 DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d]        = %08x\n", i,
 868                             dr->diepdma[i]);
 869         }
 870
 871         return 0;
 872 }
 873
 874 int dwc_otg_save_host_regs(dwc_otg_core_if_t *core_if)
 875 {
 876         struct dwc_otg_host_regs_backup *hr;
 877         int i;
 878
 879         hr = core_if->hr_backup;
 880         if (!hr) {
 881                 hr = DWC_ALLOC(sizeof(*hr));
 882                 if (!hr)
 883                         return -DWC_E_NO_MEMORY;
 884                 core_if->hr_backup = hr;
 885         }
 886
 887         hr->hcfg_local =
 888             DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
 889         hr->haintmsk_local =
 890             DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
 891         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
 892                 hr->hcintmsk_local[i] =
 893                     DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
 894         }
 895         hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
 896         hr->hfir_local =
 897             DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
 898
 899         DWC_DEBUGPL(DBG_ANY,
 900                     "=============Backing Host registers===============\n");
 901         DWC_DEBUGPL(DBG_ANY, "Backed up hcfg            = %08x\n",
 902                     hr->hcfg_local);
 903         DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
 904         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
 905                 DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
 906                             hr->hcintmsk_local[i]);
 907         }
 908         DWC_DEBUGPL(DBG_ANY, "Backed up hprt0           = %08x\n",
 909                     hr->hprt0_local);
 910         DWC_DEBUGPL(DBG_ANY, "Backed up hfir           = %08x\n",
 911                     hr->hfir_local);
 912
 913         return 0;
 914 }
 915
 916 int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
 917 {
 918         struct dwc_otg_global_regs_backup *gr;
 919         int i;
 920
 921         gr = core_if->gr_backup;
 922         if (!gr)
 923                 return -DWC_E_INVALID;
 924
 925         DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
 926         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
 927         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
 928         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
 929         DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
 930         DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
 931                         gr->gnptxfsiz_local);
 932         DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
 933                         gr->hptxfsiz_local);
 934         DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
 935                         gr->gdfifocfg_local);
 936         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 937                 DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
 938                                 gr->dtxfsiz_local[i]);
 939         }
 940
 941         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 942         DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
 943         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
 944                         (gr->gahbcfg_local));
 945         return 0;
 946 }
 947
 948 int dwc_otg_restore_dev_regs(dwc_otg_core_if_t *core_if, int rem_wakeup)
 949 {
 950         struct dwc_otg_dev_regs_backup *dr;
 951         int i;
 952
 953         dr = core_if->dr_backup;
 954
 955         if (!dr) {
 956                 return -DWC_E_INVALID;
 957         }
 958
 959         if (!rem_wakeup) {
 960                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
 961                                 dr->dctl);
 962         }
 963
 964         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
 965                         dr->daintmsk);
 966         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
 967                         dr->diepmsk);
 968         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
 969                         dr->doepmsk);
 970
 971         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
 972                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz,
 973                                 dr->dieptsiz[i]);
 974                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma,
 975                                 dr->diepdma[i]);
 976                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl,
 977                                 dr->diepctl[i]);
 978         }
 979
 980         return 0;
 981 }
 982
 983 int dwc_otg_restore_host_regs(dwc_otg_core_if_t *core_if, int reset)
 984 {
 985         struct dwc_otg_host_regs_backup *hr;
 986         int i;
 987         hr = core_if->hr_backup;
 988
 989         if (!hr)
 990                 return -DWC_E_INVALID;
 991
 992         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
 993                         hr->hcfg_local);
 994         /* if (!reset)
 995          * {
 996          *      DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir,
 997          *                      hr->hfir_local);
 998          * }
 999          */
1000
1001         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
1002                         hr->haintmsk_local);
1003         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
1004                 DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
1005                                 hr->hcintmsk_local[i]);
1006         }
1007
1008         return 0;
1009 }
1010
1011 int restore_lpm_i2c_regs(dwc_otg_core_if_t *core_if)
1012 {
1013         struct dwc_otg_global_regs_backup *gr;
1014
1015         gr = core_if->gr_backup;
1016
1017         /* Restore values for LPM and I2C */
1018 #ifdef CONFIG_USB_DWC_OTG_LPM
1019         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
1020 #endif
1021         DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
1022
1023         return 0;
1024 }
1025
1026 int restore_essential_regs(dwc_otg_core_if_t *core_if, int rmode, int is_host)
1027 {
1028         struct dwc_otg_global_regs_backup *gr;
1029         pcgcctl_data_t pcgcctl = {.d32 = 0 };
1030         gahbcfg_data_t gahbcfg = {.d32 = 0 };
1031         gusbcfg_data_t gusbcfg = {.d32 = 0 };
1032         gintmsk_data_t gintmsk = {.d32 = 0 };
1033
1034         /* Restore LPM and I2C registers */
1035         restore_lpm_i2c_regs(core_if);
1036
1037         /* Set PCGCCTL to 0 */
1038         DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
1039
1040         gr = core_if->gr_backup;
1041         /* Load restore values for [31:14] bits */
1042         DWC_WRITE_REG32(core_if->pcgcctl,
1043                         ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
1044
1045         /* Umnask global Interrupt in GAHBCFG and restore it */
1046         gahbcfg.d32 = gr->gahbcfg_local;
1047         gahbcfg.b.glblintrmsk = 1;
1048         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
1049
1050         /* Clear all pending interupts */
1051         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1052
1053         /* Unmask restore done interrupt */
1054         gintmsk.b.restoredone = 1;
1055         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
1056
1057         /* Restore GUSBCFG and HCFG/DCFG */
1058         gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
1059         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
1060
1061         if (is_host) {
1062                 hcfg_data_t hcfg = {.d32 = 0 };
1063                 hcfg.d32 = core_if->hr_backup->hcfg_local;
1064                 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
1065                                 hcfg.d32);
1066
1067                 /* Load restore values for [31:14] bits */
1068                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1069                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1070
1071                 if (rmode)
1072                         pcgcctl.b.restoremode = 1;
1073                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1074                 dwc_udelay(10);
1075
1076                 /* Load restore values for [31:14] bits
1077                  * and set EssRegRestored bit */
1078                 pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
1079                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1080                 pcgcctl.b.ess_reg_restored = 1;
1081                 if (rmode)
1082                         pcgcctl.b.restoremode = 1;
1083                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1084         } else {
1085                 dcfg_data_t dcfg = {.d32 = 0 };
1086                 dcfg.d32 = core_if->dr_backup->dcfg;
1087                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
1088                                 dcfg.d32);
1089
1090                 /* Load restore values for [31:14] bits */
1091                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1092                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1093                 if (!rmode)
1094                         pcgcctl.d32 |= 0x208;
1095                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1096                 dwc_udelay(10);
1097
1098                 /* Load restore values for [31:14] bits */
1099                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1100                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1101                 pcgcctl.b.ess_reg_restored = 1;
1102                 if (!rmode)
1103                         pcgcctl.d32 |= 0x208;
1104                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1105         }
1106
1107         return 0;
1108 }
1109
1110 /**
1111  * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
1112  * type.
1113  */
1114 static void init_fslspclksel(dwc_otg_core_if_t *core_if)
1115 {
1116         uint32_t val;
1117         hcfg_data_t hcfg;
1118
1119         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1120              (core_if->hwcfg2.b.fs_phy_type == 1) &&
1121              (core_if->core_params->ulpi_fs_ls)) ||
1122             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1123                 /* Full speed PHY */
1124                 val = DWC_HCFG_48_MHZ;
1125         } else {
1126                 /* High speed PHY running at full speed or high speed */
1127                 val = DWC_HCFG_30_60_MHZ;
1128         }
1129
1130         DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
1131         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
1132         hcfg.b.fslspclksel = val;
1133         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
1134 }
1135
1136 /**
1137  * Initializes the DevSpd field of the DCFG register depending on the PHY type
1138  * and the enumeration speed of the device.
1139  */
1140 static void init_devspd(dwc_otg_core_if_t *core_if)
1141 {
1142         uint32_t val;
1143         dcfg_data_t dcfg;
1144
1145         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1146              (core_if->hwcfg2.b.fs_phy_type == 1) &&
1147              (core_if->core_params->ulpi_fs_ls)) ||
1148             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1149                 /* Full speed PHY */
1150                 val = 0x3;
1151         } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
1152                 /* High speed PHY running at full speed */
1153                 val = 0x1;
1154         } else {
1155                 /* High speed PHY running at high speed */
1156                 val = 0x0;
1157         }
1158
1159         DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
1160
1161         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
1162         dcfg.b.devspd = val;
1163         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
1164 }
1165
1166 /**
1167  * This function calculates the number of IN EPS
1168  * using GHWCFG1 and GHWCFG2 registers values
1169  *
1170  * @param core_if Programming view of the DWC_otg controller
1171  */
1172 static uint32_t calc_num_in_eps(dwc_otg_core_if_t *core_if)
1173 {
1174         uint32_t num_in_eps = 0;
1175         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1176         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
1177         uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
1178         int i;
1179
1180         for (i = 0; i < num_eps; ++i) {
1181                 if (!(hwcfg1 & 0x1))
1182                         num_in_eps++;
1183
1184                 hwcfg1 >>= 2;
1185         }
1186
1187         if (core_if->hwcfg4.b.ded_fifo_en) {
1188                 num_in_eps =
1189                     (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
1190         }
1191
1192         return num_in_eps;
1193 }
1194
1195 /**
1196  * This function calculates the number of OUT EPS
1197  * using GHWCFG1 and GHWCFG2 registers values
1198  *
1199  * @param core_if Programming view of the DWC_otg controller
1200  */
1201 static uint32_t calc_num_out_eps(dwc_otg_core_if_t *core_if)
1202 {
1203         uint32_t num_out_eps = 0;
1204         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1205         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
1206         int i;
1207
1208         for (i = 0; i < num_eps; ++i) {
1209                 if (!(hwcfg1 & 0x1))
1210                         num_out_eps++;
1211
1212                 hwcfg1 >>= 2;
1213         }
1214         return num_out_eps;
1215 }
1216
1217 void dwc_otg_core_init(dwc_otg_core_if_t *core_if)
1218 {
1219         int i = 0;
1220         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1221         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1222         gahbcfg_data_t ahbcfg = {.d32 = 0 };
1223         gusbcfg_data_t usbcfg = {.d32 = 0 };
1224         gi2cctl_data_t i2cctl = {.d32 = 0 };
1225
1226         DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
1227         /* Common Initialization */
1228         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1229
1230         /* Program the ULPI External VBUS bit if needed */
1231         usbcfg.b.ulpi_ext_vbus_drv =
1232             (core_if->core_params->phy_ulpi_ext_vbus ==
1233              DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
1234
1235         /* Set external TS Dline pulsing */
1236         usbcfg.b.term_sel_dl_pulse =
1237             (core_if->core_params->ts_dline == 1) ? 1 : 0;
1238         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1239
1240         /* Reset the Controller */
1241         dwc_otg_core_reset(core_if);
1242
1243         core_if->adp_enable = core_if->core_params->adp_supp_enable;
1244         core_if->power_down = core_if->core_params->power_down;
1245
1246         /* Initialize parameters from Hardware configuration registers. */
1247         dev_if->num_in_eps = calc_num_in_eps(core_if);
1248         dev_if->num_out_eps = calc_num_out_eps(core_if);
1249
1250         DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
1251                     core_if->hwcfg4.b.num_dev_perio_in_ep);
1252
1253         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
1254                 dev_if->perio_tx_fifo_size[i] =
1255                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1256                 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
1257                             i, dev_if->perio_tx_fifo_size[i]);
1258         }
1259
1260         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
1261                 dev_if->tx_fifo_size[i] =
1262                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1263                 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
1264                             i, dev_if->tx_fifo_size[i]);
1265         }
1266
1267         core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
1268         core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
1269         core_if->nperio_tx_fifo_size =
1270             DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
1271
1272         DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
1273         DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
1274         DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
1275                     core_if->nperio_tx_fifo_size);
1276
1277         /* This programming sequence needs to happen in FS mode before any other
1278          * programming occurs */
1279         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
1280             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1281                 /* If FS mode with FS PHY */
1282
1283                 /* core_init() is now called on every switch so only call the
1284                  * following for the first time through. */
1285                 if (!core_if->phy_init_done) {
1286                         core_if->phy_init_done = 1;
1287                         DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
1288                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1289                         usbcfg.b.physel = 1;
1290                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1291
1292                         /* Reset after a PHY select */
1293                         dwc_otg_core_reset(core_if);
1294                 }
1295
1296                 /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1297                  * do this on HNP Dev/Host mode switches (done in dev_init and
1298                  * host_init). */
1299                 if (dwc_otg_is_host_mode(core_if))
1300                         init_fslspclksel(core_if);
1301                 else
1302                         init_devspd(core_if);
1303
1304                 if (core_if->core_params->i2c_enable) {
1305                         DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
1306                         /* Program GUSBCFG.OtgUtmifsSel to I2C */
1307                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1308                         usbcfg.b.otgutmifssel = 1;
1309                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1310
1311                         /* Program GI2CCTL.I2CEn */
1312                         i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
1313                         i2cctl.b.i2cdevaddr = 1;
1314                         i2cctl.b.i2cen = 0;
1315                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1316                         i2cctl.b.i2cen = 1;
1317                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1318                 }
1319
1320         } /* endif speed == DWC_SPEED_PARAM_FULL */
1321         else {
1322                 /* High speed PHY. */
1323                 if (!core_if->phy_init_done) {
1324                         core_if->phy_init_done = 1;
1325                         /* HS PHY parameters.  These parameters are preserved
1326                          * during soft reset so only program the first time.  Do
1327                          * a soft reset immediately after setting phyif.  */
1328
1329                         if (core_if->core_params->phy_type == 2) {
1330                                 /* ULPI interface */
1331                                 usbcfg.b.ulpi_utmi_sel = 1;
1332                                 usbcfg.b.phyif = 0;
1333                                 usbcfg.b.ddrsel =
1334                                     core_if->core_params->phy_ulpi_ddr;
1335                         } else if (core_if->core_params->phy_type == 1) {
1336                                 /* UTMI+ interface */
1337                                 usbcfg.b.ulpi_utmi_sel = 0;
1338                                 if (core_if->core_params->phy_utmi_width == 16)
1339                                         usbcfg.b.phyif = 1;
1340                                 else
1341                                         usbcfg.b.phyif = 0;
1342                         } else {
1343                                 DWC_ERROR("FS PHY TYPE\n");
1344                         }
1345                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1346                         /* Reset after setting the PHY parameters */
1347                         dwc_otg_core_reset(core_if);
1348                 }
1349         }
1350
1351         if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
1352             (core_if->hwcfg2.b.fs_phy_type == 1) &&
1353             (core_if->core_params->ulpi_fs_ls)) {
1354                 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
1355                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1356                 usbcfg.b.ulpi_fsls = 1;
1357                 usbcfg.b.ulpi_clk_sus_m = 1;
1358                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1359         } else {
1360                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1361                 usbcfg.b.ulpi_fsls = 0;
1362                 usbcfg.b.ulpi_clk_sus_m = 0;
1363                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1364         }
1365
1366         /* Program the GAHBCFG Register. */
1367         switch (core_if->hwcfg2.b.architecture) {
1368
1369         case DWC_SLAVE_ONLY_ARCH:
1370                 DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
1371                 ahbcfg.b.nptxfemplvl_txfemplvl =
1372                     DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1373                 ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1374                 core_if->dma_enable = 0;
1375                 core_if->dma_desc_enable = 0;
1376                 break;
1377
1378         case DWC_EXT_DMA_ARCH:
1379                 DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
1380                 {
1381                         uint8_t brst_sz = core_if->core_params->dma_burst_size;
1382                         ahbcfg.b.hburstlen = 0;
1383                         while (brst_sz > 1) {
1384                                 ahbcfg.b.hburstlen++;
1385                                 brst_sz >>= 1;
1386                         }
1387                 }
1388                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1389                 core_if->dma_desc_enable =
1390                     (core_if->core_params->dma_desc_enable != 0);
1391                 break;
1392
1393         case DWC_INT_DMA_ARCH:
1394                 DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
1395                 /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
1396                    Host mode ISOC in issue fix - vahrama */
1397                 ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR8;
1398                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1399                 core_if->dma_desc_enable =
1400                     (core_if->core_params->dma_desc_enable != 0);
1401                 break;
1402
1403         }
1404         if (core_if->dma_enable) {
1405                 if (core_if->dma_desc_enable)
1406                         DWC_PRINTF("Using Descriptor DMA mode\n");
1407                 else
1408                         DWC_PRINTF("Using Buffer DMA mode\n");
1409         } else {
1410                 DWC_PRINTF("Using Slave mode\n");
1411                 core_if->dma_desc_enable = 0;
1412         }
1413
1414         if (core_if->core_params->ahb_single)
1415                 ahbcfg.b.ahbsingle = 1;
1416
1417         ahbcfg.b.dmaenable = core_if->dma_enable;
1418         DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
1419
1420         core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
1421
1422         core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
1423         core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
1424         DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
1425                    ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
1426         DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
1427                    ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
1428
1429         /*
1430          * Program the GUSBCFG register.
1431          */
1432         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1433
1434         switch (core_if->hwcfg2.b.op_mode) {
1435         case DWC_MODE_HNP_SRP_CAPABLE:
1436                 usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
1437                                    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1438                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1439                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1440                 break;
1441
1442         case DWC_MODE_SRP_ONLY_CAPABLE:
1443                 usbcfg.b.hnpcap = 0;
1444                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1445                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1446                 break;
1447
1448         case DWC_MODE_NO_HNP_SRP_CAPABLE:
1449                 usbcfg.b.hnpcap = 0;
1450                 usbcfg.b.srpcap = 0;
1451                 break;
1452
1453         case DWC_MODE_SRP_CAPABLE_DEVICE:
1454                 usbcfg.b.hnpcap = 0;
1455                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1456                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1457                 break;
1458
1459         case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
1460                 usbcfg.b.hnpcap = 0;
1461                 usbcfg.b.srpcap = 0;
1462                 break;
1463
1464         case DWC_MODE_SRP_CAPABLE_HOST:
1465                 usbcfg.b.hnpcap = 0;
1466                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1467                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1468                 break;
1469
1470         case DWC_MODE_NO_SRP_CAPABLE_HOST:
1471                 usbcfg.b.hnpcap = 0;
1472                 usbcfg.b.srpcap = 0;
1473                 break;
1474         }
1475
1476         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1477
1478 #ifdef CONFIG_USB_DWC_OTG_LPM
1479         if (core_if->core_params->lpm_enable) {
1480                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
1481
1482                 /* To enable LPM support set lpm_cap_en bit */
1483                 lpmcfg.b.lpm_cap_en = 1;
1484
1485                 /* Make AppL1Res ACK */
1486                 lpmcfg.b.appl_resp = 1;
1487
1488                 /* Retry 3 times */
1489                 lpmcfg.b.retry_count = 3;
1490
1491                 DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
1492                                  0, lpmcfg.d32);
1493
1494         }
1495 #endif
1496         if (core_if->core_params->ic_usb_cap) {
1497                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
1498                 gusbcfg.b.ic_usb_cap = 1;
1499                 DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
1500                                  0, gusbcfg.d32);
1501         }
1502         {
1503                 gotgctl_data_t gotgctl = {.d32 = 0 };
1504                 gotgctl.b.otgver = core_if->core_params->otg_ver;
1505                 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
1506                                  gotgctl.d32);
1507                 /* Set OTG version supported */
1508                 core_if->otg_ver = core_if->core_params->otg_ver;
1509                 DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
1510                            core_if->core_params->otg_ver, core_if->otg_ver);
1511         }
1512
1513         /* Enable common interrupts */
1514         dwc_otg_enable_common_interrupts(core_if);
1515
1516         /* Do device or host intialization based on mode during PCD
1517          * and HCD initialization  */
1518         if (dwc_otg_is_host_mode(core_if)) {
1519                 DWC_PRINTF("^^^^^^^^^^^^^^^^^^Host Mode\n");
1520                 core_if->op_state = A_HOST;
1521         } else {
1522                 DWC_PRINTF("^^^^^^^^^^^^^^^^^Device Mode\n");
1523                 core_if->op_state = B_PERIPHERAL;
1524 #ifdef DWC_DEVICE_ONLY
1525                 dwc_otg_core_dev_init(core_if);
1526 #endif
1527         }
1528 }
1529
1530 /**
1531  * This function initializes the DWC_otg controller registers and
1532  * prepares the core for device mode or host mode operation.
1533  *
1534  * @param core_if Programming view of the DWC_otg controller
1535  *
1536  */
1537 void dwc_otg_core_init_no_reset(dwc_otg_core_if_t *core_if)
1538 {
1539         int i = 0;
1540         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1541         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1542         gahbcfg_data_t ahbcfg = {.d32 = 0 };
1543         gusbcfg_data_t usbcfg = {.d32 = 0 };
1544         gi2cctl_data_t i2cctl = {.d32 = 0 };
1545
1546         DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
1547         /* Common Initialization */
1548         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1549
1550         /* Program the ULPI External VBUS bit if needed */
1551         usbcfg.b.ulpi_ext_vbus_drv =
1552             (core_if->core_params->phy_ulpi_ext_vbus ==
1553              DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
1554
1555         /* Set external TS Dline pulsing */
1556         usbcfg.b.term_sel_dl_pulse =
1557             (core_if->core_params->ts_dline == 1) ? 1 : 0;
1558         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1559
1560         /* Reset the Controller */
1561         /* dwc_otg_core_reset(core_if); */
1562
1563         core_if->adp_enable = core_if->core_params->adp_supp_enable;
1564         core_if->power_down = core_if->core_params->power_down;
1565
1566         /* Initialize parameters from Hardware configuration registers. */
1567         dev_if->num_in_eps = calc_num_in_eps(core_if);
1568         dev_if->num_out_eps = calc_num_out_eps(core_if);
1569
1570         DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
1571                     core_if->hwcfg4.b.num_dev_perio_in_ep);
1572
1573         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
1574                 dev_if->perio_tx_fifo_size[i] =
1575                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1576                 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
1577                             i, dev_if->perio_tx_fifo_size[i]);
1578         }
1579
1580         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
1581                 dev_if->tx_fifo_size[i] =
1582                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1583                 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
1584                             i, dev_if->tx_fifo_size[i]);
1585         }
1586
1587         core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
1588         core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
1589         core_if->nperio_tx_fifo_size =
1590             DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
1591
1592         DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
1593         DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
1594         DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
1595                     core_if->nperio_tx_fifo_size);
1596
1597         /* This programming sequence needs to happen in FS mode before any other
1598          * programming occurs */
1599         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
1600             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1601                 /* If FS mode with FS PHY */
1602
1603                 /* core_init() is now called on every switch so only call the
1604                  * following for the first time through. */
1605                 if (!core_if->phy_init_done) {
1606                         core_if->phy_init_done = 1;
1607                         DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
1608                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1609                         usbcfg.b.physel = 1;
1610                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1611
1612                         /* Reset after a PHY select */
1613                         /* dwc_otg_core_reset(core_if); */
1614                 }
1615
1616                 /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1617                  * do this on HNP Dev/Host mode switches (done in dev_init and
1618                  * host_init). */
1619                 if (dwc_otg_is_host_mode(core_if))
1620                         init_fslspclksel(core_if);
1621                 else
1622                         init_devspd(core_if);
1623
1624                 if (core_if->core_params->i2c_enable) {
1625                         DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
1626                         /* Program GUSBCFG.OtgUtmifsSel to I2C */
1627                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1628                         usbcfg.b.otgutmifssel = 1;
1629                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1630
1631                         /* Program GI2CCTL.I2CEn */
1632                         i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
1633                         i2cctl.b.i2cdevaddr = 1;
1634                         i2cctl.b.i2cen = 0;
1635                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1636                         i2cctl.b.i2cen = 1;
1637                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1638                 }
1639
1640         } /* endif speed == DWC_SPEED_PARAM_FULL */
1641         else {
1642                 /* High speed PHY. */
1643                 if (!core_if->phy_init_done) {
1644                         core_if->phy_init_done = 1;
1645                         /* HS PHY parameters.  These parameters are preserved
1646                          * during soft reset so only program the first time.  Do
1647                          * a soft reset immediately after setting phyif.  */
1648
1649                         if (core_if->core_params->phy_type == 2) {
1650                                 /* ULPI interface */
1651                                 usbcfg.b.ulpi_utmi_sel = 1;
1652                                 usbcfg.b.phyif = 0;
1653                                 usbcfg.b.ddrsel =
1654                                     core_if->core_params->phy_ulpi_ddr;
1655                         } else if (core_if->core_params->phy_type == 1) {
1656                                 /* UTMI+ interface */
1657                                 usbcfg.b.ulpi_utmi_sel = 0;
1658                                 if (core_if->core_params->phy_utmi_width == 16)
1659                                         usbcfg.b.phyif = 1;
1660                                 else
1661                                         usbcfg.b.phyif = 0;
1662                         } else {
1663                                 DWC_ERROR("FS PHY TYPE\n");
1664                         }
1665                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1666                         /* Reset after setting the PHY parameters */
1667                         /* dwc_otg_core_reset(core_if); */
1668                 }
1669         }
1670
1671         if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
1672             (core_if->hwcfg2.b.fs_phy_type == 1) &&
1673             (core_if->core_params->ulpi_fs_ls)) {
1674                 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
1675                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1676                 usbcfg.b.ulpi_fsls = 1;
1677                 usbcfg.b.ulpi_clk_sus_m = 1;
1678                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1679         } else {
1680                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1681                 usbcfg.b.ulpi_fsls = 0;
1682                 usbcfg.b.ulpi_clk_sus_m = 0;
1683                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1684         }
1685
1686         /* Program the GAHBCFG Register. */
1687         switch (core_if->hwcfg2.b.architecture) {
1688
1689         case DWC_SLAVE_ONLY_ARCH:
1690                 DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
1691                 ahbcfg.b.nptxfemplvl_txfemplvl =
1692                     DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1693                 ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1694                 core_if->dma_enable = 0;
1695                 core_if->dma_desc_enable = 0;
1696                 break;
1697
1698         case DWC_EXT_DMA_ARCH:
1699                 DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
1700                 {
1701                         uint8_t brst_sz = core_if->core_params->dma_burst_size;
1702                         ahbcfg.b.hburstlen = 0;
1703                         while (brst_sz > 1) {
1704                                 ahbcfg.b.hburstlen++;
1705                                 brst_sz >>= 1;
1706                         }
1707                 }
1708                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1709                 core_if->dma_desc_enable =
1710                     (core_if->core_params->dma_desc_enable != 0);
1711                 break;
1712
1713         case DWC_INT_DMA_ARCH:
1714                 DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
1715                 /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
1716                    Host mode ISOC in issue fix - vahrama */
1717                 ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR8;
1718                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1719                 core_if->dma_desc_enable =
1720                     (core_if->core_params->dma_desc_enable != 0);
1721                 break;
1722
1723         }
1724         if (core_if->dma_enable) {
1725                 if (core_if->dma_desc_enable)
1726                         DWC_PRINTF("Using Descriptor DMA mode\n");
1727                 else
1728                         DWC_PRINTF("Using Buffer DMA mode\n");
1729         } else {
1730                 DWC_PRINTF("Using Slave mode\n");
1731                 core_if->dma_desc_enable = 0;
1732         }
1733
1734         if (core_if->core_params->ahb_single)
1735                 ahbcfg.b.ahbsingle = 1;
1736
1737         ahbcfg.b.dmaenable = core_if->dma_enable;
1738         DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
1739
1740         core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
1741
1742         core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
1743         core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
1744         DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
1745                    ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
1746         DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
1747                    ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
1748
1749         /*
1750          * Program the GUSBCFG register.
1751          */
1752         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1753
1754         switch (core_if->hwcfg2.b.op_mode) {
1755         case DWC_MODE_HNP_SRP_CAPABLE:
1756                 usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
1757                                    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1758                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1759                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1760                 break;
1761
1762         case DWC_MODE_SRP_ONLY_CAPABLE:
1763                 usbcfg.b.hnpcap = 0;
1764                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1765                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1766                 break;
1767
1768         case DWC_MODE_NO_HNP_SRP_CAPABLE:
1769                 usbcfg.b.hnpcap = 0;
1770                 usbcfg.b.srpcap = 0;
1771                 break;
1772
1773         case DWC_MODE_SRP_CAPABLE_DEVICE:
1774                 usbcfg.b.hnpcap = 0;
1775                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1776                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1777                 break;
1778
1779         case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
1780                 usbcfg.b.hnpcap = 0;
1781                 usbcfg.b.srpcap = 0;
1782                 break;
1783
1784         case DWC_MODE_SRP_CAPABLE_HOST:
1785                 usbcfg.b.hnpcap = 0;
1786                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1787                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1788                 break;
1789
1790         case DWC_MODE_NO_SRP_CAPABLE_HOST:
1791                 usbcfg.b.hnpcap = 0;
1792                 usbcfg.b.srpcap = 0;
1793                 break;
1794         }
1795
1796         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1797
1798 #ifdef CONFIG_USB_DWC_OTG_LPM
1799         if (core_if->core_params->lpm_enable) {
1800                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
1801
1802                 /* To enable LPM support set lpm_cap_en bit */
1803                 lpmcfg.b.lpm_cap_en = 1;
1804
1805                 /* Make AppL1Res ACK */
1806                 lpmcfg.b.appl_resp = 1;
1807
1808                 /* Retry 3 times */
1809                 lpmcfg.b.retry_count = 3;
1810
1811                 DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
1812                                  0, lpmcfg.d32);
1813
1814         }
1815 #endif
1816         if (core_if->core_params->ic_usb_cap) {
1817                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
1818                 gusbcfg.b.ic_usb_cap = 1;
1819                 DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
1820                                  0, gusbcfg.d32);
1821         }
1822         {
1823                 gotgctl_data_t gotgctl = {.d32 = 0 };
1824                 gotgctl.b.otgver = core_if->core_params->otg_ver;
1825                 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
1826                                  gotgctl.d32);
1827                 /* Set OTG version supported */
1828                 core_if->otg_ver = core_if->core_params->otg_ver;
1829                 DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
1830                            core_if->core_params->otg_ver, core_if->otg_ver);
1831         }
1832
1833         /* Enable common interrupts */
1834         dwc_otg_enable_common_interrupts(core_if);
1835
1836         /* Do device or host intialization based on mode during PCD
1837          * and HCD initialization  */
1838         if (dwc_otg_is_host_mode(core_if)) {
1839                 DWC_PRINTF("^^^^^^^^^^^^^^^^^^Host Mode\n");
1840                 core_if->op_state = A_HOST;
1841         } else {
1842                 DWC_PRINTF("^^^^^^^^^^^^^^^^^Device Mode\n");
1843                 core_if->op_state = B_PERIPHERAL;
1844 #ifdef DWC_DEVICE_ONLY
1845                 dwc_otg_core_dev_init(core_if);
1846 #endif
1847         }
1848 }
1849
1850 /**
1851  * This function enables the Device mode interrupts.
1852  *
1853  * @param core_if Programming view of DWC_otg controller
1854  */
1855 void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *core_if)
1856 {
1857         gintmsk_data_t intr_mask = {.d32 = 0 };
1858         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1859
1860         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
1861
1862         /* Disable all interrupts. */
1863         DWC_WRITE_REG32(&global_regs->gintmsk, 0);
1864
1865         /* Clear any pending interrupts */
1866         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
1867
1868         /* Enable the common interrupts */
1869         dwc_otg_enable_common_interrupts(core_if);
1870
1871         /* Enable interrupts */
1872         intr_mask.b.usbreset = 1;
1873         intr_mask.b.enumdone = 1;
1874         /* Disable Disconnect interrupt in Device mode */
1875         intr_mask.b.disconnect = 0;
1876
1877         if (!core_if->multiproc_int_enable) {
1878                 intr_mask.b.inepintr = 1;
1879                 intr_mask.b.outepintr = 1;
1880         }
1881
1882         intr_mask.b.erlysuspend = 1;
1883
1884         if (core_if->en_multiple_tx_fifo == 0)
1885                 intr_mask.b.epmismatch = 1;
1886
1887         /* intr_mask.b.incomplisoout = 1; */
1888         intr_mask.b.incomplisoin = 1;
1889
1890 /* Enable the ignore frame number for ISOC xfers - MAS */
1891 /* Disable to support high bandwith ISOC transfers - manukz */
1892 #if 0
1893 #ifdef DWC_UTE_PER_IO
1894         if (core_if->dma_enable) {
1895                 if (core_if->dma_desc_enable) {
1896                         dctl_data_t dctl1 = {.d32 = 0 };
1897                         dctl1.b.ifrmnum = 1;
1898                         DWC_MODIFY_REG32(&core_if->dev_if->
1899                                          dev_global_regs->dctl, 0, dctl1.d32);
1900                         DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
1901                                   DWC_READ_REG32(&core_if->
1902                                                  dev_if->dev_global_regs->
1903                                                  dctl));
1904                 }
1905         }
1906 #endif
1907 #endif
1908 #ifdef DWC_EN_ISOC
1909         if (core_if->dma_enable) {
1910                 if (core_if->dma_desc_enable == 0) {
1911                         if (core_if->pti_enh_enable) {
1912                                 dctl_data_t dctl = {.d32 = 0 };
1913                                 dctl.b.ifrmnum = 1;
1914                                 DWC_MODIFY_REG32(&core_if->dev_if->
1915                                                  dev_global_regs->dctl, 0,
1916                                                  dctl.d32);
1917                         } else {
1918                                 intr_mask.b.incomplisoin = 1;
1919                                 intr_mask.b.incomplisoout = 1;
1920                         }
1921                 }
1922         } else {
1923                 intr_mask.b.incomplisoin = 1;
1924                 intr_mask.b.incomplisoout = 1;
1925         }
1926 #endif /* DWC_EN_ISOC */
1927
1928         /** @todo NGS: Should this be a module parameter? */
1929 #ifdef USE_PERIODIC_EP
1930         intr_mask.b.isooutdrop = 1;
1931         intr_mask.b.eopframe = 1;
1932         intr_mask.b.incomplisoin = 1;
1933         intr_mask.b.incomplisoout = 1;
1934 #endif
1935
1936         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1937
1938         DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
1939                     DWC_READ_REG32(&global_regs->gintmsk));
1940 }
1941
1942 /**
1943  * This function initializes the DWC_otg controller registers for
1944  * device mode.
1945  *
1946  * @param core_if Programming view of DWC_otg controller
1947  *
1948  */
1949 void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if)
1950 {
1951         int i;
1952         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1953         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1954         dwc_otg_core_params_t *params = core_if->core_params;
1955         dcfg_data_t dcfg = {.d32 = 0 };
1956         depctl_data_t diepctl = {.d32 = 0 };
1957         grstctl_t resetctl = {.d32 = 0 };
1958         uint32_t rx_fifo_size;
1959         fifosize_data_t nptxfifosize;
1960         fifosize_data_t txfifosize;
1961         dthrctl_data_t dthrctl;
1962         fifosize_data_t ptxfifosize;
1963         /* uint16_t rxfsiz, nptxfsiz; */
1964         /* gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; */
1965         /* hwcfg3_data_t hwcfg3 = {.d32 = 0 }; */
1966         gotgctl_data_t gotgctl = {.d32 = 0 };
1967         gahbcfg_data_t gahbcfg = {.d32 = 0 };
1968
1969         /* Restart the Phy Clock */
1970         pcgcctl_data_t pcgcctl = {.d32 = 0 };
1971         /* Restart the Phy Clock */
1972         pcgcctl.b.stoppclk = 1;
1973         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
1974         dwc_udelay(10);
1975
1976         gahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR8;
1977         DWC_MODIFY_REG32(&global_regs->gahbcfg, 0, gahbcfg.b.hburstlen);
1978
1979         /* Device configuration register */
1980         init_devspd(core_if);
1981         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
1982         dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
1983         dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
1984         /* Enable Device OUT NAK in case of DDMA mode */
1985         if (core_if->core_params->dev_out_nak)
1986                 dcfg.b.endevoutnak = 1;
1987
1988         if (core_if->core_params->cont_on_bna) {
1989                 dctl_data_t dctl = {.d32 = 0 };
1990                 dctl.b.encontonbna = 1;
1991                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
1992         }
1993         /** should be done before every reset */
1994         if (core_if->otg_ver) {
1995                 core_if->otg_sts = 0;
1996                 gotgctl.b.devhnpen = 1;
1997                 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
1998                                  gotgctl.d32, 0);
1999         }
2000
2001         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
2002
2003         /* Configure data FIFO sizes */
2004
2005         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
2006 #ifdef DWC_UTE_CFI
2007                 core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
2008                 core_if->init_rxfsiz = params->dev_rx_fifo_size;
2009 #endif
2010                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
2011                             DWC_READ_REG32(&global_regs->grxfsiz));
2012
2013                 /** Set Periodic Tx FIFO Mask all bits 0 */
2014                 core_if->p_tx_msk = 0;
2015
2016                 /** Set Tx FIFO Mask all bits 0 */
2017                 core_if->tx_msk = 0;
2018                 /* core_if->en_multiple_tx_fifo equals
2019                  * core_if->hwcfg4.b.ded_fifo_en,
2020                  * and ded_fifo_en is 1 in default*/
2021                 if (core_if->en_multiple_tx_fifo == 0) {
2022                         /* Non-periodic Tx FIFO */
2023                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
2024                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
2025
2026                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
2027                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
2028
2029                         DWC_WRITE_REG32(&global_regs->gnptxfsiz,
2030                                         nptxfifosize.d32);
2031
2032                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
2033                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
2034
2035                         /**@todo NGS: Fix Periodic FIFO Sizing! */
2036                         /*
2037                          * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
2038                          * Indexes of the FIFO size module parameters in the
2039                          * dev_perio_tx_fifo_size array and the FIFO size registers in
2040                          * the dptxfsiz array run from 0 to 14.
2041                          */
2042                         /** @todo Finish debug of this */
2043                         ptxfifosize.b.startaddr =
2044                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
2045                         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep;
2046                              i++) {
2047                                 ptxfifosize.b.depth =
2048                                     params->dev_perio_tx_fifo_size[i];
2049                                 DWC_DEBUGPL(DBG_CIL,
2050                                             "initial dtxfsiz[%d]=%08x\n", i,
2051                                             DWC_READ_REG32(&global_regs->
2052                                                            dtxfsiz[i]));
2053                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
2054                                                 ptxfifosize.d32);
2055                                 DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
2056                                             i,
2057                                             DWC_READ_REG32(&global_regs->
2058                                                            dtxfsiz[i]));
2059                                 ptxfifosize.b.startaddr += ptxfifosize.b.depth;
2060                         }
2061                 } else {
2062                         /*
2063                          * Tx FIFOs These FIFOs are numbered from 1 to 15.
2064                          * Indexes of the FIFO size module parameters in the
2065                          * dev_tx_fifo_size array and the FIFO size registers in
2066                          * the dtxfsiz array run from 0 to 14.
2067                          */
2068
2069                         /* Non-periodic Tx FIFO */
2070                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
2071                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
2072
2073 #ifdef DWC_UTE_CFI
2074                         core_if->pwron_gnptxfsiz =
2075                             (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
2076                         core_if->init_gnptxfsiz =
2077                             params->dev_nperio_tx_fifo_size;
2078 #endif
2079                         rx_fifo_size = params->dev_rx_fifo_size;
2080                         DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
2081                         DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
2082                                     DWC_READ_REG32(&global_regs->grxfsiz));
2083
2084                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
2085                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
2086                         DWC_WRITE_REG32(&global_regs->gnptxfsiz,
2087                                         nptxfifosize.d32);
2088
2089                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
2090                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
2091
2092                         txfifosize.b.startaddr =
2093                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
2094
2095                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
2096
2097                                 txfifosize.b.depth =
2098                                     params->dev_tx_fifo_size[i];
2099
2100                                 DWC_DEBUGPL(DBG_CIL,
2101                                             "initial dtxfsiz[%d]=%08x\n",
2102                                             i,
2103                                             DWC_READ_REG32(&global_regs->dtxfsiz
2104                                                            [i]));
2105
2106 #ifdef DWC_UTE_CFI
2107                                 core_if->pwron_txfsiz[i] =
2108                                     (DWC_READ_REG32
2109                                      (&global_regs->dtxfsiz[i]) >> 16);
2110                                 core_if->init_txfsiz[i] =
2111                                     params->dev_tx_fifo_size[i];
2112 #endif
2113                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
2114                                                 txfifosize.d32);
2115
2116                                 DWC_DEBUGPL(DBG_CIL,
2117                                             "new dtxfsiz[%d]=%08x\n",
2118                                             i,
2119                                             DWC_READ_REG32(&global_regs->dtxfsiz
2120                                                            [i]));
2121
2122                                 txfifosize.b.startaddr += txfifosize.b.depth;
2123                         }
2124 #if 0
2125                         /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO
2126                          * Before 3.00a EpInfoBase was being configured in ep enable/disable
2127                          * routine as well. Starting from 3.00a it will be set to the end of
2128                          * allocated FIFO space here due to ep 0 OUT always keeping enabled
2129                          */
2130                         gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
2131                         hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
2132                         gdfifocfg.b.gdfifocfg =
2133                             (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
2134                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
2135                         if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
2136                                 rxfsiz =
2137                                     (DWC_READ_REG32(&global_regs->grxfsiz) &
2138                                      0x0000ffff);
2139                                 nptxfsiz =
2140                                     (DWC_READ_REG32(&global_regs->gnptxfsiz) >>
2141                                      16);
2142                                 gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
2143                         } else {
2144                                 gdfifocfg.b.epinfobase = txfifosize.b.startaddr;
2145                         }
2146                         /* DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); */
2147 #endif
2148                 }
2149         }
2150
2151         /* Flush the FIFOs */
2152         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
2153         dwc_otg_flush_rx_fifo(core_if);
2154
2155         /* Flush the Learning Queue. */
2156         resetctl.b.intknqflsh = 1;
2157         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
2158
2159         if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
2160                 core_if->start_predict = 0;
2161                 for (i = 0; i <= core_if->dev_if->num_in_eps; ++i)
2162                         core_if->nextep_seq[i] = 0xff;  /* 0xff - EP not active */
2163                 core_if->nextep_seq[0] = 0;
2164                 core_if->first_in_nextep_seq = 0;
2165                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
2166                 diepctl.b.nextep = 0;
2167                 DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
2168
2169                 /* Update IN Endpoint Mismatch Count
2170                  * by active IN NP EP count + 1 */
2171                 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
2172                 dcfg.b.epmscnt = 2;
2173                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
2174
2175                 DWC_DEBUGPL(DBG_CILV,
2176                             "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
2177                             __func__, core_if->first_in_nextep_seq);
2178                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++)
2179                         DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
2180                 DWC_DEBUGPL(DBG_CILV, "\n");
2181         }
2182
2183         /* Clear all pending Device Interrupts
2184          * @todo - if the condition needed to be checked
2185          * or in any case all pending interrutps should be cleared?
2186          */
2187         if (core_if->multiproc_int_enable) {
2188                 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
2189                         DWC_WRITE_REG32(&dev_if->
2190                                         dev_global_regs->diepeachintmsk[i], 0);
2191                 }
2192
2193                 for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
2194                         DWC_WRITE_REG32(&dev_if->
2195                                         dev_global_regs->doepeachintmsk[i], 0);
2196                 }
2197
2198                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
2199                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
2200         } else {
2201                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
2202                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
2203                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
2204                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
2205         }
2206
2207         for (i = 0; i <= dev_if->num_in_eps; i++) {
2208                 depctl_data_t depctl;
2209                 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
2210                 if (depctl.b.epena) {
2211                         depctl.d32 = 0;
2212                         depctl.b.epdis = 1;
2213                         depctl.b.snak = 1;
2214                 } else {
2215                         depctl.d32 = 0;
2216                 }
2217
2218                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
2219
2220                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
2221                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
2222                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
2223         }
2224
2225         for (i = 1; i <= dev_if->num_out_eps; i++) {
2226                 depctl_data_t depctl;
2227                 depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
2228                 if (depctl.b.epena) {
2229                         int j = 0;
2230                         dctl_data_t dctl = {.d32 = 0 };
2231                         gintmsk_data_t gintsts = {.d32 = 0 };
2232                         doepint_data_t doepint = {.d32 = 0 };
2233                         dctl.b.sgoutnak = 1;
2234                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
2235                                          dctl, 0, dctl.d32);
2236                         do {
2237                                 j++;
2238                                 dwc_udelay(10);
2239                                 gintsts.d32 =
2240                                     DWC_READ_REG32(&core_if->core_global_regs->
2241                                                    gintsts);
2242                                 if (j == 100000) {
2243                                         DWC_ERROR
2244                                             ("SNAK as not set during 10s\n");
2245                                         break;
2246                                 }
2247                         } while (!gintsts.b.goutnakeff);
2248                         gintsts.d32 = 0;
2249                         gintsts.b.goutnakeff = 1;
2250                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,
2251                                         gintsts.d32);
2252
2253                         depctl.d32 = 0;
2254                         depctl.b.epdis = 1;
2255                         depctl.b.snak = 1;
2256                         j = 0;
2257                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
2258                                         doepctl, depctl.d32);
2259                         do {
2260                                 dwc_udelay(10);
2261                                 doepint.d32 =
2262                                     DWC_READ_REG32(&core_if->
2263                                                    dev_if->out_ep_regs[i]->
2264                                                    doepint);
2265                                 if (j == 100000) {
2266                                         DWC_ERROR
2267                                             ("EPDIS was not set during 10s\n");
2268                                         break;
2269                                 }
2270                         } while (!doepint.b.epdisabled);
2271
2272                         doepint.b.epdisabled = 1;
2273                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
2274                                         doepint, doepint.d32);
2275
2276                         dctl.d32 = 0;
2277                         dctl.b.cgoutnak = 1;
2278                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
2279                                          dctl, 0, dctl.d32);
2280                 } else {
2281                         depctl.d32 = 0;
2282                 }
2283
2284                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
2285                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
2286                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
2287                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
2288         }
2289
2290         if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
2291                 dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
2292                 dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
2293                 dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
2294
2295                 dev_if->rx_thr_length = params->rx_thr_length;
2296                 dev_if->tx_thr_length = params->tx_thr_length;
2297
2298                 dev_if->setup_desc_index = 0;
2299
2300                 dthrctl.d32 = 0;
2301                 dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
2302                 dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
2303                 dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
2304                 dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
2305                 dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
2306                 dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
2307
2308                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
2309                                 dthrctl.d32);
2310
2311                 DWC_DEBUGPL(DBG_CIL,
2312                             "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
2313                             dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
2314                             dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
2315                             dthrctl.b.rx_thr_len);
2316
2317         }
2318
2319         dwc_otg_enable_device_interrupts(core_if);
2320
2321         {
2322                 diepmsk_data_t msk = {.d32 = 0 };
2323                 msk.b.txfifoundrn = 1;
2324                 if (core_if->multiproc_int_enable) {
2325                         DWC_MODIFY_REG32(&dev_if->
2326                                          dev_global_regs->diepeachintmsk[0],
2327                                          msk.d32, msk.d32);
2328                 } else {
2329                         DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
2330                                          msk.d32, msk.d32);
2331                 }
2332         }
2333
2334         if (core_if->multiproc_int_enable) {
2335                 /* Set NAK on Babble */
2336                 dctl_data_t dctl = {.d32 = 0 };
2337                 dctl.b.nakonbble = 1;
2338                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
2339         }
2340 }
2341
2342 /**
2343  * This function enables the Host mode interrupts.
2344  *
2345  * @param core_if Programming view of DWC_otg controller
2346  */
2347 void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *core_if)
2348 {
2349         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2350         gintmsk_data_t intr_mask = {.d32 = 0 };
2351
2352         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
2353
2354         /* Disable all interrupts. */
2355         DWC_WRITE_REG32(&global_regs->gintmsk, 0);
2356
2357         /* Clear any pending interrupts. */
2358         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
2359
2360         /* Enable the common interrupts */
2361         dwc_otg_enable_common_interrupts(core_if);
2362
2363         /*
2364          * Enable host mode interrupts without disturbing common
2365          * interrupts.
2366          */
2367
2368         intr_mask.b.disconnect = 1;
2369         intr_mask.b.portintr = 1;
2370         intr_mask.b.hcintr = 1;
2371
2372         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
2373 }
2374
2375 /**
2376  * This function disables the Host Mode interrupts.
2377  *
2378  * @param core_if Programming view of DWC_otg controller
2379  */
2380 void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *core_if)
2381 {
2382         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2383         gintmsk_data_t intr_mask = {.d32 = 0 };
2384
2385         DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
2386
2387         /*
2388          * Disable host mode interrupts without disturbing common
2389          * interrupts.
2390          */
2391         intr_mask.b.sofintr = 1;
2392         intr_mask.b.portintr = 1;
2393         intr_mask.b.hcintr = 1;
2394         intr_mask.b.ptxfempty = 1;
2395         intr_mask.b.nptxfempty = 1;
2396
2397         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
2398 }
2399
2400 /**
2401  * This function initializes the DWC_otg controller registers for
2402  * host mode.
2403  *
2404  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
2405  * request queues. Host channels are reset to ensure that they are ready for
2406  * performing transfers.
2407  *
2408  * @param core_if Programming view of DWC_otg controller
2409  *
2410  */
2411 void dwc_otg_core_host_init(dwc_otg_core_if_t *core_if)
2412 {
2413         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2414         dwc_otg_host_if_t *host_if = core_if->host_if;
2415         dwc_otg_core_params_t *params = core_if->core_params;
2416         hprt0_data_t hprt0 = {.d32 = 0 };
2417         fifosize_data_t nptxfifosize;
2418         fifosize_data_t ptxfifosize;
2419         /* uint16_t rxfsiz, nptxfsiz, hptxfsiz; */
2420         /* gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; */
2421         int i;
2422         hcchar_data_t hcchar;
2423         hcfg_data_t hcfg;
2424         hfir_data_t hfir;
2425         dwc_otg_hc_regs_t *hc_regs;
2426         int num_channels;
2427         gotgctl_data_t gotgctl = {.d32 = 0 };
2428         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2429         struct dwc_otg_platform_data *pldata;
2430         pldata = core_if->otg_dev->pldata;
2431
2432         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
2433
2434         /* Restart the Phy Clock */
2435         pcgcctl.b.stoppclk = 1;
2436         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
2437         dwc_udelay(10);
2438
2439         if ((core_if->otg_ver == 1) && (core_if->op_state == A_HOST)) {
2440                 DWC_PRINTF("Init: Port Power? op_state=%d\n",
2441                            core_if->op_state);
2442                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2443                 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2444                 if (hprt0.b.prtpwr == 0) {
2445                         hprt0.b.prtpwr = 1;
2446                         DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
2447                 }
2448         }
2449
2450         /* Initialize Host Configuration Register */
2451         init_fslspclksel(core_if);
2452         if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
2453                 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
2454                 hcfg.b.fslssupp = 1;
2455                 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
2456
2457         }
2458
2459         /* This bit allows dynamic reloading of the HFIR register
2460          * during runtime. This bit needs to be programmed during
2461          * initial configuration and its value must not be changed
2462          * during runtime.*/
2463         if (core_if->core_params->reload_ctl == 1) {
2464                 hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
2465                 hfir.b.hfirrldctrl = 1;
2466                 DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
2467         }
2468
2469         if (core_if->core_params->dma_desc_enable) {
2470                 uint8_t op_mode = core_if->hwcfg2.b.op_mode;
2471                 if (!
2472                     (core_if->hwcfg4.b.desc_dma
2473                      && (core_if->snpsid >= OTG_CORE_REV_2_90a)
2474                      && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
2475                          || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
2476                          || (op_mode ==
2477                              DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
2478                          || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
2479                          || (op_mode ==
2480                              DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
2481
2482                         DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
2483                                   "Either core version is below 2.90a or "
2484                                   "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
2485                                   "To run the driver in Buffer DMA host mode set dma_desc_enable "
2486                                   "module parameter to 0.\n");
2487                         return;
2488                 }
2489                 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
2490                 hcfg.b.descdma = 1;
2491                 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
2492         }
2493
2494         /* Configure data FIFO sizes */
2495         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
2496                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
2497                             core_if->total_fifo_size);
2498                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
2499                             params->host_rx_fifo_size);
2500                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
2501                             params->host_nperio_tx_fifo_size);
2502                 DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
2503                             params->host_perio_tx_fifo_size);
2504
2505                 /* Rx FIFO */
2506                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
2507                             DWC_READ_REG32(&global_regs->grxfsiz));
2508                 /* params->host_rx_fifo_size  */
2509                 DWC_WRITE_REG32(&global_regs->grxfsiz, 0x0200);
2510                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
2511                             DWC_READ_REG32(&global_regs->grxfsiz));
2512
2513                 /* Non-periodic Tx FIFO */
2514                 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
2515                             DWC_READ_REG32(&global_regs->gnptxfsiz));
2516                 /* params->host_nperio_tx_fifo_size */
2517                 nptxfifosize.b.depth = 0x0080;
2518                 /* params->host_rx_fifo_size */
2519                 nptxfifosize.b.startaddr = 0x0200;
2520                 DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
2521                 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
2522                             DWC_READ_REG32(&global_regs->gnptxfsiz));
2523
2524                 /* Periodic Tx FIFO */
2525                 DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
2526                             DWC_READ_REG32(&global_regs->hptxfsiz));
2527                 /* params->host_perio_tx_fifo_size */
2528                 ptxfifosize.b.depth = 0x0100;
2529                 /* nptxfifosize.b.startaddr + nptxfifosize.b.depth */
2530                 ptxfifosize.b.startaddr = 0x0280;
2531                 DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
2532                 DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
2533                             DWC_READ_REG32(&global_regs->hptxfsiz));
2534 #if 0
2535                 /* core_if->en_multiple_tx_fifo equals core_if->hwcfg4.b.ded_fifo_en,
2536                  * and ded_fifo_en is 1 in default
2537                  */
2538                 if (core_if->en_multiple_tx_fifo) {
2539                         /* Global DFIFOCFG calculation for Host mode
2540                          * - include RxFIFO, NPTXFIFO and HPTXFIFO */
2541                         gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
2542                         rxfsiz =
2543                             (DWC_READ_REG32(&global_regs->grxfsiz) &
2544                              0x0000ffff);
2545                         nptxfsiz =
2546                             (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
2547                         hptxfsiz =
2548                             (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
2549                         gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
2550                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
2551                 }
2552 #endif
2553         }
2554
2555         /* TODO - check this */
2556         /* Clear Host Set HNP Enable in the OTG Control Register */
2557         gotgctl.b.hstsethnpen = 1;
2558         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
2559         /* Make sure the FIFOs are flushed
2560          * all TX FIFOs */
2561         dwc_otg_flush_tx_fifo(core_if, 0x10);
2562         dwc_otg_flush_rx_fifo(core_if);
2563
2564         /* Clear Host Set HNP Enable in the OTG Control Register */
2565         gotgctl.b.hstsethnpen = 1;
2566         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
2567
2568         if (!core_if->core_params->dma_desc_enable) {
2569                 /* Flush out any leftover queued requests. */
2570                 num_channels = core_if->core_params->host_channels;
2571
2572                 for (i = 0; i < num_channels; i++) {
2573                         hc_regs = core_if->host_if->hc_regs[i];
2574                         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2575                         hcchar.b.chen = 0;
2576                         hcchar.b.chdis = 1;
2577                         hcchar.b.epdir = 0;
2578                         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2579                 }
2580
2581                 /* Halt all channels to put them into a known state. */
2582                 for (i = 0; i < num_channels; i++) {
2583                         int count = 0;
2584                         hc_regs = core_if->host_if->hc_regs[i];
2585                         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2586                         hcchar.b.chen = 1;
2587                         hcchar.b.chdis = 1;
2588                         hcchar.b.epdir = 0;
2589                         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2590                         DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__,
2591                                     i);
2592                         do {
2593                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2594                                 if (++count > 1000) {
2595                                         DWC_ERROR
2596                                             ("%s: Unable to clear halt on channel %d\n",
2597                                              __func__, i);
2598                                         break;
2599                                 }
2600                                 dwc_udelay(1);
2601                         } while (hcchar.b.chen);
2602                 }
2603         }
2604
2605         /* Turn on the vbus power. */
2606         if ((core_if->otg_ver == 0) && (core_if->op_state == A_HOST)) {
2607                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2608                 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2609                 if (hprt0.b.prtpwr == 0) {
2610                         hprt0.b.prtpwr = 1;
2611                         DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
2612                 }
2613                 if (pldata->power_enable)
2614                         pldata->power_enable(1);
2615         }
2616
2617         dwc_otg_enable_host_interrupts(core_if);
2618 }
2619
2620 /**
2621  * Prepares a host channel for transferring packets to/from a specific
2622  * endpoint. The HCCHARn register is set up with the characteristics specified
2623  * in _hc. Host channel interrupts that may need to be serviced while this
2624  * transfer is in progress are enabled.
2625  *
2626  * @param core_if Programming view of DWC_otg controller
2627  * @param hc Information needed to initialize the host channel
2628  */
2629 void dwc_otg_hc_init(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2630 {
2631         uint32_t intr_enable;
2632         hcintmsk_data_t hc_intr_mask;
2633         gintmsk_data_t gintmsk = {.d32 = 0 };
2634         hcchar_data_t hcchar;
2635         hcsplt_data_t hcsplt;
2636
2637         uint8_t hc_num = hc->hc_num;
2638         dwc_otg_host_if_t *host_if = core_if->host_if;
2639         dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
2640
2641         /* Clear old interrupt conditions for this host channel. */
2642         hc_intr_mask.d32 = 0xFFFFFFFF;
2643         hc_intr_mask.b.reserved14_31 = 0;
2644         DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
2645
2646         /* Enable channel interrupts required for this transfer. */
2647         hc_intr_mask.d32 = 0;
2648         hc_intr_mask.b.chhltd = 1;
2649         if (core_if->dma_enable) {
2650                 /* For Descriptor DMA mode core halts the channel
2651                  * on AHB error. Interrupt is not required */
2652                 if (!core_if->dma_desc_enable)
2653                         hc_intr_mask.b.ahberr = 1;
2654                 else {
2655                         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
2656                                 hc_intr_mask.b.xfercompl = 1;
2657                 }
2658
2659                 if (hc->error_state && !hc->do_split &&
2660                     hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
2661                         hc_intr_mask.b.ack = 1;
2662                         if (hc->ep_is_in) {
2663                                 hc_intr_mask.b.datatglerr = 1;
2664                                 if (hc->ep_type != DWC_OTG_EP_TYPE_INTR)
2665                                         hc_intr_mask.b.nak = 1;
2666                         }
2667                 }
2668         } else {
2669                 switch (hc->ep_type) {
2670                 case DWC_OTG_EP_TYPE_CONTROL:
2671                 case DWC_OTG_EP_TYPE_BULK:
2672                         hc_intr_mask.b.xfercompl = 1;
2673                         hc_intr_mask.b.stall = 1;
2674                         hc_intr_mask.b.xacterr = 1;
2675                         hc_intr_mask.b.datatglerr = 1;
2676                         if (hc->ep_is_in) {
2677                                 hc_intr_mask.b.bblerr = 1;
2678                         } else {
2679                                 hc_intr_mask.b.nak = 1;
2680                                 hc_intr_mask.b.nyet = 1;
2681                                 if (hc->do_ping)
2682                                         hc_intr_mask.b.ack = 1;
2683                         }
2684
2685                         if (hc->do_split) {
2686                                 hc_intr_mask.b.nak = 1;
2687                                 if (hc->complete_split)
2688                                         hc_intr_mask.b.nyet = 1;
2689                                 else
2690                                         hc_intr_mask.b.ack = 1;
2691                         }
2692
2693                         if (hc->error_state)
2694                                 hc_intr_mask.b.ack = 1;
2695                         break;
2696                 case DWC_OTG_EP_TYPE_INTR:
2697                         hc_intr_mask.b.xfercompl = 1;
2698                         hc_intr_mask.b.nak = 1;
2699                         hc_intr_mask.b.stall = 1;
2700                         hc_intr_mask.b.xacterr = 1;
2701                         hc_intr_mask.b.datatglerr = 1;
2702                         hc_intr_mask.b.frmovrun = 1;
2703
2704                         if (hc->ep_is_in)
2705                                 hc_intr_mask.b.bblerr = 1;
2706                         if (hc->error_state)
2707                                 hc_intr_mask.b.ack = 1;
2708                         if (hc->do_split) {
2709                                 if (hc->complete_split)
2710                                         hc_intr_mask.b.nyet = 1;
2711                                 else
2712                                         hc_intr_mask.b.ack = 1;
2713                         }
2714                         break;
2715                 case DWC_OTG_EP_TYPE_ISOC:
2716                         hc_intr_mask.b.xfercompl = 1;
2717                         hc_intr_mask.b.frmovrun = 1;
2718                         hc_intr_mask.b.ack = 1;
2719
2720                         if (hc->ep_is_in) {
2721                                 hc_intr_mask.b.xacterr = 1;
2722                                 hc_intr_mask.b.bblerr = 1;
2723                         }
2724                         break;
2725                 }
2726         }
2727         DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
2728
2729         /* Enable the top level host channel interrupt. */
2730         intr_enable = (1 << hc_num);
2731         DWC_MODIFY_REG32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
2732
2733         /* Make sure host channel interrupts are enabled. */
2734         gintmsk.b.hcintr = 1;
2735         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
2736
2737         /*
2738          * Program the HCCHARn register with the endpoint characteristics for
2739          * the current transfer.
2740          */
2741         hcchar.d32 = 0;
2742         hcchar.b.devaddr = hc->dev_addr;
2743         hcchar.b.epnum = hc->ep_num;
2744         hcchar.b.epdir = hc->ep_is_in;
2745         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2746         hcchar.b.eptype = hc->ep_type;
2747         hcchar.b.mps = hc->max_packet;
2748
2749         DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
2750
2751         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2752         DWC_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n", hcchar.b.devaddr);
2753         DWC_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n", hcchar.b.epnum);
2754         DWC_DEBUGPL(DBG_HCDV, "  Is In: %d\n", hcchar.b.epdir);
2755         DWC_DEBUGPL(DBG_HCDV, "  Is Low Speed: %d\n", hcchar.b.lspddev);
2756         DWC_DEBUGPL(DBG_HCDV, "  Ep Type: %d\n", hcchar.b.eptype);
2757         DWC_DEBUGPL(DBG_HCDV, "  Max Pkt: %d\n", hcchar.b.mps);
2758         DWC_DEBUGPL(DBG_HCDV, "  Multi Cnt: %d\n", hcchar.b.multicnt);
2759
2760         /*
2761          * Program the HCSPLIT register for SPLITs
2762          */
2763         hcsplt.d32 = 0;
2764         if (hc->do_split) {
2765                 DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
2766                             hc->hc_num,
2767                             hc->complete_split ? "CSPLIT" : "SSPLIT");
2768                 hcsplt.b.compsplt = hc->complete_split;
2769                 hcsplt.b.xactpos = hc->xact_pos;
2770                 hcsplt.b.hubaddr = hc->hub_addr;
2771                 hcsplt.b.prtaddr = hc->port_addr;
2772                 DWC_DEBUGPL(DBG_HCDV, "   comp split %d\n", hc->complete_split);
2773                 DWC_DEBUGPL(DBG_HCDV, "   xact pos %d\n", hc->xact_pos);
2774                 DWC_DEBUGPL(DBG_HCDV, "   hub addr %d\n", hc->hub_addr);
2775                 DWC_DEBUGPL(DBG_HCDV, "   port addr %d\n", hc->port_addr);
2776                 DWC_DEBUGPL(DBG_HCDV, "   is_in %d\n", hc->ep_is_in);
2777                 DWC_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n", hcchar.b.mps);
2778                 DWC_DEBUGPL(DBG_HCDV, "   xferlen: %d\n", hc->xfer_len);
2779         }
2780         DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
2781
2782 }
2783
2784 /**
2785  * Attempts to halt a host channel. This function should only be called in
2786  * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
2787  * normal circumstances in DMA mode, the controller halts the channel when the
2788  * transfer is complete or a condition occurs that requires application
2789  * intervention.
2790  *
2791  * In slave mode, checks for a free request queue entry, then sets the Channel
2792  * Enable and Channel Disable bits of the Host Channel Characteristics
2793  * register of the specified channel to intiate the halt. If there is no free
2794  * request queue entry, sets only the Channel Disable bit of the HCCHARn
2795  * register to flush requests for this channel. In the latter case, sets a
2796  * flag to indicate that the host channel needs to be halted when a request
2797  * queue slot is open.
2798  *
2799  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
2800  * HCCHARn register. The controller ensures there is space in the request
2801  * queue before submitting the halt request.
2802  *
2803  * Some time may elapse before the core flushes any posted requests for this
2804  * host channel and halts. The Channel Halted interrupt handler completes the
2805  * deactivation of the host channel.
2806  *
2807  * @param core_if Controller register interface.
2808  * @param hc Host channel to halt.
2809  * @param halt_status Reason for halting the channel.
2810  */
2811 void dwc_otg_hc_halt(dwc_otg_core_if_t *core_if,
2812                      dwc_hc_t *hc, dwc_otg_halt_status_e halt_status)
2813 {
2814         gnptxsts_data_t nptxsts;
2815         hptxsts_data_t hptxsts;
2816         hcchar_data_t hcchar;
2817         dwc_otg_hc_regs_t *hc_regs;
2818         dwc_otg_core_global_regs_t *global_regs;
2819         dwc_otg_host_global_regs_t *host_global_regs;
2820
2821         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2822         global_regs = core_if->core_global_regs;
2823         host_global_regs = core_if->host_if->host_global_regs;
2824
2825         DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
2826                    "halt_status = %d\n", halt_status);
2827
2828         if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
2829             halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
2830                 /*
2831                  * Disable all channel interrupts except Ch Halted. The QTD
2832                  * and QH state associated with this transfer has been cleared
2833                  * (in the case of URB_DEQUEUE), so the channel needs to be
2834                  * shut down carefully to prevent crashes.
2835                  */
2836                 hcintmsk_data_t hcintmsk;
2837                 hcintmsk.d32 = 0;
2838                 hcintmsk.b.chhltd = 1;
2839                 DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
2840
2841                 /*
2842                  * Make sure no other interrupts besides halt are currently
2843                  * pending. Handling another interrupt could cause a crash due
2844                  * to the QTD and QH state.
2845                  */
2846                 DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
2847
2848                 /*
2849                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
2850                  * even if the channel was already halted for some other
2851                  * reason.
2852                  */
2853                 hc->halt_status = halt_status;
2854
2855                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2856                 if (hcchar.b.chen == 0) {
2857                         /*
2858                          * The channel is either already halted or it hasn't
2859                          * started yet. In DMA mode, the transfer may halt if
2860                          * it finishes normally or a condition occurs that
2861                          * requires driver intervention. Don't want to halt
2862                          * the channel again. In either Slave or DMA mode,
2863                          * it's possible that the transfer has been assigned
2864                          * to a channel, but not started yet when an URB is
2865                          * dequeued. Don't want to halt a channel that hasn't
2866                          * started yet.
2867                          */
2868                         return;
2869                 }
2870         }
2871         if (hc->halt_pending) {
2872                 /*
2873                  * A halt has already been issued for this channel. This might
2874                  * happen when a transfer is aborted by a higher level in
2875                  * the stack.
2876                  */
2877 #ifdef DEBUG
2878                 DWC_PRINTF
2879                     ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
2880                      __func__, hc->hc_num);
2881
2882 #endif
2883                 return;
2884         }
2885
2886         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2887
2888         /* No need to set the bit in DDMA for disabling the channel
2889          * TODO check it everywhere channel is disabled */
2890         if (!core_if->core_params->dma_desc_enable)
2891                 hcchar.b.chen = 1;
2892         hcchar.b.chdis = 1;
2893
2894         if (!core_if->dma_enable) {
2895                 /* Check for space in the request queue to issue the halt. */
2896                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
2897                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
2898                         nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
2899                         if (nptxsts.b.nptxqspcavail == 0)
2900                                 hcchar.b.chen = 0;
2901                 } else {
2902                         hptxsts.d32 =
2903                             DWC_READ_REG32(&host_global_regs->hptxsts);
2904                         if ((hptxsts.b.ptxqspcavail == 0)
2905                             || (core_if->queuing_high_bandwidth)) {
2906                                 hcchar.b.chen = 0;
2907                         }
2908                 }
2909         }
2910         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2911
2912         hc->halt_status = halt_status;
2913
2914         if (hcchar.b.chen) {
2915                 hc->halt_pending = 1;
2916                 hc->halt_on_queue = 0;
2917         } else {
2918                 hc->halt_on_queue = 1;
2919         }
2920
2921         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2922         DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
2923         DWC_DEBUGPL(DBG_HCDV, "  halt_pending: %d\n", hc->halt_pending);
2924         DWC_DEBUGPL(DBG_HCDV, "  halt_on_queue: %d\n", hc->halt_on_queue);
2925         DWC_DEBUGPL(DBG_HCDV, "  halt_status: %d\n", hc->halt_status);
2926
2927         return;
2928 }
2929
2930 /**
2931  * Clears the transfer state for a host channel. This function is normally
2932  * called after a transfer is done and the host channel is being released.
2933  *
2934  * @param core_if Programming view of DWC_otg controller.
2935  * @param hc Identifies the host channel to clean up.
2936  */
2937 void dwc_otg_hc_cleanup(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2938 {
2939         dwc_otg_hc_regs_t *hc_regs;
2940
2941         hc->xfer_started = 0;
2942
2943         /*
2944          * Clear channel interrupt enables and any unhandled channel interrupt
2945          * conditions.
2946          */
2947         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2948         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
2949         DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
2950 #ifdef DEBUG
2951         DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
2952 #endif
2953 }
2954
2955 /**
2956  * Sets the channel property that indicates in which frame a periodic transfer
2957  * should occur. This is always set to the _next_ frame. This function has no
2958  * effect on non-periodic transfers.
2959  *
2960  * @param core_if Programming view of DWC_otg controller.
2961  * @param hc Identifies the host channel to set up and its properties.
2962  * @param hcchar Current value of the HCCHAR register for the specified host
2963  * channel.
2964  */
2965 static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *core_if,
2966                                          dwc_hc_t *hc, hcchar_data_t *hcchar)
2967 {
2968         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2969             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2970                 hfnum_data_t hfnum;
2971                 hfnum.d32 =
2972                     DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
2973
2974                 /* 1 if _next_ frame is odd, 0 if it's even */
2975                 hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
2976 #ifdef DEBUG
2977                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
2978                     && !hc->complete_split) {
2979                         switch (hfnum.b.frnum & 0x7) {
2980                         case 7:
2981                                 core_if->hfnum_7_samples++;
2982                                 core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
2983                                 break;
2984                         case 0:
2985                                 core_if->hfnum_0_samples++;
2986                                 core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
2987                                 break;
2988                         default:
2989                                 core_if->hfnum_other_samples++;
2990                                 core_if->hfnum_other_frrem_accum +=
2991                                     hfnum.b.frrem;
2992                                 break;
2993                         }
2994                 }
2995 #endif
2996         }
2997 }
2998
2999 #ifdef DEBUG
3000 void hc_xfer_timeout(void *ptr)
3001 {
3002         hc_xfer_info_t *xfer_info = NULL;
3003         int hc_num = 0;
3004
3005         if (ptr)
3006                 xfer_info = (hc_xfer_info_t *) ptr;
3007
3008         if (!xfer_info->hc) {
3009                 DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
3010                 return;
3011         }
3012
3013         hc_num = xfer_info->hc->hc_num;
3014         DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
3015         DWC_WARN("      start_hcchar_val 0x%08x\n",
3016                  xfer_info->core_if->start_hcchar_val[hc_num]);
3017 }
3018 #endif
3019
3020 void ep_xfer_timeout(void *ptr)
3021 {
3022         ep_xfer_info_t *xfer_info = NULL;
3023         int ep_num = 0;
3024         dctl_data_t dctl = {.d32 = 0 };
3025         gintsts_data_t gintsts = {.d32 = 0 };
3026         gintmsk_data_t gintmsk = {.d32 = 0 };
3027
3028         if (ptr)
3029                 xfer_info = (ep_xfer_info_t *) ptr;
3030
3031         if (!xfer_info->ep) {
3032                 DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
3033                 return;
3034         }
3035
3036         ep_num = xfer_info->ep->num;
3037         DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
3038         /* Put the sate to 2 as it was time outed */
3039         xfer_info->state = 2;
3040
3041         dctl.d32 =
3042             DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
3043         gintsts.d32 =
3044             DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
3045         gintmsk.d32 =
3046             DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
3047
3048         if (!gintmsk.b.goutnakeff) {
3049                 /* Unmask it */
3050                 gintmsk.b.goutnakeff = 1;
3051                 DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
3052                                 gintmsk.d32);
3053
3054         }
3055
3056         if (!gintsts.b.goutnakeff)
3057                 dctl.b.sgoutnak = 1;
3058
3059         DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
3060                         dctl.d32);
3061
3062 }
3063
3064 void set_pid_isoc(dwc_hc_t *hc)
3065 {
3066         /* Set up the initial PID for the transfer. */
3067         if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
3068                 if (hc->ep_is_in) {
3069                         if (hc->multi_count == 1)
3070                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
3071                         else if (hc->multi_count == 2)
3072                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
3073                         else
3074                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
3075                 } else {
3076                         if (hc->multi_count == 1)
3077                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
3078                         else
3079                                 hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
3080                 }
3081         } else {
3082                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
3083         }
3084 }
3085
3086 /**
3087  * This function does the setup for a data transfer for a host channel and
3088  * starts the transfer. May be called in either Slave mode or DMA mode. In
3089  * Slave mode, the caller must ensure that there is sufficient space in the
3090  * request queue and Tx Data FIFO.
3091  *
3092  * For an OUT transfer in Slave mode, it loads a data packet into the
3093  * appropriate FIFO. If necessary, additional data packets will be loaded in
3094  * the Host ISR.
3095  *
3096  * For an IN transfer in Slave mode, a data packet is requested. The data
3097  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
3098  * additional data packets are requested in the Host ISR.
3099  *
3100  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
3101  * register along with a packet count of 1 and the channel is enabled. This
3102  * causes a single PING transaction to occur. Other fields in HCTSIZ are
3103  * simply set to 0 since no data transfer occurs in this case.
3104  *
3105  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
3106  * all the information required to perform the subsequent data transfer. In
3107  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
3108  * controller performs the entire PING protocol, then starts the data
3109  * transfer.
3110  *
3111  * @param core_if Programming view of DWC_otg controller.
3112  * @param hc Information needed to initialize the host channel. The xfer_len
3113  * value may be reduced to accommodate the max widths of the XferSize and
3114  * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
3115  * to reflect the final xfer_len value.
3116  */
3117 void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3118 {
3119         hcchar_data_t hcchar;
3120         hctsiz_data_t hctsiz;
3121         uint16_t num_packets;
3122         uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
3123         uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
3124         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3125
3126         hctsiz.d32 = 0;
3127
3128         if (hc->do_ping) {
3129                 if (!core_if->dma_enable) {
3130                         dwc_otg_hc_do_ping(core_if, hc);
3131                         hc->xfer_started = 1;
3132                         return;
3133                 } else {
3134                         hctsiz.b.dopng = 1;
3135                 }
3136         }
3137
3138         if (hc->do_split) {
3139                 num_packets = 1;
3140
3141                 if (hc->complete_split && !hc->ep_is_in) {
3142                         /* For CSPLIT OUT Transfer, set the size to 0 so the
3143                          * core doesn't expect any data written to the FIFO */
3144                         hc->xfer_len = 0;
3145                 } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
3146                         hc->xfer_len = hc->max_packet;
3147                 } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
3148                         hc->xfer_len = 188;
3149                 }
3150
3151                 hctsiz.b.xfersize = hc->xfer_len;
3152         } else {
3153                 /*
3154                  * Ensure that the transfer length and packet count will fit
3155                  * in the widths allocated for them in the HCTSIZn register.
3156                  */
3157                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
3158                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
3159                         /*
3160                          * Make sure the transfer size is no larger than one
3161                          * (micro)frame's worth of data. (A check was done
3162                          * when the periodic transfer was accepted to ensure
3163                          * that a (micro)frame's worth of data can be
3164                          * programmed into a channel.)
3165                          */
3166                         uint32_t max_periodic_len =
3167                             hc->multi_count * hc->max_packet;
3168                         if (hc->xfer_len > max_periodic_len)
3169                                 hc->xfer_len = max_periodic_len;
3170                 } else if (hc->xfer_len > max_hc_xfer_size) {
3171                         /* Make sure that xfer_len is a
3172                          * multiple of max packet size. */
3173                         hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
3174                 }
3175
3176                 if (hc->xfer_len > 0) {
3177                         num_packets =
3178                             (hc->xfer_len + hc->max_packet -
3179                              1) / hc->max_packet;
3180                         if (num_packets > max_hc_pkt_count) {
3181                                 num_packets = max_hc_pkt_count;
3182                                 hc->xfer_len = num_packets * hc->max_packet;
3183                         }
3184                 } else {
3185                         /* Need 1 packet for transfer length of 0. */
3186                         num_packets = 1;
3187                 }
3188
3189                 if (hc->ep_is_in) {
3190                         /* Always program an integral # of max packets for IN transfers. */
3191                         hc->xfer_len = num_packets * hc->max_packet;
3192                 }
3193
3194                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
3195                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
3196                         /*
3197                          * Make sure that the multi_count field matches the
3198                          * actual transfer length.
3199                          */
3200                         hc->multi_count = num_packets;
3201                 }
3202
3203                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
3204                         set_pid_isoc(hc);
3205
3206                 hctsiz.b.xfersize = hc->xfer_len;
3207         }
3208
3209         hc->start_pkt_count = num_packets;
3210         hctsiz.b.pktcnt = num_packets;
3211         hctsiz.b.pid = hc->data_pid_start;
3212         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
3213
3214         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3215         DWC_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
3216         DWC_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n", hctsiz.b.pktcnt);
3217         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
3218
3219         if (core_if->dma_enable) {
3220                 dwc_dma_t dma_addr;
3221                 if (hc->align_buff)
3222                         dma_addr = hc->align_buff;
3223                 else
3224                         dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
3225                 DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
3226         }
3227
3228         /* Start the split */
3229         if (hc->do_split) {
3230                 hcsplt_data_t hcsplt;
3231                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
3232                 hcsplt.b.spltena = 1;
3233                 DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
3234         }
3235
3236         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3237         hcchar.b.multicnt = hc->multi_count;
3238         hc_set_even_odd_frame(core_if, hc, &hcchar);
3239 #ifdef DEBUG
3240         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
3241         if (hcchar.b.chdis) {
3242                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
3243                          __func__, hc->hc_num, hcchar.d32);
3244         }
3245 #endif
3246
3247         /* Set host channel enable after all other setup is complete. */
3248         hcchar.b.chen = 1;
3249         hcchar.b.chdis = 0;
3250         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3251
3252         hc->xfer_started = 1;
3253         hc->requests++;
3254
3255         if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
3256                 /* Load OUT packet into the appropriate Tx FIFO. */
3257                 dwc_otg_hc_write_packet(core_if, hc);
3258         }
3259 #ifdef DEBUG
3260         if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
3261                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
3262                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
3263
3264                 /* Start a timer for this transfer. */
3265                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
3266         }
3267 #endif
3268 }
3269
3270 /**
3271  * This function does the setup for a data transfer for a host channel
3272  * and starts the transfer in Descriptor DMA mode.
3273  *
3274  * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
3275  * Sets PID and NTD values. For periodic transfers
3276  * initializes SCHED_INFO field with micro-frame bitmap.
3277  *
3278  * Initializes HCDMA register with descriptor list address and CTD value
3279  * then starts the transfer via enabling the channel.
3280  *
3281  * @param core_if Programming view of DWC_otg controller.
3282  * @param hc Information needed to initialize the host channel.
3283  */
3284 void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3285 {
3286         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3287         hcchar_data_t hcchar;
3288         hctsiz_data_t hctsiz;
3289         hcdma_data_t hcdma;
3290
3291         hctsiz.d32 = 0;
3292
3293         if (hc->do_ping)
3294                 hctsiz.b_ddma.dopng = 1;
3295
3296         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
3297                 set_pid_isoc(hc);
3298
3299         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
3300         hctsiz.b_ddma.pid = hc->data_pid_start;
3301         /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
3302         hctsiz.b_ddma.ntd = hc->ntd - 1;
3303         /* Non-zero only for high-speed interrupt endpoints */
3304         hctsiz.b_ddma.schinfo = hc->schinfo;
3305
3306         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3307         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
3308         DWC_DEBUGPL(DBG_HCDV, "  NTD: %d\n", hctsiz.b_ddma.ntd);
3309
3310         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
3311
3312         hcdma.d32 = 0;
3313         hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
3314
3315         /* Always start from first descriptor. */
3316         hcdma.b.ctd = 0;
3317         DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
3318
3319         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3320         hcchar.b.multicnt = hc->multi_count;
3321
3322 #ifdef DEBUG
3323         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
3324         if (hcchar.b.chdis) {
3325                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
3326                          __func__, hc->hc_num, hcchar.d32);
3327         }
3328 #endif
3329
3330         /* Set host channel enable after all other setup is complete. */
3331         hcchar.b.chen = 1;
3332         hcchar.b.chdis = 0;
3333
3334         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3335
3336         hc->xfer_started = 1;
3337         hc->requests++;
3338
3339 #ifdef DEBUG
3340         if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
3341             && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
3342                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
3343                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
3344                 /* Start a timer for this transfer. */
3345                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
3346         }
3347 #endif
3348
3349 }
3350
3351 /**
3352  * This function continues a data transfer that was started by previous call
3353  * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
3354  * sufficient space in the request queue and Tx Data FIFO. This function
3355  * should only be called in Slave mode. In DMA mode, the controller acts
3356  * autonomously to complete transfers programmed to a host channel.
3357  *
3358  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
3359  * if there is any data remaining to be queued. For an IN transfer, another
3360  * data packet is always requested. For the SETUP phase of a control transfer,
3361  * this function does nothing.
3362  *
3363  * @return 1 if a new request is queued, 0 if no more requests are required
3364  * for this transfer.
3365  */
3366 int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3367 {
3368         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3369
3370         if (hc->do_split) {
3371                 /* SPLITs always queue just once per channel */
3372                 return 0;
3373         } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
3374                 /* SETUPs are queued only once since they can't be NAKed. */
3375                 return 0;
3376         } else if (hc->ep_is_in) {
3377                 /*
3378                  * Always queue another request for other IN transfers. If
3379                  * back-to-back INs are issued and NAKs are received for both,
3380                  * the driver may still be processing the first NAK when the
3381                  * second NAK is received. When the interrupt handler clears
3382                  * the NAK interrupt for the first NAK, the second NAK will
3383                  * not be seen. So we can't depend on the NAK interrupt
3384                  * handler to requeue a NAKed request. Instead, IN requests
3385                  * are issued each time this function is called. When the
3386                  * transfer completes, the extra requests for the channel will
3387                  * be flushed.
3388                  */
3389                 hcchar_data_t hcchar;
3390                 dwc_otg_hc_regs_t *hc_regs =
3391                     core_if->host_if->hc_regs[hc->hc_num];
3392
3393                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3394                 hc_set_even_odd_frame(core_if, hc, &hcchar);
3395                 hcchar.b.chen = 1;
3396                 hcchar.b.chdis = 0;
3397                 DWC_DEBUGPL(DBG_HCDV, "  IN xfer: hcchar = 0x%08x\n",
3398                             hcchar.d32);
3399                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3400                 hc->requests++;
3401                 return 1;
3402         } else {
3403                 /* OUT transfers. */
3404                 if (hc->xfer_count < hc->xfer_len) {
3405                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
3406                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
3407                                 hcchar_data_t hcchar;
3408                                 dwc_otg_hc_regs_t *hc_regs;
3409                                 hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3410                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3411                                 hc_set_even_odd_frame(core_if, hc, &hcchar);
3412                         }
3413
3414                         /* Load OUT packet into the appropriate Tx FIFO. */
3415                         dwc_otg_hc_write_packet(core_if, hc);
3416                         hc->requests++;
3417                         return 1;
3418                 } else {
3419                         return 0;
3420                 }
3421         }
3422 }
3423
3424 /**
3425  * Starts a PING transfer. This function should only be called in Slave mode.
3426  * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
3427  */
3428 void dwc_otg_hc_do_ping(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3429 {
3430         hcchar_data_t hcchar;
3431         hctsiz_data_t hctsiz;
3432         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3433
3434         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3435
3436         hctsiz.d32 = 0;
3437         hctsiz.b.dopng = 1;
3438         hctsiz.b.pktcnt = 1;
3439         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
3440
3441         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3442         hcchar.b.chen = 1;
3443         hcchar.b.chdis = 0;
3444         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3445 }
3446
3447 /*
3448  * This function writes a packet into the Tx FIFO associated with the Host
3449  * Channel. For a channel associated with a non-periodic EP, the non-periodic
3450  * Tx FIFO is written. For a channel associated with a periodic EP, the
3451  * periodic Tx FIFO is written. This function should only be called in Slave
3452  * mode.
3453  *
3454  * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
3455  * then number of bytes written to the Tx FIFO.
3456  */
3457 void dwc_otg_hc_write_packet(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3458 {
3459         uint32_t i;
3460         uint32_t remaining_count;
3461         uint32_t byte_count;
3462         uint32_t dword_count;
3463
3464         uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
3465         uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
3466
3467         remaining_count = hc->xfer_len - hc->xfer_count;
3468         if (remaining_count > hc->max_packet)
3469                 byte_count = hc->max_packet;
3470         else
3471                 byte_count = remaining_count;
3472
3473         dword_count = (byte_count + 3) / 4;
3474
3475         if ((((unsigned long)data_buff) & 0x3) == 0) {
3476                 /* xfer_buff is DWORD aligned. */
3477                 for (i = 0; i < dword_count; i++, data_buff++)
3478                         DWC_WRITE_REG32(data_fifo, *data_buff);
3479         } else {
3480                 /* xfer_buff is not DWORD aligned. */
3481                 for (i = 0; i < dword_count; i++, data_buff++) {
3482                         uint32_t data;
3483                         data =
3484                             (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
3485                              16 | data_buff[3] << 24);
3486                         DWC_WRITE_REG32(data_fifo, data);
3487                 }
3488         }
3489
3490         hc->xfer_count += byte_count;
3491         hc->xfer_buff += byte_count;
3492 }
3493
3494 /**
3495  * Gets the current USB frame number. This is the frame number from the last
3496  * SOF packet.
3497  */
3498 uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *core_if)
3499 {
3500         dsts_data_t dsts;
3501         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
3502
3503         /* read current frame/microframe number from DSTS register */
3504         return dsts.b.soffn;
3505 }
3506
3507 /**
3508  * Calculates and gets the frame Interval value of HFIR register according PHY
3509  * type and speed.The application can modify a value of HFIR register only after
3510  * the Port Enable bit of the Host Port Control and Status register
3511  * (HPRT.PrtEnaPort) has been set.
3512 */
3513
3514 uint32_t calc_frame_interval(dwc_otg_core_if_t *core_if)
3515 {
3516         gusbcfg_data_t usbcfg;
3517         hwcfg2_data_t hwcfg2;
3518         hprt0_data_t hprt0;
3519         int clock = 60;         /* default value */
3520         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
3521         hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
3522         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
3523         if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
3524                 clock = 60;
3525         if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
3526                 clock = 48;
3527         if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3528             !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
3529                 clock = 30;
3530         if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3531             !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
3532                 clock = 60;
3533         if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3534             !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
3535                 clock = 48;
3536         if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
3537                 clock = 48;
3538         if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
3539                 clock = 48;
3540         if (hprt0.b.prtspd == 0)
3541                 /* High speed case */
3542                 return 125 * clock;
3543         else
3544                 /* FS/LS case */
3545                 return 1000 * clock;
3546 }
3547
3548 /**
3549  * This function reads a setup packet from the Rx FIFO into the destination
3550  * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
3551  * Interrupt routine when a SETUP packet has been received in Slave mode.
3552  *
3553  * @param core_if Programming view of DWC_otg controller.
3554  * @param dest Destination buffer for packet data.
3555  */
3556 void dwc_otg_read_setup_packet(dwc_otg_core_if_t *core_if, uint32_t *dest)
3557 {
3558         device_grxsts_data_t status;
3559         /* Get the 8 bytes of a setup transaction data */
3560
3561         /* Pop 2 DWORDS off the receive data FIFO into memory */
3562         dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
3563         dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
3564         if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
3565                 status.d32 =
3566                     DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
3567                 DWC_DEBUGPL(DBG_ANY,
3568                             "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
3569                             status.b.epnum, status.b.bcnt, status.b.pktsts,
3570                             status.b.fn, status.b.fn);
3571         }
3572 }
3573
3574 /**
3575  * This function enables EP0 OUT to receive SETUP packets and configures EP0
3576  * IN for transmitting packets. It is normally called when the
3577  * "Enumeration Done" interrupt occurs.
3578  *
3579  * @param core_if Programming view of DWC_otg controller.
3580  * @param ep The EP0 data.
3581  */
3582 void dwc_otg_ep0_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3583 {
3584         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3585         dsts_data_t dsts;
3586         depctl_data_t diepctl;
3587         depctl_data_t doepctl;
3588         dctl_data_t dctl = {.d32 = 0 };
3589
3590         ep->stp_rollover = 0;
3591         /* Read the Device Status and Endpoint 0 Control registers */
3592         dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
3593         diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
3594         doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
3595
3596         /* Set the MPS of the IN EP based on the enumeration speed */
3597         switch (dsts.b.enumspd) {
3598         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
3599         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
3600         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
3601                 diepctl.b.mps = DWC_DEP0CTL_MPS_64;
3602                 break;
3603         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
3604                 diepctl.b.mps = DWC_DEP0CTL_MPS_8;
3605                 break;
3606         }
3607
3608         DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
3609
3610         /* Enable OUT EP for receive */
3611         if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
3612                 doepctl.b.epena = 1;
3613                 DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
3614         }
3615 #ifdef VERBOSE
3616         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
3617                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
3618         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
3619                     DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
3620 #endif
3621         dctl.b.cgnpinnak = 1;
3622
3623         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
3624         DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
3625                     DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
3626
3627 }
3628
3629 /**
3630  * This function activates an EP.  The Device EP control register for
3631  * the EP is configured as defined in the ep structure. Note: This
3632  * function is not used for EP0.
3633  *
3634  * @param core_if Programming view of DWC_otg controller.
3635  * @param ep The EP to activate.
3636  */
3637 void dwc_otg_ep_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3638 {
3639         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3640         depctl_data_t depctl;
3641         volatile uint32_t *addr;
3642         daint_data_t daintmsk = {.d32 = 0 };
3643         dcfg_data_t dcfg;
3644         uint8_t i;
3645
3646         DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
3647                     (ep->is_in ? "IN" : "OUT"));
3648
3649 #ifdef DWC_UTE_PER_IO
3650         ep->xiso_frame_num = 0xFFFFFFFF;
3651         ep->xiso_active_xfers = 0;
3652         ep->xiso_queued_xfers = 0;
3653 #endif
3654         /* Read DEPCTLn register */
3655         if (ep->is_in == 1) {
3656                 addr = &dev_if->in_ep_regs[ep->num]->diepctl;
3657                 daintmsk.ep.in = 1 << ep->num;
3658         } else {
3659                 addr = &dev_if->out_ep_regs[ep->num]->doepctl;
3660                 daintmsk.ep.out = 1 << ep->num;
3661         }
3662
3663         /* If the EP is already active don't change the EP Control
3664          * register. */
3665         depctl.d32 = DWC_READ_REG32(addr);
3666         if (!depctl.b.usbactep) {
3667                 depctl.b.mps = ep->maxpacket;
3668                 depctl.b.eptype = ep->type;
3669                 depctl.b.txfnum = ep->tx_fifo_num;
3670
3671                 if (ep->type == DWC_OTG_EP_TYPE_ISOC)
3672                         depctl.b.setd0pid = 1;
3673                 else
3674                         depctl.b.setd0pid = 1;
3675
3676                 depctl.b.usbactep = 1;
3677
3678                 /* Update nextep_seq array and EPMSCNT in DCFG */
3679                 if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) {/*NP IN EP*/
3680                         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3681                                 if (core_if->nextep_seq[i] ==
3682                                     core_if->first_in_nextep_seq)
3683                                         break;
3684                         }
3685                         core_if->nextep_seq[i] = ep->num;
3686                         core_if->nextep_seq[ep->num] =
3687                             core_if->first_in_nextep_seq;
3688                         depctl.b.nextep = core_if->nextep_seq[ep->num];
3689                         dcfg.d32 =
3690                             DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
3691                         dcfg.b.epmscnt++;
3692                         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg,
3693                                         dcfg.d32);
3694
3695                         DWC_DEBUGPL(DBG_PCDV,
3696                                     "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
3697                                     __func__, core_if->first_in_nextep_seq);
3698                         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3699                                 DWC_DEBUGPL(DBG_PCDV, "%2d\n",
3700                                             core_if->nextep_seq[i]);
3701                         }
3702
3703                 }
3704
3705                 DWC_WRITE_REG32(addr, depctl.d32);
3706                 DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
3707         }
3708
3709         /* Enable the Interrupt for this EP */
3710         if (core_if->multiproc_int_enable) {
3711                 if (ep->is_in == 1) {
3712                         diepmsk_data_t diepmsk = {.d32 = 0 };
3713                         diepmsk.b.xfercompl = 1;
3714                         diepmsk.b.timeout = 1;
3715                         diepmsk.b.epdisabled = 1;
3716                         diepmsk.b.ahberr = 1;
3717                         diepmsk.b.intknepmis = 1;
3718                         if (!core_if->en_multiple_tx_fifo
3719                             && core_if->dma_enable)
3720                                 diepmsk.b.intknepmis = 0;
3721                         diepmsk.b.txfifoundrn = 1;
3722                         if (ep->type == DWC_OTG_EP_TYPE_ISOC)
3723                                 diepmsk.b.nak = 1;
3724
3725                         /*
3726                         if (core_if->dma_desc_enable) {
3727                                 diepmsk.b.bna = 1;
3728                         }
3729
3730                         if (core_if->dma_enable) {
3731                                 doepmsk.b.nak = 1;
3732                         }
3733                         */
3734                         DWC_WRITE_REG32(&dev_if->
3735                                         dev_global_regs->diepeachintmsk[ep->
3736                                                                         num],
3737                                         diepmsk.d32);
3738
3739                 } else {
3740                         doepmsk_data_t doepmsk = {.d32 = 0 };
3741                         doepmsk.b.xfercompl = 1;
3742                         doepmsk.b.ahberr = 1;
3743                         doepmsk.b.epdisabled = 1;
3744                         if (ep->type == DWC_OTG_EP_TYPE_ISOC)
3745                                 doepmsk.b.outtknepdis = 1;
3746
3747                         /*
3748                         if (core_if->dma_desc_enable) {
3749                                 doepmsk.b.bna = 1;
3750                         }
3751                         doepmsk.b.babble = 1;
3752                         doepmsk.b.nyet = 1;
3753                         doepmsk.b.nak = 1;
3754                         */
3755
3756                         DWC_WRITE_REG32(&dev_if->
3757                                         dev_global_regs->doepeachintmsk[ep->
3758                                                                         num],
3759                                         doepmsk.d32);
3760                 }
3761                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
3762                                  0, daintmsk.d32);
3763         } else {
3764                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3765                         if (ep->is_in) {
3766                                 diepmsk_data_t diepmsk = {.d32 = 0 };
3767                                 diepmsk.b.nak = 1;
3768                                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->
3769                                                  diepmsk, 0, diepmsk.d32);
3770                         } else {
3771                                 doepmsk_data_t doepmsk = {.d32 = 0 };
3772                                 doepmsk.b.outtknepdis = 1;
3773                                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->
3774                                                  doepmsk, 0, doepmsk.d32);
3775                         }
3776                 }
3777                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
3778                                  0, daintmsk.d32);
3779         }
3780
3781         DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
3782                     DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
3783
3784         ep->stall_clear_flag = 0;
3785
3786         return;
3787 }
3788
3789 /**
3790  * This function deactivates an EP. This is done by clearing the USB Active
3791  * EP bit in the Device EP control register. Note: This function is not used
3792  * for EP0. EP0 cannot be deactivated.
3793  *
3794  * @param core_if Programming view of DWC_otg controller.
3795  * @param ep The EP to deactivate.
3796  */
3797 void dwc_otg_ep_deactivate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3798 {
3799         depctl_data_t depctl = {.d32 = 0 };
3800         volatile uint32_t *addr;
3801         daint_data_t daintmsk = {.d32 = 0 };
3802         dcfg_data_t dcfg;
3803         uint8_t i = 0;
3804
3805 #ifdef DWC_UTE_PER_IO
3806         ep->xiso_frame_num = 0xFFFFFFFF;
3807         ep->xiso_active_xfers = 0;
3808         ep->xiso_queued_xfers = 0;
3809 #endif
3810
3811         /* Read DEPCTLn register */
3812         if (ep->is_in == 1) {
3813                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
3814                 daintmsk.ep.in = 1 << ep->num;
3815         } else {
3816                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
3817                 daintmsk.ep.out = 1 << ep->num;
3818         }
3819
3820         depctl.d32 = DWC_READ_REG32(addr);
3821
3822         depctl.b.usbactep = 0;
3823
3824         /* Update nextep_seq array and EPMSCNT in DCFG
3825          * NP EP IN */
3826         if (!(depctl.b.eptype & 1) && ep->is_in == 1) {
3827                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3828                         if (core_if->nextep_seq[i] == ep->num)
3829                                 break;
3830                 }
3831                 core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
3832                 if (core_if->first_in_nextep_seq == ep->num)
3833                         core_if->first_in_nextep_seq = i;
3834                 core_if->nextep_seq[ep->num] = 0xff;
3835                 depctl.b.nextep = 0;
3836                 dcfg.d32 =
3837                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
3838                 dcfg.b.epmscnt--;
3839                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
3840                                 dcfg.d32);
3841
3842                 DWC_DEBUGPL(DBG_PCDV,
3843                             "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
3844                             __func__, core_if->first_in_nextep_seq);
3845                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++)
3846                         DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
3847         }
3848
3849         if (ep->is_in == 1)
3850                 depctl.b.txfnum = 0;
3851
3852         if (core_if->dma_desc_enable)
3853                 depctl.b.epdis = 1;
3854
3855         DWC_WRITE_REG32(addr, depctl.d32);
3856         depctl.d32 = DWC_READ_REG32(addr);
3857         if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
3858             && depctl.b.epena) {
3859                 depctl_data_t depctl = {.d32 = 0 };
3860                 if (ep->is_in) {
3861                         diepint_data_t diepint = {.d32 = 0 };
3862
3863                         depctl.b.snak = 1;
3864                         DWC_WRITE_REG32(&core_if->dev_if->
3865                                         in_ep_regs[ep->num]->diepctl,
3866                                         depctl.d32);
3867                         do {
3868                                 dwc_udelay(10);
3869                                 diepint.d32 =
3870                                     DWC_READ_REG32(&core_if->dev_if->
3871                                                    in_ep_regs[ep->
3872                                                               num]->diepint);
3873                         } while (!diepint.b.inepnakeff);
3874                         diepint.b.inepnakeff = 1;
3875                         DWC_WRITE_REG32(&core_if->dev_if->
3876                                         in_ep_regs[ep->num]->diepint,
3877                                         diepint.d32);
3878                         depctl.d32 = 0;
3879                         depctl.b.epdis = 1;
3880                         DWC_WRITE_REG32(&core_if->dev_if->
3881                                         in_ep_regs[ep->num]->diepctl,
3882                                         depctl.d32);
3883                         do {
3884                                 dwc_udelay(10);
3885                                 diepint.d32 =
3886                                     DWC_READ_REG32(&core_if->dev_if->
3887                                                    in_ep_regs[ep->
3888                                                               num]->diepint);
3889                         } while (!diepint.b.epdisabled);
3890                         diepint.b.epdisabled = 1;
3891                         DWC_WRITE_REG32(&core_if->dev_if->
3892                                         in_ep_regs[ep->num]->diepint,
3893                                         diepint.d32);
3894                 } else {
3895                         dctl_data_t dctl = {.d32 = 0 };
3896                         gintmsk_data_t gintsts = {.d32 = 0 };
3897                         doepint_data_t doepint = {.d32 = 0 };
3898                         dctl.b.sgoutnak = 1;
3899                         DWC_MODIFY_REG32(&core_if->dev_if->
3900                                          dev_global_regs->dctl, 0, dctl.d32);
3901                         do {
3902                                 dwc_udelay(10);
3903                                 gintsts.d32 =
3904                                     DWC_READ_REG32(&core_if->core_global_regs->
3905                                                    gintsts);
3906                         } while (!gintsts.b.goutnakeff);
3907                         gintsts.d32 = 0;
3908                         gintsts.b.goutnakeff = 1;
3909                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,
3910                                         gintsts.d32);
3911
3912                         depctl.d32 = 0;
3913                         depctl.b.epdis = 1;
3914                         depctl.b.snak = 1;
3915                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
3916                                         doepctl, depctl.d32);
3917                         do {
3918                                 dwc_udelay(10);
3919                                 doepint.d32 =
3920                                     DWC_READ_REG32(&core_if->
3921                                                    dev_if->out_ep_regs[ep->
3922                                                                        num]->
3923                                                    doepint);
3924                         } while (!doepint.b.epdisabled);
3925
3926                         doepint.b.epdisabled = 1;
3927                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
3928                                         doepint, doepint.d32);
3929
3930                         dctl.d32 = 0;
3931                         dctl.b.cgoutnak = 1;
3932                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
3933                                          dctl, 0, dctl.d32);
3934                 }
3935         }
3936
3937         /* Disable the Interrupt for this EP */
3938         if (core_if->multiproc_int_enable) {
3939                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
3940                                  daintmsk.d32, 0);
3941
3942                 if (ep->is_in == 1) {
3943                         DWC_WRITE_REG32(&core_if->dev_if->
3944                                         dev_global_regs->diepeachintmsk[ep->
3945                                                                         num],
3946                                         0);
3947                 } else {
3948                         DWC_WRITE_REG32(&core_if->dev_if->
3949                                         dev_global_regs->doepeachintmsk[ep->
3950                                                                         num],
3951                                         0);
3952                 }
3953         } else {
3954                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
3955                                  daintmsk.d32, 0);
3956         }
3957
3958 }
3959
3960 /**
3961  * This function initializes dma descriptor chain.
3962  *
3963  * @param core_if Programming view of DWC_otg controller.
3964  * @param ep The EP to start the transfer on.
3965  */
3966 static void init_dma_desc_chain(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3967 {
3968         dwc_otg_dev_dma_desc_t *dma_desc;
3969         uint32_t offset;
3970         uint32_t xfer_est;
3971         int i;
3972         unsigned maxxfer_local, total_len;
3973
3974         if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
3975             (ep->maxpacket % 4)) {
3976                 maxxfer_local = ep->maxpacket;
3977                 total_len = ep->xfer_len;
3978         } else {
3979                 maxxfer_local = ep->maxxfer;
3980                 total_len = ep->total_len;
3981         }
3982
3983         ep->desc_cnt = (total_len / maxxfer_local) +
3984             ((total_len % maxxfer_local) ? 1 : 0);
3985
3986         if (!ep->desc_cnt)
3987                 ep->desc_cnt = 1;
3988
3989         if (ep->desc_cnt > MAX_DMA_DESC_CNT)
3990                 ep->desc_cnt = MAX_DMA_DESC_CNT;
3991
3992         dma_desc = ep->desc_addr;
3993         if (maxxfer_local == ep->maxpacket) {
3994                 if ((total_len % maxxfer_local) &&
3995                     (total_len / maxxfer_local < MAX_DMA_DESC_CNT)) {
3996                         xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
3997                             (total_len % maxxfer_local);
3998                 } else
3999                         xfer_est = ep->desc_cnt * maxxfer_local;
4000         } else
4001                 xfer_est = total_len;
4002         offset = 0;
4003         for (i = 0; i < ep->desc_cnt; ++i) {
4004                 /** DMA Descriptor Setup */
4005                 if (xfer_est > maxxfer_local) {
4006                         dma_desc->status.b.bs = BS_HOST_BUSY;
4007                         dma_desc->status.b.l = 0;
4008                         dma_desc->status.b.ioc = 0;
4009                         dma_desc->status.b.sp = 0;
4010                         dma_desc->status.b.bytes = maxxfer_local;
4011                         dma_desc->buf = ep->dma_addr + offset;
4012                         dma_desc->status.b.sts = 0;
4013                         dma_desc->status.b.bs = BS_HOST_READY;
4014
4015                         xfer_est -= maxxfer_local;
4016                         offset += maxxfer_local;
4017                 } else {
4018                         dma_desc->status.b.bs = BS_HOST_BUSY;
4019                         dma_desc->status.b.l = 1;
4020                         dma_desc->status.b.ioc = 1;
4021                         if (ep->is_in) {
4022                                 dma_desc->status.b.sp =
4023                                     (xfer_est %
4024                                      ep->
4025                                      maxpacket) ? 1 : ((ep->sent_zlp) ? 1 : 0);
4026                                 dma_desc->status.b.bytes = xfer_est;
4027                         } else {
4028                                 if (maxxfer_local == ep->maxpacket)
4029                                         dma_desc->status.b.bytes = xfer_est;
4030                                 else
4031                                         dma_desc->status.b.bytes =
4032                                             xfer_est +
4033                                             ((4 - (xfer_est & 0x3)) & 0x3);
4034                         }
4035
4036                         dma_desc->buf = ep->dma_addr + offset;
4037                         dma_desc->status.b.sts = 0;
4038                         dma_desc->status.b.bs = BS_HOST_READY;
4039                 }
4040                 dma_desc++;
4041         }
4042 }
4043
4044 /**
4045  * This function is called when to write ISOC data into appropriate dedicated
4046  * periodic FIFO.
4047  */
4048 static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t *core_if,
4049                                   dwc_ep_t *dwc_ep)
4050 {
4051         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
4052         dwc_otg_dev_in_ep_regs_t *ep_regs;
4053         dtxfsts_data_t txstatus = {.d32 = 0 };
4054         uint32_t len = 0;
4055         int epnum = dwc_ep->num;
4056         int dwords;
4057
4058         DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
4059
4060         ep_regs = core_if->dev_if->in_ep_regs[epnum];
4061
4062         len = dwc_ep->xfer_len - dwc_ep->xfer_count;
4063
4064         if (len > dwc_ep->maxpacket)
4065                 len = dwc_ep->maxpacket;
4066
4067         dwords = (len + 3) / 4;
4068
4069         /* While there is space in the queue and space in the FIFO and
4070          * More data to tranfer, Write packets to the Tx FIFO */
4071         txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
4072         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
4073
4074         while (txstatus.b.txfspcavail > dwords &&
4075                dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
4076                 /* Write the FIFO */
4077                 dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
4078
4079                 len = dwc_ep->xfer_len - dwc_ep->xfer_count;
4080                 if (len > dwc_ep->maxpacket)
4081                         len = dwc_ep->maxpacket;
4082
4083                 dwords = (len + 3) / 4;
4084                 txstatus.d32 =
4085                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
4086                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
4087                             txstatus.d32);
4088         }
4089
4090         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
4091                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
4092
4093         return 1;
4094 }
4095
4096 /**
4097  * This function does the setup for a data transfer for an EP and
4098  * starts the transfer. For an IN transfer, the packets will be
4099  * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
4100  * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
4101  *
4102  * @param core_if Programming view of DWC_otg controller.
4103  * @param ep The EP to start the transfer on.
4104  */
4105
4106 void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4107 {
4108         depctl_data_t depctl;
4109         deptsiz_data_t deptsiz;
4110         gintmsk_data_t intr_mask = {.d32 = 0 };
4111
4112         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
4113         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
4114                     "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
4115                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
4116                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
4117                     ep->total_len);
4118         /* IN endpoint */
4119         if (ep->is_in == 1) {
4120                 dwc_otg_dev_in_ep_regs_t *in_regs =
4121                     core_if->dev_if->in_ep_regs[ep->num];
4122
4123                 gnptxsts_data_t gtxstatus;
4124
4125                 gtxstatus.d32 =
4126                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
4127
4128                 if (core_if->en_multiple_tx_fifo == 0
4129                     && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
4130 #ifdef DEBUG
4131                         DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
4132 #endif
4133                         return;
4134                 }
4135
4136                 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
4137                 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
4138
4139                 if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
4140                         ep->xfer_len +=
4141                             (ep->maxxfer <
4142                              (ep->total_len -
4143                               ep->xfer_len)) ? ep->maxxfer : (ep->total_len -
4144                                                               ep->xfer_len);
4145                 else
4146                         ep->xfer_len +=
4147                             (MAX_PKT_CNT * ep->maxpacket <
4148                              (ep->total_len -
4149                               ep->xfer_len)) ? MAX_PKT_CNT *
4150                             ep->maxpacket : (ep->total_len - ep->xfer_len);
4151
4152                 /* Zero Length Packet? */
4153                 if ((ep->xfer_len - ep->xfer_count) == 0) {
4154                         deptsiz.b.xfersize = 0;
4155                         deptsiz.b.pktcnt = 1;
4156                 } else {
4157                         /* Program the transfer size and packet count
4158                          *      as follows: xfersize = N * maxpacket +
4159                          *      short_packet pktcnt = N + (short_packet
4160                          *      exist ? 1 : 0)
4161                          */
4162                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
4163                         deptsiz.b.pktcnt =
4164                             (ep->xfer_len - ep->xfer_count - 1 +
4165                              ep->maxpacket) / ep->maxpacket;
4166                         if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
4167                                 deptsiz.b.pktcnt = MAX_PKT_CNT;
4168                                 deptsiz.b.xfersize =
4169                                     deptsiz.b.pktcnt * ep->maxpacket;
4170                         }
4171                         if (ep->type == DWC_OTG_EP_TYPE_ISOC)
4172                                 deptsiz.b.mc = deptsiz.b.pktcnt;
4173                 }
4174
4175                 /* Write the DMA register */
4176                 if (core_if->dma_enable) {
4177                         if (core_if->dma_desc_enable == 0) {
4178                                 if (ep->type != DWC_OTG_EP_TYPE_ISOC)
4179                                         deptsiz.b.mc = 1;
4180                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
4181                                                 deptsiz.d32);
4182                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4183                                                 (uint32_t) ep->dma_addr);
4184                         } else {
4185 #ifdef DWC_UTE_CFI
4186                                 /* The descriptor chain should be
4187                                  * already initialized by now */
4188                                 if (ep->buff_mode != BM_STANDARD) {
4189                                         DWC_WRITE_REG32(&in_regs->diepdma,
4190                                                         ep->descs_dma_addr);
4191                                 } else {
4192 #endif
4193                                         init_dma_desc_chain(core_if, ep);
4194                                 /** DIEPDMAn Register write */
4195                                         DWC_WRITE_REG32(&in_regs->diepdma,
4196                                                         ep->dma_desc_addr);
4197 #ifdef DWC_UTE_CFI
4198                                 }
4199 #endif
4200                         }
4201                 } else {
4202                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4203                         if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
4204                                 /**
4205                                  * Enable the Non-Periodic Tx FIFO empty interrupt,
4206                                  * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
4207                                  * the data will be written into the fifo by the ISR.
4208                                  */
4209                                 if (core_if->en_multiple_tx_fifo == 0) {
4210                                         intr_mask.b.nptxfempty = 1;
4211                                         DWC_MODIFY_REG32
4212                                             (&core_if->core_global_regs->
4213                                              gintmsk, intr_mask.d32,
4214                                              intr_mask.d32);
4215                                 } else {
4216                                         /* Enable the Tx FIFO Empty Interrupt for this EP */
4217                                         if (ep->xfer_len > 0) {
4218                                                 uint32_t fifoemptymsk = 0;
4219                                                 fifoemptymsk = 1 << ep->num;
4220                                                 DWC_MODIFY_REG32
4221                                                     (&core_if->dev_if->
4222                                                      dev_global_regs->
4223                                                      dtknqr4_fifoemptymsk, 0,
4224                                                      fifoemptymsk);
4225
4226                                         }
4227                                 }
4228                         } else {
4229                                 write_isoc_tx_fifo(core_if, ep);
4230                         }
4231                 }
4232                 if (!core_if->core_params->en_multiple_tx_fifo
4233                     && core_if->dma_enable)
4234                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4235
4236                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
4237                         dsts_data_t dsts = {.d32 = 0 };
4238                         if (ep->bInterval == 1) {
4239                                 dsts.d32 =
4240                                     DWC_READ_REG32(&core_if->
4241                                                    dev_if->dev_global_regs->
4242                                                    dsts);
4243                                 ep->frame_num = dsts.b.soffn + ep->bInterval;
4244                                 if (ep->frame_num > 0x3FFF) {
4245                                         ep->frm_overrun = 1;
4246                                         ep->frame_num &= 0x3FFF;
4247                                 } else
4248                                         ep->frm_overrun = 0;
4249                                 if (ep->frame_num & 0x1)
4250                                         depctl.b.setd1pid = 1;
4251                                 else
4252                                         depctl.b.setd0pid = 1;
4253                         }
4254                 }
4255                 /* EP enable, IN data in FIFO */
4256                 depctl.b.cnak = 1;
4257                 depctl.b.epena = 1;
4258                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4259
4260         } else {
4261                 /* OUT endpoint */
4262                 dwc_otg_dev_out_ep_regs_t *out_regs =
4263                     core_if->dev_if->out_ep_regs[ep->num];
4264
4265                 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
4266                 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
4267
4268                 if (!core_if->dma_desc_enable) {
4269                         if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
4270                                 ep->xfer_len +=
4271                                     (ep->maxxfer <
4272                                      (ep->total_len -
4273                                       ep->xfer_len)) ? ep->maxxfer : (ep->
4274                                                                       total_len
4275                                                                       -
4276                                                                       ep->
4277                                                                       xfer_len);
4278                         else
4279                                 ep->xfer_len +=
4280                                     (MAX_PKT_CNT * ep->maxpacket <
4281                                      (ep->total_len -
4282                                       ep->xfer_len)) ? MAX_PKT_CNT *
4283                                     ep->maxpacket : (ep->total_len -
4284                                                      ep->xfer_len);
4285                 }
4286
4287                 /* Program the transfer size and packet count as follows:
4288                  *
4289                  *      pktcnt = N
4290                  *      xfersize = N * maxpacket
4291                  */
4292                 if ((ep->xfer_len - ep->xfer_count) == 0) {
4293                         /* Zero Length Packet */
4294                         deptsiz.b.xfersize = ep->maxpacket;
4295                         deptsiz.b.pktcnt = 1;
4296                 } else {
4297                         deptsiz.b.pktcnt =
4298                             (ep->xfer_len - ep->xfer_count +
4299                              (ep->maxpacket - 1)) / ep->maxpacket;
4300                         if (deptsiz.b.pktcnt > MAX_PKT_CNT)
4301                                 deptsiz.b.pktcnt = MAX_PKT_CNT;
4302                         if (!core_if->dma_desc_enable) {
4303                                 ep->xfer_len =
4304                                     deptsiz.b.pktcnt * ep->maxpacket +
4305                                     ep->xfer_count;
4306                         }
4307                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
4308                 }
4309
4310                 DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
4311                             ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
4312
4313                 if (core_if->dma_enable) {
4314                         if (!core_if->dma_desc_enable) {
4315                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
4316                                                 deptsiz.d32);
4317
4318                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4319                                                 (uint32_t) ep->dma_addr);
4320                         } else {
4321 #ifdef DWC_UTE_CFI
4322                                 /* The descriptor chain should be
4323                                  * already initialized by now */
4324                                 if (ep->buff_mode != BM_STANDARD) {
4325                                         DWC_WRITE_REG32(&out_regs->doepdma,
4326                                                         ep->descs_dma_addr);
4327                                 } else {
4328 #endif
4329                                         /* This is used for
4330                                          * interrupt out transfers*/
4331                                         if (!ep->xfer_len)
4332                                                 ep->xfer_len = ep->total_len;
4333                                         init_dma_desc_chain(core_if, ep);
4334
4335                                         if (core_if->core_params->dev_out_nak) {
4336                                                 if (ep->type ==
4337                                                     DWC_OTG_EP_TYPE_BULK) {
4338                                                         deptsiz.b.pktcnt =
4339                                                             (ep->total_len +
4340                                                              (ep->maxpacket -
4341                                                               1)) /
4342                                                             ep->maxpacket;
4343                                                         deptsiz.b.xfersize =
4344                                                             ep->total_len;
4345                                                         /* Remember initial value of doeptsiz */
4346                                                         core_if->
4347                                                             start_doeptsiz_val
4348                                                             [ep->num] =
4349                                                             deptsiz.d32;
4350                                                         DWC_WRITE_REG32
4351                                                             (&out_regs->
4352                                                              doeptsiz,
4353                                                              deptsiz.d32);
4354                                                 }
4355                                         }
4356                                 /** DOEPDMAn Register write */
4357                                         DWC_WRITE_REG32(&out_regs->doepdma,
4358                                                         ep->dma_desc_addr);
4359 #ifdef DWC_UTE_CFI
4360                                 }
4361 #endif
4362                         }
4363                 } else {
4364                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4365                 }
4366
4367                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
4368                         dsts_data_t dsts = {.d32 = 0 };
4369                         if (ep->bInterval == 1) {
4370                                 dsts.d32 =
4371                                     DWC_READ_REG32(&core_if->
4372                                                    dev_if->dev_global_regs->
4373                                                    dsts);
4374                                 ep->frame_num = dsts.b.soffn + ep->bInterval;
4375                                 if (ep->frame_num > 0x3FFF) {
4376                                         ep->frm_overrun = 1;
4377                                         ep->frame_num &= 0x3FFF;
4378                                 } else
4379                                         ep->frm_overrun = 0;
4380
4381                                 if (ep->frame_num & 0x1)
4382                                         depctl.b.setd1pid = 1;
4383                                 else
4384                                         depctl.b.setd0pid = 1;
4385                         }
4386                 }
4387
4388                 /* EP enable */
4389                 depctl.b.cnak = 1;
4390                 depctl.b.epena = 1;
4391
4392                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
4393
4394                 DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
4395                             DWC_READ_REG32(&out_regs->doepctl),
4396                             DWC_READ_REG32(&out_regs->doeptsiz));
4397                 DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
4398                             DWC_READ_REG32(&core_if->dev_if->
4399                                            dev_global_regs->daintmsk),
4400                             DWC_READ_REG32(&core_if->
4401                                            core_global_regs->gintmsk));
4402
4403                 /* Timer is scheduling only for out bulk transfers for
4404                  * "Device DDMA OUT NAK Enhancement" feature to inform user
4405                  * about received data payload in case of timeout
4406                  */
4407                 if (core_if->core_params->dev_out_nak) {
4408                         if (ep->type == DWC_OTG_EP_TYPE_BULK) {
4409                                 core_if->ep_xfer_info[ep->num].core_if =
4410                                     core_if;
4411                                 core_if->ep_xfer_info[ep->num].ep = ep;
4412                                 core_if->ep_xfer_info[ep->num].state = 1;
4413
4414                                 /* Start a timer for this transfer. */
4415                                 DWC_TIMER_SCHEDULE(core_if->
4416                                                    ep_xfer_timer[ep->num],
4417                                                    10000);
4418                         }
4419                 }
4420         }
4421 }
4422
4423 /**
4424  * This function setup a zero length transfer in Buffer DMA and
4425  * Slave modes for usb requests with zero field set
4426  *
4427  * @param core_if Programming view of DWC_otg controller.
4428  * @param ep The EP to start the transfer on.
4429  *
4430  */
4431 void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4432 {
4433
4434         depctl_data_t depctl;
4435         deptsiz_data_t deptsiz;
4436         gintmsk_data_t intr_mask = {.d32 = 0 };
4437
4438         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
4439         DWC_PRINTF("zero length transfer is called\n");
4440
4441         /* IN endpoint */
4442         if (ep->is_in == 1) {
4443                 dwc_otg_dev_in_ep_regs_t *in_regs =
4444                     core_if->dev_if->in_ep_regs[ep->num];
4445
4446                 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
4447                 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
4448
4449                 deptsiz.b.xfersize = 0;
4450                 deptsiz.b.pktcnt = 1;
4451
4452                 /* Write the DMA register */
4453                 if (core_if->dma_enable) {
4454                         if (core_if->dma_desc_enable == 0) {
4455                                 deptsiz.b.mc = 1;
4456                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
4457                                                 deptsiz.d32);
4458                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4459                                                 (uint32_t) ep->dma_addr);
4460                         }
4461                 } else {
4462                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4463                         /**
4464                          * Enable the Non-Periodic Tx FIFO empty interrupt,
4465                          * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
4466                          * the data will be written into the fifo by the ISR.
4467                          */
4468                         if (core_if->en_multiple_tx_fifo == 0) {
4469                                 intr_mask.b.nptxfempty = 1;
4470                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
4471                                                  gintmsk, intr_mask.d32,
4472                                                  intr_mask.d32);
4473                         } else {
4474                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
4475                                 if (ep->xfer_len > 0) {
4476                                         uint32_t fifoemptymsk = 0;
4477                                         fifoemptymsk = 1 << ep->num;
4478                                         DWC_MODIFY_REG32(&core_if->dev_if->
4479                                                          dev_global_regs->
4480                                                          dtknqr4_fifoemptymsk,
4481                                                          0, fifoemptymsk);
4482                                 }
4483                         }
4484                 }
4485
4486                 if (!core_if->core_params->en_multiple_tx_fifo
4487                     && core_if->dma_enable)
4488                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4489                 /* EP enable, IN data in FIFO */
4490                 depctl.b.cnak = 1;
4491                 depctl.b.epena = 1;
4492                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4493
4494         } else {
4495                 /* OUT endpoint */
4496                 dwc_otg_dev_out_ep_regs_t *out_regs =
4497                     core_if->dev_if->out_ep_regs[ep->num];
4498
4499                 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
4500                 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
4501
4502                 /* Zero Length Packet */
4503                 deptsiz.b.xfersize = ep->maxpacket;
4504                 deptsiz.b.pktcnt = 1;
4505
4506                 if (core_if->dma_enable) {
4507                         if (!core_if->dma_desc_enable) {
4508                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
4509                                                 deptsiz.d32);
4510
4511                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4512                                                 (uint32_t) ep->dma_addr);
4513                         }
4514                 } else {
4515                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4516                 }
4517
4518                 /* EP enable */
4519                 depctl.b.cnak = 1;
4520                 depctl.b.epena = 1;
4521
4522                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
4523
4524         }
4525 }
4526
4527 /**
4528  * This function does the setup for a data transfer for EP0 and starts
4529  * the transfer.  For an IN transfer, the packets will be loaded into
4530  * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
4531  * unloaded from the Rx FIFO in the ISR.
4532  *
4533  * @param core_if Programming view of DWC_otg controller.
4534  * @param ep The EP0 data.
4535  */
4536 void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4537 {
4538         depctl_data_t depctl;
4539         deptsiz0_data_t deptsiz;
4540         gintmsk_data_t intr_mask = {.d32 = 0 };
4541         dwc_otg_dev_dma_desc_t *dma_desc;
4542
4543         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
4544                     "xfer_buff=%p start_xfer_buff=%p \n",
4545                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
4546                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
4547
4548         ep->total_len = ep->xfer_len;
4549
4550         /* IN endpoint */
4551         if (ep->is_in == 1) {
4552                 dwc_otg_dev_in_ep_regs_t *in_regs =
4553                     core_if->dev_if->in_ep_regs[0];
4554
4555                 gnptxsts_data_t gtxstatus;
4556
4557                 if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
4558                         depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4559                         if (depctl.b.epena)
4560                                 return;
4561                 }
4562
4563                 gtxstatus.d32 =
4564                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
4565
4566                 /* If dedicated FIFO every time flush fifo before enable ep */
4567                 if (core_if->en_multiple_tx_fifo
4568                     && core_if->snpsid >= OTG_CORE_REV_3_00a)
4569                         dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
4570
4571                 if (core_if->en_multiple_tx_fifo == 0
4572                     && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
4573 #ifdef DEBUG
4574                         deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4575                         DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
4576                                     DWC_READ_REG32(&in_regs->diepctl));
4577                         DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
4578                                     deptsiz.d32,
4579                                     deptsiz.b.xfersize, deptsiz.b.pktcnt);
4580                         DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
4581                                    gtxstatus.d32);
4582 #endif
4583                         return;
4584                 }
4585
4586                 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4587                 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4588
4589                 /* Zero Length Packet? */
4590                 if (ep->xfer_len == 0) {
4591                         deptsiz.b.xfersize = 0;
4592                         deptsiz.b.pktcnt = 1;
4593                 } else {
4594                         /* Program the transfer size and packet count
4595                          *      as follows: xfersize = N * maxpacket +
4596                          *      short_packet pktcnt = N + (short_packet
4597                          *      exist ? 1 : 0)
4598                          */
4599                         if (ep->xfer_len > ep->maxpacket) {
4600                                 ep->xfer_len = ep->maxpacket;
4601                                 deptsiz.b.xfersize = ep->maxpacket;
4602                         } else {
4603                                 deptsiz.b.xfersize = ep->xfer_len;
4604                         }
4605                         deptsiz.b.pktcnt = 1;
4606
4607                 }
4608                 DWC_DEBUGPL(DBG_PCDV,
4609                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
4610                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4611                             deptsiz.d32);
4612
4613                 /* Write the DMA register */
4614                 if (core_if->dma_enable) {
4615                         if (core_if->dma_desc_enable == 0) {
4616                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
4617                                                 deptsiz.d32);
4618
4619                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4620                                                 (uint32_t) ep->dma_addr);
4621                         } else {
4622                                 dma_desc = core_if->dev_if->in_desc_addr;
4623
4624                                 /** DMA Descriptor Setup */
4625                                 dma_desc->status.b.bs = BS_HOST_BUSY;
4626                                 dma_desc->status.b.l = 1;
4627                                 dma_desc->status.b.ioc = 1;
4628                                 dma_desc->status.b.sp =
4629                                     (ep->xfer_len == ep->maxpacket) ? 0 : 1;
4630                                 dma_desc->status.b.bytes = ep->xfer_len;
4631                                 dma_desc->buf = ep->dma_addr;
4632                                 dma_desc->status.b.sts = 0;
4633                                 dma_desc->status.b.bs = BS_HOST_READY;
4634
4635                                 /** DIEPDMA0 Register write */
4636                                 DWC_WRITE_REG32(&in_regs->diepdma,
4637                                                 core_if->dev_if->
4638                                                 dma_in_desc_addr);
4639                         }
4640                 } else {
4641                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4642                 }
4643
4644                 if (!core_if->core_params->en_multiple_tx_fifo
4645                     && core_if->dma_enable)
4646                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4647                 /* EP enable, IN data in FIFO */
4648                 depctl.b.cnak = 1;
4649                 depctl.b.epena = 1;
4650                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4651
4652                 /**
4653                  * Enable the Non-Periodic Tx FIFO empty interrupt, the
4654                  * data will be written into the fifo by the ISR.
4655                  */
4656                 if (!core_if->dma_enable) {
4657                         if (core_if->en_multiple_tx_fifo == 0) {
4658                                 intr_mask.b.nptxfempty = 1;
4659                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
4660                                                  gintmsk, intr_mask.d32,
4661                                                  intr_mask.d32);
4662                         } else {
4663                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
4664                                 if (ep->xfer_len > 0) {
4665                                         uint32_t fifoemptymsk = 0;
4666                                         fifoemptymsk |= 1 << ep->num;
4667                                         DWC_MODIFY_REG32(&core_if->dev_if->
4668                                                          dev_global_regs->
4669                                                          dtknqr4_fifoemptymsk,
4670                                                          0, fifoemptymsk);
4671                                 }
4672                         }
4673                 }
4674         } else {
4675                 /* OUT endpoint */
4676                 dwc_otg_dev_out_ep_regs_t *out_regs =
4677                     core_if->dev_if->out_ep_regs[0];
4678
4679                 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
4680                 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
4681
4682                 /* Program the transfer size and packet count as follows:
4683                  *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
4684                  *      pktcnt = N                                                                                      */
4685                 /* Zero Length Packet */
4686                 deptsiz.b.xfersize = ep->maxpacket;
4687                 deptsiz.b.pktcnt = 1;
4688                 if (core_if->snpsid >= OTG_CORE_REV_3_00a)
4689                         deptsiz.b.supcnt = 1;
4690
4691                 DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
4692                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
4693
4694                 if (core_if->dma_enable) {
4695                         if (!core_if->dma_desc_enable) {
4696                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
4697                                                 deptsiz.d32);
4698
4699                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4700                                                 (uint32_t) ep->dma_addr);
4701                         } else {
4702                                 dma_desc = core_if->dev_if->out_desc_addr;
4703
4704                                 /** DMA Descriptor Setup */
4705                                 dma_desc->status.b.bs = BS_HOST_BUSY;
4706                                 if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
4707                                         dma_desc->status.b.mtrf = 0;
4708                                         dma_desc->status.b.sr = 0;
4709                                 }
4710                                 dma_desc->status.b.l = 1;
4711                                 dma_desc->status.b.ioc = 1;
4712                                 dma_desc->status.b.bytes = ep->maxpacket;
4713                                 dma_desc->buf = ep->dma_addr;
4714                                 dma_desc->status.b.sts = 0;
4715                                 dma_desc->status.b.bs = BS_HOST_READY;
4716
4717                                 /** DOEPDMA0 Register write */
4718                                 DWC_WRITE_REG32(&out_regs->doepdma,
4719                                                 core_if->
4720                                                 dev_if->dma_out_desc_addr);
4721                         }
4722                 } else {
4723                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4724                 }
4725
4726                 /* EP enable */
4727                 depctl.b.cnak = 1;
4728                 depctl.b.epena = 1;
4729                 DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
4730         }
4731 }
4732
4733 /**
4734  * This function continues control IN transfers started by
4735  * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
4736  * single packet.  NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
4737  * bit for the packet count.
4738  *
4739  * @param core_if Programming view of DWC_otg controller.
4740  * @param ep The EP0 data.
4741  */
4742 void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4743 {
4744         depctl_data_t depctl;
4745         deptsiz0_data_t deptsiz;
4746         gintmsk_data_t intr_mask = {.d32 = 0 };
4747         dwc_otg_dev_dma_desc_t *dma_desc;
4748
4749         if (ep->is_in == 1) {
4750                 dwc_otg_dev_in_ep_regs_t *in_regs =
4751                     core_if->dev_if->in_ep_regs[0];
4752                 gnptxsts_data_t tx_status = {.d32 = 0 };
4753
4754                 tx_status.d32 =
4755                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
4756                 /** @todo Should there be check for room in the Tx
4757                  * Status Queue.  If not remove the code above this comment. */
4758
4759                 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4760                 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4761
4762                 /* Program the transfer size and packet count
4763                  *      as follows: xfersize = N * maxpacket +
4764                  *      short_packet pktcnt = N + (short_packet
4765                  *      exist ? 1 : 0)
4766                  */
4767
4768                 if (core_if->dma_desc_enable == 0) {
4769                         deptsiz.b.xfersize =
4770                             (ep->total_len - ep->xfer_count) >
4771                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
4772                                                              ep->xfer_count);
4773                         deptsiz.b.pktcnt = 1;
4774                         if (core_if->dma_enable == 0)
4775                                 ep->xfer_len += deptsiz.b.xfersize;
4776                         else
4777                                 ep->xfer_len = deptsiz.b.xfersize;
4778                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4779                 } else {
4780                         ep->xfer_len =
4781                             (ep->total_len - ep->xfer_count) >
4782                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
4783                                                              ep->xfer_count);
4784
4785                         dma_desc = core_if->dev_if->in_desc_addr;
4786
4787                         /** DMA Descriptor Setup */
4788                         dma_desc->status.b.bs = BS_HOST_BUSY;
4789                         dma_desc->status.b.l = 1;
4790                         dma_desc->status.b.ioc = 1;
4791                         dma_desc->status.b.sp =
4792                             (ep->xfer_len == ep->maxpacket) ? 0 : 1;
4793                         dma_desc->status.b.bytes = ep->xfer_len;
4794                         dma_desc->buf = ep->dma_addr;
4795                         dma_desc->status.b.sts = 0;
4796                         dma_desc->status.b.bs = BS_HOST_READY;
4797
4798                         /** DIEPDMA0 Register write */
4799                         DWC_WRITE_REG32(&in_regs->diepdma,
4800                                         core_if->dev_if->dma_in_desc_addr);
4801                 }
4802
4803                 DWC_DEBUGPL(DBG_PCDV,
4804                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
4805                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4806                             deptsiz.d32);
4807
4808                 /* Write the DMA register */
4809                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4810                         if (core_if->dma_desc_enable == 0)
4811                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4812                                                 (uint32_t) ep->dma_addr);
4813                 }
4814                 if (!core_if->core_params->en_multiple_tx_fifo
4815                     && core_if->dma_enable)
4816                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4817                 /* EP enable, IN data in FIFO */
4818                 depctl.b.cnak = 1;
4819                 depctl.b.epena = 1;
4820                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4821
4822                 /**
4823                  * Enable the Non-Periodic Tx FIFO empty interrupt, the
4824                  * data will be written into the fifo by the ISR.
4825                  */
4826                 if (!core_if->dma_enable) {
4827                         if (core_if->en_multiple_tx_fifo == 0) {
4828                                 /* First clear it from GINTSTS */
4829                                 intr_mask.b.nptxfempty = 1;
4830                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
4831                                                  gintmsk, intr_mask.d32,
4832                                                  intr_mask.d32);
4833
4834                         } else {
4835                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
4836                                 if (ep->xfer_len > 0) {
4837                                         uint32_t fifoemptymsk = 0;
4838                                         fifoemptymsk |= 1 << ep->num;
4839                                         DWC_MODIFY_REG32(&core_if->dev_if->
4840                                                          dev_global_regs->
4841                                                          dtknqr4_fifoemptymsk,
4842                                                          0, fifoemptymsk);
4843                                 }
4844                         }
4845                 }
4846         } else {
4847                 dwc_otg_dev_out_ep_regs_t *out_regs =
4848                     core_if->dev_if->out_ep_regs[0];
4849
4850                 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
4851                 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
4852
4853                 /* Program the transfer size and packet count
4854                  *      as follows: xfersize = N * maxpacket +
4855                  *      short_packet pktcnt = N + (short_packet
4856                  *      exist ? 1 : 0)
4857                  */
4858                 deptsiz.b.xfersize = ep->maxpacket;
4859                 deptsiz.b.pktcnt = 1;
4860
4861                 if (core_if->dma_desc_enable == 0) {
4862                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4863                 } else {
4864                         dma_desc = core_if->dev_if->out_desc_addr;
4865
4866                         /** DMA Descriptor Setup */
4867                         dma_desc->status.b.bs = BS_HOST_BUSY;
4868                         dma_desc->status.b.l = 1;
4869                         dma_desc->status.b.ioc = 1;
4870                         dma_desc->status.b.bytes = ep->maxpacket;
4871                         dma_desc->buf = ep->dma_addr;
4872                         dma_desc->status.b.sts = 0;
4873                         dma_desc->status.b.bs = BS_HOST_READY;
4874
4875                         /** DOEPDMA0 Register write */
4876                         DWC_WRITE_REG32(&out_regs->doepdma,
4877                                         core_if->dev_if->dma_out_desc_addr);
4878                 }
4879
4880                 DWC_DEBUGPL(DBG_PCDV,
4881                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
4882                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4883                             deptsiz.d32);
4884
4885                 /* Write the DMA register */
4886                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4887                         if (core_if->dma_desc_enable == 0)
4888                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4889                                                 (uint32_t) ep->dma_addr);
4890
4891                 }
4892
4893                 /* EP enable, IN data in FIFO */
4894                 depctl.b.cnak = 1;
4895                 depctl.b.epena = 1;
4896                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
4897
4898         }
4899 }
4900
4901 #ifdef DEBUG
4902 void dump_msg(const u8 *buf, unsigned int length)
4903 {
4904         unsigned int start, num, i;
4905         char line[52], *p;
4906
4907         if (length >= 512)
4908                 return;
4909         start = 0;
4910         while (length > 0) {
4911                 num = length < 16u ? length : 16u;
4912                 p = line;
4913                 for (i = 0; i < num; ++i) {
4914                         if (i == 8)
4915                                 *p++ = ' ';
4916                         DWC_SPRINTF(p, " %02x", buf[i]);
4917                         p += 3;
4918                 }
4919                 *p = 0;
4920                 DWC_PRINTF("%6x: %s\n", start, line);
4921                 buf += num;
4922                 start += num;
4923                 length -= num;
4924         }
4925 }
4926 #else
4927 static inline void dump_msg(const u8 *buf, unsigned int length)
4928 {
4929 }
4930 #endif
4931
4932 /**
4933  * This function writes a packet into the Tx FIFO associated with the
4934  * EP. For non-periodic EPs the non-periodic Tx FIFO is written.  For
4935  * periodic EPs the periodic Tx FIFO associated with the EP is written
4936  * with all packets for the next micro-frame.
4937  *
4938  * @param core_if Programming view of DWC_otg controller.
4939  * @param ep The EP to write packet for.
4940  * @param dma Indicates if DMA is being used.
4941  */
4942 void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep,
4943                              int dma)
4944 {
4945         /**
4946          * The buffer is padded to DWORD on a per packet basis in
4947          * slave/dma mode if the MPS is not DWORD aligned. The last
4948          * packet, if short, is also padded to a multiple of DWORD.
4949          *
4950          * ep->xfer_buff always starts DWORD aligned in memory and is a
4951          * multiple of DWORD in length
4952          *
4953          * ep->xfer_len can be any number of bytes
4954          *
4955          * ep->xfer_count is a multiple of ep->maxpacket until the last
4956          *      packet
4957          *
4958          * FIFO access is DWORD */
4959
4960         uint32_t i;
4961         uint32_t byte_count;
4962         uint32_t dword_count;
4963         uint32_t *fifo;
4964         uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
4965
4966         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
4967                     ep);
4968         if (ep->xfer_count >= ep->xfer_len) {
4969                 DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
4970                 return;
4971         }
4972
4973         /* Find the byte length of the packet either short packet or MPS */
4974         if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket)
4975                 byte_count = ep->xfer_len - ep->xfer_count;
4976         else
4977                 byte_count = ep->maxpacket;
4978
4979         /* Find the DWORD length, padded by extra bytes as neccessary if MPS
4980          * is not a multiple of DWORD */
4981         dword_count = (byte_count + 3) / 4;
4982
4983 #ifdef VERBOSE
4984         dump_msg(ep->xfer_buff, byte_count);
4985 #endif
4986
4987         /**@todo NGS Where are the Periodic Tx FIFO addresses
4988          * intialized?  What should this be? */
4989
4990         fifo = core_if->data_fifo[ep->num];
4991
4992         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
4993                     fifo, data_buff, *data_buff, byte_count);
4994
4995         if (!dma) {
4996                 for (i = 0; i < dword_count; i++, data_buff++)
4997                         DWC_WRITE_REG32(fifo, *data_buff);
4998         }
4999
5000         ep->xfer_count += byte_count;
5001         ep->xfer_buff += byte_count;
5002         ep->dma_addr += byte_count;
5003 }
5004
5005 /**
5006  * Set the EP STALL.
5007  *
5008  * @param core_if Programming view of DWC_otg controller.
5009  * @param ep The EP to set the stall on.
5010  */
5011 void dwc_otg_ep_set_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5012 {
5013         depctl_data_t depctl;
5014         volatile uint32_t *depctl_addr;
5015
5016         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
5017                     (ep->is_in ? "IN" : "OUT"));
5018
5019         if (ep->is_in == 1) {
5020                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
5021                 depctl.d32 = DWC_READ_REG32(depctl_addr);
5022
5023                 /* set the disable and stall bits */
5024                 if (depctl.b.epena)
5025                         depctl.b.epdis = 1;
5026                 depctl.b.stall = 1;
5027                 DWC_WRITE_REG32(depctl_addr, depctl.d32);
5028         } else {
5029                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
5030                 depctl.d32 = DWC_READ_REG32(depctl_addr);
5031
5032                 /* set the stall bit */
5033                 depctl.b.stall = 1;
5034                 DWC_WRITE_REG32(depctl_addr, depctl.d32);
5035         }
5036
5037         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
5038
5039         return;
5040 }
5041
5042 /**
5043  * Clear the EP STALL.
5044  *
5045  * @param core_if Programming view of DWC_otg controller.
5046  * @param ep The EP to clear stall from.
5047  */
5048 void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5049 {
5050         depctl_data_t depctl;
5051         volatile uint32_t *depctl_addr;
5052
5053         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
5054                     (ep->is_in ? "IN" : "OUT"));
5055
5056         if (ep->is_in == 1)
5057                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
5058         else
5059                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
5060
5061         depctl.d32 = DWC_READ_REG32(depctl_addr);
5062
5063         /* clear the stall bits */
5064         depctl.b.stall = 0;
5065
5066         /*
5067          * USB Spec 9.4.5: For endpoints using data toggle, regardless
5068          * of whether an endpoint has the Halt feature set, a
5069          * ClearFeature(ENDPOINT_HALT) request always results in the
5070          * data toggle being reinitialized to DATA0.
5071          */
5072         if (ep->type == DWC_OTG_EP_TYPE_INTR ||
5073             ep->type == DWC_OTG_EP_TYPE_BULK) {
5074                 depctl.b.setd0pid = 1;  /* DATA0 */
5075         }
5076
5077         DWC_WRITE_REG32(depctl_addr, depctl.d32);
5078         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
5079         return;
5080 }
5081
5082 /**
5083  * This function reads a packet from the Rx FIFO into the destination
5084  * buffer. To read SETUP data use dwc_otg_read_setup_packet.
5085  *
5086  * @param core_if Programming view of DWC_otg controller.
5087  * @param dest    Destination buffer for the packet.
5088  * @param bytes  Number of bytes to copy to the destination.
5089  */
5090 void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
5091                          uint8_t *dest, uint16_t bytes)
5092 {
5093         int i;
5094         int word_count = (bytes + 3) / 4;
5095
5096         volatile uint32_t *fifo = core_if->data_fifo[0];
5097         uint32_t *data_buff = (uint32_t *) dest;
5098
5099         /**
5100          * @todo Account for the case where _dest is not dword aligned. This
5101          * requires reading data from the FIFO into a uint32_t temp buffer,
5102          * then moving it into the data buffer.
5103          */
5104
5105         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
5106                     core_if, dest, bytes);
5107
5108         for (i = 0; i < word_count; i++, data_buff++)
5109                 *data_buff = DWC_READ_REG32(fifo);
5110
5111         return;
5112 }
5113
5114 /**
5115  * This functions reads the device registers and prints them
5116  *
5117  * @param core_if Programming view of DWC_otg controller.
5118  */
5119 void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *core_if)
5120 {
5121         int i;
5122         volatile uint32_t *addr;
5123         uint32_t hwcfg1;
5124
5125         hwcfg1 = ~core_if->core_global_regs->ghwcfg1;
5126
5127         DWC_PRINTF("Device Global Registers\n");
5128         addr = &core_if->dev_if->dev_global_regs->dcfg;
5129         DWC_PRINTF("DCFG                 @0x%08lX : 0x%08X\n",
5130                    (unsigned long)addr, DWC_READ_REG32(addr));
5131         addr = &core_if->dev_if->dev_global_regs->dctl;
5132         DWC_PRINTF("DCTL                 @0x%08lX : 0x%08X\n",
5133                    (unsigned long)addr, DWC_READ_REG32(addr));
5134         addr = &core_if->dev_if->dev_global_regs->dsts;
5135         DWC_PRINTF("DSTS                 @0x%08lX : 0x%08X\n",
5136                    (unsigned long)addr, DWC_READ_REG32(addr));
5137         addr = &core_if->dev_if->dev_global_regs->diepmsk;
5138         DWC_PRINTF("DIEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5139                    DWC_READ_REG32(addr));
5140         addr = &core_if->dev_if->dev_global_regs->doepmsk;
5141         DWC_PRINTF("DOEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5142                    DWC_READ_REG32(addr));
5143         addr = &core_if->dev_if->dev_global_regs->daint;
5144         DWC_PRINTF("DAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5145                    DWC_READ_REG32(addr));
5146         addr = &core_if->dev_if->dev_global_regs->daintmsk;
5147         DWC_PRINTF("DAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5148                    DWC_READ_REG32(addr));
5149         addr = &core_if->dev_if->dev_global_regs->dtknqr1;
5150         DWC_PRINTF("DTKNQR1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5151                    DWC_READ_REG32(addr));
5152         if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
5153                 addr = &core_if->dev_if->dev_global_regs->dtknqr2;
5154                 DWC_PRINTF("DTKNQR2      @0x%08lX : 0x%08X\n",
5155                            (unsigned long)addr, DWC_READ_REG32(addr));
5156         }
5157
5158         addr = &core_if->dev_if->dev_global_regs->dvbusdis;
5159         DWC_PRINTF("DVBUSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5160                    DWC_READ_REG32(addr));
5161
5162         addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
5163         DWC_PRINTF("DVBUSPULSE  @0x%08lX : 0x%08X\n",
5164                    (unsigned long)addr, DWC_READ_REG32(addr));
5165
5166         addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
5167         DWC_PRINTF("DTKNQR3_DTHRCTL      @0x%08lX : 0x%08X\n",
5168                    (unsigned long)addr, DWC_READ_REG32(addr));
5169
5170         if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
5171                 addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
5172                 DWC_PRINTF("DTKNQR4      @0x%08lX : 0x%08X\n",
5173                            (unsigned long)addr, DWC_READ_REG32(addr));
5174         }
5175
5176         addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
5177         DWC_PRINTF("FIFOEMPMSK   @0x%08lX : 0x%08X\n", (unsigned long)addr,
5178                    DWC_READ_REG32(addr));
5179
5180         if (core_if->hwcfg2.b.multi_proc_int) {
5181
5182                 addr = &core_if->dev_if->dev_global_regs->deachint;
5183                 DWC_PRINTF("DEACHINT     @0x%08lX : 0x%08X\n",
5184                            (unsigned long)addr, DWC_READ_REG32(addr));
5185                 addr = &core_if->dev_if->dev_global_regs->deachintmsk;
5186                 DWC_PRINTF("DEACHINTMSK  @0x%08lX : 0x%08X\n",
5187                            (unsigned long)addr, DWC_READ_REG32(addr));
5188
5189                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
5190                         addr =
5191                             &core_if->dev_if->dev_global_regs->
5192                             diepeachintmsk[i];
5193                         DWC_PRINTF("DIEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
5194                                    i, (unsigned long)addr,
5195                                    DWC_READ_REG32(addr));
5196                 }
5197
5198                 for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
5199                         addr =
5200                             &core_if->dev_if->dev_global_regs->
5201                             doepeachintmsk[i];
5202                         DWC_PRINTF("DOEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
5203                                    i, (unsigned long)addr,
5204                                    DWC_READ_REG32(addr));
5205                 }
5206         }
5207
5208         for (i = 0; i <= core_if->core_params->dev_endpoints; i++) {
5209                 if (hwcfg1 & (2 << (i << 1))) {
5210                         DWC_PRINTF("Device IN EP %d Registers\n", i);
5211                         addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
5212                         DWC_PRINTF("DIEPCTL      @0x%08lX : 0x%08X\n",
5213                                    (unsigned long)addr, DWC_READ_REG32(addr));
5214                         addr = &core_if->dev_if->in_ep_regs[i]->diepint;
5215                         DWC_PRINTF("DIEPINT      @0x%08lX : 0x%08X\n",
5216                                    (unsigned long)addr, DWC_READ_REG32(addr));
5217                         addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
5218                         DWC_PRINTF("DIETSIZ      @0x%08lX : 0x%08X\n",
5219                                    (unsigned long)addr, DWC_READ_REG32(addr));
5220                         addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
5221                         DWC_PRINTF("DIEPDMA      @0x%08lX : 0x%08X\n",
5222                                    (unsigned long)addr, DWC_READ_REG32(addr));
5223                         addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
5224                         DWC_PRINTF("DTXFSTS      @0x%08lX : 0x%08X\n",
5225                                    (unsigned long)addr, DWC_READ_REG32(addr));
5226                         addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
5227                         DWC_PRINTF("DIEPDMAB     @0x%08lX : 0x%08X\n",
5228                                    (unsigned long)addr,
5229                                    0 /*DWC_READ_REG32(addr) */);
5230                 }
5231         }
5232
5233         for (i = 0; i <= core_if->core_params->dev_endpoints; i++) {
5234                 if (hwcfg1 & (1 << (i << 1))) {
5235                         DWC_PRINTF("Device OUT EP %d Registers\n", i);
5236                         addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
5237                         DWC_PRINTF("DOEPCTL      @0x%08lX : 0x%08X\n",
5238                                    (unsigned long)addr, DWC_READ_REG32(addr));
5239                         addr = &core_if->dev_if->out_ep_regs[i]->doepint;
5240                         DWC_PRINTF("DOEPINT      @0x%08lX : 0x%08X\n",
5241                                    (unsigned long)addr, DWC_READ_REG32(addr));
5242                         addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
5243                         DWC_PRINTF("DOETSIZ      @0x%08lX : 0x%08X\n",
5244                                    (unsigned long)addr, DWC_READ_REG32(addr));
5245                         addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
5246                         DWC_PRINTF("DOEPDMA      @0x%08lX : 0x%08X\n",
5247                                    (unsigned long)addr, DWC_READ_REG32(addr));
5248                         /* Don't access this register in SLAVE mode */
5249                         if (core_if->dma_enable) {
5250                                 addr =
5251                                     &core_if->dev_if->out_ep_regs[i]->doepdmab;
5252                                 DWC_PRINTF("DOEPDMAB     @0x%08lX : 0x%08X\n",
5253                                            (unsigned long)addr,
5254                                            DWC_READ_REG32(addr));
5255                         }
5256                 }
5257
5258         }
5259 }
5260
5261 /**
5262  * This functions reads the SPRAM and prints its content
5263  *
5264  * @param core_if Programming view of DWC_otg controller.
5265  */
5266 void dwc_otg_dump_spram(dwc_otg_core_if_t *core_if)
5267 {
5268         volatile uint8_t *addr, *start_addr, *end_addr;
5269
5270         DWC_PRINTF("SPRAM Data:\n");
5271         start_addr = (void *)core_if->core_global_regs;
5272         DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
5273         start_addr += 0x00028000;
5274         end_addr = (void *)core_if->core_global_regs;
5275         end_addr += 0x000280e0;
5276
5277         for (addr = start_addr; addr < end_addr; addr += 16) {
5278                 DWC_PRINTF
5279                     ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
5280                      (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
5281                      addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
5282                      addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
5283                     );
5284         }
5285
5286         return;
5287 }
5288
5289 /**
5290  * This function reads the host registers and prints them
5291  *
5292  * @param core_if Programming view of DWC_otg controller.
5293  */
5294 void dwc_otg_dump_host_registers(dwc_otg_core_if_t *core_if)
5295 {
5296         int i;
5297         volatile uint32_t *addr;
5298
5299         DWC_PRINTF("Host Global Registers\n");
5300         addr = &core_if->host_if->host_global_regs->hcfg;
5301         DWC_PRINTF("HCFG                 @0x%08lX : 0x%08X\n",
5302                    (unsigned long)addr, DWC_READ_REG32(addr));
5303         addr = &core_if->host_if->host_global_regs->hfir;
5304         DWC_PRINTF("HFIR                 @0x%08lX : 0x%08X\n",
5305                    (unsigned long)addr, DWC_READ_REG32(addr));
5306         addr = &core_if->host_if->host_global_regs->hfnum;
5307         DWC_PRINTF("HFNUM        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5308                    DWC_READ_REG32(addr));
5309         addr = &core_if->host_if->host_global_regs->hptxsts;
5310         DWC_PRINTF("HPTXSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5311                    DWC_READ_REG32(addr));
5312         addr = &core_if->host_if->host_global_regs->haint;
5313         DWC_PRINTF("HAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5314                    DWC_READ_REG32(addr));
5315         addr = &core_if->host_if->host_global_regs->haintmsk;
5316         DWC_PRINTF("HAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5317                    DWC_READ_REG32(addr));
5318         if (core_if->dma_desc_enable) {
5319                 addr = &core_if->host_if->host_global_regs->hflbaddr;
5320                 DWC_PRINTF("HFLBADDR     @0x%08lX : 0x%08X\n",
5321                            (unsigned long)addr, DWC_READ_REG32(addr));
5322         }
5323
5324         addr = core_if->host_if->hprt0;
5325         DWC_PRINTF("HPRT0        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5326                    DWC_READ_REG32(addr));
5327
5328         for (i = 0; i < core_if->core_params->host_channels; i++) {
5329                 DWC_PRINTF("Host Channel %d Specific Registers\n", i);
5330                 addr = &core_if->host_if->hc_regs[i]->hcchar;
5331                 DWC_PRINTF("HCCHAR       @0x%08lX : 0x%08X\n",
5332                            (unsigned long)addr, DWC_READ_REG32(addr));
5333                 addr = &core_if->host_if->hc_regs[i]->hcsplt;
5334                 DWC_PRINTF("HCSPLT       @0x%08lX : 0x%08X\n",
5335                            (unsigned long)addr, DWC_READ_REG32(addr));
5336                 addr = &core_if->host_if->hc_regs[i]->hcint;
5337                 DWC_PRINTF("HCINT        @0x%08lX : 0x%08X\n",
5338                            (unsigned long)addr, DWC_READ_REG32(addr));
5339                 addr = &core_if->host_if->hc_regs[i]->hcintmsk;
5340                 DWC_PRINTF("HCINTMSK     @0x%08lX : 0x%08X\n",
5341                            (unsigned long)addr, DWC_READ_REG32(addr));
5342                 addr = &core_if->host_if->hc_regs[i]->hctsiz;
5343                 DWC_PRINTF("HCTSIZ       @0x%08lX : 0x%08X\n",
5344                            (unsigned long)addr, DWC_READ_REG32(addr));
5345                 addr = &core_if->host_if->hc_regs[i]->hcdma;
5346                 DWC_PRINTF("HCDMA        @0x%08lX : 0x%08X\n",
5347                            (unsigned long)addr, DWC_READ_REG32(addr));
5348                 if (core_if->dma_desc_enable) {
5349                         addr = &core_if->host_if->hc_regs[i]->hcdmab;
5350                         DWC_PRINTF("HCDMAB       @0x%08lX : 0x%08X\n",
5351                                    (unsigned long)addr, DWC_READ_REG32(addr));
5352                 }
5353
5354         }
5355         return;
5356 }
5357
5358 /**
5359  * This function reads the core global registers and prints them
5360  *
5361  * @param core_if Programming view of DWC_otg controller.
5362  */
5363 void dwc_otg_dump_global_registers(dwc_otg_core_if_t *core_if)
5364 {
5365         int i, ep_num;
5366         volatile uint32_t *addr;
5367         char *txfsiz;
5368
5369         DWC_PRINTF("Core Global Registers\n");
5370         addr = &core_if->core_global_regs->gotgctl;
5371         DWC_PRINTF("GOTGCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5372                    DWC_READ_REG32(addr));
5373         addr = &core_if->core_global_regs->gotgint;
5374         DWC_PRINTF("GOTGINT      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5375                    DWC_READ_REG32(addr));
5376         addr = &core_if->core_global_regs->gahbcfg;
5377         DWC_PRINTF("GAHBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5378                    DWC_READ_REG32(addr));
5379         addr = &core_if->core_global_regs->gusbcfg;
5380         DWC_PRINTF("GUSBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5381                    DWC_READ_REG32(addr));
5382         addr = &core_if->core_global_regs->grstctl;
5383         DWC_PRINTF("GRSTCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5384                    DWC_READ_REG32(addr));
5385         addr = &core_if->core_global_regs->gintsts;
5386         DWC_PRINTF("GINTSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5387                    DWC_READ_REG32(addr));
5388         addr = &core_if->core_global_regs->gintmsk;
5389         DWC_PRINTF("GINTMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5390                    DWC_READ_REG32(addr));
5391         addr = &core_if->core_global_regs->grxstsr;
5392         DWC_PRINTF("GRXSTSR      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5393                    DWC_READ_REG32(addr));
5394         addr = &core_if->core_global_regs->grxfsiz;
5395         DWC_PRINTF("GRXFSIZ      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5396                    DWC_READ_REG32(addr));
5397         addr = &core_if->core_global_regs->gnptxfsiz;
5398         DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
5399                    DWC_READ_REG32(addr));
5400         addr = &core_if->core_global_regs->gnptxsts;
5401         DWC_PRINTF("GNPTXSTS     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5402                    DWC_READ_REG32(addr));
5403         addr = &core_if->core_global_regs->gi2cctl;
5404         DWC_PRINTF("GI2CCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5405                    DWC_READ_REG32(addr));
5406         addr = &core_if->core_global_regs->gpvndctl;
5407         DWC_PRINTF("GPVNDCTL     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5408                    DWC_READ_REG32(addr));
5409         addr = &core_if->core_global_regs->ggpio;
5410         DWC_PRINTF("GGPIO        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5411                    DWC_READ_REG32(addr));
5412         addr = &core_if->core_global_regs->guid;
5413         DWC_PRINTF("GUID                 @0x%08lX : 0x%08X\n",
5414                    (unsigned long)addr, DWC_READ_REG32(addr));
5415         addr = &core_if->core_global_regs->gsnpsid;
5416         DWC_PRINTF("GSNPSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5417                    DWC_READ_REG32(addr));
5418         addr = &core_if->core_global_regs->ghwcfg1;
5419         DWC_PRINTF("GHWCFG1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5420                    DWC_READ_REG32(addr));
5421         addr = &core_if->core_global_regs->ghwcfg2;
5422         DWC_PRINTF("GHWCFG2      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5423                    DWC_READ_REG32(addr));
5424         addr = &core_if->core_global_regs->ghwcfg3;
5425         DWC_PRINTF("GHWCFG3      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5426                    DWC_READ_REG32(addr));
5427         addr = &core_if->core_global_regs->ghwcfg4;
5428         DWC_PRINTF("GHWCFG4      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5429                    DWC_READ_REG32(addr));
5430         addr = &core_if->core_global_regs->glpmcfg;
5431         DWC_PRINTF("GLPMCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5432                    DWC_READ_REG32(addr));
5433         addr = &core_if->core_global_regs->gpwrdn;
5434         DWC_PRINTF("GPWRDN       @0x%08lX : 0x%08X\n", (unsigned long)addr,
5435                    DWC_READ_REG32(addr));
5436         addr = &core_if->core_global_regs->gdfifocfg;
5437         DWC_PRINTF("GDFIFOCFG    @0x%08lX : 0x%08X\n", (unsigned long)addr,
5438                    DWC_READ_REG32(addr));
5439         addr = &core_if->core_global_regs->hptxfsiz;
5440         DWC_PRINTF("HPTXFSIZ     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5441                    DWC_READ_REG32(addr));
5442
5443         if (core_if->en_multiple_tx_fifo == 0) {
5444                 ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
5445                 txfsiz = "DPTXFSIZ";
5446         } else {
5447                 ep_num = core_if->hwcfg4.b.num_in_eps;
5448                 txfsiz = "DIENPTXF";
5449         }
5450         for (i = 0; i < ep_num; i++) {
5451                 addr = &core_if->core_global_regs->dtxfsiz[i];
5452                 DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
5453                            (unsigned long)addr, DWC_READ_REG32(addr));
5454         }
5455         addr = core_if->pcgcctl;
5456         DWC_PRINTF("PCGCCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5457                    DWC_READ_REG32(addr));
5458 }
5459
5460 /**
5461  * Flush a Tx FIFO.
5462  *
5463  * @param core_if Programming view of DWC_otg controller.
5464  * @param num Tx FIFO to flush.
5465  */
5466 void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *core_if, const int num)
5467 {
5468         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5469         volatile grstctl_t greset = {.d32 = 0 };
5470         int count = 0;
5471
5472         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
5473
5474         greset.b.txfflsh = 1;
5475         greset.b.txfnum = num;
5476         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5477
5478         do {
5479                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5480                 if (++count > 10000) {
5481                         DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
5482                                  __func__, greset.d32,
5483                                  DWC_READ_REG32(&global_regs->gnptxsts));
5484                         break;
5485                 }
5486                 dwc_udelay(1);
5487         } while (greset.b.txfflsh == 1);
5488
5489         /* Wait for 3 PHY Clocks */
5490         dwc_udelay(1);
5491 }
5492
5493 /**
5494  * Flush Rx FIFO.
5495  *
5496  * @param core_if Programming view of DWC_otg controller.
5497  */
5498 void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *core_if)
5499 {
5500         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5501         volatile grstctl_t greset = {.d32 = 0 };
5502         int count = 0;
5503
5504         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
5505         /*
5506          *
5507          */
5508         greset.b.rxfflsh = 1;
5509         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5510
5511         do {
5512                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5513                 if (++count > 10000) {
5514                         DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
5515                                  greset.d32);
5516                         break;
5517                 }
5518                 dwc_udelay(1);
5519         } while (greset.b.rxfflsh == 1);
5520
5521         /* Wait for 3 PHY Clocks */
5522         dwc_udelay(1);
5523 }
5524
5525 /**
5526  * Do core a soft reset of the core.  Be careful with this because it
5527  * resets all the internal state machines of the core.
5528  */
5529 void dwc_otg_core_reset(dwc_otg_core_if_t *core_if)
5530 {
5531         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5532         volatile grstctl_t greset = {.d32 = 0 };
5533         volatile gusbcfg_data_t usbcfg = {.d32 = 0 };
5534         int count = 0;
5535
5536         DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
5537         /* Wait for AHB master IDLE state. */
5538         do {
5539                 dwc_udelay(10);
5540                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5541                 if (++count > 100000) {
5542                         DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
5543                                  greset.d32);
5544                         return;
5545                 }
5546         } while (greset.b.ahbidle == 0);
5547
5548         /* Core Soft Reset */
5549         count = 0;
5550         greset.b.csftrst = 1;
5551         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5552
5553         do {
5554                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5555                 if (++count > 10000) {
5556                         DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
5557                                  __func__, greset.d32);
5558                         break;
5559                 }
5560                 dwc_udelay(1);
5561         } while (greset.b.csftrst == 1);
5562
5563         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
5564         if (core_if->usb_mode == USB_MODE_FORCE_HOST) {
5565                 usbcfg.b.force_host_mode = 1;
5566                 usbcfg.b.force_dev_mode = 0;
5567         } else if (core_if->usb_mode == USB_MODE_FORCE_DEVICE) {
5568                 usbcfg.b.force_host_mode = 0;
5569                 usbcfg.b.force_dev_mode = 1;
5570         } else {
5571                 usbcfg.b.force_host_mode = 0;
5572                 usbcfg.b.force_dev_mode = 0;
5573         }
5574         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
5575
5576         /* Wait for 3 PHY Clocks */
5577         dwc_mdelay(100);
5578
5579 }
5580
5581 uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
5582 {
5583         return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
5584 }
5585
5586 uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
5587 {
5588         return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
5589 }
5590
5591 /**
5592  * Register HCD callbacks. The callbacks are used to start and stop
5593  * the HCD for interrupt processing.
5594  *
5595  * @param core_if Programming view of DWC_otg controller.
5596  * @param cb the HCD callback structure.
5597  * @param p pointer to be passed to callback function (usb_hcd*).
5598  */
5599 void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *core_if,
5600                                         dwc_otg_cil_callbacks_t *cb, void *p)
5601 {
5602         core_if->hcd_cb = cb;
5603         /* cb->p = p; */
5604         core_if->hcd_cb_p = p;
5605 }
5606
5607 /**
5608  * Register PCD callbacks. The callbacks are used to start and stop
5609  * the PCD for interrupt processing.
5610  *
5611  * @param core_if Programming view of DWC_otg controller.
5612  * @param cb the PCD callback structure.
5613  * @param p pointer to be passed to callback function (pcd*).
5614  */
5615 void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *core_if,
5616                                         dwc_otg_cil_callbacks_t *cb, void *p)
5617 {
5618         core_if->pcd_cb = cb;
5619         cb->p = p;
5620 }
5621
5622 #ifdef DWC_EN_ISOC
5623
5624 /**
5625  * This function writes isoc data per 1 (micro)frame into tx fifo
5626  *
5627  * @param core_if Programming view of DWC_otg controller.
5628  * @param ep The EP to start the transfer on.
5629  *
5630  */
5631 void write_isoc_frame_data(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5632 {
5633         dwc_otg_dev_in_ep_regs_t *ep_regs;
5634         dtxfsts_data_t txstatus = {.d32 = 0 };
5635         uint32_t len = 0;
5636         uint32_t dwords;
5637
5638         ep->xfer_len = ep->data_per_frame;
5639         ep->xfer_count = 0;
5640
5641         ep_regs = core_if->dev_if->in_ep_regs[ep->num];
5642
5643         len = ep->xfer_len - ep->xfer_count;
5644
5645         if (len > ep->maxpacket) {
5646                 len = ep->maxpacket;
5647         }
5648
5649         dwords = (len + 3) / 4;
5650
5651         /* While there is space in the queue and space in the FIFO and
5652          * More data to tranfer, Write packets to the Tx FIFO */
5653         txstatus.d32 =
5654             DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
5655         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
5656
5657         while (txstatus.b.txfspcavail > dwords &&
5658                ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
5659                 /* Write the FIFO */
5660                 dwc_otg_ep_write_packet(core_if, ep, 0);
5661
5662                 len = ep->xfer_len - ep->xfer_count;
5663                 if (len > ep->maxpacket) {
5664                         len = ep->maxpacket;
5665                 }
5666
5667                 dwords = (len + 3) / 4;
5668                 txstatus.d32 =
5669                     DWC_READ_REG32(&core_if->dev_if->
5670                                    in_ep_regs[ep->num]->dtxfsts);
5671                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
5672                             txstatus.d32);
5673         }
5674 }
5675
5676 /**
5677  * This function initializes a descriptor chain for Isochronous transfer
5678  *
5679  * @param core_if Programming view of DWC_otg controller.
5680  * @param ep The EP to start the transfer on.
5681  *
5682  */
5683 void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if,
5684                                        dwc_ep_t *ep)
5685 {
5686         deptsiz_data_t deptsiz = {.d32 = 0 };
5687         depctl_data_t depctl = {.d32 = 0 };
5688         dsts_data_t dsts = {.d32 = 0 };
5689         volatile uint32_t *addr;
5690
5691         if (ep->is_in)
5692                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
5693         else
5694                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
5695
5696         ep->xfer_len = ep->data_per_frame;
5697         ep->xfer_count = 0;
5698         ep->xfer_buff = ep->cur_pkt_addr;
5699         ep->dma_addr = ep->cur_pkt_dma_addr;
5700
5701         if (ep->is_in) {
5702                 /* Program the transfer size and packet count
5703                  *      as follows: xfersize = N * maxpacket +
5704                  *      short_packet pktcnt = N + (short_packet
5705                  *      exist ? 1 : 0)
5706                  */
5707                 deptsiz.b.xfersize = ep->xfer_len;
5708                 deptsiz.b.pktcnt =
5709                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
5710                 deptsiz.b.mc = deptsiz.b.pktcnt;
5711                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
5712                                 deptsiz.d32);
5713
5714                 /* Write the DMA register */
5715                 if (core_if->dma_enable) {
5716                         DWC_WRITE_REG32(&
5717                                         (core_if->dev_if->
5718                                          in_ep_regs[ep->num]->diepdma),
5719                                         (uint32_t) ep->dma_addr);
5720                 }
5721         } else {
5722                 deptsiz.b.pktcnt =
5723                     (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
5724                 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
5725
5726                 DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
5727                                 doeptsiz, deptsiz.d32);
5728
5729                 if (core_if->dma_enable) {
5730                         DWC_WRITE_REG32(&
5731                                         (core_if->dev_if->out_ep_regs[ep->num]->
5732                                          doepdma), (uint32_t) ep->dma_addr);
5733                 }
5734         }
5735
5736         /** Enable endpoint, clear nak  */
5737
5738         depctl.d32 = 0;
5739         if (ep->bInterval == 1) {
5740                 dsts.d32 =
5741                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
5742                 ep->next_frame = dsts.b.soffn + ep->bInterval;
5743
5744                 if (ep->next_frame & 0x1)
5745                         depctl.b.setd1pid = 1;
5746                 else
5747                         depctl.b.setd0pid = 1;
5748         } else {
5749                 ep->next_frame += ep->bInterval;
5750
5751                 if (ep->next_frame & 0x1)
5752                         depctl.b.setd1pid = 1;
5753                 else
5754                         depctl.b.setd0pid = 1;
5755         }
5756         depctl.b.epena = 1;
5757         depctl.b.cnak = 1;
5758
5759         DWC_MODIFY_REG32(addr, 0, depctl.d32);
5760         depctl.d32 = DWC_READ_REG32(addr);
5761
5762         if (ep->is_in && core_if->dma_enable == 0) {
5763                 write_isoc_frame_data(core_if, ep);
5764         }
5765
5766 }
5767 #endif /* DWC_EN_ISOC */
5768
5769 static void dwc_otg_set_uninitialized(int32_t *p, int size)
5770 {
5771         int i;
5772         for (i = 0; i < size; i++) {
5773                 p[i] = -1;
5774         }
5775 }
5776
5777 static int dwc_otg_param_initialized(int32_t val)
5778 {
5779         return val != -1;
5780 }
5781
5782 static int dwc_otg_setup_params(dwc_otg_core_if_t *core_if)
5783 {
5784         gintsts_data_t gintsts;
5785         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
5786
5787         core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
5788         if (!core_if->core_params)
5789                 return -DWC_E_NO_MEMORY;
5790         dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
5791                                   sizeof(*core_if->core_params) /
5792                                   sizeof(int32_t));
5793         DWC_PRINTF("Setting default values for core params\n");
5794         dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
5795         dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
5796         dwc_otg_set_param_dma_desc_enable(core_if,
5797                                           dwc_param_dma_desc_enable_default);
5798         dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
5799         dwc_otg_set_param_dma_burst_size(core_if,
5800                                          dwc_param_dma_burst_size_default);
5801         dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
5802                                                        dwc_param_host_support_fs_ls_low_power_default);
5803         dwc_otg_set_param_enable_dynamic_fifo(core_if,
5804                                               dwc_param_enable_dynamic_fifo_default);
5805         dwc_otg_set_param_data_fifo_size(core_if,
5806                                          dwc_param_data_fifo_size_default);
5807         dwc_otg_set_param_dev_rx_fifo_size(core_if,
5808                                            dwc_param_dev_rx_fifo_size_default);
5809         dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
5810                                                   dwc_param_dev_nperio_tx_fifo_size_default);
5811         dwc_otg_set_param_host_rx_fifo_size(core_if,
5812                                             dwc_param_host_rx_fifo_size_default);
5813         dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
5814                                                    dwc_param_host_nperio_tx_fifo_size_default);
5815         dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
5816                                                   dwc_param_host_perio_tx_fifo_size_default);
5817         dwc_otg_set_param_max_transfer_size(core_if,
5818                                             dwc_param_max_transfer_size_default);
5819         dwc_otg_set_param_max_packet_count(core_if,
5820                                            dwc_param_max_packet_count_default);
5821         dwc_otg_set_param_host_channels(core_if,
5822                                         dwc_param_host_channels_default);
5823         dwc_otg_set_param_dev_endpoints(core_if,
5824                                         dwc_param_dev_endpoints_default);
5825         dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
5826         dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
5827         dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
5828                                                     dwc_param_host_ls_low_power_phy_clk_default);
5829         dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
5830         dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
5831                                             dwc_param_phy_ulpi_ext_vbus_default);
5832         dwc_otg_set_param_phy_utmi_width(core_if,
5833                                          dwc_param_phy_utmi_width_default);
5834         dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
5835         dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
5836         dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
5837         dwc_otg_set_param_en_multiple_tx_fifo(core_if,
5838                                               dwc_param_en_multiple_tx_fifo_default);
5839
5840         /* do not set dev_perio_tx_fifo_size and dev_tx_fifo_size here
5841          * set validate parameter values in "set_parameters" later.
5842          */
5843 #if 0
5844         if (gintsts.b.curmode) {
5845                 /* Force device mode to get power-on values of device FIFOs */
5846                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
5847                 gusbcfg.d32 =
5848                     DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
5849                 gusbcfg.b.force_dev_mode = 1;
5850                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
5851                                 gusbcfg.d32);
5852                 dwc_mdelay(100);
5853                 for (i = 0; i < 15; i++) {
5854                         dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
5855                                                                  dwc_param_dev_perio_tx_fifo_size_default,
5856                                                                  i);
5857                 }
5858                 for (i = 0; i < 15; i++) {
5859                         dwc_otg_set_param_dev_tx_fifo_size(core_if,
5860                                                            dwc_param_dev_tx_fifo_size_default,
5861                                                            i);
5862                 }
5863                 gusbcfg.d32 =
5864                     DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
5865                 gusbcfg.b.force_dev_mode = 0;
5866                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
5867                                 gusbcfg.d32);
5868                 dwc_mdelay(100);
5869         } else {
5870                 for (i = 0; i < 15; i++) {
5871                         dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
5872                                                                  dwc_param_dev_perio_tx_fifo_size_default,
5873                                                                  i);
5874                 }
5875                 for (i = 0; i < 15; i++) {
5876                         dwc_otg_set_param_dev_tx_fifo_size(core_if,
5877                                                            dwc_param_dev_tx_fifo_size_default,
5878                                                            i);
5879                 }
5880         }
5881 #endif
5882         dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
5883         dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
5884         dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
5885         dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
5886
5887         dwc_otg_set_param_besl_enable(core_if, dwc_param_besl_enable_default);
5888         dwc_otg_set_param_baseline_besl(core_if,
5889                                         dwc_param_baseline_besl_default);
5890         dwc_otg_set_param_deep_besl(core_if, dwc_param_deep_besl_default);
5891
5892         dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
5893         dwc_otg_set_param_tx_thr_length(core_if,
5894                                         dwc_param_tx_thr_length_default);
5895         dwc_otg_set_param_rx_thr_length(core_if,
5896                                         dwc_param_rx_thr_length_default);
5897         dwc_otg_set_param_ahb_thr_ratio(core_if,
5898                                         dwc_param_ahb_thr_ratio_default);
5899         dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
5900         dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
5901         dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
5902         dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
5903         dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
5904         dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
5905         dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
5906         return 0;
5907 }
5908
5909 uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t *core_if)
5910 {
5911         return core_if->dma_enable;
5912 }
5913
5914 /* Checks if the parameter is outside of its valid range of values */
5915 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
5916                 (((_param_) < (_low_)) || \
5917                 ((_param_) > (_high_)))
5918
5919 /* Parameter access functions */
5920 int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t *core_if, int32_t val)
5921 {
5922         int valid;
5923         int retval = 0;
5924         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
5925                 DWC_WARN("Wrong value for otg_cap parameter\n");
5926                 DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
5927                 retval = -DWC_E_INVALID;
5928                 goto out;
5929         }
5930
5931         valid = 1;
5932         switch (val) {
5933         case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
5934                 if (core_if->hwcfg2.b.op_mode !=
5935                     DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5936                         valid = 0;
5937                 break;
5938         case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
5939                 if ((core_if->hwcfg2.b.op_mode !=
5940                      DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5941                     && (core_if->hwcfg2.b.op_mode !=
5942                         DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
5943                     && (core_if->hwcfg2.b.op_mode !=
5944                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
5945                     && (core_if->hwcfg2.b.op_mode !=
5946                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
5947                         valid = 0;
5948                 }
5949                 break;
5950         case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
5951                 /* always valid */
5952                 break;
5953         }
5954         if (!valid) {
5955                 if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
5956                         DWC_ERROR
5957                             ("%d invalid for otg_cap paremter. Check HW configuration.\n",
5958                              val);
5959                 }
5960                 val =
5961                     (((core_if->hwcfg2.b.op_mode ==
5962                        DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5963                       || (core_if->hwcfg2.b.op_mode ==
5964                           DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
5965                       || (core_if->hwcfg2.b.op_mode ==
5966                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
5967                       || (core_if->hwcfg2.b.op_mode ==
5968                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
5969                      DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
5970                      DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
5971                 retval = -DWC_E_INVALID;
5972         }
5973
5974         core_if->core_params->otg_cap = val;
5975 out:
5976         return retval;
5977 }
5978
5979 int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t *core_if)
5980 {
5981         return core_if->core_params->otg_cap;
5982 }
5983
5984 int dwc_otg_set_param_opt(dwc_otg_core_if_t *core_if, int32_t val)
5985 {
5986         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5987                 DWC_WARN("Wrong value for opt parameter\n");
5988                 return -DWC_E_INVALID;
5989         }
5990         core_if->core_params->opt = val;
5991         return 0;
5992 }
5993
5994 int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t *core_if)
5995 {
5996         return core_if->core_params->opt;
5997 }
5998
5999 int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t *core_if, int32_t val)
6000 {
6001         int retval = 0;
6002         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6003                 DWC_WARN("Wrong value for dma enable\n");
6004                 return -DWC_E_INVALID;
6005         }
6006
6007         if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
6008                 if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
6009                         DWC_ERROR
6010                             ("%d invalid for dma_enable paremter. Check HW configuration.\n",
6011                              val);
6012                 }
6013                 val = 0;
6014                 retval = -DWC_E_INVALID;
6015         }
6016
6017         core_if->core_params->dma_enable = val;
6018         if (val == 0) {
6019                 dwc_otg_set_param_dma_desc_enable(core_if, 0);
6020         }
6021         return retval;
6022 }
6023
6024 int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t *core_if)
6025 {
6026         return core_if->core_params->dma_enable;
6027 }
6028
6029 int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t *core_if, int32_t val)
6030 {
6031         int retval = 0;
6032         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6033                 DWC_WARN("Wrong value for dma_enable\n");
6034                 DWC_WARN("dma_desc_enable must be 0 or 1\n");
6035                 return -DWC_E_INVALID;
6036         }
6037
6038         if ((val == 1)
6039             && ((dwc_otg_get_param_dma_enable(core_if) == 0)
6040                 || (core_if->hwcfg4.b.desc_dma == 0))) {
6041                 if (dwc_otg_param_initialized
6042                     (core_if->core_params->dma_desc_enable)) {
6043                         DWC_ERROR
6044                             ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
6045                              val);
6046                 }
6047                 val = 0;
6048                 retval = -DWC_E_INVALID;
6049         }
6050         core_if->core_params->dma_desc_enable = val;
6051         return retval;
6052 }
6053
6054 int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t *core_if)
6055 {
6056         return core_if->core_params->dma_desc_enable;
6057 }
6058
6059 int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *core_if,
6060                                                    int32_t val)
6061 {
6062         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6063                 DWC_WARN("Wrong value for host_support_fs_low_power\n");
6064                 DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
6065                 return -DWC_E_INVALID;
6066         }
6067         core_if->core_params->host_support_fs_ls_low_power = val;
6068         return 0;
6069 }
6070
6071 int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
6072                                                        *core_if)
6073 {
6074         return core_if->core_params->host_support_fs_ls_low_power;
6075 }
6076
6077 int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t *core_if,
6078                                           int32_t val)
6079 {
6080         int retval = 0;
6081         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6082                 DWC_WARN("Wrong value for enable_dynamic_fifo\n");
6083                 DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
6084                 return -DWC_E_INVALID;
6085         }
6086
6087         if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
6088                 if (dwc_otg_param_initialized
6089                     (core_if->core_params->enable_dynamic_fifo)) {
6090                         DWC_ERROR
6091                             ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
6092                              val);
6093                 }
6094                 val = 0;
6095                 retval = -DWC_E_INVALID;
6096         }
6097         core_if->core_params->enable_dynamic_fifo = val;
6098         return retval;
6099 }
6100
6101 int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *core_if)
6102 {
6103         return core_if->core_params->enable_dynamic_fifo;
6104 }
6105
6106 int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t *core_if, int32_t val)
6107 {
6108         int retval = 0;
6109         if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
6110                 DWC_WARN("Wrong value for data_fifo_size\n");
6111                 DWC_WARN("data_fifo_size must be 32-32768\n");
6112                 return -DWC_E_INVALID;
6113         }
6114
6115         if (val > core_if->hwcfg3.b.dfifo_depth) {
6116                 if (dwc_otg_param_initialized
6117                     (core_if->core_params->data_fifo_size)) {
6118                         DWC_ERROR
6119                             ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
6120                              val);
6121                 }
6122                 val = core_if->hwcfg3.b.dfifo_depth;
6123                 retval = -DWC_E_INVALID;
6124         }
6125
6126         core_if->core_params->data_fifo_size = val;
6127         return retval;
6128 }
6129
6130 int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t *core_if)
6131 {
6132         return core_if->core_params->data_fifo_size;
6133 }
6134
6135 int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t *core_if, int32_t val)
6136 {
6137         int retval = 0;
6138         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6139                 DWC_WARN("Wrong value for dev_rx_fifo_size\n");
6140                 DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
6141                 return -DWC_E_INVALID;
6142         }
6143
6144         if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
6145                 if (dwc_otg_param_initialized
6146                     (core_if->core_params->dev_rx_fifo_size)) {
6147                         DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n",
6148                                  val);
6149                 }
6150                 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
6151                 retval = -DWC_E_INVALID;
6152         }
6153
6154         core_if->core_params->dev_rx_fifo_size = val;
6155         return retval;
6156 }
6157
6158 int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t *core_if)
6159 {
6160         return core_if->core_params->dev_rx_fifo_size;
6161 }
6162
6163 int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if,
6164                                               int32_t val)
6165 {
6166         int retval = 0;
6167
6168         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6169                 DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
6170                 DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
6171                 return -DWC_E_INVALID;
6172         }
6173
6174         if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
6175                 if (dwc_otg_param_initialized
6176                     (core_if->core_params->dev_nperio_tx_fifo_size)) {
6177                         DWC_ERROR
6178                             ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
6179                              val);
6180                 }
6181                 val =
6182                     (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
6183                      16);
6184                 retval = -DWC_E_INVALID;
6185         }
6186
6187         core_if->core_params->dev_nperio_tx_fifo_size = val;
6188         return retval;
6189 }
6190
6191 int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if)
6192 {
6193         return core_if->core_params->dev_nperio_tx_fifo_size;
6194 }
6195
6196 int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t *core_if,
6197                                         int32_t val)
6198 {
6199         int retval = 0;
6200
6201         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6202                 DWC_WARN("Wrong value for host_rx_fifo_size\n");
6203                 DWC_WARN("host_rx_fifo_size must be 16-32768\n");
6204                 return -DWC_E_INVALID;
6205         }
6206
6207         if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
6208                 if (dwc_otg_param_initialized
6209                     (core_if->core_params->host_rx_fifo_size)) {
6210                         DWC_ERROR
6211                             ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
6212                              val);
6213                 }
6214                 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
6215                 retval = -DWC_E_INVALID;
6216         }
6217
6218         core_if->core_params->host_rx_fifo_size = val;
6219         return retval;
6220
6221 }
6222
6223 int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t *core_if)
6224 {
6225         return core_if->core_params->host_rx_fifo_size;
6226 }
6227
6228 int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if,
6229                                                int32_t val)
6230 {
6231         int retval = 0;
6232
6233         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6234                 DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
6235                 DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
6236                 return -DWC_E_INVALID;
6237         }
6238
6239         if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
6240                 if (dwc_otg_param_initialized
6241                     (core_if->core_params->host_nperio_tx_fifo_size)) {
6242                         DWC_ERROR
6243                             ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
6244                              val);
6245                 }
6246                 val =
6247                     (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
6248                      16);
6249                 retval = -DWC_E_INVALID;
6250         }
6251
6252         core_if->core_params->host_nperio_tx_fifo_size = val;
6253         return retval;
6254 }
6255
6256 int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if)
6257 {
6258         return core_if->core_params->host_nperio_tx_fifo_size;
6259 }
6260
6261 int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *core_if,
6262                                               int32_t val)
6263 {
6264         int retval = 0;
6265         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6266                 DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
6267                 DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
6268                 return -DWC_E_INVALID;
6269         }
6270
6271         if (val > ((core_if->hptxfsiz.d32) >> 16)) {
6272                 if (dwc_otg_param_initialized
6273                     (core_if->core_params->host_perio_tx_fifo_size)) {
6274                         DWC_ERROR
6275                             ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
6276                              val);
6277                 }
6278                 val = (core_if->hptxfsiz.d32) >> 16;
6279                 retval = -DWC_E_INVALID;
6280         }
6281
6282         core_if->core_params->host_perio_tx_fifo_size = val;
6283         return retval;
6284 }
6285
6286 int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *core_if)
6287 {
6288         return core_if->core_params->host_perio_tx_fifo_size;
6289 }
6290
6291 int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t *core_if,
6292                                         int32_t val)
6293 {
6294         int retval = 0;
6295
6296         if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
6297                 DWC_WARN("Wrong value for max_transfer_size\n");
6298                 DWC_WARN("max_transfer_size must be 2047-524288\n");
6299                 return -DWC_E_INVALID;
6300         }
6301
6302         if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
6303                 if (dwc_otg_param_initialized
6304                     (core_if->core_params->max_transfer_size)) {
6305                         DWC_ERROR
6306                             ("%d invalid for max_transfer_size. Check HW configuration.\n",
6307                              val);
6308                 }
6309                 val =
6310                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
6311                      1);
6312                 retval = -DWC_E_INVALID;
6313         }
6314
6315         core_if->core_params->max_transfer_size = val;
6316         return retval;
6317 }
6318
6319 int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t *core_if)
6320 {
6321         return core_if->core_params->max_transfer_size;
6322 }
6323
6324 int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t *core_if, int32_t val)
6325 {
6326         int retval = 0;
6327
6328         if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
6329                 DWC_WARN("Wrong value for max_packet_count\n");
6330                 DWC_WARN("max_packet_count must be 15-511\n");
6331                 return -DWC_E_INVALID;
6332         }
6333
6334         if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
6335                 if (dwc_otg_param_initialized
6336                     (core_if->core_params->max_packet_count)) {
6337                         DWC_ERROR
6338                             ("%d invalid for max_packet_count. Check HW configuration.\n",
6339                              val);
6340                 }
6341                 val =
6342                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
6343                 retval = -DWC_E_INVALID;
6344         }
6345
6346         core_if->core_params->max_packet_count = val;
6347         return retval;
6348 }
6349
6350 int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t *core_if)
6351 {
6352         return core_if->core_params->max_packet_count;
6353 }
6354
6355 int dwc_otg_set_param_host_channels(dwc_otg_core_if_t *core_if, int32_t val)
6356 {
6357         int retval = 0;
6358
6359         if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
6360                 DWC_WARN("Wrong value for host_channels\n");
6361                 DWC_WARN("host_channels must be 1-16\n");
6362                 return -DWC_E_INVALID;
6363         }
6364
6365         if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
6366                 if (dwc_otg_param_initialized
6367                     (core_if->core_params->host_channels)) {
6368                         DWC_ERROR
6369                             ("%d invalid for host_channels. Check HW configurations.\n",
6370                              val);
6371                 }
6372                 val = (core_if->hwcfg2.b.num_host_chan + 1);
6373                 retval = -DWC_E_INVALID;
6374         }
6375
6376         core_if->core_params->host_channels = val;
6377         return retval;
6378 }
6379
6380 int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t *core_if)
6381 {
6382         return core_if->core_params->host_channels;
6383 }
6384
6385 int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t *core_if, int32_t val)
6386 {
6387         int retval = 0;
6388
6389         if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
6390                 DWC_WARN("Wrong value for dev_endpoints\n");
6391                 DWC_WARN("dev_endpoints must be 1-15\n");
6392                 return -DWC_E_INVALID;
6393         }
6394
6395         if (val > (core_if->hwcfg2.b.num_dev_ep)) {
6396                 if (dwc_otg_param_initialized
6397                     (core_if->core_params->dev_endpoints)) {
6398                         DWC_ERROR
6399                             ("%d invalid for dev_endpoints. Check HW configurations.\n",
6400                              val);
6401                 }
6402                 val = core_if->hwcfg2.b.num_dev_ep;
6403                 retval = -DWC_E_INVALID;
6404         }
6405
6406         core_if->core_params->dev_endpoints = val;
6407         return retval;
6408 }
6409
6410 int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t *core_if)
6411 {
6412         return core_if->core_params->dev_endpoints;
6413 }
6414
6415 int dwc_otg_set_param_phy_type(dwc_otg_core_if_t *core_if, int32_t val)
6416 {
6417         int retval = 0;
6418         int valid = 0;
6419
6420         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
6421                 DWC_WARN("Wrong value for phy_type\n");
6422                 DWC_WARN("phy_type must be 0,1 or 2\n");
6423                 return -DWC_E_INVALID;
6424         }
6425 #ifndef NO_FS_PHY_HW_CHECKS
6426         if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
6427             ((core_if->hwcfg2.b.hs_phy_type == 1) ||
6428              (core_if->hwcfg2.b.hs_phy_type == 3))) {
6429                 valid = 1;
6430         } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
6431                    ((core_if->hwcfg2.b.hs_phy_type == 2) ||
6432                     (core_if->hwcfg2.b.hs_phy_type == 3))) {
6433                 valid = 1;
6434         } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
6435                    (core_if->hwcfg2.b.fs_phy_type == 1)) {
6436                 valid = 1;
6437         }
6438         if (!valid) {
6439                 if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
6440                         DWC_ERROR
6441                             ("%d invalid for phy_type. Check HW configurations.\n",
6442                              val);
6443                 }
6444                 if (core_if->hwcfg2.b.hs_phy_type) {
6445                         if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
6446                             (core_if->hwcfg2.b.hs_phy_type == 1)) {
6447                                 val = DWC_PHY_TYPE_PARAM_UTMI;
6448                         } else {
6449                                 val = DWC_PHY_TYPE_PARAM_ULPI;
6450                         }
6451                 }
6452                 retval = -DWC_E_INVALID;
6453         }
6454 #endif
6455         core_if->core_params->phy_type = val;
6456         return retval;
6457 }
6458
6459 int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t *core_if)
6460 {
6461         return core_if->core_params->phy_type;
6462 }
6463
6464 int dwc_otg_set_param_speed(dwc_otg_core_if_t *core_if, int32_t val)
6465 {
6466         int retval = 0;
6467         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6468                 DWC_WARN("Wrong value for speed parameter\n");
6469                 DWC_WARN("max_speed parameter must be 0 or 1\n");
6470                 return -DWC_E_INVALID;
6471         }
6472         if ((val == 0)
6473             && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
6474                 if (dwc_otg_param_initialized(core_if->core_params->speed)) {
6475                         DWC_ERROR
6476                             ("%d invalid for speed paremter. Check HW configuration.\n",
6477                              val);
6478                 }
6479                 val =
6480                     (dwc_otg_get_param_phy_type(core_if) ==
6481                      DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
6482                 retval = -DWC_E_INVALID;
6483         }
6484         core_if->core_params->speed = val;
6485         return retval;
6486 }
6487
6488 int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t *core_if)
6489 {
6490         return core_if->core_params->speed;
6491 }
6492
6493 int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *core_if,
6494                                                 int32_t val)
6495 {
6496         int retval = 0;
6497
6498         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6499                 DWC_WARN
6500                     ("Wrong value for host_ls_low_power_phy_clk parameter\n");
6501                 DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
6502                 return -DWC_E_INVALID;
6503         }
6504
6505         if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
6506             && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
6507                 if (dwc_otg_param_initialized
6508                     (core_if->core_params->host_ls_low_power_phy_clk)) {
6509                         DWC_ERROR
6510                             ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
6511                              val);
6512                 }
6513                 val =
6514                     (dwc_otg_get_param_phy_type(core_if) ==
6515                      DWC_PHY_TYPE_PARAM_FS) ?
6516                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
6517                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
6518                 retval = -DWC_E_INVALID;
6519         }
6520
6521         core_if->core_params->host_ls_low_power_phy_clk = val;
6522         return retval;
6523 }
6524
6525 int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *core_if)
6526 {
6527         return core_if->core_params->host_ls_low_power_phy_clk;
6528 }
6529
6530 int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t *core_if, int32_t val)
6531 {
6532         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6533                 DWC_WARN("Wrong value for phy_ulpi_ddr\n");
6534                 DWC_WARN("phy_upli_ddr must be 0 or 1\n");
6535                 return -DWC_E_INVALID;
6536         }
6537
6538         core_if->core_params->phy_ulpi_ddr = val;
6539         return 0;
6540 }
6541
6542 int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t *core_if)
6543 {
6544         return core_if->core_params->phy_ulpi_ddr;
6545 }
6546
6547 int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t *core_if,
6548                                         int32_t val)
6549 {
6550         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6551                 DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
6552                 DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
6553                 return -DWC_E_INVALID;
6554         }
6555
6556         core_if->core_params->phy_ulpi_ext_vbus = val;
6557         return 0;
6558 }
6559
6560 int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t *core_if)
6561 {
6562         return core_if->core_params->phy_ulpi_ext_vbus;
6563 }
6564
6565 int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t *core_if, int32_t val)
6566 {
6567         if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
6568                 DWC_WARN("Wrong valaue for phy_utmi_width\n");
6569                 DWC_WARN("phy_utmi_width must be 8 or 16\n");
6570                 return -DWC_E_INVALID;
6571         }
6572
6573         core_if->core_params->phy_utmi_width = val;
6574         return 0;
6575 }
6576
6577 int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t *core_if)
6578 {
6579         return core_if->core_params->phy_utmi_width;
6580 }
6581
6582 int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t *core_if, int32_t val)
6583 {
6584         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6585                 DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
6586                 DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
6587                 return -DWC_E_INVALID;
6588         }
6589
6590         core_if->core_params->ulpi_fs_ls = val;
6591         return 0;
6592 }
6593
6594 int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t *core_if)
6595 {
6596         return core_if->core_params->ulpi_fs_ls;
6597 }
6598
6599 int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t *core_if, int32_t val)
6600 {
6601         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6602                 DWC_WARN("Wrong valaue for ts_dline\n");
6603                 DWC_WARN("ts_dline must be 0 or 1\n");
6604                 return -DWC_E_INVALID;
6605         }
6606
6607         core_if->core_params->ts_dline = val;
6608         return 0;
6609 }
6610
6611 int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t *core_if)
6612 {
6613         return core_if->core_params->ts_dline;
6614 }
6615
6616 int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t *core_if, int32_t val)
6617 {
6618         int retval = 0;
6619         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6620                 DWC_WARN("Wrong valaue for i2c_enable\n");
6621                 DWC_WARN("i2c_enable must be 0 or 1\n");
6622                 return -DWC_E_INVALID;
6623         }
6624 #ifndef NO_FS_PHY_HW_CHECK
6625         if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
6626                 if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
6627                         DWC_ERROR
6628                             ("%d invalid for i2c_enable. Check HW configuration.\n",
6629                              val);
6630                 }
6631                 val = 0;
6632                 retval = -DWC_E_INVALID;
6633         }
6634 #endif
6635
6636         core_if->core_params->i2c_enable = val;
6637         return retval;
6638 }
6639
6640 int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t *core_if)
6641 {
6642         return core_if->core_params->i2c_enable;
6643 }
6644
6645 int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *core_if,
6646                                              int32_t val, int fifo_num)
6647 {
6648         int retval = 0;
6649         gintsts_data_t gintsts;
6650         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
6651
6652         if (core_if->hwcfg4.b.ded_fifo_en == 0) {
6653                 if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
6654                         DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
6655                         DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
6656                         return -DWC_E_INVALID;
6657                 }
6658
6659                 if (val >
6660                     (DWC_READ_REG32
6661                      (&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16)) {
6662                         printk("%d   ",
6663                                DWC_READ_REG32(&core_if->core_global_regs->
6664                                               dtxfsiz[fifo_num]) >> 16);
6665                         printk("val = %d fifo_num = %d\n", val, fifo_num);
6666                         DWC_WARN("Value is larger then power-on FIFO size\n");
6667                         if (dwc_otg_param_initialized
6668                             (core_if->core_params->
6669                              dev_perio_tx_fifo_size[fifo_num])) {
6670                                 DWC_ERROR
6671                                     ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
6672                                      val, fifo_num);
6673                         }
6674                         val =
6675                             (DWC_READ_REG32
6676                              (&core_if->core_global_regs->
6677                               dtxfsiz[fifo_num]) >> 16);
6678                         retval = -DWC_E_INVALID;
6679                 }
6680
6681                 core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
6682         }
6683         return retval;
6684 }
6685
6686 int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *core_if,
6687                                                  int fifo_num)
6688 {
6689         return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
6690 }
6691
6692 int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t *core_if,
6693                                           int32_t val)
6694 {
6695         int retval = 0;
6696         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6697                 DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
6698                 DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
6699                 return -DWC_E_INVALID;
6700         }
6701
6702         if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
6703                 if (dwc_otg_param_initialized
6704                     (core_if->core_params->en_multiple_tx_fifo)) {
6705                         DWC_ERROR
6706                             ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
6707                              val);
6708                 }
6709                 val = 0;
6710                 retval = -DWC_E_INVALID;
6711         }
6712
6713         core_if->core_params->en_multiple_tx_fifo = val;
6714         return retval;
6715 }
6716
6717 int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *core_if)
6718 {
6719         return core_if->core_params->en_multiple_tx_fifo;
6720 }
6721
6722 int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t *core_if, int32_t val,
6723                                        int fifo_num)
6724 {
6725         int retval = 0;
6726         fifosize_data_t txfifosize;
6727         txfifosize.d32 =
6728             DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]);
6729
6730         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6731                 DWC_WARN("Wrong value for dev_tx_fifo_size\n");
6732                 DWC_WARN("dev_tx_fifo_size must be 16-32768\n");
6733                 return -DWC_E_INVALID;
6734         }
6735
6736         core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
6737         return retval;
6738 }
6739
6740 int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t *core_if,
6741                                            int fifo_num)
6742 {
6743         return core_if->core_params->dev_tx_fifo_size[fifo_num];
6744 }
6745
6746 int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t *core_if, int32_t val)
6747 {
6748         int retval = 0;
6749
6750         if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
6751                 DWC_WARN("Wrong value for thr_ctl\n");
6752                 DWC_WARN("thr_ctl must be 0-7\n");
6753                 return -DWC_E_INVALID;
6754         }
6755
6756         if ((val != 0) &&
6757             (!dwc_otg_get_param_dma_enable(core_if) ||
6758              !core_if->hwcfg4.b.ded_fifo_en)) {
6759                 if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
6760                         DWC_ERROR
6761                             ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
6762                              val);
6763                 }
6764                 val = 0;
6765                 retval = -DWC_E_INVALID;
6766         }
6767
6768         core_if->core_params->thr_ctl = val;
6769         return retval;
6770 }
6771
6772 int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t *core_if)
6773 {
6774         return core_if->core_params->thr_ctl;
6775 }
6776
6777 int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t *core_if, int32_t val)
6778 {
6779         int retval = 0;
6780
6781         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6782                 DWC_WARN("Wrong value for lpm_enable\n");
6783                 DWC_WARN("lpm_enable must be 0 or 1\n");
6784                 return -DWC_E_INVALID;
6785         }
6786
6787         if (val && !core_if->hwcfg3.b.otg_lpm_en) {
6788                 if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
6789                         DWC_ERROR
6790                             ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
6791                              val);
6792                 }
6793                 val = 0;
6794                 retval = -DWC_E_INVALID;
6795         }
6796
6797         core_if->core_params->lpm_enable = val;
6798         return retval;
6799 }
6800
6801 int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t *core_if)
6802 {
6803         return core_if->core_params->lpm_enable;
6804 }
6805
6806 int dwc_otg_set_param_besl_enable(dwc_otg_core_if_t *core_if, int32_t val)
6807 {
6808         int retval = 0;
6809
6810         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6811                 DWC_WARN("Wrong value for besl_enable\n");
6812                 DWC_WARN("besl_enable must be 0 or 1\n");
6813                 return -DWC_E_INVALID;
6814         }
6815
6816         core_if->core_params->besl_enable = val;
6817
6818         if (val) {
6819                 retval += dwc_otg_set_param_lpm_enable(core_if, val);
6820         }
6821
6822         return retval;
6823 }
6824
6825 int32_t dwc_otg_get_param_besl_enable(dwc_otg_core_if_t *core_if)
6826 {
6827         return core_if->core_params->besl_enable;
6828 }
6829
6830 int dwc_otg_set_param_baseline_besl(dwc_otg_core_if_t *core_if, int32_t val)
6831 {
6832         int retval = 0;
6833
6834         if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
6835                 DWC_WARN("Wrong value for baseline_besl\n");
6836                 DWC_WARN("baseline_besl must be 0-15\n");
6837                 return -DWC_E_INVALID;
6838         }
6839
6840         core_if->core_params->baseline_besl = val;
6841         return retval;
6842 }
6843
6844 int32_t dwc_otg_get_param_baseline_besl(dwc_otg_core_if_t *core_if)
6845 {
6846         return core_if->core_params->baseline_besl;
6847 }
6848
6849 int dwc_otg_set_param_deep_besl(dwc_otg_core_if_t *core_if, int32_t val)
6850 {
6851         int retval = 0;
6852
6853         if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
6854                 DWC_WARN("Wrong value for deep_besl\n");
6855                 DWC_WARN("deep_besl must be 0-15\n");
6856                 return -DWC_E_INVALID;
6857         }
6858
6859         core_if->core_params->deep_besl = val;
6860         return retval;
6861 }
6862
6863 int32_t dwc_otg_get_param_deep_besl(dwc_otg_core_if_t *core_if)
6864 {
6865         return core_if->core_params->deep_besl;
6866 }
6867
6868 int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t *core_if, int32_t val)
6869 {
6870         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
6871                 DWC_WARN("Wrong valaue for tx_thr_length\n");
6872                 DWC_WARN("tx_thr_length must be 8 - 128\n");
6873                 return -DWC_E_INVALID;
6874         }
6875
6876         core_if->core_params->tx_thr_length = val;
6877         return 0;
6878 }
6879
6880 int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t *core_if)
6881 {
6882         return core_if->core_params->tx_thr_length;
6883 }
6884
6885 int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t *core_if, int32_t val)
6886 {
6887         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
6888                 DWC_WARN("Wrong valaue for rx_thr_length\n");
6889                 DWC_WARN("rx_thr_length must be 8 - 128\n");
6890                 return -DWC_E_INVALID;
6891         }
6892
6893         core_if->core_params->rx_thr_length = val;
6894         return 0;
6895 }
6896
6897 int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t *core_if)
6898 {
6899         return core_if->core_params->rx_thr_length;
6900 }
6901
6902 int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t *core_if, int32_t val)
6903 {
6904         if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
6905             DWC_OTG_PARAM_TEST(val, 4, 4) &&
6906             DWC_OTG_PARAM_TEST(val, 8, 8) &&
6907             DWC_OTG_PARAM_TEST(val, 16, 16) &&
6908             DWC_OTG_PARAM_TEST(val, 32, 32) &&
6909             DWC_OTG_PARAM_TEST(val, 64, 64) &&
6910             DWC_OTG_PARAM_TEST(val, 128, 128) &&
6911             DWC_OTG_PARAM_TEST(val, 256, 256)) {
6912                 DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
6913                 return -DWC_E_INVALID;
6914         }
6915         core_if->core_params->dma_burst_size = val;
6916         return 0;
6917 }
6918
6919 int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t *core_if)
6920 {
6921         return core_if->core_params->dma_burst_size;
6922 }
6923
6924 int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t *core_if, int32_t val)
6925 {
6926         int retval = 0;
6927         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6928                 DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
6929                 return -DWC_E_INVALID;
6930         }
6931         if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
6932                 if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
6933                         DWC_ERROR
6934                             ("%d invalid for parameter pti_enable. Check HW configuration.\n",
6935                              val);
6936                 }
6937                 retval = -DWC_E_INVALID;
6938                 val = 0;
6939         }
6940         core_if->core_params->pti_enable = val;
6941         return retval;
6942 }
6943
6944 int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t *core_if)
6945 {
6946         return core_if->core_params->pti_enable;
6947 }
6948
6949 int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t *core_if, int32_t val)
6950 {
6951         int retval = 0;
6952         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6953                 DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
6954                 return -DWC_E_INVALID;
6955         }
6956         if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
6957                 if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
6958                         DWC_ERROR
6959                             ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
6960                              val);
6961                 }
6962                 retval = -DWC_E_INVALID;
6963                 val = 0;
6964         }
6965         core_if->core_params->mpi_enable = val;
6966         return retval;
6967 }
6968
6969 int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t *core_if)
6970 {
6971         return core_if->core_params->mpi_enable;
6972 }
6973
6974 int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t *core_if, int32_t val)
6975 {
6976         int retval = 0;
6977         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6978                 DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
6979                 return -DWC_E_INVALID;
6980         }
6981         if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
6982                 if (dwc_otg_param_initialized
6983                     (core_if->core_params->adp_supp_enable)) {
6984                         DWC_ERROR
6985                             ("%d invalid for parameter adp_enable. Check HW configuration.\n",
6986                              val);
6987                 }
6988                 retval = -DWC_E_INVALID;
6989                 val = 0;
6990         }
6991         core_if->core_params->adp_supp_enable = val;
6992         /* Set OTG version 2.0 in case of enabling ADP */
6993         if (val)
6994                 dwc_otg_set_param_otg_ver(core_if, 1);
6995
6996         return retval;
6997 }
6998
6999 int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t *core_if)
7000 {
7001         return core_if->core_params->adp_supp_enable;
7002 }
7003
7004 int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t *core_if, int32_t val)
7005 {
7006         int retval = 0;
7007         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7008                 DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
7009                 DWC_WARN("ic_usb_cap must be 0 or 1\n");
7010                 return -DWC_E_INVALID;
7011         }
7012
7013         if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
7014                 if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
7015                         DWC_ERROR
7016                             ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
7017                              val);
7018                 }
7019                 retval = -DWC_E_INVALID;
7020                 val = 0;
7021         }
7022         core_if->core_params->ic_usb_cap = val;
7023         return retval;
7024 }
7025
7026 int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t *core_if)
7027 {
7028         return core_if->core_params->ic_usb_cap;
7029 }
7030
7031 int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t *core_if, int32_t val)
7032 {
7033         int retval = 0;
7034         int valid = 1;
7035
7036         if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
7037                 DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
7038                 DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
7039                 return -DWC_E_INVALID;
7040         }
7041
7042         if (val
7043             && (core_if->snpsid < OTG_CORE_REV_2_81a
7044                 || !dwc_otg_get_param_thr_ctl(core_if))) {
7045                 valid = 0;
7046         } else if (val
7047                    && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
7048                        4)) {
7049                 valid = 0;
7050         }
7051         if (valid == 0) {
7052                 if (dwc_otg_param_initialized
7053                     (core_if->core_params->ahb_thr_ratio)) {
7054                         DWC_ERROR
7055                             ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
7056                              val);
7057                 }
7058                 retval = -DWC_E_INVALID;
7059                 val = 0;
7060         }
7061
7062         core_if->core_params->ahb_thr_ratio = val;
7063         return retval;
7064 }
7065
7066 int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t *core_if)
7067 {
7068         return core_if->core_params->ahb_thr_ratio;
7069 }
7070
7071 int dwc_otg_set_param_power_down(dwc_otg_core_if_t *core_if, int32_t val)
7072 {
7073         int retval = 0;
7074         int valid = 1;
7075         hwcfg4_data_t hwcfg4 = {.d32 = 0 };
7076         hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
7077
7078         if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
7079                 DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
7080                 DWC_WARN("power_down must be 0 - 2\n");
7081                 return -DWC_E_INVALID;
7082         }
7083
7084         if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
7085                 valid = 0;
7086         }
7087         if ((val == 3)
7088             && ((core_if->snpsid < OTG_CORE_REV_3_00a)
7089                 || (hwcfg4.b.xhiber == 0))) {
7090                 valid = 0;
7091         }
7092         if (valid == 0) {
7093                 if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
7094                         DWC_ERROR
7095                             ("%d invalid for parameter power_down. Check HW configuration.\n",
7096                              val);
7097                 }
7098                 retval = -DWC_E_INVALID;
7099                 val = 0;
7100         }
7101         core_if->core_params->power_down = val;
7102         return retval;
7103 }
7104
7105 int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t *core_if)
7106 {
7107         return core_if->core_params->power_down;
7108 }
7109
7110 int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t *core_if, int32_t val)
7111 {
7112         int retval = 0;
7113         int valid = 1;
7114
7115         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7116                 DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
7117                 DWC_WARN("reload_ctl must be 0 or 1\n");
7118                 return -DWC_E_INVALID;
7119         }
7120
7121         if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
7122                 valid = 0;
7123         }
7124         if (valid == 0) {
7125                 if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
7126                         DWC_ERROR("%d invalid for parameter reload_ctl."
7127                                   "Check HW configuration.\n", val);
7128                 }
7129                 retval = -DWC_E_INVALID;
7130                 val = 0;
7131         }
7132         core_if->core_params->reload_ctl = val;
7133         return retval;
7134 }
7135
7136 int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t *core_if)
7137 {
7138         return core_if->core_params->reload_ctl;
7139 }
7140
7141 int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t *core_if, int32_t val)
7142 {
7143         int retval = 0;
7144         int valid = 1;
7145
7146         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7147                 DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
7148                 DWC_WARN("dev_out_nak must be 0 or 1\n");
7149                 return -DWC_E_INVALID;
7150         }
7151
7152         if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
7153                            !(core_if->core_params->dma_desc_enable))) {
7154                 valid = 0;
7155         }
7156         if (valid == 0) {
7157                 if (dwc_otg_param_initialized
7158                     (core_if->core_params->dev_out_nak)) {
7159                         DWC_ERROR("%d invalid for parameter dev_out_nak."
7160                                   "Check HW configuration.\n", val);
7161                 }
7162                 retval = -DWC_E_INVALID;
7163                 val = 0;
7164         }
7165         core_if->core_params->dev_out_nak = val;
7166         return retval;
7167 }
7168
7169 int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t *core_if)
7170 {
7171         return core_if->core_params->dev_out_nak;
7172 }
7173
7174 int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t *core_if, int32_t val)
7175 {
7176         int retval = 0;
7177         int valid = 1;
7178
7179         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7180                 DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
7181                 DWC_WARN("cont_on_bna must be 0 or 1\n");
7182                 return -DWC_E_INVALID;
7183         }
7184
7185         if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
7186                            !(core_if->core_params->dma_desc_enable))) {
7187                 valid = 0;
7188         }
7189         if (valid == 0) {
7190                 if (dwc_otg_param_initialized
7191                     (core_if->core_params->cont_on_bna)) {
7192                         DWC_ERROR("%d invalid for parameter cont_on_bna."
7193                                   "Check HW configuration.\n", val);
7194                 }
7195                 retval = -DWC_E_INVALID;
7196                 val = 0;
7197         }
7198         core_if->core_params->cont_on_bna = val;
7199         return retval;
7200 }
7201
7202 int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t *core_if)
7203 {
7204         return core_if->core_params->cont_on_bna;
7205 }
7206
7207 int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t *core_if, int32_t val)
7208 {
7209         int retval = 0;
7210         int valid = 1;
7211
7212         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7213                 DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
7214                 DWC_WARN("ahb_single must be 0 or 1\n");
7215                 return -DWC_E_INVALID;
7216         }
7217
7218         if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
7219                 valid = 0;
7220         }
7221         if (valid == 0) {
7222                 if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
7223                         DWC_ERROR("%d invalid for parameter ahb_single."
7224                                   "Check HW configuration.\n", val);
7225                 }
7226                 retval = -DWC_E_INVALID;
7227                 val = 0;
7228         }
7229         core_if->core_params->ahb_single = val;
7230         return retval;
7231 }
7232
7233 int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t *core_if)
7234 {
7235         return core_if->core_params->ahb_single;
7236 }
7237
7238 int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t *core_if, int32_t val)
7239 {
7240         int retval = 0;
7241
7242         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7243                 DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
7244                 DWC_WARN
7245                     ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
7246                 return -DWC_E_INVALID;
7247         }
7248
7249         core_if->core_params->otg_ver = val;
7250         return retval;
7251 }
7252
7253 int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t *core_if)
7254 {
7255         return core_if->core_params->otg_ver;
7256 }
7257
7258 uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t *core_if)
7259 {
7260         gotgctl_data_t otgctl;
7261         otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
7262         return otgctl.b.hstnegscs;
7263 }
7264
7265 uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t *core_if)
7266 {
7267         gotgctl_data_t otgctl;
7268         otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
7269         return otgctl.b.sesreqscs;
7270 }
7271
7272 void dwc_otg_set_hnpreq(dwc_otg_core_if_t *core_if, uint32_t val)
7273 {
7274         if (core_if->otg_ver == 0) {
7275                 gotgctl_data_t otgctl;
7276                 otgctl.d32 =
7277                     DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
7278                 otgctl.b.hnpreq = val;
7279                 DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl,
7280                                 otgctl.d32);
7281         } else {
7282                 core_if->otg_sts = val;
7283         }
7284 }
7285
7286 uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t *core_if)
7287 {
7288         return core_if->snpsid;
7289 }
7290
7291 uint32_t dwc_otg_get_mode(dwc_otg_core_if_t *core_if)
7292 {
7293         gintsts_data_t gintsts;
7294         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
7295         return gintsts.b.curmode;
7296 }
7297
7298 uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t *core_if)
7299 {
7300         gusbcfg_data_t usbcfg;
7301         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7302         return usbcfg.b.hnpcap;
7303 }
7304
7305 void dwc_otg_set_hnpcapable(dwc_otg_core_if_t *core_if, uint32_t val)
7306 {
7307         gusbcfg_data_t usbcfg;
7308         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7309         usbcfg.b.hnpcap = val;
7310         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
7311 }
7312
7313 uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t *core_if)
7314 {
7315         gusbcfg_data_t usbcfg;
7316         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7317         return usbcfg.b.srpcap;
7318 }
7319
7320 void dwc_otg_set_srpcapable(dwc_otg_core_if_t *core_if, uint32_t val)
7321 {
7322         gusbcfg_data_t usbcfg;
7323         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7324         usbcfg.b.srpcap = val;
7325         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
7326 }
7327
7328 uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t *core_if)
7329 {
7330         dcfg_data_t dcfg;
7331         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
7332         return dcfg.b.devspd;
7333 }
7334
7335 void dwc_otg_set_devspeed(dwc_otg_core_if_t *core_if, uint32_t val)
7336 {
7337         dcfg_data_t dcfg;
7338         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
7339         dcfg.b.devspd = val;
7340         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
7341 }
7342
7343 uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t *core_if)
7344 {
7345         hprt0_data_t hprt0;
7346         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
7347         return hprt0.b.prtconnsts;
7348 }
7349
7350 uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t *core_if)
7351 {
7352         dsts_data_t dsts;
7353         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
7354         return dsts.b.enumspd;
7355 }
7356
7357 uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t *core_if)
7358 {
7359         hprt0_data_t hprt0;
7360         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
7361         return hprt0.b.prtpwr;
7362
7363 }
7364
7365 uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t *core_if)
7366 {
7367         return core_if->hibernation_suspend;
7368 }
7369
7370 void dwc_otg_set_prtpower(dwc_otg_core_if_t *core_if, uint32_t val)
7371 {
7372         hprt0_data_t hprt0;
7373         hprt0.d32 = dwc_otg_read_hprt0(core_if);
7374         hprt0.b.prtpwr = val;
7375         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
7376 }
7377
7378 uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t *core_if)
7379 {
7380         hprt0_data_t hprt0;
7381         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
7382         return hprt0.b.prtsusp;
7383
7384 }
7385
7386 void dwc_otg_set_prtsuspend(dwc_otg_core_if_t *core_if, uint32_t val)
7387 {
7388         hprt0_data_t hprt0;
7389         hprt0.d32 = dwc_otg_read_hprt0(core_if);
7390         hprt0.b.prtsusp = val;
7391         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
7392 }
7393
7394 uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t *core_if)
7395 {
7396         hfir_data_t hfir;
7397         hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
7398         return hfir.b.frint;
7399
7400 }
7401
7402 void dwc_otg_set_fr_interval(dwc_otg_core_if_t *core_if, uint32_t val)
7403 {
7404         hfir_data_t hfir;
7405         uint32_t fram_int;
7406         fram_int = calc_frame_interval(core_if);
7407         hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
7408         if (!core_if->core_params->reload_ctl) {
7409                 DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
7410                          "not set to 1.\nShould load driver with reload_ctl=1"
7411                          " module parameter\n");
7412                 return;
7413         }
7414         switch (fram_int) {
7415         case 3750:
7416                 if ((val < 3350) || (val > 4150)) {
7417                         DWC_WARN("HFIR interval for HS core and 30 MHz"
7418                                  "clock freq should be from 3350 to 4150\n");
7419                         return;
7420                 }
7421                 break;
7422         case 30000:
7423                 if ((val < 26820) || (val > 33180)) {
7424                         DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
7425                                  "clock freq should be from 26820 to 33180\n");
7426                         return;
7427                 }
7428                 break;
7429         case 6000:
7430                 if ((val < 5360) || (val > 6640)) {
7431                         DWC_WARN("HFIR interval for HS core and 48 MHz"
7432                                  "clock freq should be from 5360 to 6640\n");
7433                         return;
7434                 }
7435                 break;
7436         case 48000:
7437                 if ((val < 42912) || (val > 53088)) {
7438                         DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
7439                                  "clock freq should be from 42912 to 53088\n");
7440                         return;
7441                 }
7442                 break;
7443         case 7500:
7444                 if ((val < 6700) || (val > 8300)) {
7445                         DWC_WARN("HFIR interval for HS core and 60 MHz"
7446                                  "clock freq should be from 6700 to 8300\n");
7447                         return;
7448                 }
7449                 break;
7450         case 60000:
7451                 if ((val < 53640) || (val > 65536)) {
7452                         DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
7453                                  "clock freq should be from 53640 to 65536\n");
7454                         return;
7455                 }
7456                 break;
7457         default:
7458                 DWC_WARN("Unknown frame interval\n");
7459                 return;
7460                 break;
7461
7462         }
7463         hfir.b.frint = val;
7464         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
7465 }
7466
7467 uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t *core_if)
7468 {
7469         hcfg_data_t hcfg;
7470         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
7471         return hcfg.b.modechtimen;
7472
7473 }
7474
7475 void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t *core_if, uint32_t val)
7476 {
7477         hcfg_data_t hcfg;
7478         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
7479         hcfg.b.modechtimen = val;
7480         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
7481 }
7482
7483 void dwc_otg_set_prtresume(dwc_otg_core_if_t *core_if, uint32_t val)
7484 {
7485         hprt0_data_t hprt0;
7486         hprt0.d32 = dwc_otg_read_hprt0(core_if);
7487         hprt0.b.prtres = val;
7488         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
7489 }
7490
7491 uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t *core_if)
7492 {
7493         dctl_data_t dctl;
7494         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7495         return dctl.b.rmtwkupsig;
7496 }
7497
7498 uint32_t dwc_otg_get_beslreject(dwc_otg_core_if_t *core_if)
7499 {
7500         dctl_data_t dctl;
7501         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7502         return dctl.b.besl_reject;
7503 }
7504
7505 void dwc_otg_set_beslreject(dwc_otg_core_if_t *core_if, uint32_t val)
7506 {
7507         dctl_data_t dctl;
7508         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7509         dctl.b.besl_reject = val;
7510         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
7511 }
7512
7513 uint32_t dwc_otg_get_hirdthresh(dwc_otg_core_if_t *core_if)
7514 {
7515         glpmcfg_data_t lpmcfg;
7516         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7517         return lpmcfg.b.hird_thres;
7518 }
7519
7520 void dwc_otg_set_hirdthresh(dwc_otg_core_if_t *core_if, uint32_t val)
7521 {
7522         glpmcfg_data_t lpmcfg;
7523
7524         if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
7525                 DWC_WARN("Wrong valaue for hird_thres\n");
7526                 DWC_WARN("hird_thres must be 0-f\n");
7527                 return;
7528         }
7529
7530         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7531         lpmcfg.b.hird_thres |= val;
7532         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7533 }
7534
7535 uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t *core_if)
7536 {
7537         glpmcfg_data_t lpmcfg;
7538         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7539
7540         DWC_ASSERT(!
7541                    ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
7542                    "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
7543                    core_if->lx_state, lpmcfg.b.prt_sleep_sts);
7544
7545         return lpmcfg.b.prt_sleep_sts;
7546 }
7547
7548 uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t *core_if)
7549 {
7550         glpmcfg_data_t lpmcfg;
7551         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7552         return lpmcfg.b.rem_wkup_en;
7553 }
7554
7555 uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t *core_if)
7556 {
7557         glpmcfg_data_t lpmcfg;
7558         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7559         return lpmcfg.b.appl_resp;
7560 }
7561
7562 void dwc_otg_set_lpmresponse(dwc_otg_core_if_t *core_if, uint32_t val)
7563 {
7564         glpmcfg_data_t lpmcfg;
7565         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7566         lpmcfg.b.appl_resp = val;
7567         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7568 }
7569
7570 uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t *core_if)
7571 {
7572         glpmcfg_data_t lpmcfg;
7573         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7574         return lpmcfg.b.hsic_connect;
7575 }
7576
7577 void dwc_otg_set_hsic_connect(dwc_otg_core_if_t *core_if, uint32_t val)
7578 {
7579         glpmcfg_data_t lpmcfg;
7580         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7581         lpmcfg.b.hsic_connect = val;
7582         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7583 }
7584
7585 uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t *core_if)
7586 {
7587         glpmcfg_data_t lpmcfg;
7588         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7589         return lpmcfg.b.inv_sel_hsic;
7590
7591 }
7592
7593 void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t *core_if, uint32_t val)
7594 {
7595         glpmcfg_data_t lpmcfg;
7596         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7597         lpmcfg.b.inv_sel_hsic = val;
7598         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7599 }
7600
7601 uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t *core_if)
7602 {
7603         return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
7604 }
7605
7606 void dwc_otg_set_gotgctl(dwc_otg_core_if_t *core_if, uint32_t val)
7607 {
7608         DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
7609 }
7610
7611 uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t *core_if)
7612 {
7613         return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7614 }
7615
7616 void dwc_otg_set_gusbcfg(dwc_otg_core_if_t *core_if, uint32_t val)
7617 {
7618         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
7619 }
7620
7621 uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t *core_if)
7622 {
7623         return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
7624 }
7625
7626 void dwc_otg_set_grxfsiz(dwc_otg_core_if_t *core_if, uint32_t val)
7627 {
7628         DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
7629 }
7630
7631 uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t *core_if)
7632 {
7633         return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
7634 }
7635
7636 void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t *core_if, uint32_t val)
7637 {
7638         DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
7639 }
7640
7641 uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t *core_if)
7642 {
7643         return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
7644 }
7645
7646 void dwc_otg_set_gpvndctl(dwc_otg_core_if_t *core_if, uint32_t val)
7647 {
7648         DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
7649 }
7650
7651 uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t *core_if)
7652 {
7653         return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
7654 }
7655
7656 void dwc_otg_set_ggpio(dwc_otg_core_if_t *core_if, uint32_t val)
7657 {
7658         DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
7659 }
7660
7661 uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t *core_if)
7662 {
7663         return DWC_READ_REG32(core_if->host_if->hprt0);
7664
7665 }
7666
7667 void dwc_otg_set_hprt0(dwc_otg_core_if_t *core_if, uint32_t val)
7668 {
7669         DWC_WRITE_REG32(core_if->host_if->hprt0, val);
7670 }
7671
7672 uint32_t dwc_otg_get_guid(dwc_otg_core_if_t *core_if)
7673 {
7674         return DWC_READ_REG32(&core_if->core_global_regs->guid);
7675 }
7676
7677 void dwc_otg_set_guid(dwc_otg_core_if_t *core_if, uint32_t val)
7678 {
7679         DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
7680 }
7681
7682 uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t *core_if)
7683 {
7684         return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
7685 }
7686
7687 uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t *core_if)
7688 {
7689         return ((core_if->otg_ver ==
7690                  1) ? (uint16_t) 0x0200 : (uint16_t) 0x0103);
7691 }
7692
7693 /**
7694  * Start the SRP timer to detect when the SRP does not complete within
7695  * 6 seconds.
7696  *
7697  * @param core_if the pointer to core_if strucure.
7698  */
7699 void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t *core_if)
7700 {
7701         core_if->srp_timer_started = 1;
7702         DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */);
7703 }
7704
7705 void dwc_otg_initiate_srp(void *p)
7706 {
7707         dwc_otg_core_if_t *core_if = p;
7708         uint32_t *addr = (uint32_t *)&(core_if->core_global_regs->gotgctl);
7709         gotgctl_data_t mem;
7710         gotgctl_data_t val;
7711
7712         val.d32 = DWC_READ_REG32(addr);
7713         if (val.b.sesreq) {
7714                 DWC_ERROR("Session Request Already active!\n");
7715                 return;
7716         }
7717
7718         DWC_INFO("Session Request Initated\n");
7719         mem.d32 = DWC_READ_REG32(addr);
7720         mem.b.sesreq = 1;
7721         DWC_WRITE_REG32(addr, mem.d32);
7722
7723         /* Start the SRP timer */
7724         dwc_otg_pcd_start_srp_timer(core_if);
7725         return;
7726 }
7727
7728 int dwc_otg_check_haps_status(dwc_otg_core_if_t *core_if)
7729 {
7730         int retval = 0;
7731
7732         if (DWC_READ_REG32(&core_if->core_global_regs->gsnpsid) == 0xffffffff) {
7733                 return -1;
7734         } else {
7735                 return retval;
7736         }
7737
7738 }
7739
7740 void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode)
7741 {
7742         gusbcfg_data_t usbcfg = {.d32 = 0 };
7743
7744         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7745         switch (mode) {
7746         case USB_MODE_FORCE_HOST:
7747                 usbcfg.b.force_host_mode = 1;
7748                 usbcfg.b.force_dev_mode = 0;
7749                 break;
7750         case USB_MODE_FORCE_DEVICE:
7751                 usbcfg.b.force_host_mode = 0;
7752                 usbcfg.b.force_dev_mode = 1;
7753                 break;
7754         case USB_MODE_NORMAL:
7755                 usbcfg.b.force_host_mode = 0;
7756                 usbcfg.b.force_dev_mode = 0;
7757                 break;
7758         }
7759         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
7760 }