drivers/usb/dwc_otg_310/dwc_otg_cil.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
   3  * $Revision: #198 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  *
  36  * The Core Interface Layer provides basic services for accessing and
  37  * managing the DWC_otg hardware. These services are used by both the
  38  * Host Controller Driver and the Peripheral Controller Driver.
  39  *
  40  * The CIL manages the memory map for the core so that the HCD and PCD
  41  * don't have to do this separately. It also handles basic tasks like
  42  * reading/writing the registers and data FIFOs in the controller.
  43  * Some of the data access functions provide encapsulation of several
  44  * operations required to perform a task, such as writing multiple
  45  * registers to start a transfer. Finally, the CIL performs basic
  46  * services that are not specific to either the host or device modes
  47  * of operation. These services include management of the OTG Host
  48  * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
  49  * Diagnostic API is also provided to allow testing of the controller
  50  * hardware.
  51  *
  52  * The Core Interface Layer has the following requirements:
  53  * - Provides basic controller operations.
  54  * - Minimal use of OS services.
  55  * - The OS services used will be abstracted by using inline functions
  56  *       or macros.
  57  *
  58  */
  59
  60 #include "common_port/dwc_os.h"
  61 #include "dwc_otg_regs.h"
  62 #include "dwc_otg_cil.h"
  63 #include "dwc_otg_driver.h"
  64 #include "usbdev_rk.h"
  65 #include "dwc_otg_hcd.h"
  66
  67 static int dwc_otg_setup_params(dwc_otg_core_if_t *core_if);
  68
  69 /**
  70  * This function is called to initialize the DWC_otg CSR data
  71  * structures. The register addresses in the device and host
  72  * structures are initialized from the base address supplied by the
  73  * caller. The calling function must make the OS calls to get the
  74  * base address of the DWC_otg controller registers. The core_params
  75  * argument holds the parameters that specify how the core should be
  76  * configured.
  77  *
  78  * @param reg_base_addr Base address of DWC_otg core registers
  79  *
  80  */
  81 dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *reg_base_addr)
  82 {
  83         dwc_otg_core_if_t *core_if = 0;
  84         dwc_otg_dev_if_t *dev_if = 0;
  85         dwc_otg_host_if_t *host_if = 0;
  86         uint8_t *reg_base = (uint8_t *) reg_base_addr;
  87         int i = 0;
  88
  89         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
  90
  91         core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
  92
  93         if (core_if == NULL) {
  94                 DWC_DEBUGPL(DBG_CIL,
  95                             "Allocation of dwc_otg_core_if_t failed\n");
  96                 return 0;
  97         }
  98         core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
  99
 100         /*
 101          * Allocate the Device Mode structures.
 102          */
 103         dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
 104
 105         if (dev_if == NULL) {
 106                 DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
 107                 DWC_FREE(core_if);
 108                 return 0;
 109         }
 110
 111         dev_if->dev_global_regs =
 112             (dwc_otg_device_global_regs_t *) (reg_base +
 113                                               DWC_DEV_GLOBAL_REG_OFFSET);
 114
 115         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 116                 dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
 117                     (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
 118                      (i * DWC_EP_REG_OFFSET));
 119
 120                 dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
 121                     (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
 122                      (i * DWC_EP_REG_OFFSET));
 123                 DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
 124                             i, &dev_if->in_ep_regs[i]->diepctl);
 125                 DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
 126                             i, &dev_if->out_ep_regs[i]->doepctl);
 127         }
 128
 129         dev_if->speed = 0;      /* unknown */
 130
 131         core_if->dev_if = dev_if;
 132
 133         /*
 134          * Allocate the Host Mode structures.
 135          */
 136         host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
 137
 138         if (host_if == NULL) {
 139                 DWC_DEBUGPL(DBG_CIL,
 140                             "Allocation of dwc_otg_host_if_t failed\n");
 141                 DWC_FREE(dev_if);
 142                 DWC_FREE(core_if);
 143                 return 0;
 144         }
 145
 146         host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
 147             (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
 148
 149         host_if->hprt0 =
 150             (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
 151
 152         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 153                 host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
 154                     (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
 155                      (i * DWC_OTG_CHAN_REGS_OFFSET));
 156                 DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
 157                             i, &host_if->hc_regs[i]->hcchar);
 158         }
 159
 160         host_if->num_host_channels = MAX_EPS_CHANNELS;
 161         core_if->host_if = host_if;
 162
 163         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 164                 core_if->data_fifo[i] =
 165                     (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
 166                                   (i * DWC_OTG_DATA_FIFO_SIZE));
 167                 DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
 168                             i, (unsigned long)core_if->data_fifo[i]);
 169         }
 170
 171         core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
 172
 173         /* Initiate lx_state to L3 disconnected state */
 174         core_if->lx_state = DWC_OTG_L3;
 175         /*
 176          * Store the contents of the hardware configuration registers here for
 177          * easy access later.
 178          */
 179         core_if->hwcfg1.d32 =
 180             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
 181         core_if->hwcfg2.d32 =
 182             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
 183         core_if->hwcfg3.d32 =
 184             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
 185         core_if->hwcfg4.d32 =
 186             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
 187
 188         /* do not get HPTXFSIZ here, it's unused.
 189          * set global_regs->hptxfsiz in dwc_otg_core_host_init.
 190          * for 3.10a version, host20 FIFO can't be configed,
 191          * because host20 hwcfg2.b.dynamic_fifo = 0.
 192          */
 193 #if 0
 194         /* Force host mode to get HPTXFSIZ exact power on value */
 195         {
 196                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
 197                 gusbcfg.d32 =
 198                     DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
 199                 gusbcfg.b.force_host_mode = 1;
 200                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
 201                                 gusbcfg.d32);
 202                 dwc_mdelay(100);
 203                 core_if->hptxfsiz.d32 =
 204                     DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
 205                 gusbcfg.d32 =
 206                     DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
 207                 gusbcfg.b.force_host_mode = 0;
 208                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
 209                                 gusbcfg.d32);
 210                 dwc_mdelay(100);
 211         }
 212 #endif
 213
 214         DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
 215         DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
 216         DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
 217         DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
 218
 219         core_if->hcfg.d32 =
 220             DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
 221         core_if->dcfg.d32 =
 222             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
 223
 224         DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
 225         DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
 226
 227         DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
 228         DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
 229         DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
 230         DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
 231                     core_if->hwcfg2.b.num_host_chan);
 232         DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
 233                     core_if->hwcfg2.b.nonperio_tx_q_depth);
 234         DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
 235                     core_if->hwcfg2.b.host_perio_tx_q_depth);
 236         DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
 237                     core_if->hwcfg2.b.dev_token_q_depth);
 238
 239         DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
 240                     core_if->hwcfg3.b.dfifo_depth);
 241         DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
 242                     core_if->hwcfg3.b.xfer_size_cntr_width);
 243
 244         /*
 245          * Set the SRP sucess bit for FS-I2c
 246          */
 247         core_if->srp_success = 0;
 248         core_if->srp_timer_started = 0;
 249
 250         /*
 251          * Create new workqueue and init works
 252          */
 253         core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
 254         if (core_if->wq_otg == 0) {
 255                 DWC_WARN("DWC_WORKQ_ALLOC failed\n");
 256                 DWC_FREE(host_if);
 257                 DWC_FREE(dev_if);
 258                 DWC_FREE(core_if);
 259                 return 0;
 260         }
 261
 262         core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
 263         DWC_PRINTF("%p\n", &core_if->core_global_regs->gsnpsid);
 264         DWC_PRINTF("Core Release: %x.%x%x%x\n",
 265                    (core_if->snpsid >> 12 & 0xF),
 266                    (core_if->snpsid >> 8 & 0xF),
 267                    (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
 268
 269         core_if->wkp_tasklet =
 270             DWC_TASK_ALLOC("wkp_tasklet", w_wakeup_detected, core_if);
 271
 272         if (dwc_otg_setup_params(core_if))
 273                 DWC_WARN("Error while setting core params\n");
 274
 275         core_if->hibernation_suspend = 0;
 276         if (core_if->otg_ver)
 277                 core_if->test_mode = 0;
 278
 279         /** ADP initialization */
 280         dwc_otg_adp_init(core_if);
 281
 282         return core_if;
 283 }
 284
 285 /**
 286  * This function frees the structures allocated by dwc_otg_cil_init().
 287  *
 288  * @param core_if The core interface pointer returned from
 289  * dwc_otg_cil_init().
 290  *
 291  */
 292 void dwc_otg_cil_remove(dwc_otg_core_if_t *core_if)
 293 {
 294         dctl_data_t dctl = {.d32 = 0 };
 295         /* Disable all interrupts */
 296         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
 297         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
 298
 299         dctl.b.sftdiscon = 1;
 300         if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
 301                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
 302                                  dctl.d32);
 303         }
 304
 305         if (core_if->wq_otg) {
 306                 DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
 307                 DWC_WORKQ_FREE(core_if->wq_otg);
 308         }
 309         if (core_if->dev_if)
 310                 DWC_FREE(core_if->dev_if);
 311         if (core_if->host_if)
 312                 DWC_FREE(core_if->host_if);
 313
 314         /** Remove ADP Stuff  */
 315         dwc_otg_adp_remove(core_if);
 316         if (core_if->core_params)
 317                 DWC_FREE(core_if->core_params);
 318         if (core_if->wkp_tasklet)
 319                 DWC_TASK_FREE(core_if->wkp_tasklet);
 320         if (core_if->srp_timer)
 321                 DWC_TIMER_FREE(core_if->srp_timer);
 322
 323         DWC_FREE(core_if);
 324 }
 325
 326 /**
 327  * This function enables the controller's Global Interrupt in the AHB Config
 328  * register.
 329  *
 330  * @param core_if Programming view of DWC_otg controller.
 331  */
 332 void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t *core_if)
 333 {
 334         gahbcfg_data_t ahbcfg = {.d32 = 0 };
 335         ahbcfg.b.glblintrmsk = 1;       /* Enable interrupts */
 336         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
 337 }
 338
 339 /**
 340  * This function disables the controller's Global Interrupt in the AHB Config
 341  * register.
 342  *
 343  * @param core_if Programming view of DWC_otg controller.
 344  */
 345 void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t *core_if)
 346 {
 347         gahbcfg_data_t ahbcfg = {.d32 = 0 };
 348         ahbcfg.b.glblintrmsk = 1;       /* Disable interrupts */
 349         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
 350 }
 351
 352 /**
 353  * This function initializes the commmon interrupts, used in both
 354  * device and host modes.
 355  *
 356  * @param core_if Programming view of the DWC_otg controller
 357  *
 358  */
 359 static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *core_if)
 360 {
 361         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
 362         gintmsk_data_t intr_mask = {.d32 = 0 };
 363
 364         /* Clear any pending OTG Interrupts */
 365         DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
 366
 367         /* Clear any pending interrupts */
 368         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
 369
 370         /*
 371          * Enable the interrupts in the GINTMSK.
 372          */
 373         intr_mask.b.modemismatch = 1;
 374         intr_mask.b.otgintr = 1;
 375
 376         if (!core_if->dma_enable) {
 377                 intr_mask.b.rxstsqlvl = 1;
 378         }
 379
 380         intr_mask.b.conidstschng = 1;
 381         intr_mask.b.wkupintr = 1;
 382         intr_mask.b.disconnect = 0;
 383         intr_mask.b.usbsuspend = 1;
 384         /* intr_mask.b.sessreqintr = 1; */
 385 #ifdef CONFIG_USB_DWC_OTG_LPM
 386         if (core_if->core_params->lpm_enable)
 387                 intr_mask.b.lpmtranrcvd = 1;
 388 #endif
 389         DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
 390 }
 391
 392 /*
 393  * The restore operation is modified to support Synopsys Emulated Powerdown and
 394  * Hibernation. This function is for exiting from Device mode hibernation by
 395  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
 396  * @param core_if Programming view of DWC_otg controller.
 397  * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
 398  * @param reset - indicates whether resume is initiated by Reset.
 399  */
 400 int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t *core_if,
 401                                        int rem_wakeup, int reset)
 402 {
 403         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 404         pcgcctl_data_t pcgcctl = {.d32 = 0 };
 405         dctl_data_t dctl = {.d32 = 0 };
 406
 407         int timeout = 2000;
 408
 409         if (!core_if->hibernation_suspend) {
 410                 DWC_PRINTF("Already exited from Hibernation\n");
 411                 return 1;
 412         }
 413
 414         DWC_DEBUGPL(DBG_PCD, "%s called\n", __func__);
 415         /* Switch-on voltage to the core */
 416         gpwrdn.b.pwrdnswtch = 1;
 417         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 418         dwc_udelay(10);
 419
 420         /* Reset core */
 421         gpwrdn.d32 = 0;
 422         gpwrdn.b.pwrdnrstn = 1;
 423         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 424         dwc_udelay(10);
 425
 426         /* Assert Restore signal */
 427         gpwrdn.d32 = 0;
 428         gpwrdn.b.restore = 1;
 429         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 430         dwc_udelay(10);
 431
 432         /* Disable power clamps */
 433         gpwrdn.d32 = 0;
 434         gpwrdn.b.pwrdnclmp = 1;
 435         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 436
 437         if (rem_wakeup)
 438                 dwc_udelay(70);
 439
 440         /* Deassert Reset core */
 441         gpwrdn.d32 = 0;
 442         gpwrdn.b.pwrdnrstn = 1;
 443         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 444         dwc_udelay(10);
 445
 446         /* Disable PMU interrupt */
 447         gpwrdn.d32 = 0;
 448         gpwrdn.b.pmuintsel = 1;
 449         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 450
 451         /* Mask interrupts from gpwrdn */
 452         gpwrdn.d32 = 0;
 453         gpwrdn.b.connect_det_msk = 1;
 454         gpwrdn.b.srp_det_msk = 1;
 455         gpwrdn.b.disconn_det_msk = 1;
 456         gpwrdn.b.rst_det_msk = 1;
 457         gpwrdn.b.lnstchng_msk = 1;
 458         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 459
 460         /* Indicates that we are going out from hibernation */
 461         core_if->hibernation_suspend = 0;
 462
 463         /*
 464          * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
 465          * indicates restore from remote_wakeup
 466          */
 467         restore_essential_regs(core_if, rem_wakeup, 0);
 468
 469         /*
 470          * Wait a little for seeing new value of variable hibernation_suspend if
 471          * Restore done interrupt received before polling
 472          */
 473         dwc_udelay(10);
 474
 475         if (core_if->hibernation_suspend == 0) {
 476                 /*
 477                  * Wait For Restore_done Interrupt. This mechanism of polling the
 478                  * interrupt is introduced to avoid any possible race conditions
 479                  */
 480                 do {
 481                         gintsts_data_t gintsts;
 482                         gintsts.d32 =
 483                             DWC_READ_REG32(&core_if->core_global_regs->gintsts);
 484                         if (gintsts.b.restoredone) {
 485                                 gintsts.d32 = 0;
 486                                 gintsts.b.restoredone = 1;
 487                                 DWC_WRITE_REG32(&core_if->
 488                                                 core_global_regs->gintsts,
 489                                                 gintsts.d32);
 490                                 DWC_PRINTF("Restore Done Interrupt seen\n");
 491                                 break;
 492                         }
 493                         dwc_udelay(10);
 494                 } while (--timeout);
 495                 if (!timeout) {
 496                         DWC_PRINTF
 497                             ("Restore Done interrupt wasn't generated here\n");
 498                 }
 499         }
 500         /* Clear all pending interupts */
 501         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 502
 503         /* De-assert Restore */
 504         gpwrdn.d32 = 0;
 505         gpwrdn.b.restore = 1;
 506         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 507         dwc_udelay(10);
 508
 509         if (!rem_wakeup) {
 510                 pcgcctl.d32 = 0;
 511                 pcgcctl.b.rstpdwnmodule = 1;
 512                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
 513         }
 514
 515         /* Restore GUSBCFG and DCFG */
 516         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
 517                         core_if->gr_backup->gusbcfg_local);
 518         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
 519                         core_if->dr_backup->dcfg);
 520
 521         /* De-assert Wakeup Logic */
 522         gpwrdn.d32 = 0;
 523         gpwrdn.b.pmuactv = 1;
 524         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 525         dwc_udelay(10);
 526
 527         if (!rem_wakeup) {
 528                 /* Set Device programming done bit */
 529                 dctl.b.pwronprgdone = 1;
 530                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
 531                                  dctl.d32);
 532         } else {
 533                 /* Start Remote Wakeup Signaling */
 534                 dctl.d32 = core_if->dr_backup->dctl;
 535                 dctl.b.rmtwkupsig = 1;
 536                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
 537                                 dctl.d32);
 538         }
 539
 540         dwc_mdelay(2);
 541         /* Clear all pending interupts */
 542         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 543
 544         /* Restore global registers */
 545         dwc_otg_restore_global_regs(core_if);
 546         /* Restore device global registers */
 547         dwc_otg_restore_dev_regs(core_if, rem_wakeup);
 548
 549         if (rem_wakeup) {
 550                 dwc_mdelay(7);
 551                 dctl.d32 = 0;
 552                 dctl.b.rmtwkupsig = 1;
 553                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
 554                                  dctl.d32, 0);
 555         }
 556
 557         core_if->hibernation_suspend = 0;
 558         /* The core will be in ON STATE */
 559         core_if->lx_state = DWC_OTG_L0;
 560         DWC_PRINTF("Hibernation recovery completes here\n");
 561
 562         return 1;
 563 }
 564
 565 /*
 566  * The restore operation is modified to support Synopsys Emulated Powerdown and
 567  * Hibernation. This function is for exiting from Host mode hibernation by
 568  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
 569  * @param core_if Programming view of DWC_otg controller.
 570  * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
 571  * @param reset - indicates whether resume is initiated by Reset.
 572  */
 573 int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t *core_if,
 574                                      int rem_wakeup, int reset)
 575 {
 576         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 577         hprt0_data_t hprt0 = {.d32 = 0 };
 578
 579         int timeout = 2000;
 580
 581         DWC_DEBUGPL(DBG_HCD, "%s called\n", __func__);
 582         /* Switch-on voltage to the core */
 583         gpwrdn.b.pwrdnswtch = 1;
 584         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 585         dwc_udelay(10);
 586
 587         /* Reset core */
 588         gpwrdn.d32 = 0;
 589         gpwrdn.b.pwrdnrstn = 1;
 590         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 591         dwc_udelay(10);
 592
 593         /* Assert Restore signal */
 594         gpwrdn.d32 = 0;
 595         gpwrdn.b.restore = 1;
 596         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 597         dwc_udelay(10);
 598
 599         /* Disable power clamps */
 600         gpwrdn.d32 = 0;
 601         gpwrdn.b.pwrdnclmp = 1;
 602         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 603
 604         if (!rem_wakeup)
 605                 dwc_udelay(50);
 606
 607         /* Deassert Reset core */
 608         gpwrdn.d32 = 0;
 609         gpwrdn.b.pwrdnrstn = 1;
 610         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 611         dwc_udelay(10);
 612
 613         /* Disable PMU interrupt */
 614         gpwrdn.d32 = 0;
 615         gpwrdn.b.pmuintsel = 1;
 616         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 617
 618         gpwrdn.d32 = 0;
 619         gpwrdn.b.connect_det_msk = 1;
 620         gpwrdn.b.srp_det_msk = 1;
 621         gpwrdn.b.disconn_det_msk = 1;
 622         gpwrdn.b.rst_det_msk = 1;
 623         gpwrdn.b.lnstchng_msk = 1;
 624         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 625
 626         /* Indicates that we are going out from hibernation */
 627         core_if->hibernation_suspend = 0;
 628
 629         /* Set Restore Essential Regs bit in PCGCCTL register */
 630         restore_essential_regs(core_if, rem_wakeup, 1);
 631
 632         /* Wait a little for seeing new value of variable hibernation_suspend if
 633          * Restore done interrupt received before polling */
 634         dwc_udelay(10);
 635
 636         if (core_if->hibernation_suspend == 0) {
 637                 /* Wait For Restore_done Interrupt. This mechanism of polling the
 638                  * interrupt is introduced to avoid any possible race conditions
 639                  */
 640                 do {
 641                         gintsts_data_t gintsts;
 642                         gintsts.d32 =
 643                             DWC_READ_REG32(&core_if->core_global_regs->gintsts);
 644                         if (gintsts.b.restoredone) {
 645                                 gintsts.d32 = 0;
 646                                 gintsts.b.restoredone = 1;
 647                                 DWC_WRITE_REG32(&core_if->core_global_regs->
 648                                                 gintsts, gintsts.d32);
 649                                 DWC_DEBUGPL(DBG_HCD,
 650                                             "Restore Done Interrupt seen\n");
 651                                 break;
 652                         }
 653                         dwc_udelay(10);
 654                 } while (--timeout);
 655                 if (!timeout)
 656                         DWC_WARN("Restore Done interrupt wasn't generated\n");
 657         }
 658
 659         /* Set the flag's value to 0 again after
 660          * receiving restore done interrupt */
 661         core_if->hibernation_suspend = 0;
 662
 663         /* This step is not described in functional spec but if not wait for this
 664          * delay, mismatch interrupts occurred because just after restore core is
 665          * in Device mode(gintsts.curmode == 0) */
 666         dwc_mdelay(100);
 667
 668         /* Clear all pending interrupts */
 669         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 670
 671         /* De-assert Restore */
 672         gpwrdn.d32 = 0;
 673         gpwrdn.b.restore = 1;
 674         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 675         dwc_udelay(10);
 676
 677         /* Restore GUSBCFG and HCFG */
 678         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
 679                         core_if->gr_backup->gusbcfg_local);
 680         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
 681                         core_if->hr_backup->hcfg_local);
 682
 683         /* De-assert Wakeup Logic */
 684         gpwrdn.d32 = 0;
 685         gpwrdn.b.pmuactv = 1;
 686         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 687         dwc_udelay(10);
 688
 689         /* Start the Resume operation by programming HPRT0 */
 690         hprt0.d32 = core_if->hr_backup->hprt0_local;
 691         hprt0.b.prtpwr = 1;
 692         hprt0.b.prtena = 0;
 693         hprt0.b.prtsusp = 0;
 694         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 695
 696         DWC_PRINTF("Resume Starts Now\n");
 697         if (!reset) {
 698                 /* Indicates it is Resume Operation */
 699                 hprt0.d32 = core_if->hr_backup->hprt0_local;
 700                 hprt0.b.prtres = 1;
 701                 hprt0.b.prtpwr = 1;
 702                 hprt0.b.prtena = 0;
 703                 hprt0.b.prtsusp = 0;
 704                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 705
 706                 if (!rem_wakeup)
 707                         hprt0.b.prtres = 0;
 708                 /* Wait for Resume time and then program HPRT again */
 709                 dwc_mdelay(100);
 710                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 711
 712         } else {
 713                 /* Indicates it is Reset Operation */
 714                 hprt0.d32 = core_if->hr_backup->hprt0_local;
 715                 hprt0.b.prtrst = 1;
 716                 hprt0.b.prtpwr = 1;
 717                 hprt0.b.prtena = 0;
 718                 hprt0.b.prtsusp = 0;
 719                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 720                 /* Wait for Reset time and then program HPRT again */
 721                 dwc_mdelay(60);
 722                 hprt0.b.prtrst = 0;
 723                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 724         }
 725         /* Clear all interrupt status */
 726         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 727         hprt0.b.prtconndet = 1;
 728         hprt0.b.prtenchng = 1;
 729         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 730
 731         /* Clear all pending interupts */
 732         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 733
 734         /* Restore global registers */
 735         dwc_otg_restore_global_regs(core_if);
 736         /* Restore host global registers */
 737         dwc_otg_restore_host_regs(core_if, reset);
 738
 739         /* The core will be in ON STATE */
 740         core_if->lx_state = DWC_OTG_L0;
 741         DWC_PRINTF("Hibernation recovery is complete here\n");
 742         return 0;
 743 }
 744
 745 /** Saves some register values into system memory. */
 746 int dwc_otg_save_global_regs(dwc_otg_core_if_t *core_if)
 747 {
 748         struct dwc_otg_global_regs_backup *gr;
 749         int i;
 750
 751         gr = core_if->gr_backup;
 752         if (!gr) {
 753                 gr = DWC_ALLOC(sizeof(*gr));
 754                 if (!gr)
 755                         return -DWC_E_NO_MEMORY;
 756                 core_if->gr_backup = gr;
 757         }
 758
 759         gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
 760         gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
 761         gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
 762         gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
 763         gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
 764         gr->gnptxfsiz_local =
 765             DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
 766         gr->hptxfsiz_local =
 767             DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
 768 #ifdef CONFIG_USB_DWC_OTG_LPM
 769         gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
 770 #endif
 771         gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
 772         gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
 773         gr->gdfifocfg_local =
 774             DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
 775         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 776                 gr->dtxfsiz_local[i] =
 777                     DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
 778         }
 779
 780         DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
 781         DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl   = %08x\n", gr->gotgctl_local);
 782         DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
 783         DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg   = %08x\n", gr->gahbcfg_local);
 784         DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg   = %08x\n", gr->gusbcfg_local);
 785         DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz   = %08x\n", gr->grxfsiz_local);
 786         DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
 787                     gr->gnptxfsiz_local);
 788         DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz  = %08x\n",
 789                     gr->hptxfsiz_local);
 790 #ifdef CONFIG_USB_DWC_OTG_LPM
 791         DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg   = %08x\n", gr->glpmcfg_local);
 792 #endif
 793         DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl   = %08x\n", gr->gi2cctl_local);
 794         DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl   = %08x\n", gr->pcgcctl_local);
 795         DWC_DEBUGPL(DBG_ANY, "Backed up gdfifocfg   = %08x\n",
 796                     gr->gdfifocfg_local);
 797
 798         return 0;
 799 }
 800
 801 /** Saves GINTMSK register before setting the msk bits. */
 802 int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t *core_if)
 803 {
 804         struct dwc_otg_global_regs_backup *gr;
 805
 806         gr = core_if->gr_backup;
 807         if (!gr) {
 808                 gr = DWC_ALLOC(sizeof(*gr));
 809                 if (!gr)
 810                         return -DWC_E_NO_MEMORY;
 811                 core_if->gr_backup = gr;
 812         }
 813
 814         gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
 815
 816         DWC_DEBUGPL(DBG_ANY,
 817                     "=============Backing GINTMSK registers============\n");
 818         DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
 819
 820         return 0;
 821 }
 822
 823 int dwc_otg_save_dev_regs(dwc_otg_core_if_t *core_if)
 824 {
 825         struct dwc_otg_dev_regs_backup *dr;
 826         int i;
 827
 828         dr = core_if->dr_backup;
 829         if (!dr) {
 830                 dr = DWC_ALLOC(sizeof(*dr));
 831                 if (!dr)
 832                         return -DWC_E_NO_MEMORY;
 833                 core_if->dr_backup = dr;
 834         }
 835
 836         dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
 837         dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
 838         dr->daintmsk =
 839             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
 840         dr->diepmsk =
 841             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
 842         dr->doepmsk =
 843             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
 844
 845         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
 846                 dr->diepctl[i] =
 847                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
 848                 dr->dieptsiz[i] =
 849                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
 850                 dr->diepdma[i] =
 851                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
 852         }
 853
 854         DWC_DEBUGPL(DBG_ANY,
 855                     "=============Backing Host registers==============\n");
 856         DWC_DEBUGPL(DBG_ANY, "Backed up dcfg            = %08x\n", dr->dcfg);
 857         DWC_DEBUGPL(DBG_ANY, "Backed up dctl        = %08x\n", dr->dctl);
 858         DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk            = %08x\n",
 859                     dr->daintmsk);
 860         DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk        = %08x\n", dr->diepmsk);
 861         DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk        = %08x\n", dr->doepmsk);
 862         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
 863                 DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d]        = %08x\n", i,
 864                             dr->diepctl[i]);
 865                 DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d]        = %08x\n",
 866                             i, dr->dieptsiz[i]);
 867                 DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d]        = %08x\n", i,
 868                             dr->diepdma[i]);
 869         }
 870
 871         return 0;
 872 }
 873
 874 int dwc_otg_save_host_regs(dwc_otg_core_if_t *core_if)
 875 {
 876         struct dwc_otg_host_regs_backup *hr;
 877         int i;
 878
 879         hr = core_if->hr_backup;
 880         if (!hr) {
 881                 hr = DWC_ALLOC(sizeof(*hr));
 882                 if (!hr)
 883                         return -DWC_E_NO_MEMORY;
 884                 core_if->hr_backup = hr;
 885         }
 886
 887         hr->hcfg_local =
 888             DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
 889         hr->haintmsk_local =
 890             DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
 891         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
 892                 hr->hcintmsk_local[i] =
 893                     DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
 894         }
 895         hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
 896         hr->hfir_local =
 897             DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
 898
 899         DWC_DEBUGPL(DBG_ANY,
 900                     "=============Backing Host registers===============\n");
 901         DWC_DEBUGPL(DBG_ANY, "Backed up hcfg            = %08x\n",
 902                     hr->hcfg_local);
 903         DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
 904         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
 905                 DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
 906                             hr->hcintmsk_local[i]);
 907         }
 908         DWC_DEBUGPL(DBG_ANY, "Backed up hprt0           = %08x\n",
 909                     hr->hprt0_local);
 910         DWC_DEBUGPL(DBG_ANY, "Backed up hfir           = %08x\n",
 911                     hr->hfir_local);
 912
 913         return 0;
 914 }
 915
 916 int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
 917 {
 918         struct dwc_otg_global_regs_backup *gr;
 919         int i;
 920
 921         gr = core_if->gr_backup;
 922         if (!gr)
 923                 return -DWC_E_INVALID;
 924
 925         DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
 926         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
 927         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
 928         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
 929         DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
 930         DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
 931                         gr->gnptxfsiz_local);
 932         DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
 933                         gr->hptxfsiz_local);
 934         DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
 935                         gr->gdfifocfg_local);
 936         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 937                 DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
 938                                 gr->dtxfsiz_local[i]);
 939         }
 940
 941         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 942         DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
 943         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
 944                         (gr->gahbcfg_local));
 945         return 0;
 946 }
 947
 948 int dwc_otg_restore_dev_regs(dwc_otg_core_if_t *core_if, int rem_wakeup)
 949 {
 950         struct dwc_otg_dev_regs_backup *dr;
 951         int i;
 952
 953         dr = core_if->dr_backup;
 954
 955         if (!dr) {
 956                 return -DWC_E_INVALID;
 957         }
 958
 959         if (!rem_wakeup) {
 960                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
 961                                 dr->dctl);
 962         }
 963
 964         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
 965                         dr->daintmsk);
 966         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
 967                         dr->diepmsk);
 968         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
 969                         dr->doepmsk);
 970
 971         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
 972                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz,
 973                                 dr->dieptsiz[i]);
 974                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma,
 975                                 dr->diepdma[i]);
 976                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl,
 977                                 dr->diepctl[i]);
 978         }
 979
 980         return 0;
 981 }
 982
 983 int dwc_otg_restore_host_regs(dwc_otg_core_if_t *core_if, int reset)
 984 {
 985         struct dwc_otg_host_regs_backup *hr;
 986         int i;
 987         hr = core_if->hr_backup;
 988
 989         if (!hr)
 990                 return -DWC_E_INVALID;
 991
 992         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
 993                         hr->hcfg_local);
 994         /* if (!reset)
 995          * {
 996          *      DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir,
 997          *                      hr->hfir_local);
 998          * }
 999          */
1000
1001         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
1002                         hr->haintmsk_local);
1003         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
1004                 DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
1005                                 hr->hcintmsk_local[i]);
1006         }
1007
1008         return 0;
1009 }
1010
1011 int restore_lpm_i2c_regs(dwc_otg_core_if_t *core_if)
1012 {
1013         struct dwc_otg_global_regs_backup *gr;
1014
1015         gr = core_if->gr_backup;
1016
1017         /* Restore values for LPM and I2C */
1018 #ifdef CONFIG_USB_DWC_OTG_LPM
1019         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
1020 #endif
1021         DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
1022
1023         return 0;
1024 }
1025
1026 int restore_essential_regs(dwc_otg_core_if_t *core_if, int rmode, int is_host)
1027 {
1028         struct dwc_otg_global_regs_backup *gr;
1029         pcgcctl_data_t pcgcctl = {.d32 = 0 };
1030         gahbcfg_data_t gahbcfg = {.d32 = 0 };
1031         gusbcfg_data_t gusbcfg = {.d32 = 0 };
1032         gintmsk_data_t gintmsk = {.d32 = 0 };
1033
1034         /* Restore LPM and I2C registers */
1035         restore_lpm_i2c_regs(core_if);
1036
1037         /* Set PCGCCTL to 0 */
1038         DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
1039
1040         gr = core_if->gr_backup;
1041         /* Load restore values for [31:14] bits */
1042         DWC_WRITE_REG32(core_if->pcgcctl,
1043                         ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
1044
1045         /* Umnask global Interrupt in GAHBCFG and restore it */
1046         gahbcfg.d32 = gr->gahbcfg_local;
1047         gahbcfg.b.glblintrmsk = 1;
1048         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
1049
1050         /* Clear all pending interupts */
1051         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1052
1053         /* Unmask restore done interrupt */
1054         gintmsk.b.restoredone = 1;
1055         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
1056
1057         /* Restore GUSBCFG and HCFG/DCFG */
1058         gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
1059         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
1060
1061         if (is_host) {
1062                 hcfg_data_t hcfg = {.d32 = 0 };
1063                 hcfg.d32 = core_if->hr_backup->hcfg_local;
1064                 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
1065                                 hcfg.d32);
1066
1067                 /* Load restore values for [31:14] bits */
1068                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1069                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1070
1071                 if (rmode)
1072                         pcgcctl.b.restoremode = 1;
1073                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1074                 dwc_udelay(10);
1075
1076                 /* Load restore values for [31:14] bits
1077                  * and set EssRegRestored bit */
1078                 pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
1079                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1080                 pcgcctl.b.ess_reg_restored = 1;
1081                 if (rmode)
1082                         pcgcctl.b.restoremode = 1;
1083                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1084         } else {
1085                 dcfg_data_t dcfg = {.d32 = 0 };
1086                 dcfg.d32 = core_if->dr_backup->dcfg;
1087                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
1088                                 dcfg.d32);
1089
1090                 /* Load restore values for [31:14] bits */
1091                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1092                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1093                 if (!rmode)
1094                         pcgcctl.d32 |= 0x208;
1095                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1096                 dwc_udelay(10);
1097
1098                 /* Load restore values for [31:14] bits */
1099                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1100                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1101                 pcgcctl.b.ess_reg_restored = 1;
1102                 if (!rmode)
1103                         pcgcctl.d32 |= 0x208;
1104                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1105         }
1106
1107         return 0;
1108 }
1109
1110 /**
1111  * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
1112  * type.
1113  */
1114 static void init_fslspclksel(dwc_otg_core_if_t *core_if)
1115 {
1116         uint32_t val;
1117         hcfg_data_t hcfg;
1118
1119         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1120              (core_if->hwcfg2.b.fs_phy_type == 1) &&
1121              (core_if->core_params->ulpi_fs_ls)) ||
1122             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1123                 /* Full speed PHY */
1124                 val = DWC_HCFG_48_MHZ;
1125         } else {
1126                 /* High speed PHY running at full speed or high speed */
1127                 val = DWC_HCFG_30_60_MHZ;
1128         }
1129
1130         DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
1131         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
1132         hcfg.b.fslspclksel = val;
1133         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
1134 }
1135
1136 /**
1137  * Initializes the DevSpd field of the DCFG register depending on the PHY type
1138  * and the enumeration speed of the device.
1139  */
1140 static void init_devspd(dwc_otg_core_if_t *core_if)
1141 {
1142         uint32_t val;
1143         dcfg_data_t dcfg;
1144
1145         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1146              (core_if->hwcfg2.b.fs_phy_type == 1) &&
1147              (core_if->core_params->ulpi_fs_ls)) ||
1148             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1149                 /* Full speed PHY */
1150                 val = 0x3;
1151         } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
1152                 /* High speed PHY running at full speed */
1153                 val = 0x1;
1154         } else {
1155                 /* High speed PHY running at high speed */
1156                 val = 0x0;
1157         }
1158
1159         DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
1160
1161         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
1162         dcfg.b.devspd = val;
1163         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
1164 }
1165
1166 /**
1167  * This function calculates the number of IN EPS
1168  * using GHWCFG1 and GHWCFG2 registers values
1169  *
1170  * @param core_if Programming view of the DWC_otg controller
1171  */
1172 static uint32_t calc_num_in_eps(dwc_otg_core_if_t *core_if)
1173 {
1174         uint32_t num_in_eps = 0;
1175         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1176         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
1177         uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
1178         int i;
1179
1180         for (i = 0; i < num_eps; ++i) {
1181                 if (!(hwcfg1 & 0x1))
1182                         num_in_eps++;
1183
1184                 hwcfg1 >>= 2;
1185         }
1186
1187         if (core_if->hwcfg4.b.ded_fifo_en) {
1188                 num_in_eps =
1189                     (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
1190         }
1191
1192         return num_in_eps;
1193 }
1194
1195 /**
1196  * This function calculates the number of OUT EPS
1197  * using GHWCFG1 and GHWCFG2 registers values
1198  *
1199  * @param core_if Programming view of the DWC_otg controller
1200  */
1201 static uint32_t calc_num_out_eps(dwc_otg_core_if_t *core_if)
1202 {
1203         uint32_t num_out_eps = 0;
1204         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1205         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
1206         int i;
1207
1208         for (i = 0; i < num_eps; ++i) {
1209                 if (!(hwcfg1 & 0x1))
1210                         num_out_eps++;
1211
1212                 hwcfg1 >>= 2;
1213         }
1214         return num_out_eps;
1215 }
1216
1217 void dwc_otg_core_init(dwc_otg_core_if_t *core_if)
1218 {
1219         int i = 0;
1220         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1221         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1222         gahbcfg_data_t ahbcfg = {.d32 = 0 };
1223         gusbcfg_data_t usbcfg = {.d32 = 0 };
1224         gi2cctl_data_t i2cctl = {.d32 = 0 };
1225
1226         DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
1227         /* Common Initialization */
1228         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1229
1230         /* Program the ULPI External VBUS bit if needed */
1231         usbcfg.b.ulpi_ext_vbus_drv =
1232             (core_if->core_params->phy_ulpi_ext_vbus ==
1233              DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
1234
1235         /* Set external TS Dline pulsing */
1236         usbcfg.b.term_sel_dl_pulse =
1237             (core_if->core_params->ts_dline == 1) ? 1 : 0;
1238         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1239
1240         /* Reset the Controller */
1241         dwc_otg_core_reset(core_if);
1242
1243         core_if->adp_enable = core_if->core_params->adp_supp_enable;
1244         core_if->power_down = core_if->core_params->power_down;
1245
1246         /* Initialize parameters from Hardware configuration registers. */
1247         dev_if->num_in_eps = calc_num_in_eps(core_if);
1248         dev_if->num_out_eps = calc_num_out_eps(core_if);
1249
1250         DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
1251                     core_if->hwcfg4.b.num_dev_perio_in_ep);
1252
1253         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
1254                 dev_if->perio_tx_fifo_size[i] =
1255                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1256                 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
1257                             i, dev_if->perio_tx_fifo_size[i]);
1258         }
1259
1260         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
1261                 dev_if->tx_fifo_size[i] =
1262                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1263                 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
1264                             i, dev_if->tx_fifo_size[i]);
1265         }
1266
1267         core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
1268         core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
1269         core_if->nperio_tx_fifo_size =
1270             DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
1271
1272         DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
1273         DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
1274         DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
1275                     core_if->nperio_tx_fifo_size);
1276
1277         /* This programming sequence needs to happen in FS mode before any other
1278          * programming occurs */
1279         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
1280             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1281                 /* If FS mode with FS PHY */
1282
1283                 /* core_init() is now called on every switch so only call the
1284                  * following for the first time through. */
1285                 if (!core_if->phy_init_done) {
1286                         core_if->phy_init_done = 1;
1287                         DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
1288                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1289                         usbcfg.b.physel = 1;
1290                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1291
1292                         /* Reset after a PHY select */
1293                         dwc_otg_core_reset(core_if);
1294                 }
1295
1296                 /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1297                  * do this on HNP Dev/Host mode switches (done in dev_init and
1298                  * host_init). */
1299                 if (dwc_otg_is_host_mode(core_if))
1300                         init_fslspclksel(core_if);
1301                 else
1302                         init_devspd(core_if);
1303
1304                 if (core_if->core_params->i2c_enable) {
1305                         DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
1306                         /* Program GUSBCFG.OtgUtmifsSel to I2C */
1307                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1308                         usbcfg.b.otgutmifssel = 1;
1309                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1310
1311                         /* Program GI2CCTL.I2CEn */
1312                         i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
1313                         i2cctl.b.i2cdevaddr = 1;
1314                         i2cctl.b.i2cen = 0;
1315                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1316                         i2cctl.b.i2cen = 1;
1317                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1318                 }
1319
1320         } /* endif speed == DWC_SPEED_PARAM_FULL */
1321         else {
1322                 /* High speed PHY. */
1323                 if (!core_if->phy_init_done) {
1324                         core_if->phy_init_done = 1;
1325                         /* HS PHY parameters.  These parameters are preserved
1326                          * during soft reset so only program the first time.  Do
1327                          * a soft reset immediately after setting phyif.  */
1328
1329                         if (core_if->core_params->phy_type == 2) {
1330                                 /* ULPI interface */
1331                                 usbcfg.b.ulpi_utmi_sel = 1;
1332                                 usbcfg.b.phyif = 0;
1333                                 usbcfg.b.ddrsel =
1334                                     core_if->core_params->phy_ulpi_ddr;
1335                         } else if (core_if->core_params->phy_type == 1) {
1336                                 /* UTMI+ interface */
1337                                 usbcfg.b.ulpi_utmi_sel = 0;
1338                                 if (core_if->core_params->phy_utmi_width == 16)
1339                                         usbcfg.b.phyif = 1;
1340                                 else
1341                                         usbcfg.b.phyif = 0;
1342                         } else {
1343                                 DWC_ERROR("FS PHY TYPE\n");
1344                         }
1345                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1346                         /* Reset after setting the PHY parameters */
1347                         dwc_otg_core_reset(core_if);
1348                 }
1349         }
1350
1351         if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
1352             (core_if->hwcfg2.b.fs_phy_type == 1) &&
1353             (core_if->core_params->ulpi_fs_ls)) {
1354                 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
1355                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1356                 usbcfg.b.ulpi_fsls = 1;
1357                 usbcfg.b.ulpi_clk_sus_m = 1;
1358                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1359         } else {
1360                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1361                 usbcfg.b.ulpi_fsls = 0;
1362                 usbcfg.b.ulpi_clk_sus_m = 0;
1363                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1364         }
1365
1366         /* Program the GAHBCFG Register. */
1367         switch (core_if->hwcfg2.b.architecture) {
1368
1369         case DWC_SLAVE_ONLY_ARCH:
1370                 DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
1371                 ahbcfg.b.nptxfemplvl_txfemplvl =
1372                     DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1373                 ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1374                 core_if->dma_enable = 0;
1375                 core_if->dma_desc_enable = 0;
1376                 break;
1377
1378         case DWC_EXT_DMA_ARCH:
1379                 DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
1380                 {
1381                         uint8_t brst_sz = core_if->core_params->dma_burst_size;
1382                         ahbcfg.b.hburstlen = 0;
1383                         while (brst_sz > 1) {
1384                                 ahbcfg.b.hburstlen++;
1385                                 brst_sz >>= 1;
1386                         }
1387                 }
1388                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1389                 core_if->dma_desc_enable =
1390                     (core_if->core_params->dma_desc_enable != 0);
1391                 break;
1392
1393         case DWC_INT_DMA_ARCH:
1394                 DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
1395                 /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
1396                    Host mode ISOC in issue fix - vahrama */
1397                 ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR8;
1398                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1399                 core_if->dma_desc_enable =
1400                     (core_if->core_params->dma_desc_enable != 0);
1401                 break;
1402
1403         }
1404         if (core_if->dma_enable) {
1405                 if (core_if->dma_desc_enable)
1406                         DWC_PRINTF("Using Descriptor DMA mode\n");
1407                 else
1408                         DWC_PRINTF("Using Buffer DMA mode\n");
1409         } else {
1410                 DWC_PRINTF("Using Slave mode\n");
1411                 core_if->dma_desc_enable = 0;
1412         }
1413
1414         if (core_if->core_params->ahb_single)
1415                 ahbcfg.b.ahbsingle = 1;
1416
1417         ahbcfg.b.dmaenable = core_if->dma_enable;
1418         DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
1419
1420         core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
1421
1422         core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
1423         core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
1424         DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
1425                    ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
1426         DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
1427                    ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
1428
1429         /*
1430          * Program the GUSBCFG register.
1431          */
1432         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1433
1434         switch (core_if->hwcfg2.b.op_mode) {
1435         case DWC_MODE_HNP_SRP_CAPABLE:
1436                 usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
1437                                    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1438                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1439                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1440                 break;
1441
1442         case DWC_MODE_SRP_ONLY_CAPABLE:
1443                 usbcfg.b.hnpcap = 0;
1444                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1445                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1446                 break;
1447
1448         case DWC_MODE_NO_HNP_SRP_CAPABLE:
1449                 usbcfg.b.hnpcap = 0;
1450                 usbcfg.b.srpcap = 0;
1451                 break;
1452
1453         case DWC_MODE_SRP_CAPABLE_DEVICE:
1454                 usbcfg.b.hnpcap = 0;
1455                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1456                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1457                 break;
1458
1459         case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
1460                 usbcfg.b.hnpcap = 0;
1461                 usbcfg.b.srpcap = 0;
1462                 break;
1463
1464         case DWC_MODE_SRP_CAPABLE_HOST:
1465                 usbcfg.b.hnpcap = 0;
1466                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1467                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1468                 break;
1469
1470         case DWC_MODE_NO_SRP_CAPABLE_HOST:
1471                 usbcfg.b.hnpcap = 0;
1472                 usbcfg.b.srpcap = 0;
1473                 break;
1474         }
1475
1476         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1477
1478 #ifdef CONFIG_USB_DWC_OTG_LPM
1479         if (core_if->core_params->lpm_enable) {
1480                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
1481
1482                 /* To enable LPM support set lpm_cap_en bit */
1483                 lpmcfg.b.lpm_cap_en = 1;
1484
1485                 /* Make AppL1Res ACK */
1486                 lpmcfg.b.appl_resp = 1;
1487
1488                 /* Retry 3 times */
1489                 lpmcfg.b.retry_count = 3;
1490
1491                 DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
1492                                  0, lpmcfg.d32);
1493
1494         }
1495 #endif
1496         if (core_if->core_params->ic_usb_cap) {
1497                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
1498                 gusbcfg.b.ic_usb_cap = 1;
1499                 DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
1500                                  0, gusbcfg.d32);
1501         }
1502         {
1503                 gotgctl_data_t gotgctl = {.d32 = 0 };
1504                 gotgctl.b.otgver = core_if->core_params->otg_ver;
1505                 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
1506                                  gotgctl.d32);
1507                 /* Set OTG version supported */
1508                 core_if->otg_ver = core_if->core_params->otg_ver;
1509                 DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
1510                            core_if->core_params->otg_ver, core_if->otg_ver);
1511         }
1512
1513         /* Enable common interrupts */
1514         dwc_otg_enable_common_interrupts(core_if);
1515
1516         /* Do device or host intialization based on mode during PCD
1517          * and HCD initialization  */
1518         if (dwc_otg_is_host_mode(core_if)) {
1519                 DWC_PRINTF("^^^^^^^^^^^^^^^^^^Host Mode\n");
1520                 core_if->op_state = A_HOST;
1521         } else {
1522                 DWC_PRINTF("^^^^^^^^^^^^^^^^^Device Mode\n");
1523                 core_if->op_state = B_PERIPHERAL;
1524 #ifdef DWC_DEVICE_ONLY
1525                 dwc_otg_core_dev_init(core_if);
1526 #endif
1527         }
1528 }
1529
1530 /**
1531  * This function initializes the DWC_otg controller registers and
1532  * prepares the core for device mode or host mode operation.
1533  *
1534  * @param core_if Programming view of the DWC_otg controller
1535  *
1536  */
1537 void dwc_otg_core_init_no_reset(dwc_otg_core_if_t *core_if)
1538 {
1539         int i = 0;
1540         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1541         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1542         gahbcfg_data_t ahbcfg = {.d32 = 0 };
1543         gusbcfg_data_t usbcfg = {.d32 = 0 };
1544         gi2cctl_data_t i2cctl = {.d32 = 0 };
1545
1546         DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
1547         /* Common Initialization */
1548         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1549
1550         /* Program the ULPI External VBUS bit if needed */
1551         usbcfg.b.ulpi_ext_vbus_drv =
1552             (core_if->core_params->phy_ulpi_ext_vbus ==
1553              DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
1554
1555         /* Set external TS Dline pulsing */
1556         usbcfg.b.term_sel_dl_pulse =
1557             (core_if->core_params->ts_dline == 1) ? 1 : 0;
1558         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1559
1560         /* Reset the Controller */
1561         /* dwc_otg_core_reset(core_if); */
1562
1563         core_if->adp_enable = core_if->core_params->adp_supp_enable;
1564         core_if->power_down = core_if->core_params->power_down;
1565
1566         /* Initialize parameters from Hardware configuration registers. */
1567         dev_if->num_in_eps = calc_num_in_eps(core_if);
1568         dev_if->num_out_eps = calc_num_out_eps(core_if);
1569
1570         DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
1571                     core_if->hwcfg4.b.num_dev_perio_in_ep);
1572
1573         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
1574                 dev_if->perio_tx_fifo_size[i] =
1575                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1576                 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
1577                             i, dev_if->perio_tx_fifo_size[i]);
1578         }
1579
1580         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
1581                 dev_if->tx_fifo_size[i] =
1582                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1583                 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
1584                             i, dev_if->tx_fifo_size[i]);
1585         }
1586
1587         core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
1588         core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
1589         core_if->nperio_tx_fifo_size =
1590             DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
1591
1592         DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
1593         DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
1594         DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
1595                     core_if->nperio_tx_fifo_size);
1596
1597         /* This programming sequence needs to happen in FS mode before any other
1598          * programming occurs */
1599         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
1600             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1601                 /* If FS mode with FS PHY */
1602
1603                 /* core_init() is now called on every switch so only call the
1604                  * following for the first time through. */
1605                 if (!core_if->phy_init_done) {
1606                         core_if->phy_init_done = 1;
1607                         DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
1608                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1609                         usbcfg.b.physel = 1;
1610                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1611
1612                         /* Reset after a PHY select */
1613                         /* dwc_otg_core_reset(core_if); */
1614                 }
1615
1616                 /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1617                  * do this on HNP Dev/Host mode switches (done in dev_init and
1618                  * host_init). */
1619                 if (dwc_otg_is_host_mode(core_if))
1620                         init_fslspclksel(core_if);
1621                 else
1622                         init_devspd(core_if);
1623
1624                 if (core_if->core_params->i2c_enable) {
1625                         DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
1626                         /* Program GUSBCFG.OtgUtmifsSel to I2C */
1627                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1628                         usbcfg.b.otgutmifssel = 1;
1629                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1630
1631                         /* Program GI2CCTL.I2CEn */
1632                         i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
1633                         i2cctl.b.i2cdevaddr = 1;
1634                         i2cctl.b.i2cen = 0;
1635                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1636                         i2cctl.b.i2cen = 1;
1637                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1638                 }
1639
1640         } /* endif speed == DWC_SPEED_PARAM_FULL */
1641         else {
1642                 /* High speed PHY. */
1643                 if (!core_if->phy_init_done) {
1644                         core_if->phy_init_done = 1;
1645                         /* HS PHY parameters.  These parameters are preserved
1646                          * during soft reset so only program the first time.  Do
1647                          * a soft reset immediately after setting phyif.  */
1648
1649                         if (core_if->core_params->phy_type == 2) {
1650                                 /* ULPI interface */
1651                                 usbcfg.b.ulpi_utmi_sel = 1;
1652                                 usbcfg.b.phyif = 0;
1653                                 usbcfg.b.ddrsel =
1654                                     core_if->core_params->phy_ulpi_ddr;
1655                         } else if (core_if->core_params->phy_type == 1) {
1656                                 /* UTMI+ interface */
1657                                 usbcfg.b.ulpi_utmi_sel = 0;
1658                                 if (core_if->core_params->phy_utmi_width == 16)
1659                                         usbcfg.b.phyif = 1;
1660                                 else
1661                                         usbcfg.b.phyif = 0;
1662                         } else {
1663                                 DWC_ERROR("FS PHY TYPE\n");
1664                         }
1665                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1666                         /* Reset after setting the PHY parameters */
1667                         /* dwc_otg_core_reset(core_if); */
1668                 }
1669         }
1670
1671         if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
1672             (core_if->hwcfg2.b.fs_phy_type == 1) &&
1673             (core_if->core_params->ulpi_fs_ls)) {
1674                 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
1675                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1676                 usbcfg.b.ulpi_fsls = 1;
1677                 usbcfg.b.ulpi_clk_sus_m = 1;
1678                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1679         } else {
1680                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1681                 usbcfg.b.ulpi_fsls = 0;
1682                 usbcfg.b.ulpi_clk_sus_m = 0;
1683                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1684         }
1685
1686         /* Program the GAHBCFG Register. */
1687         switch (core_if->hwcfg2.b.architecture) {
1688
1689         case DWC_SLAVE_ONLY_ARCH:
1690                 DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
1691                 ahbcfg.b.nptxfemplvl_txfemplvl =
1692                     DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1693                 ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1694                 core_if->dma_enable = 0;
1695                 core_if->dma_desc_enable = 0;
1696                 break;
1697
1698         case DWC_EXT_DMA_ARCH:
1699                 DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
1700                 {
1701                         uint8_t brst_sz = core_if->core_params->dma_burst_size;
1702                         ahbcfg.b.hburstlen = 0;
1703                         while (brst_sz > 1) {
1704                                 ahbcfg.b.hburstlen++;
1705                                 brst_sz >>= 1;
1706                         }
1707                 }
1708                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1709                 core_if->dma_desc_enable =
1710                     (core_if->core_params->dma_desc_enable != 0);
1711                 break;
1712
1713         case DWC_INT_DMA_ARCH:
1714                 DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
1715                 /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
1716                    Host mode ISOC in issue fix - vahrama */
1717                 ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR8;
1718                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1719                 core_if->dma_desc_enable =
1720                     (core_if->core_params->dma_desc_enable != 0);
1721                 break;
1722
1723         }
1724         if (core_if->dma_enable) {
1725                 if (core_if->dma_desc_enable)
1726                         DWC_PRINTF("Using Descriptor DMA mode\n");
1727                 else
1728                         DWC_PRINTF("Using Buffer DMA mode\n");
1729         } else {
1730                 DWC_PRINTF("Using Slave mode\n");
1731                 core_if->dma_desc_enable = 0;
1732         }
1733
1734         if (core_if->core_params->ahb_single)
1735                 ahbcfg.b.ahbsingle = 1;
1736
1737         ahbcfg.b.dmaenable = core_if->dma_enable;
1738         DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
1739
1740         core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
1741
1742         core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
1743         core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
1744         DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
1745                    ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
1746         DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
1747                    ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
1748
1749         /*
1750          * Program the GUSBCFG register.
1751          */
1752         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1753
1754         switch (core_if->hwcfg2.b.op_mode) {
1755         case DWC_MODE_HNP_SRP_CAPABLE:
1756                 usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
1757                                    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1758                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1759                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1760                 break;
1761
1762         case DWC_MODE_SRP_ONLY_CAPABLE:
1763                 usbcfg.b.hnpcap = 0;
1764                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1765                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1766                 break;
1767
1768         case DWC_MODE_NO_HNP_SRP_CAPABLE:
1769                 usbcfg.b.hnpcap = 0;
1770                 usbcfg.b.srpcap = 0;
1771                 break;
1772
1773         case DWC_MODE_SRP_CAPABLE_DEVICE:
1774                 usbcfg.b.hnpcap = 0;
1775                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1776                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1777                 break;
1778
1779         case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
1780                 usbcfg.b.hnpcap = 0;
1781                 usbcfg.b.srpcap = 0;
1782                 break;
1783
1784         case DWC_MODE_SRP_CAPABLE_HOST:
1785                 usbcfg.b.hnpcap = 0;
1786                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1787                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1788                 break;
1789
1790         case DWC_MODE_NO_SRP_CAPABLE_HOST:
1791                 usbcfg.b.hnpcap = 0;
1792                 usbcfg.b.srpcap = 0;
1793                 break;
1794         }
1795
1796         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1797
1798 #ifdef CONFIG_USB_DWC_OTG_LPM
1799         if (core_if->core_params->lpm_enable) {
1800                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
1801
1802                 /* To enable LPM support set lpm_cap_en bit */
1803                 lpmcfg.b.lpm_cap_en = 1;
1804
1805                 /* Make AppL1Res ACK */
1806                 lpmcfg.b.appl_resp = 1;
1807
1808                 /* Retry 3 times */
1809                 lpmcfg.b.retry_count = 3;
1810
1811                 DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
1812                                  0, lpmcfg.d32);
1813
1814         }
1815 #endif
1816         if (core_if->core_params->ic_usb_cap) {
1817                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
1818                 gusbcfg.b.ic_usb_cap = 1;
1819                 DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
1820                                  0, gusbcfg.d32);
1821         }
1822         {
1823                 gotgctl_data_t gotgctl = {.d32 = 0 };
1824                 gotgctl.b.otgver = core_if->core_params->otg_ver;
1825                 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
1826                                  gotgctl.d32);
1827                 /* Set OTG version supported */
1828                 core_if->otg_ver = core_if->core_params->otg_ver;
1829                 DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
1830                            core_if->core_params->otg_ver, core_if->otg_ver);
1831         }
1832
1833         /* Enable common interrupts */
1834         dwc_otg_enable_common_interrupts(core_if);
1835
1836         /* Do device or host intialization based on mode during PCD
1837          * and HCD initialization  */
1838         if (dwc_otg_is_host_mode(core_if)) {
1839                 DWC_PRINTF("^^^^^^^^^^^^^^^^^^Host Mode\n");
1840                 core_if->op_state = A_HOST;
1841         } else {
1842                 DWC_PRINTF("^^^^^^^^^^^^^^^^^Device Mode\n");
1843                 core_if->op_state = B_PERIPHERAL;
1844 #ifdef DWC_DEVICE_ONLY
1845                 dwc_otg_core_dev_init(core_if);
1846 #endif
1847         }
1848 }
1849
1850 /**
1851  * This function enables the Device mode interrupts.
1852  *
1853  * @param core_if Programming view of DWC_otg controller
1854  */
1855 void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *core_if)
1856 {
1857         gintmsk_data_t intr_mask = {.d32 = 0 };
1858         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1859
1860         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
1861
1862         /* Disable all interrupts. */
1863         DWC_WRITE_REG32(&global_regs->gintmsk, 0);
1864
1865         /* Clear any pending interrupts */
1866         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
1867
1868         /* Enable the common interrupts */
1869         dwc_otg_enable_common_interrupts(core_if);
1870
1871         /* Enable interrupts */
1872         intr_mask.b.usbreset = 1;
1873         intr_mask.b.enumdone = 1;
1874         /* Disable Disconnect interrupt in Device mode */
1875         intr_mask.b.disconnect = 0;
1876
1877         if (!core_if->multiproc_int_enable) {
1878                 intr_mask.b.inepintr = 1;
1879                 intr_mask.b.outepintr = 1;
1880         }
1881
1882         intr_mask.b.erlysuspend = 1;
1883
1884         if (core_if->en_multiple_tx_fifo == 0)
1885                 intr_mask.b.epmismatch = 1;
1886
1887         /* intr_mask.b.incomplisoout = 1; */
1888         intr_mask.b.incomplisoin = 1;
1889
1890 /* Enable the ignore frame number for ISOC xfers - MAS */
1891 /* Disable to support high bandwith ISOC transfers - manukz */
1892 #if 0
1893 #ifdef DWC_UTE_PER_IO
1894         if (core_if->dma_enable) {
1895                 if (core_if->dma_desc_enable) {
1896                         dctl_data_t dctl1 = {.d32 = 0 };
1897                         dctl1.b.ifrmnum = 1;
1898                         DWC_MODIFY_REG32(&core_if->dev_if->
1899                                          dev_global_regs->dctl, 0, dctl1.d32);
1900                         DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
1901                                   DWC_READ_REG32(&core_if->
1902                                                  dev_if->dev_global_regs->
1903                                                  dctl));
1904                 }
1905         }
1906 #endif
1907 #endif
1908 #ifdef DWC_EN_ISOC
1909         if (core_if->dma_enable) {
1910                 if (core_if->dma_desc_enable == 0) {
1911                         if (core_if->pti_enh_enable) {
1912                                 dctl_data_t dctl = {.d32 = 0 };
1913                                 dctl.b.ifrmnum = 1;
1914                                 DWC_MODIFY_REG32(&core_if->dev_if->
1915                                                  dev_global_regs->dctl, 0,
1916                                                  dctl.d32);
1917                         } else {
1918                                 intr_mask.b.incomplisoin = 1;
1919                                 intr_mask.b.incomplisoout = 1;
1920                         }
1921                 }
1922         } else {
1923                 intr_mask.b.incomplisoin = 1;
1924                 intr_mask.b.incomplisoout = 1;
1925         }
1926 #endif /* DWC_EN_ISOC */
1927
1928         /** @todo NGS: Should this be a module parameter? */
1929 #ifdef USE_PERIODIC_EP
1930         intr_mask.b.isooutdrop = 1;
1931         intr_mask.b.eopframe = 1;
1932         intr_mask.b.incomplisoin = 1;
1933         intr_mask.b.incomplisoout = 1;
1934 #endif
1935
1936         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1937
1938         DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
1939                     DWC_READ_REG32(&global_regs->gintmsk));
1940 }
1941
1942 /**
1943  * This function initializes the DWC_otg controller registers for
1944  * device mode.
1945  *
1946  * @param core_if Programming view of DWC_otg controller
1947  *
1948  */
1949 void dwc_otg_core_dev_init(dwc_otg_core_if_t *core_if)
1950 {
1951         int i;
1952         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1953         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1954         dwc_otg_core_params_t *params = core_if->core_params;
1955         dcfg_data_t dcfg = {.d32 = 0 };
1956         depctl_data_t diepctl = {.d32 = 0 };
1957         grstctl_t resetctl = {.d32 = 0 };
1958         uint32_t rx_fifo_size;
1959         fifosize_data_t nptxfifosize;
1960         fifosize_data_t txfifosize;
1961         dthrctl_data_t dthrctl;
1962         fifosize_data_t ptxfifosize;
1963         /* uint16_t rxfsiz, nptxfsiz; */
1964         /* gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; */
1965         /* hwcfg3_data_t hwcfg3 = {.d32 = 0 }; */
1966         gotgctl_data_t gotgctl = {.d32 = 0 };
1967         gahbcfg_data_t gahbcfg = {.d32 = 0 };
1968
1969         /* Restart the Phy Clock */
1970         pcgcctl_data_t pcgcctl = {.d32 = 0 };
1971         /* Restart the Phy Clock */
1972         pcgcctl.b.stoppclk = 1;
1973         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
1974         dwc_udelay(10);
1975
1976         gahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR8;
1977         DWC_MODIFY_REG32(&global_regs->gahbcfg, 0, gahbcfg.d32);
1978
1979         /* Device configuration register */
1980         init_devspd(core_if);
1981         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
1982         dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
1983         dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
1984         /* Enable Device OUT NAK in case of DDMA mode */
1985         if (core_if->core_params->dev_out_nak)
1986                 dcfg.b.endevoutnak = 1;
1987
1988         if (core_if->core_params->cont_on_bna) {
1989                 dctl_data_t dctl = {.d32 = 0 };
1990                 dctl.b.encontonbna = 1;
1991                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
1992         }
1993         /** should be done before every reset */
1994         if (core_if->otg_ver) {
1995                 core_if->otg_sts = 0;
1996                 gotgctl.b.devhnpen = 1;
1997                 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
1998                                  gotgctl.d32, 0);
1999         }
2000
2001         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
2002
2003         /* Configure data FIFO sizes */
2004
2005         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
2006 #ifdef DWC_UTE_CFI
2007                 core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
2008                 core_if->init_rxfsiz = params->dev_rx_fifo_size;
2009 #endif
2010                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
2011                             DWC_READ_REG32(&global_regs->grxfsiz));
2012
2013                 /** Set Periodic Tx FIFO Mask all bits 0 */
2014                 core_if->p_tx_msk = 0;
2015
2016                 /** Set Tx FIFO Mask all bits 0 */
2017                 core_if->tx_msk = 0;
2018                 /* core_if->en_multiple_tx_fifo equals
2019                  * core_if->hwcfg4.b.ded_fifo_en,
2020                  * and ded_fifo_en is 1 in default*/
2021                 if (core_if->en_multiple_tx_fifo == 0) {
2022                         /* Non-periodic Tx FIFO */
2023                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
2024                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
2025
2026                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
2027                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
2028
2029                         DWC_WRITE_REG32(&global_regs->gnptxfsiz,
2030                                         nptxfifosize.d32);
2031
2032                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
2033                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
2034
2035                         /**@todo NGS: Fix Periodic FIFO Sizing! */
2036                         /*
2037                          * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
2038                          * Indexes of the FIFO size module parameters in the
2039                          * dev_perio_tx_fifo_size array and the FIFO size registers in
2040                          * the dptxfsiz array run from 0 to 14.
2041                          */
2042                         /** @todo Finish debug of this */
2043                         ptxfifosize.b.startaddr =
2044                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
2045                         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep;
2046                              i++) {
2047                                 ptxfifosize.b.depth =
2048                                     params->dev_perio_tx_fifo_size[i];
2049                                 DWC_DEBUGPL(DBG_CIL,
2050                                             "initial dtxfsiz[%d]=%08x\n", i,
2051                                             DWC_READ_REG32(&global_regs->
2052                                                            dtxfsiz[i]));
2053                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
2054                                                 ptxfifosize.d32);
2055                                 DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
2056                                             i,
2057                                             DWC_READ_REG32(&global_regs->
2058                                                            dtxfsiz[i]));
2059                                 ptxfifosize.b.startaddr += ptxfifosize.b.depth;
2060                         }
2061                 } else {
2062                         /*
2063                          * Tx FIFOs These FIFOs are numbered from 1 to 15.
2064                          * Indexes of the FIFO size module parameters in the
2065                          * dev_tx_fifo_size array and the FIFO size registers in
2066                          * the dtxfsiz array run from 0 to 14.
2067                          */
2068
2069                         /* Non-periodic Tx FIFO */
2070                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
2071                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
2072
2073 #ifdef DWC_UTE_CFI
2074                         core_if->pwron_gnptxfsiz =
2075                             (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
2076                         core_if->init_gnptxfsiz =
2077                             params->dev_nperio_tx_fifo_size;
2078 #endif
2079                         rx_fifo_size = params->dev_rx_fifo_size;
2080                         DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
2081                         DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
2082                                     DWC_READ_REG32(&global_regs->grxfsiz));
2083
2084                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
2085                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
2086                         DWC_WRITE_REG32(&global_regs->gnptxfsiz,
2087                                         nptxfifosize.d32);
2088
2089                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
2090                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
2091
2092                         txfifosize.b.startaddr =
2093                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
2094
2095                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
2096
2097                                 txfifosize.b.depth =
2098                                     params->dev_tx_fifo_size[i];
2099
2100                                 DWC_DEBUGPL(DBG_CIL,
2101                                             "initial dtxfsiz[%d]=%08x\n",
2102                                             i,
2103                                             DWC_READ_REG32(&global_regs->dtxfsiz
2104                                                            [i]));
2105
2106 #ifdef DWC_UTE_CFI
2107                                 core_if->pwron_txfsiz[i] =
2108                                     (DWC_READ_REG32
2109                                      (&global_regs->dtxfsiz[i]) >> 16);
2110                                 core_if->init_txfsiz[i] =
2111                                     params->dev_tx_fifo_size[i];
2112 #endif
2113                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
2114                                                 txfifosize.d32);
2115
2116                                 DWC_DEBUGPL(DBG_CIL,
2117                                             "new dtxfsiz[%d]=%08x\n",
2118                                             i,
2119                                             DWC_READ_REG32(&global_regs->dtxfsiz
2120                                                            [i]));
2121
2122                                 txfifosize.b.startaddr += txfifosize.b.depth;
2123                         }
2124 #if 0
2125                         /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO
2126                          * Before 3.00a EpInfoBase was being configured in ep enable/disable
2127                          * routine as well. Starting from 3.00a it will be set to the end of
2128                          * allocated FIFO space here due to ep 0 OUT always keeping enabled
2129                          */
2130                         gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
2131                         hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
2132                         gdfifocfg.b.gdfifocfg =
2133                             (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
2134                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
2135                         if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
2136                                 rxfsiz =
2137                                     (DWC_READ_REG32(&global_regs->grxfsiz) &
2138                                      0x0000ffff);
2139                                 nptxfsiz =
2140                                     (DWC_READ_REG32(&global_regs->gnptxfsiz) >>
2141                                      16);
2142                                 gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
2143                         } else {
2144                                 gdfifocfg.b.epinfobase = txfifosize.b.startaddr;
2145                         }
2146                         /* DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); */
2147 #endif
2148                 }
2149         }
2150
2151         /* Flush the FIFOs */
2152         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
2153         dwc_otg_flush_rx_fifo(core_if);
2154
2155         /* Flush the Learning Queue. */
2156         resetctl.b.intknqflsh = 1;
2157         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
2158
2159         if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
2160                 core_if->start_predict = 0;
2161                 for (i = 0; i <= core_if->dev_if->num_in_eps; ++i)
2162                         core_if->nextep_seq[i] = 0xff;  /* 0xff - EP not active */
2163                 core_if->nextep_seq[0] = 0;
2164                 core_if->first_in_nextep_seq = 0;
2165                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
2166                 diepctl.b.nextep = 0;
2167                 DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
2168
2169                 /* Update IN Endpoint Mismatch Count
2170                  * by active IN NP EP count + 1 */
2171                 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
2172                 dcfg.b.epmscnt = 2;
2173                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
2174
2175                 DWC_DEBUGPL(DBG_CILV,
2176                             "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
2177                             __func__, core_if->first_in_nextep_seq);
2178                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++)
2179                         DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
2180                 DWC_DEBUGPL(DBG_CILV, "\n");
2181         }
2182
2183         /* Clear all pending Device Interrupts
2184          * @todo - if the condition needed to be checked
2185          * or in any case all pending interrutps should be cleared?
2186          */
2187         if (core_if->multiproc_int_enable) {
2188                 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
2189                         DWC_WRITE_REG32(&dev_if->
2190                                         dev_global_regs->diepeachintmsk[i], 0);
2191                 }
2192
2193                 for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
2194                         DWC_WRITE_REG32(&dev_if->
2195                                         dev_global_regs->doepeachintmsk[i], 0);
2196                 }
2197
2198                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
2199                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
2200         } else {
2201                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
2202                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
2203                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
2204                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
2205         }
2206
2207         for (i = 0; i <= dev_if->num_in_eps; i++) {
2208                 depctl_data_t depctl;
2209                 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
2210                 if (depctl.b.epena) {
2211                         depctl.d32 = 0;
2212                         depctl.b.epdis = 1;
2213                         depctl.b.snak = 1;
2214                 } else {
2215                         depctl.d32 = 0;
2216                 }
2217
2218                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
2219
2220                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
2221                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
2222                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
2223         }
2224
2225         for (i = 1; i <= dev_if->num_out_eps; i++) {
2226                 depctl_data_t depctl;
2227                 depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
2228                 if (depctl.b.epena) {
2229                         int j = 0;
2230                         dctl_data_t dctl = {.d32 = 0 };
2231                         gintmsk_data_t gintsts = {.d32 = 0 };
2232                         doepint_data_t doepint = {.d32 = 0 };
2233                         dctl.b.sgoutnak = 1;
2234                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
2235                                          dctl, 0, dctl.d32);
2236                         do {
2237                                 j++;
2238                                 dwc_udelay(10);
2239                                 gintsts.d32 =
2240                                     DWC_READ_REG32(&core_if->core_global_regs->
2241                                                    gintsts);
2242                                 if (j == 100000) {
2243                                         DWC_ERROR
2244                                             ("SNAK as not set during 10s\n");
2245                                         break;
2246                                 }
2247                         } while (!gintsts.b.goutnakeff);
2248                         gintsts.d32 = 0;
2249                         gintsts.b.goutnakeff = 1;
2250                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,
2251                                         gintsts.d32);
2252
2253                         depctl.d32 = 0;
2254                         depctl.b.epdis = 1;
2255                         depctl.b.snak = 1;
2256                         j = 0;
2257                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
2258                                         doepctl, depctl.d32);
2259                         do {
2260                                 dwc_udelay(10);
2261                                 doepint.d32 =
2262                                     DWC_READ_REG32(&core_if->
2263                                                    dev_if->out_ep_regs[i]->
2264                                                    doepint);
2265                                 if (j++ >= 10000) {
2266                                         DWC_ERROR
2267                                             ("EPDIS was not set during 1s\n");
2268                                         break;
2269                                 }
2270                         } while (!doepint.b.epdisabled);
2271
2272                         doepint.b.epdisabled = 1;
2273                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
2274                                         doepint, doepint.d32);
2275
2276                         dctl.d32 = 0;
2277                         dctl.b.cgoutnak = 1;
2278                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
2279                                          dctl, 0, dctl.d32);
2280                 } else {
2281                         depctl.d32 = 0;
2282                 }
2283
2284                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
2285                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
2286                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
2287                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
2288         }
2289
2290         if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
2291                 dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
2292                 dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
2293                 dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
2294
2295                 dev_if->rx_thr_length = params->rx_thr_length;
2296                 dev_if->tx_thr_length = params->tx_thr_length;
2297
2298                 dev_if->setup_desc_index = 0;
2299
2300                 dthrctl.d32 = 0;
2301                 dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
2302                 dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
2303                 dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
2304                 dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
2305                 dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
2306                 dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
2307
2308                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
2309                                 dthrctl.d32);
2310
2311                 DWC_DEBUGPL(DBG_CIL,
2312                             "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
2313                             dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
2314                             dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
2315                             dthrctl.b.rx_thr_len);
2316
2317         }
2318
2319         dwc_otg_enable_device_interrupts(core_if);
2320
2321         {
2322                 diepmsk_data_t msk = {.d32 = 0 };
2323                 msk.b.txfifoundrn = 1;
2324                 if (core_if->multiproc_int_enable) {
2325                         DWC_MODIFY_REG32(&dev_if->
2326                                          dev_global_regs->diepeachintmsk[0],
2327                                          msk.d32, msk.d32);
2328                 } else {
2329                         DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
2330                                          msk.d32, msk.d32);
2331                 }
2332         }
2333
2334         if (core_if->multiproc_int_enable) {
2335                 /* Set NAK on Babble */
2336                 dctl_data_t dctl = {.d32 = 0 };
2337                 dctl.b.nakonbble = 1;
2338                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
2339         }
2340 }
2341
2342 /**
2343  * This function enables the Host mode interrupts.
2344  *
2345  * @param core_if Programming view of DWC_otg controller
2346  */
2347 void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *core_if)
2348 {
2349         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2350         gintmsk_data_t intr_mask = {.d32 = 0 };
2351
2352         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
2353
2354         /* Disable all interrupts. */
2355         DWC_WRITE_REG32(&global_regs->gintmsk, 0);
2356
2357         /* Clear any pending interrupts. */
2358         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
2359
2360         /* Enable the common interrupts */
2361         dwc_otg_enable_common_interrupts(core_if);
2362
2363         /*
2364          * Enable host mode interrupts without disturbing common
2365          * interrupts.
2366          */
2367
2368         intr_mask.b.disconnect = 1;
2369         intr_mask.b.portintr = 1;
2370         intr_mask.b.hcintr = 1;
2371
2372         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
2373 }
2374
2375 /**
2376  * This function disables the Host Mode interrupts.
2377  *
2378  * @param core_if Programming view of DWC_otg controller
2379  */
2380 void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *core_if)
2381 {
2382         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2383         gintmsk_data_t intr_mask = {.d32 = 0 };
2384
2385         DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
2386
2387         /*
2388          * Disable host mode interrupts without disturbing common
2389          * interrupts.
2390          */
2391         intr_mask.b.sofintr = 1;
2392         intr_mask.b.portintr = 1;
2393         intr_mask.b.hcintr = 1;
2394         intr_mask.b.ptxfempty = 1;
2395         intr_mask.b.nptxfempty = 1;
2396
2397         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
2398         /* Clear pending interrupts */
2399         DWC_WRITE_REG32(&global_regs->gintsts, intr_mask.d32);
2400 }
2401
2402 /**
2403  * This function initializes the DWC_otg controller registers for
2404  * host mode.
2405  *
2406  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
2407  * request queues. Host channels are reset to ensure that they are ready for
2408  * performing transfers.
2409  *
2410  * @param core_if Programming view of DWC_otg controller
2411  *
2412  */
2413 void dwc_otg_core_host_init(dwc_otg_core_if_t *core_if)
2414 {
2415         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2416         dwc_otg_host_if_t *host_if = core_if->host_if;
2417         dwc_otg_core_params_t *params = core_if->core_params;
2418         hprt0_data_t hprt0 = {.d32 = 0 };
2419         fifosize_data_t nptxfifosize;
2420         fifosize_data_t ptxfifosize;
2421         /* uint16_t rxfsiz, nptxfsiz, hptxfsiz; */
2422         /* gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; */
2423         int i;
2424         hcchar_data_t hcchar;
2425         hcfg_data_t hcfg;
2426         hfir_data_t hfir;
2427         dwc_otg_hc_regs_t *hc_regs;
2428         int num_channels;
2429         gotgctl_data_t gotgctl = {.d32 = 0 };
2430         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2431         struct dwc_otg_platform_data *pldata;
2432         pldata = core_if->otg_dev->pldata;
2433
2434         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
2435
2436         /* Restart the Phy Clock */
2437         pcgcctl.b.stoppclk = 1;
2438         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
2439         dwc_udelay(10);
2440
2441         if ((core_if->otg_ver == 1) && (core_if->op_state == A_HOST)) {
2442                 DWC_PRINTF("Init: Port Power? op_state=%d\n",
2443                            core_if->op_state);
2444                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2445                 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2446                 if (hprt0.b.prtpwr == 0) {
2447                         hprt0.b.prtpwr = 1;
2448                         DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
2449                 }
2450         }
2451
2452         /* Initialize Host Configuration Register */
2453         init_fslspclksel(core_if);
2454         if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
2455                 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
2456                 hcfg.b.fslssupp = 1;
2457                 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
2458
2459         }
2460
2461         /* This bit allows dynamic reloading of the HFIR register
2462          * during runtime. This bit needs to be programmed during
2463          * initial configuration and its value must not be changed
2464          * during runtime.*/
2465         if (core_if->core_params->reload_ctl == 1) {
2466                 hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
2467                 hfir.b.hfirrldctrl = 1;
2468                 DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
2469         }
2470
2471         if (core_if->core_params->dma_desc_enable) {
2472                 uint8_t op_mode = core_if->hwcfg2.b.op_mode;
2473                 if (!
2474                     (core_if->hwcfg4.b.desc_dma
2475                      && (core_if->snpsid >= OTG_CORE_REV_2_90a)
2476                      && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
2477                          || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
2478                          || (op_mode ==
2479                              DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
2480                          || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
2481                          || (op_mode ==
2482                              DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
2483
2484                         DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
2485                                   "Either core version is below 2.90a or "
2486                                   "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
2487                                   "To run the driver in Buffer DMA host mode set dma_desc_enable "
2488                                   "module parameter to 0.\n");
2489                         return;
2490                 }
2491                 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
2492                 hcfg.b.descdma = 1;
2493                 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
2494         }
2495
2496         /* Configure data FIFO sizes */
2497         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
2498                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
2499                             core_if->total_fifo_size);
2500                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
2501                             params->host_rx_fifo_size);
2502                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
2503                             params->host_nperio_tx_fifo_size);
2504                 DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
2505                             params->host_perio_tx_fifo_size);
2506
2507                 /* Rx FIFO */
2508                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
2509                             DWC_READ_REG32(&global_regs->grxfsiz));
2510                 /* params->host_rx_fifo_size  */
2511                 DWC_WRITE_REG32(&global_regs->grxfsiz, 0x0200);
2512                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
2513                             DWC_READ_REG32(&global_regs->grxfsiz));
2514
2515                 /* Non-periodic Tx FIFO */
2516                 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
2517                             DWC_READ_REG32(&global_regs->gnptxfsiz));
2518                 /* params->host_nperio_tx_fifo_size */
2519                 nptxfifosize.b.depth = 0x0080;
2520                 /* params->host_rx_fifo_size */
2521                 nptxfifosize.b.startaddr = 0x0200;
2522                 DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
2523                 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
2524                             DWC_READ_REG32(&global_regs->gnptxfsiz));
2525
2526                 /* Periodic Tx FIFO */
2527                 DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
2528                             DWC_READ_REG32(&global_regs->hptxfsiz));
2529                 /* params->host_perio_tx_fifo_size */
2530                 ptxfifosize.b.depth = 0x0100;
2531                 /* nptxfifosize.b.startaddr + nptxfifosize.b.depth */
2532                 ptxfifosize.b.startaddr = 0x0280;
2533                 DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
2534                 DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
2535                             DWC_READ_REG32(&global_regs->hptxfsiz));
2536 #if 0
2537                 /* core_if->en_multiple_tx_fifo equals core_if->hwcfg4.b.ded_fifo_en,
2538                  * and ded_fifo_en is 1 in default
2539                  */
2540                 if (core_if->en_multiple_tx_fifo) {
2541                         /* Global DFIFOCFG calculation for Host mode
2542                          * - include RxFIFO, NPTXFIFO and HPTXFIFO */
2543                         gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
2544                         rxfsiz =
2545                             (DWC_READ_REG32(&global_regs->grxfsiz) &
2546                              0x0000ffff);
2547                         nptxfsiz =
2548                             (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
2549                         hptxfsiz =
2550                             (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
2551                         gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
2552                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
2553                 }
2554 #endif
2555         }
2556
2557         /* TODO - check this */
2558         /* Clear Host Set HNP Enable in the OTG Control Register */
2559         gotgctl.b.hstsethnpen = 1;
2560         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
2561         /* Make sure the FIFOs are flushed
2562          * all TX FIFOs */
2563         dwc_otg_flush_tx_fifo(core_if, 0x10);
2564         dwc_otg_flush_rx_fifo(core_if);
2565
2566         /* Clear Host Set HNP Enable in the OTG Control Register */
2567         gotgctl.b.hstsethnpen = 1;
2568         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
2569
2570         if (!core_if->core_params->dma_desc_enable) {
2571                 /* Flush out any leftover queued requests. */
2572                 num_channels = core_if->core_params->host_channels;
2573
2574                 for (i = 0; i < num_channels; i++) {
2575                         hc_regs = core_if->host_if->hc_regs[i];
2576                         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2577                         hcchar.b.chen = 0;
2578                         hcchar.b.chdis = 1;
2579                         hcchar.b.epdir = 0;
2580                         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2581                 }
2582
2583                 /* Halt all channels to put them into a known state. */
2584                 for (i = 0; i < num_channels; i++) {
2585                         int count = 0;
2586                         hc_regs = core_if->host_if->hc_regs[i];
2587                         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2588                         hcchar.b.chen = 1;
2589                         hcchar.b.chdis = 1;
2590                         hcchar.b.epdir = 0;
2591                         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2592                         DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__,
2593                                     i);
2594                         do {
2595                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2596                                 if (++count > 1000) {
2597                                         DWC_ERROR
2598                                             ("%s: Unable to clear halt on channel %d\n",
2599                                              __func__, i);
2600                                         break;
2601                                 }
2602                                 dwc_udelay(1);
2603                         } while (hcchar.b.chen);
2604                 }
2605         }
2606
2607         /* Turn on the vbus power. */
2608         if ((core_if->otg_ver == 0) && (core_if->op_state == A_HOST)) {
2609                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2610                 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2611                 if (hprt0.b.prtpwr == 0) {
2612                         hprt0.b.prtpwr = 1;
2613                         DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
2614                 }
2615                 if (pldata->power_enable)
2616                         pldata->power_enable(1);
2617         }
2618
2619         dwc_otg_enable_host_interrupts(core_if);
2620 }
2621
2622 /**
2623  * Prepares a host channel for transferring packets to/from a specific
2624  * endpoint. The HCCHARn register is set up with the characteristics specified
2625  * in _hc. Host channel interrupts that may need to be serviced while this
2626  * transfer is in progress are enabled.
2627  *
2628  * @param core_if Programming view of DWC_otg controller
2629  * @param hc Information needed to initialize the host channel
2630  */
2631 void dwc_otg_hc_init(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2632 {
2633         uint32_t intr_enable;
2634         hcintmsk_data_t hc_intr_mask;
2635         gintmsk_data_t gintmsk = {.d32 = 0 };
2636         hcchar_data_t hcchar;
2637         hcsplt_data_t hcsplt;
2638
2639         uint8_t hc_num = hc->hc_num;
2640         dwc_otg_host_if_t *host_if = core_if->host_if;
2641         dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
2642
2643         /* Clear old interrupt conditions for this host channel. */
2644         hc_intr_mask.d32 = 0xFFFFFFFF;
2645         hc_intr_mask.b.reserved14_31 = 0;
2646         DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
2647
2648         /* Enable channel interrupts required for this transfer. */
2649         hc_intr_mask.d32 = 0;
2650         hc_intr_mask.b.chhltd = 1;
2651         if (core_if->dma_enable) {
2652                 /* For Descriptor DMA mode core halts the channel
2653                  * on AHB error. Interrupt is not required */
2654                 if (!core_if->dma_desc_enable)
2655                         hc_intr_mask.b.ahberr = 1;
2656                 else {
2657                         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
2658                                 hc_intr_mask.b.xfercompl = 1;
2659                 }
2660
2661                 if (hc->error_state && !hc->do_split &&
2662                     hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
2663                         hc_intr_mask.b.ack = 1;
2664                         if (hc->ep_is_in) {
2665                                 hc_intr_mask.b.datatglerr = 1;
2666                                 if (hc->ep_type != DWC_OTG_EP_TYPE_INTR)
2667                                         hc_intr_mask.b.nak = 1;
2668                         }
2669                 }
2670         } else {
2671                 switch (hc->ep_type) {
2672                 case DWC_OTG_EP_TYPE_CONTROL:
2673                 case DWC_OTG_EP_TYPE_BULK:
2674                         hc_intr_mask.b.xfercompl = 1;
2675                         hc_intr_mask.b.stall = 1;
2676                         hc_intr_mask.b.xacterr = 1;
2677                         hc_intr_mask.b.datatglerr = 1;
2678                         if (hc->ep_is_in) {
2679                                 hc_intr_mask.b.bblerr = 1;
2680                         } else {
2681                                 hc_intr_mask.b.nak = 1;
2682                                 hc_intr_mask.b.nyet = 1;
2683                                 if (hc->do_ping)
2684                                         hc_intr_mask.b.ack = 1;
2685                         }
2686
2687                         if (hc->do_split) {
2688                                 hc_intr_mask.b.nak = 1;
2689                                 if (hc->complete_split)
2690                                         hc_intr_mask.b.nyet = 1;
2691                                 else
2692                                         hc_intr_mask.b.ack = 1;
2693                         }
2694
2695                         if (hc->error_state)
2696                                 hc_intr_mask.b.ack = 1;
2697                         break;
2698                 case DWC_OTG_EP_TYPE_INTR:
2699                         hc_intr_mask.b.xfercompl = 1;
2700                         hc_intr_mask.b.nak = 1;
2701                         hc_intr_mask.b.stall = 1;
2702                         hc_intr_mask.b.xacterr = 1;
2703                         hc_intr_mask.b.datatglerr = 1;
2704                         hc_intr_mask.b.frmovrun = 1;
2705
2706                         if (hc->ep_is_in)
2707                                 hc_intr_mask.b.bblerr = 1;
2708                         if (hc->error_state)
2709                                 hc_intr_mask.b.ack = 1;
2710                         if (hc->do_split) {
2711                                 if (hc->complete_split)
2712                                         hc_intr_mask.b.nyet = 1;
2713                                 else
2714                                         hc_intr_mask.b.ack = 1;
2715                         }
2716                         break;
2717                 case DWC_OTG_EP_TYPE_ISOC:
2718                         hc_intr_mask.b.xfercompl = 1;
2719                         hc_intr_mask.b.frmovrun = 1;
2720                         hc_intr_mask.b.ack = 1;
2721
2722                         if (hc->ep_is_in) {
2723                                 hc_intr_mask.b.xacterr = 1;
2724                                 hc_intr_mask.b.bblerr = 1;
2725                         }
2726                         break;
2727                 }
2728         }
2729         DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
2730
2731         /* Enable the top level host channel interrupt. */
2732         intr_enable = (1 << hc_num);
2733         DWC_MODIFY_REG32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
2734
2735         /* Make sure host channel interrupts are enabled. */
2736         gintmsk.b.hcintr = 1;
2737         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
2738
2739         /*
2740          * Program the HCCHARn register with the endpoint characteristics for
2741          * the current transfer.
2742          */
2743         hcchar.d32 = 0;
2744         hcchar.b.devaddr = hc->dev_addr;
2745         hcchar.b.epnum = hc->ep_num;
2746         hcchar.b.epdir = hc->ep_is_in;
2747         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2748         hcchar.b.eptype = hc->ep_type;
2749         hcchar.b.mps = hc->max_packet;
2750
2751         DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
2752
2753         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2754         DWC_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n", hcchar.b.devaddr);
2755         DWC_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n", hcchar.b.epnum);
2756         DWC_DEBUGPL(DBG_HCDV, "  Is In: %d\n", hcchar.b.epdir);
2757         DWC_DEBUGPL(DBG_HCDV, "  Is Low Speed: %d\n", hcchar.b.lspddev);
2758         DWC_DEBUGPL(DBG_HCDV, "  Ep Type: %d\n", hcchar.b.eptype);
2759         DWC_DEBUGPL(DBG_HCDV, "  Max Pkt: %d\n", hcchar.b.mps);
2760         DWC_DEBUGPL(DBG_HCDV, "  Multi Cnt: %d\n", hcchar.b.multicnt);
2761
2762         /*
2763          * Program the HCSPLIT register for SPLITs
2764          */
2765         hcsplt.d32 = 0;
2766         if (hc->do_split) {
2767                 DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
2768                             hc->hc_num,
2769                             hc->complete_split ? "CSPLIT" : "SSPLIT");
2770                 hcsplt.b.compsplt = hc->complete_split;
2771                 hcsplt.b.xactpos = hc->xact_pos;
2772                 hcsplt.b.hubaddr = hc->hub_addr;
2773                 hcsplt.b.prtaddr = hc->port_addr;
2774                 DWC_DEBUGPL(DBG_HCDV, "   comp split %d\n", hc->complete_split);
2775                 DWC_DEBUGPL(DBG_HCDV, "   xact pos %d\n", hc->xact_pos);
2776                 DWC_DEBUGPL(DBG_HCDV, "   hub addr %d\n", hc->hub_addr);
2777                 DWC_DEBUGPL(DBG_HCDV, "   port addr %d\n", hc->port_addr);
2778                 DWC_DEBUGPL(DBG_HCDV, "   is_in %d\n", hc->ep_is_in);
2779                 DWC_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n", hcchar.b.mps);
2780                 DWC_DEBUGPL(DBG_HCDV, "   xferlen: %d\n", hc->xfer_len);
2781         }
2782         DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
2783
2784 }
2785
2786 /**
2787  * Attempts to halt a host channel. This function should only be called in
2788  * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
2789  * normal circumstances in DMA mode, the controller halts the channel when the
2790  * transfer is complete or a condition occurs that requires application
2791  * intervention.
2792  *
2793  * In slave mode, checks for a free request queue entry, then sets the Channel
2794  * Enable and Channel Disable bits of the Host Channel Characteristics
2795  * register of the specified channel to intiate the halt. If there is no free
2796  * request queue entry, sets only the Channel Disable bit of the HCCHARn
2797  * register to flush requests for this channel. In the latter case, sets a
2798  * flag to indicate that the host channel needs to be halted when a request
2799  * queue slot is open.
2800  *
2801  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
2802  * HCCHARn register. The controller ensures there is space in the request
2803  * queue before submitting the halt request.
2804  *
2805  * Some time may elapse before the core flushes any posted requests for this
2806  * host channel and halts. The Channel Halted interrupt handler completes the
2807  * deactivation of the host channel.
2808  *
2809  * @param core_if Controller register interface.
2810  * @param hc Host channel to halt.
2811  * @param halt_status Reason for halting the channel.
2812  */
2813 void dwc_otg_hc_halt(dwc_otg_core_if_t *core_if,
2814                      dwc_hc_t *hc, dwc_otg_halt_status_e halt_status)
2815 {
2816         gnptxsts_data_t nptxsts;
2817         hptxsts_data_t hptxsts;
2818         hcchar_data_t hcchar;
2819         dwc_otg_hc_regs_t *hc_regs;
2820         dwc_otg_core_global_regs_t *global_regs;
2821         dwc_otg_host_global_regs_t *host_global_regs;
2822
2823         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2824         global_regs = core_if->core_global_regs;
2825         host_global_regs = core_if->host_if->host_global_regs;
2826
2827         DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
2828                    "halt_status = %d\n", halt_status);
2829
2830         if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
2831             halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
2832                 /*
2833                  * Disable all channel interrupts except Ch Halted. The QTD
2834                  * and QH state associated with this transfer has been cleared
2835                  * (in the case of URB_DEQUEUE), so the channel needs to be
2836                  * shut down carefully to prevent crashes.
2837                  */
2838                 hcintmsk_data_t hcintmsk;
2839                 hcintmsk.d32 = 0;
2840                 hcintmsk.b.chhltd = 1;
2841                 DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
2842
2843                 /*
2844                  * Make sure no other interrupts besides halt are currently
2845                  * pending. Handling another interrupt could cause a crash due
2846                  * to the QTD and QH state.
2847                  */
2848                 DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
2849
2850                 /*
2851                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
2852                  * even if the channel was already halted for some other
2853                  * reason.
2854                  */
2855                 hc->halt_status = halt_status;
2856
2857                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2858                 if (hcchar.b.chen == 0) {
2859                         /*
2860                          * The channel is either already halted or it hasn't
2861                          * started yet. In DMA mode, the transfer may halt if
2862                          * it finishes normally or a condition occurs that
2863                          * requires driver intervention. Don't want to halt
2864                          * the channel again. In either Slave or DMA mode,
2865                          * it's possible that the transfer has been assigned
2866                          * to a channel, but not started yet when an URB is
2867                          * dequeued. Don't want to halt a channel that hasn't
2868                          * started yet.
2869                          */
2870                         return;
2871                 }
2872         }
2873         if (hc->halt_pending) {
2874                 /*
2875                  * A halt has already been issued for this channel. This might
2876                  * happen when a transfer is aborted by a higher level in
2877                  * the stack.
2878                  */
2879 #ifdef DEBUG
2880                 DWC_PRINTF
2881                     ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
2882                      __func__, hc->hc_num);
2883
2884 #endif
2885                 return;
2886         }
2887
2888         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2889
2890         /* No need to set the bit in DDMA for disabling the channel
2891          * TODO check it everywhere channel is disabled */
2892         if (!core_if->core_params->dma_desc_enable)
2893                 hcchar.b.chen = 1;
2894         hcchar.b.chdis = 1;
2895
2896         if (!core_if->dma_enable) {
2897                 /* Check for space in the request queue to issue the halt. */
2898                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
2899                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
2900                         nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
2901                         if (nptxsts.b.nptxqspcavail == 0)
2902                                 hcchar.b.chen = 0;
2903                 } else {
2904                         hptxsts.d32 =
2905                             DWC_READ_REG32(&host_global_regs->hptxsts);
2906                         if ((hptxsts.b.ptxqspcavail == 0)
2907                             || (core_if->queuing_high_bandwidth)) {
2908                                 hcchar.b.chen = 0;
2909                         }
2910                 }
2911         }
2912         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2913
2914         hc->halt_status = halt_status;
2915
2916         if (hcchar.b.chen) {
2917                 hc->halt_pending = 1;
2918                 hc->halt_on_queue = 0;
2919         } else {
2920                 hc->halt_on_queue = 1;
2921         }
2922
2923         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2924         DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
2925         DWC_DEBUGPL(DBG_HCDV, "  halt_pending: %d\n", hc->halt_pending);
2926         DWC_DEBUGPL(DBG_HCDV, "  halt_on_queue: %d\n", hc->halt_on_queue);
2927         DWC_DEBUGPL(DBG_HCDV, "  halt_status: %d\n", hc->halt_status);
2928
2929         return;
2930 }
2931
2932 /**
2933  * Clears the transfer state for a host channel. This function is normally
2934  * called after a transfer is done and the host channel is being released.
2935  *
2936  * @param core_if Programming view of DWC_otg controller.
2937  * @param hc Identifies the host channel to clean up.
2938  */
2939 void dwc_otg_hc_cleanup(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
2940 {
2941         dwc_otg_hc_regs_t *hc_regs;
2942
2943         hc->xfer_started = 0;
2944
2945         /*
2946          * Clear channel interrupt enables and any unhandled channel interrupt
2947          * conditions.
2948          */
2949         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2950         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
2951         DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
2952 #ifdef DEBUG
2953         DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
2954 #endif
2955 }
2956
2957 /**
2958  * Sets the channel property that indicates in which frame a periodic transfer
2959  * should occur. This is always set to the _next_ frame. This function has no
2960  * effect on non-periodic transfers.
2961  *
2962  * @param core_if Programming view of DWC_otg controller.
2963  * @param hc Identifies the host channel to set up and its properties.
2964  * @param hcchar Current value of the HCCHAR register for the specified host
2965  * channel.
2966  */
2967 static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *core_if,
2968                                          dwc_hc_t *hc, hcchar_data_t *hcchar)
2969 {
2970         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2971             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2972                 hfnum_data_t hfnum;
2973                 hfnum.d32 =
2974                     DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
2975
2976                 /* 1 if _next_ frame is odd, 0 if it's even */
2977                 hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
2978 #ifdef DEBUG
2979                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
2980                     && !hc->complete_split) {
2981                         switch (hfnum.b.frnum & 0x7) {
2982                         case 7:
2983                                 core_if->hfnum_7_samples++;
2984                                 core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
2985                                 break;
2986                         case 0:
2987                                 core_if->hfnum_0_samples++;
2988                                 core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
2989                                 break;
2990                         default:
2991                                 core_if->hfnum_other_samples++;
2992                                 core_if->hfnum_other_frrem_accum +=
2993                                     hfnum.b.frrem;
2994                                 break;
2995                         }
2996                 }
2997 #endif
2998         }
2999 }
3000
3001 #ifdef DEBUG
3002 void hc_xfer_timeout(void *ptr)
3003 {
3004         hc_xfer_info_t *xfer_info = NULL;
3005         int hc_num = 0;
3006
3007         if (ptr)
3008                 xfer_info = (hc_xfer_info_t *) ptr;
3009
3010         if (!xfer_info->hc) {
3011                 DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
3012                 return;
3013         }
3014
3015         hc_num = xfer_info->hc->hc_num;
3016         DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
3017         DWC_WARN("      start_hcchar_val 0x%08x\n",
3018                  xfer_info->core_if->start_hcchar_val[hc_num]);
3019 }
3020 #endif
3021
3022 void ep_xfer_timeout(void *ptr)
3023 {
3024         ep_xfer_info_t *xfer_info = NULL;
3025         int ep_num = 0;
3026         dctl_data_t dctl = {.d32 = 0 };
3027         gintsts_data_t gintsts = {.d32 = 0 };
3028         gintmsk_data_t gintmsk = {.d32 = 0 };
3029
3030         if (ptr)
3031                 xfer_info = (ep_xfer_info_t *) ptr;
3032
3033         if (!xfer_info->ep) {
3034                 DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
3035                 return;
3036         }
3037
3038         ep_num = xfer_info->ep->num;
3039         DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
3040         /* Put the sate to 2 as it was time outed */
3041         xfer_info->state = 2;
3042
3043         dctl.d32 =
3044             DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
3045         gintsts.d32 =
3046             DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
3047         gintmsk.d32 =
3048             DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
3049
3050         if (!gintmsk.b.goutnakeff) {
3051                 /* Unmask it */
3052                 gintmsk.b.goutnakeff = 1;
3053                 DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
3054                                 gintmsk.d32);
3055
3056         }
3057
3058         if (!gintsts.b.goutnakeff)
3059                 dctl.b.sgoutnak = 1;
3060
3061         DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
3062                         dctl.d32);
3063
3064 }
3065
3066 void set_pid_isoc(dwc_hc_t *hc)
3067 {
3068         /* Set up the initial PID for the transfer. */
3069         if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
3070                 if (hc->ep_is_in) {
3071                         if (hc->multi_count == 1)
3072                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
3073                         else if (hc->multi_count == 2)
3074                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
3075                         else
3076                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
3077                 } else {
3078                         if (hc->multi_count == 1)
3079                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
3080                         else
3081                                 hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
3082                 }
3083         } else {
3084                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
3085         }
3086 }
3087
3088 /**
3089  * This function does the setup for a data transfer for a host channel and
3090  * starts the transfer. May be called in either Slave mode or DMA mode. In
3091  * Slave mode, the caller must ensure that there is sufficient space in the
3092  * request queue and Tx Data FIFO.
3093  *
3094  * For an OUT transfer in Slave mode, it loads a data packet into the
3095  * appropriate FIFO. If necessary, additional data packets will be loaded in
3096  * the Host ISR.
3097  *
3098  * For an IN transfer in Slave mode, a data packet is requested. The data
3099  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
3100  * additional data packets are requested in the Host ISR.
3101  *
3102  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
3103  * register along with a packet count of 1 and the channel is enabled. This
3104  * causes a single PING transaction to occur. Other fields in HCTSIZ are
3105  * simply set to 0 since no data transfer occurs in this case.
3106  *
3107  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
3108  * all the information required to perform the subsequent data transfer. In
3109  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
3110  * controller performs the entire PING protocol, then starts the data
3111  * transfer.
3112  *
3113  * @param core_if Programming view of DWC_otg controller.
3114  * @param hc Information needed to initialize the host channel. The xfer_len
3115  * value may be reduced to accommodate the max widths of the XferSize and
3116  * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
3117  * to reflect the final xfer_len value.
3118  */
3119 void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3120 {
3121         hcchar_data_t hcchar;
3122         hctsiz_data_t hctsiz;
3123         uint16_t num_packets;
3124         uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
3125         uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
3126         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3127
3128         hctsiz.d32 = 0;
3129
3130         if (hc->do_ping) {
3131                 if (!core_if->dma_enable) {
3132                         dwc_otg_hc_do_ping(core_if, hc);
3133                         hc->xfer_started = 1;
3134                         return;
3135                 } else {
3136                         hctsiz.b.dopng = 1;
3137                 }
3138         }
3139
3140         if (hc->do_split) {
3141                 num_packets = 1;
3142
3143                 if (hc->complete_split && !hc->ep_is_in) {
3144                         /* For CSPLIT OUT Transfer, set the size to 0 so the
3145                          * core doesn't expect any data written to the FIFO */
3146                         hc->xfer_len = 0;
3147                 } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
3148                         hc->xfer_len = hc->max_packet;
3149                 } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
3150                         hc->xfer_len = 188;
3151                 }
3152
3153                 hctsiz.b.xfersize = hc->xfer_len;
3154         } else {
3155                 /*
3156                  * Ensure that the transfer length and packet count will fit
3157                  * in the widths allocated for them in the HCTSIZn register.
3158                  */
3159                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
3160                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
3161                         /*
3162                          * Make sure the transfer size is no larger than one
3163                          * (micro)frame's worth of data. (A check was done
3164                          * when the periodic transfer was accepted to ensure
3165                          * that a (micro)frame's worth of data can be
3166                          * programmed into a channel.)
3167                          */
3168                         uint32_t max_periodic_len =
3169                             hc->multi_count * hc->max_packet;
3170                         if (hc->xfer_len > max_periodic_len)
3171                                 hc->xfer_len = max_periodic_len;
3172                 } else if (hc->xfer_len > max_hc_xfer_size) {
3173                         /* Make sure that xfer_len is a
3174                          * multiple of max packet size. */
3175                         hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
3176                 }
3177
3178                 if (hc->xfer_len > 0) {
3179                         num_packets =
3180                             (hc->xfer_len + hc->max_packet -
3181                              1) / hc->max_packet;
3182                         if (num_packets > max_hc_pkt_count) {
3183                                 num_packets = max_hc_pkt_count;
3184                                 hc->xfer_len = num_packets * hc->max_packet;
3185                         }
3186                 } else {
3187                         /* Need 1 packet for transfer length of 0. */
3188                         num_packets = 1;
3189                 }
3190
3191                 if (hc->ep_is_in) {
3192                         /* Always program an integral # of max packets for IN transfers. */
3193                         hc->xfer_len = num_packets * hc->max_packet;
3194                 }
3195
3196                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
3197                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
3198                         /*
3199                          * Make sure that the multi_count field matches the
3200                          * actual transfer length.
3201                          */
3202                         hc->multi_count = num_packets;
3203                 }
3204
3205                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
3206                         set_pid_isoc(hc);
3207
3208                 hctsiz.b.xfersize = hc->xfer_len;
3209         }
3210
3211         hc->start_pkt_count = num_packets;
3212         hctsiz.b.pktcnt = num_packets;
3213         hctsiz.b.pid = hc->data_pid_start;
3214         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
3215
3216         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3217         DWC_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
3218         DWC_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n", hctsiz.b.pktcnt);
3219         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
3220
3221         if (core_if->dma_enable) {
3222                 dwc_dma_t dma_addr;
3223                 if (hc->align_buff)
3224                         dma_addr = hc->align_buff;
3225                 else
3226                         dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
3227                 DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
3228         }
3229
3230         /* Start the split */
3231         if (hc->do_split) {
3232                 hcsplt_data_t hcsplt;
3233                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
3234                 hcsplt.b.spltena = 1;
3235                 DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
3236         }
3237
3238         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3239         hcchar.b.multicnt = hc->multi_count;
3240         hc_set_even_odd_frame(core_if, hc, &hcchar);
3241 #ifdef DEBUG
3242         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
3243         if (hcchar.b.chdis) {
3244                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
3245                          __func__, hc->hc_num, hcchar.d32);
3246         }
3247 #endif
3248
3249         /* Set host channel enable after all other setup is complete. */
3250         hcchar.b.chen = 1;
3251         hcchar.b.chdis = 0;
3252         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3253
3254         hc->xfer_started = 1;
3255         hc->requests++;
3256
3257         if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
3258                 /* Load OUT packet into the appropriate Tx FIFO. */
3259                 dwc_otg_hc_write_packet(core_if, hc);
3260         }
3261 #ifdef DEBUG
3262         if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
3263                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
3264                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
3265
3266                 /* Start a timer for this transfer. */
3267                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
3268         }
3269 #endif
3270 }
3271
3272 /**
3273  * This function does the setup for a data transfer for a host channel
3274  * and starts the transfer in Descriptor DMA mode.
3275  *
3276  * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
3277  * Sets PID and NTD values. For periodic transfers
3278  * initializes SCHED_INFO field with micro-frame bitmap.
3279  *
3280  * Initializes HCDMA register with descriptor list address and CTD value
3281  * then starts the transfer via enabling the channel.
3282  *
3283  * @param core_if Programming view of DWC_otg controller.
3284  * @param hc Information needed to initialize the host channel.
3285  */
3286 void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3287 {
3288         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3289         hcchar_data_t hcchar;
3290         hctsiz_data_t hctsiz;
3291         hcdma_data_t hcdma;
3292
3293         hctsiz.d32 = 0;
3294
3295         if (hc->do_ping)
3296                 hctsiz.b_ddma.dopng = 1;
3297
3298         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
3299                 set_pid_isoc(hc);
3300
3301         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
3302         hctsiz.b_ddma.pid = hc->data_pid_start;
3303         /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
3304         hctsiz.b_ddma.ntd = hc->ntd - 1;
3305         /* Non-zero only for high-speed interrupt endpoints */
3306         hctsiz.b_ddma.schinfo = hc->schinfo;
3307
3308         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3309         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
3310         DWC_DEBUGPL(DBG_HCDV, "  NTD: %d\n", hctsiz.b_ddma.ntd);
3311
3312         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
3313
3314         hcdma.d32 = 0;
3315         hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
3316
3317         /* Always start from first descriptor. */
3318         hcdma.b.ctd = 0;
3319         DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
3320
3321         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3322         hcchar.b.multicnt = hc->multi_count;
3323
3324 #ifdef DEBUG
3325         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
3326         if (hcchar.b.chdis) {
3327                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
3328                          __func__, hc->hc_num, hcchar.d32);
3329         }
3330 #endif
3331
3332         /* Set host channel enable after all other setup is complete. */
3333         hcchar.b.chen = 1;
3334         hcchar.b.chdis = 0;
3335
3336         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3337
3338         hc->xfer_started = 1;
3339         hc->requests++;
3340
3341 #ifdef DEBUG
3342         if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
3343             && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
3344                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
3345                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
3346                 /* Start a timer for this transfer. */
3347                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
3348         }
3349 #endif
3350
3351 }
3352
3353 /**
3354  * This function continues a data transfer that was started by previous call
3355  * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
3356  * sufficient space in the request queue and Tx Data FIFO. This function
3357  * should only be called in Slave mode. In DMA mode, the controller acts
3358  * autonomously to complete transfers programmed to a host channel.
3359  *
3360  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
3361  * if there is any data remaining to be queued. For an IN transfer, another
3362  * data packet is always requested. For the SETUP phase of a control transfer,
3363  * this function does nothing.
3364  *
3365  * @return 1 if a new request is queued, 0 if no more requests are required
3366  * for this transfer.
3367  */
3368 int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3369 {
3370         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3371
3372         if (hc->do_split) {
3373                 /* SPLITs always queue just once per channel */
3374                 return 0;
3375         } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
3376                 /* SETUPs are queued only once since they can't be NAKed. */
3377                 return 0;
3378         } else if (hc->ep_is_in) {
3379                 /*
3380                  * Always queue another request for other IN transfers. If
3381                  * back-to-back INs are issued and NAKs are received for both,
3382                  * the driver may still be processing the first NAK when the
3383                  * second NAK is received. When the interrupt handler clears
3384                  * the NAK interrupt for the first NAK, the second NAK will
3385                  * not be seen. So we can't depend on the NAK interrupt
3386                  * handler to requeue a NAKed request. Instead, IN requests
3387                  * are issued each time this function is called. When the
3388                  * transfer completes, the extra requests for the channel will
3389                  * be flushed.
3390                  */
3391                 hcchar_data_t hcchar;
3392                 dwc_otg_hc_regs_t *hc_regs =
3393                     core_if->host_if->hc_regs[hc->hc_num];
3394
3395                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3396                 hc_set_even_odd_frame(core_if, hc, &hcchar);
3397                 hcchar.b.chen = 1;
3398                 hcchar.b.chdis = 0;
3399                 DWC_DEBUGPL(DBG_HCDV, "  IN xfer: hcchar = 0x%08x\n",
3400                             hcchar.d32);
3401                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3402                 hc->requests++;
3403                 return 1;
3404         } else {
3405                 /* OUT transfers. */
3406                 if (hc->xfer_count < hc->xfer_len) {
3407                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
3408                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
3409                                 hcchar_data_t hcchar;
3410                                 dwc_otg_hc_regs_t *hc_regs;
3411                                 hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3412                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3413                                 hc_set_even_odd_frame(core_if, hc, &hcchar);
3414                         }
3415
3416                         /* Load OUT packet into the appropriate Tx FIFO. */
3417                         dwc_otg_hc_write_packet(core_if, hc);
3418                         hc->requests++;
3419                         return 1;
3420                 } else {
3421                         return 0;
3422                 }
3423         }
3424 }
3425
3426 /**
3427  * Starts a PING transfer. This function should only be called in Slave mode.
3428  * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
3429  */
3430 void dwc_otg_hc_do_ping(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3431 {
3432         hcchar_data_t hcchar;
3433         hctsiz_data_t hctsiz;
3434         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3435
3436         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3437
3438         hctsiz.d32 = 0;
3439         hctsiz.b.dopng = 1;
3440         hctsiz.b.pktcnt = 1;
3441         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
3442
3443         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3444         hcchar.b.chen = 1;
3445         hcchar.b.chdis = 0;
3446         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3447 }
3448
3449 /*
3450  * This function writes a packet into the Tx FIFO associated with the Host
3451  * Channel. For a channel associated with a non-periodic EP, the non-periodic
3452  * Tx FIFO is written. For a channel associated with a periodic EP, the
3453  * periodic Tx FIFO is written. This function should only be called in Slave
3454  * mode.
3455  *
3456  * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
3457  * then number of bytes written to the Tx FIFO.
3458  */
3459 void dwc_otg_hc_write_packet(dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
3460 {
3461         uint32_t i;
3462         uint32_t remaining_count;
3463         uint32_t byte_count;
3464         uint32_t dword_count;
3465
3466         uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
3467         uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
3468
3469         remaining_count = hc->xfer_len - hc->xfer_count;
3470         if (remaining_count > hc->max_packet)
3471                 byte_count = hc->max_packet;
3472         else
3473                 byte_count = remaining_count;
3474
3475         dword_count = (byte_count + 3) / 4;
3476
3477         if ((((unsigned long)data_buff) & 0x3) == 0) {
3478                 /* xfer_buff is DWORD aligned. */
3479                 for (i = 0; i < dword_count; i++, data_buff++)
3480                         DWC_WRITE_REG32(data_fifo, *data_buff);
3481         } else {
3482                 /* xfer_buff is not DWORD aligned. */
3483                 for (i = 0; i < dword_count; i++, data_buff++) {
3484                         uint32_t data;
3485                         data =
3486                             (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
3487                              16 | data_buff[3] << 24);
3488                         DWC_WRITE_REG32(data_fifo, data);
3489                 }
3490         }
3491
3492         hc->xfer_count += byte_count;
3493         hc->xfer_buff += byte_count;
3494 }
3495
3496 /**
3497  * Gets the current USB frame number. This is the frame number from the last
3498  * SOF packet.
3499  */
3500 uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *core_if)
3501 {
3502         dsts_data_t dsts;
3503         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
3504
3505         /* read current frame/microframe number from DSTS register */
3506         return dsts.b.soffn;
3507 }
3508
3509 /**
3510  * Calculates and gets the frame Interval value of HFIR register according PHY
3511  * type and speed.The application can modify a value of HFIR register only after
3512  * the Port Enable bit of the Host Port Control and Status register
3513  * (HPRT.PrtEnaPort) has been set.
3514 */
3515
3516 uint32_t calc_frame_interval(dwc_otg_core_if_t *core_if)
3517 {
3518         gusbcfg_data_t usbcfg;
3519         hwcfg2_data_t hwcfg2;
3520         hprt0_data_t hprt0;
3521         int clock = 60;         /* default value */
3522         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
3523         hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
3524         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
3525         if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
3526                 clock = 60;
3527         if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
3528                 clock = 48;
3529         if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3530             !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
3531                 clock = 30;
3532         if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3533             !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
3534                 clock = 60;
3535         if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3536             !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
3537                 clock = 48;
3538         if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
3539                 clock = 48;
3540         if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
3541                 clock = 48;
3542         if (hprt0.b.prtspd == 0)
3543                 /* High speed case */
3544                 return 125 * clock;
3545         else
3546                 /* FS/LS case */
3547                 return 1000 * clock;
3548 }
3549
3550 /**
3551  * This function reads a setup packet from the Rx FIFO into the destination
3552  * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
3553  * Interrupt routine when a SETUP packet has been received in Slave mode.
3554  *
3555  * @param core_if Programming view of DWC_otg controller.
3556  * @param dest Destination buffer for packet data.
3557  */
3558 void dwc_otg_read_setup_packet(dwc_otg_core_if_t *core_if, uint32_t *dest)
3559 {
3560         device_grxsts_data_t status;
3561         /* Get the 8 bytes of a setup transaction data */
3562
3563         /* Pop 2 DWORDS off the receive data FIFO into memory */
3564         dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
3565         dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
3566         if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
3567                 status.d32 =
3568                     DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
3569                 DWC_DEBUGPL(DBG_ANY,
3570                             "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
3571                             status.b.epnum, status.b.bcnt, status.b.pktsts,
3572                             status.b.fn, status.b.fn);
3573         }
3574 }
3575
3576 /**
3577  * This function enables EP0 OUT to receive SETUP packets and configures EP0
3578  * IN for transmitting packets. It is normally called when the
3579  * "Enumeration Done" interrupt occurs.
3580  *
3581  * @param core_if Programming view of DWC_otg controller.
3582  * @param ep The EP0 data.
3583  */
3584 void dwc_otg_ep0_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3585 {
3586         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3587         dsts_data_t dsts;
3588         depctl_data_t diepctl;
3589         depctl_data_t doepctl;
3590         dctl_data_t dctl = {.d32 = 0 };
3591
3592         ep->stp_rollover = 0;
3593         /* Read the Device Status and Endpoint 0 Control registers */
3594         dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
3595         diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
3596         doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
3597
3598         /* Set the MPS of the IN EP based on the enumeration speed */
3599         switch (dsts.b.enumspd) {
3600         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
3601         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
3602         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
3603                 diepctl.b.mps = DWC_DEP0CTL_MPS_64;
3604                 break;
3605         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
3606                 diepctl.b.mps = DWC_DEP0CTL_MPS_8;
3607                 break;
3608         }
3609
3610         DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
3611
3612         /* Enable OUT EP for receive */
3613         if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
3614                 doepctl.b.epena = 1;
3615                 DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
3616         }
3617 #ifdef VERBOSE
3618         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
3619                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
3620         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
3621                     DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
3622 #endif
3623         dctl.b.cgnpinnak = 1;
3624
3625         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
3626         DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
3627                     DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
3628
3629 }
3630
3631 /**
3632  * This function activates an EP.  The Device EP control register for
3633  * the EP is configured as defined in the ep structure. Note: This
3634  * function is not used for EP0.
3635  *
3636  * @param core_if Programming view of DWC_otg controller.
3637  * @param ep The EP to activate.
3638  */
3639 void dwc_otg_ep_activate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3640 {
3641         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3642         depctl_data_t depctl;
3643         volatile uint32_t *addr;
3644         daint_data_t daintmsk = {.d32 = 0 };
3645         dcfg_data_t dcfg;
3646         uint8_t i;
3647
3648         DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
3649                     (ep->is_in ? "IN" : "OUT"));
3650
3651 #ifdef DWC_UTE_PER_IO
3652         ep->xiso_frame_num = 0xFFFFFFFF;
3653         ep->xiso_active_xfers = 0;
3654         ep->xiso_queued_xfers = 0;
3655 #endif
3656         /* Read DEPCTLn register */
3657         if (ep->is_in == 1) {
3658                 addr = &dev_if->in_ep_regs[ep->num]->diepctl;
3659                 daintmsk.ep.in = 1 << ep->num;
3660         } else {
3661                 addr = &dev_if->out_ep_regs[ep->num]->doepctl;
3662                 daintmsk.ep.out = 1 << ep->num;
3663         }
3664
3665         /* If the EP is already active don't change the EP Control
3666          * register. */
3667         depctl.d32 = DWC_READ_REG32(addr);
3668         if (!depctl.b.usbactep) {
3669                 depctl.b.mps = ep->maxpacket;
3670                 depctl.b.eptype = ep->type;
3671                 depctl.b.txfnum = ep->tx_fifo_num;
3672
3673                 if (ep->type == DWC_OTG_EP_TYPE_ISOC)
3674                         depctl.b.setd0pid = 1;
3675                 else
3676                         depctl.b.setd0pid = 1;
3677
3678                 depctl.b.usbactep = 1;
3679
3680                 /* Update nextep_seq array and EPMSCNT in DCFG */
3681                 if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) {/*NP IN EP*/
3682                         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3683                                 if (core_if->nextep_seq[i] ==
3684                                     core_if->first_in_nextep_seq)
3685                                         break;
3686                         }
3687                         core_if->nextep_seq[i] = ep->num;
3688                         core_if->nextep_seq[ep->num] =
3689                             core_if->first_in_nextep_seq;
3690                         depctl.b.nextep = core_if->nextep_seq[ep->num];
3691                         dcfg.d32 =
3692                             DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
3693                         dcfg.b.epmscnt++;
3694                         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg,
3695                                         dcfg.d32);
3696
3697                         DWC_DEBUGPL(DBG_PCDV,
3698                                     "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
3699                                     __func__, core_if->first_in_nextep_seq);
3700                         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3701                                 DWC_DEBUGPL(DBG_PCDV, "%2d\n",
3702                                             core_if->nextep_seq[i]);
3703                         }
3704
3705                 }
3706
3707                 DWC_WRITE_REG32(addr, depctl.d32);
3708                 DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
3709         }
3710
3711         /* Enable the Interrupt for this EP */
3712         if (core_if->multiproc_int_enable) {
3713                 if (ep->is_in == 1) {
3714                         diepmsk_data_t diepmsk = {.d32 = 0 };
3715                         diepmsk.b.xfercompl = 1;
3716                         diepmsk.b.timeout = 1;
3717                         diepmsk.b.epdisabled = 1;
3718                         diepmsk.b.ahberr = 1;
3719                         diepmsk.b.intknepmis = 1;
3720                         if (!core_if->en_multiple_tx_fifo
3721                             && core_if->dma_enable)
3722                                 diepmsk.b.intknepmis = 0;
3723                         diepmsk.b.txfifoundrn = 1;
3724                         if (ep->type == DWC_OTG_EP_TYPE_ISOC)
3725                                 diepmsk.b.nak = 1;
3726
3727                         /*
3728                         if (core_if->dma_desc_enable) {
3729                                 diepmsk.b.bna = 1;
3730                         }
3731
3732                         if (core_if->dma_enable) {
3733                                 doepmsk.b.nak = 1;
3734                         }
3735                         */
3736                         DWC_WRITE_REG32(&dev_if->
3737                                         dev_global_regs->diepeachintmsk[ep->
3738                                                                         num],
3739                                         diepmsk.d32);
3740
3741                 } else {
3742                         doepmsk_data_t doepmsk = {.d32 = 0 };
3743                         doepmsk.b.xfercompl = 1;
3744                         doepmsk.b.ahberr = 1;
3745                         doepmsk.b.epdisabled = 1;
3746                         if (ep->type == DWC_OTG_EP_TYPE_ISOC)
3747                                 doepmsk.b.outtknepdis = 1;
3748
3749                         /*
3750                         if (core_if->dma_desc_enable) {
3751                                 doepmsk.b.bna = 1;
3752                         }
3753                         doepmsk.b.babble = 1;
3754                         doepmsk.b.nyet = 1;
3755                         doepmsk.b.nak = 1;
3756                         */
3757
3758                         DWC_WRITE_REG32(&dev_if->
3759                                         dev_global_regs->doepeachintmsk[ep->
3760                                                                         num],
3761                                         doepmsk.d32);
3762                 }
3763                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
3764                                  0, daintmsk.d32);
3765         } else {
3766                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3767                         if (ep->is_in) {
3768                                 diepmsk_data_t diepmsk = {.d32 = 0 };
3769                                 diepmsk.b.nak = 1;
3770                                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->
3771                                                  diepmsk, 0, diepmsk.d32);
3772                         } else {
3773                                 doepmsk_data_t doepmsk = {.d32 = 0 };
3774                                 doepmsk.b.outtknepdis = 1;
3775                                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->
3776                                                  doepmsk, 0, doepmsk.d32);
3777                         }
3778                 }
3779                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
3780                                  0, daintmsk.d32);
3781         }
3782
3783         DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
3784                     DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
3785
3786         ep->stall_clear_flag = 0;
3787
3788         return;
3789 }
3790
3791 /**
3792  * This function deactivates an EP. This is done by clearing the USB Active
3793  * EP bit in the Device EP control register. Note: This function is not used
3794  * for EP0. EP0 cannot be deactivated.
3795  *
3796  * @param core_if Programming view of DWC_otg controller.
3797  * @param ep The EP to deactivate.
3798  */
3799 void dwc_otg_ep_deactivate(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3800 {
3801         depctl_data_t depctl = {.d32 = 0 };
3802         volatile uint32_t *addr;
3803         daint_data_t daintmsk = {.d32 = 0 };
3804         dcfg_data_t dcfg;
3805         uint8_t i = 0;
3806
3807 #ifdef DWC_UTE_PER_IO
3808         ep->xiso_frame_num = 0xFFFFFFFF;
3809         ep->xiso_active_xfers = 0;
3810         ep->xiso_queued_xfers = 0;
3811 #endif
3812
3813         /* Read DEPCTLn register */
3814         if (ep->is_in == 1) {
3815                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
3816                 daintmsk.ep.in = 1 << ep->num;
3817         } else {
3818                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
3819                 daintmsk.ep.out = 1 << ep->num;
3820         }
3821
3822         depctl.d32 = DWC_READ_REG32(addr);
3823
3824         depctl.b.usbactep = 0;
3825
3826         /* Update nextep_seq array and EPMSCNT in DCFG
3827          * NP EP IN */
3828         if (!(depctl.b.eptype & 1) && ep->is_in == 1) {
3829                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3830                         if (core_if->nextep_seq[i] == ep->num)
3831                                 break;
3832                 }
3833                 core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
3834                 if (core_if->first_in_nextep_seq == ep->num)
3835                         core_if->first_in_nextep_seq = i;
3836                 core_if->nextep_seq[ep->num] = 0xff;
3837                 depctl.b.nextep = 0;
3838                 dcfg.d32 =
3839                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
3840                 dcfg.b.epmscnt--;
3841                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
3842                                 dcfg.d32);
3843
3844                 DWC_DEBUGPL(DBG_PCDV,
3845                             "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
3846                             __func__, core_if->first_in_nextep_seq);
3847                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++)
3848                         DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
3849         }
3850
3851         if (ep->is_in == 1)
3852                 depctl.b.txfnum = 0;
3853
3854         if (core_if->dma_desc_enable)
3855                 depctl.b.epdis = 1;
3856
3857         DWC_WRITE_REG32(addr, depctl.d32);
3858         depctl.d32 = DWC_READ_REG32(addr);
3859         if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
3860             && depctl.b.epena) {
3861                 depctl_data_t depctl = {.d32 = 0 };
3862                 if (ep->is_in) {
3863                         diepint_data_t diepint = {.d32 = 0 };
3864
3865                         depctl.b.snak = 1;
3866                         DWC_WRITE_REG32(&core_if->dev_if->
3867                                         in_ep_regs[ep->num]->diepctl,
3868                                         depctl.d32);
3869                         do {
3870                                 dwc_udelay(10);
3871                                 diepint.d32 =
3872                                     DWC_READ_REG32(&core_if->dev_if->
3873                                                    in_ep_regs[ep->
3874                                                               num]->diepint);
3875                         } while (!diepint.b.inepnakeff);
3876                         diepint.b.inepnakeff = 1;
3877                         DWC_WRITE_REG32(&core_if->dev_if->
3878                                         in_ep_regs[ep->num]->diepint,
3879                                         diepint.d32);
3880                         depctl.d32 = 0;
3881                         depctl.b.epdis = 1;
3882                         DWC_WRITE_REG32(&core_if->dev_if->
3883                                         in_ep_regs[ep->num]->diepctl,
3884                                         depctl.d32);
3885                         do {
3886                                 dwc_udelay(10);
3887                                 diepint.d32 =
3888                                     DWC_READ_REG32(&core_if->dev_if->
3889                                                    in_ep_regs[ep->
3890                                                               num]->diepint);
3891                         } while (!diepint.b.epdisabled);
3892                         diepint.b.epdisabled = 1;
3893                         DWC_WRITE_REG32(&core_if->dev_if->
3894                                         in_ep_regs[ep->num]->diepint,
3895                                         diepint.d32);
3896                 } else {
3897                         dctl_data_t dctl = {.d32 = 0 };
3898                         gintmsk_data_t gintsts = {.d32 = 0 };
3899                         doepint_data_t doepint = {.d32 = 0 };
3900                         dctl.b.sgoutnak = 1;
3901                         DWC_MODIFY_REG32(&core_if->dev_if->
3902                                          dev_global_regs->dctl, 0, dctl.d32);
3903                         do {
3904                                 dwc_udelay(10);
3905                                 gintsts.d32 =
3906                                     DWC_READ_REG32(&core_if->core_global_regs->
3907                                                    gintsts);
3908                         } while (!gintsts.b.goutnakeff);
3909                         gintsts.d32 = 0;
3910                         gintsts.b.goutnakeff = 1;
3911                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,
3912                                         gintsts.d32);
3913
3914                         depctl.d32 = 0;
3915                         depctl.b.epdis = 1;
3916                         depctl.b.snak = 1;
3917                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
3918                                         doepctl, depctl.d32);
3919                         do {
3920                                 dwc_udelay(10);
3921                                 doepint.d32 =
3922                                     DWC_READ_REG32(&core_if->
3923                                                    dev_if->out_ep_regs[ep->
3924                                                                        num]->
3925                                                    doepint);
3926                         } while (!doepint.b.epdisabled);
3927
3928                         doepint.b.epdisabled = 1;
3929                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
3930                                         doepint, doepint.d32);
3931
3932                         dctl.d32 = 0;
3933                         dctl.b.cgoutnak = 1;
3934                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
3935                                          dctl, 0, dctl.d32);
3936                 }
3937         }
3938
3939         /* Disable the Interrupt for this EP */
3940         if (core_if->multiproc_int_enable) {
3941                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
3942                                  daintmsk.d32, 0);
3943
3944                 if (ep->is_in == 1) {
3945                         DWC_WRITE_REG32(&core_if->dev_if->
3946                                         dev_global_regs->diepeachintmsk[ep->
3947                                                                         num],
3948                                         0);
3949                 } else {
3950                         DWC_WRITE_REG32(&core_if->dev_if->
3951                                         dev_global_regs->doepeachintmsk[ep->
3952                                                                         num],
3953                                         0);
3954                 }
3955         } else {
3956                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
3957                                  daintmsk.d32, 0);
3958         }
3959
3960 }
3961
3962 /**
3963  * This function initializes dma descriptor chain.
3964  *
3965  * @param core_if Programming view of DWC_otg controller.
3966  * @param ep The EP to start the transfer on.
3967  */
3968 static void init_dma_desc_chain(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
3969 {
3970         dwc_otg_dev_dma_desc_t *dma_desc;
3971         uint32_t offset;
3972         uint32_t xfer_est;
3973         int i;
3974         unsigned maxxfer_local, total_len;
3975
3976         if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
3977             (ep->maxpacket % 4)) {
3978                 maxxfer_local = ep->maxpacket;
3979                 total_len = ep->xfer_len;
3980         } else {
3981                 maxxfer_local = ep->maxxfer;
3982                 total_len = ep->total_len;
3983         }
3984
3985         ep->desc_cnt = (total_len / maxxfer_local) +
3986             ((total_len % maxxfer_local) ? 1 : 0);
3987
3988         if (!ep->desc_cnt)
3989                 ep->desc_cnt = 1;
3990
3991         if (ep->desc_cnt > MAX_DMA_DESC_CNT)
3992                 ep->desc_cnt = MAX_DMA_DESC_CNT;
3993
3994         dma_desc = ep->desc_addr;
3995         if (maxxfer_local == ep->maxpacket) {
3996                 if ((total_len % maxxfer_local) &&
3997                     (total_len / maxxfer_local < MAX_DMA_DESC_CNT)) {
3998                         xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
3999                             (total_len % maxxfer_local);
4000                 } else
4001                         xfer_est = ep->desc_cnt * maxxfer_local;
4002         } else
4003                 xfer_est = total_len;
4004         offset = 0;
4005         for (i = 0; i < ep->desc_cnt; ++i) {
4006                 /** DMA Descriptor Setup */
4007                 if (xfer_est > maxxfer_local) {
4008                         dma_desc->status.b.bs = BS_HOST_BUSY;
4009                         dma_desc->status.b.l = 0;
4010                         dma_desc->status.b.ioc = 0;
4011                         dma_desc->status.b.sp = 0;
4012                         dma_desc->status.b.bytes = maxxfer_local;
4013                         dma_desc->buf = ep->dma_addr + offset;
4014                         dma_desc->status.b.sts = 0;
4015                         dma_desc->status.b.bs = BS_HOST_READY;
4016
4017                         xfer_est -= maxxfer_local;
4018                         offset += maxxfer_local;
4019                 } else {
4020                         dma_desc->status.b.bs = BS_HOST_BUSY;
4021                         dma_desc->status.b.l = 1;
4022                         dma_desc->status.b.ioc = 1;
4023                         if (ep->is_in) {
4024                                 dma_desc->status.b.sp =
4025                                     (xfer_est %
4026                                      ep->
4027                                      maxpacket) ? 1 : ((ep->sent_zlp) ? 1 : 0);
4028                                 dma_desc->status.b.bytes = xfer_est;
4029                         } else {
4030                                 if (maxxfer_local == ep->maxpacket)
4031                                         dma_desc->status.b.bytes = xfer_est;
4032                                 else
4033                                         dma_desc->status.b.bytes =
4034                                             xfer_est +
4035                                             ((4 - (xfer_est & 0x3)) & 0x3);
4036                         }
4037
4038                         dma_desc->buf = ep->dma_addr + offset;
4039                         dma_desc->status.b.sts = 0;
4040                         dma_desc->status.b.bs = BS_HOST_READY;
4041                 }
4042                 dma_desc++;
4043         }
4044 }
4045
4046 /**
4047  * This function is called when to write ISOC data into appropriate dedicated
4048  * periodic FIFO.
4049  */
4050 static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t *core_if,
4051                                   dwc_ep_t *dwc_ep)
4052 {
4053         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
4054         dwc_otg_dev_in_ep_regs_t *ep_regs;
4055         dtxfsts_data_t txstatus = {.d32 = 0 };
4056         uint32_t len = 0;
4057         int epnum = dwc_ep->num;
4058         int dwords;
4059
4060         DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
4061
4062         ep_regs = core_if->dev_if->in_ep_regs[epnum];
4063
4064         len = dwc_ep->xfer_len - dwc_ep->xfer_count;
4065
4066         if (len > dwc_ep->maxpacket)
4067                 len = dwc_ep->maxpacket;
4068
4069         dwords = (len + 3) / 4;
4070
4071         /* While there is space in the queue and space in the FIFO and
4072          * More data to tranfer, Write packets to the Tx FIFO */
4073         txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
4074         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
4075
4076         while (txstatus.b.txfspcavail > dwords &&
4077                dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
4078                 /* Write the FIFO */
4079                 dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
4080
4081                 len = dwc_ep->xfer_len - dwc_ep->xfer_count;
4082                 if (len > dwc_ep->maxpacket)
4083                         len = dwc_ep->maxpacket;
4084
4085                 dwords = (len + 3) / 4;
4086                 txstatus.d32 =
4087                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
4088                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
4089                             txstatus.d32);
4090         }
4091
4092         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
4093                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
4094
4095         return 1;
4096 }
4097
4098 /**
4099  * This function does the setup for a data transfer for an EP and
4100  * starts the transfer. For an IN transfer, the packets will be
4101  * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
4102  * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
4103  *
4104  * @param core_if Programming view of DWC_otg controller.
4105  * @param ep The EP to start the transfer on.
4106  */
4107
4108 void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4109 {
4110         depctl_data_t depctl;
4111         deptsiz_data_t deptsiz;
4112         gintmsk_data_t intr_mask = {.d32 = 0 };
4113
4114         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
4115         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
4116                     "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
4117                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
4118                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
4119                     ep->total_len);
4120         /* IN endpoint */
4121         if (ep->is_in == 1) {
4122                 dwc_otg_dev_in_ep_regs_t *in_regs =
4123                     core_if->dev_if->in_ep_regs[ep->num];
4124
4125                 gnptxsts_data_t gtxstatus;
4126
4127                 gtxstatus.d32 =
4128                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
4129
4130                 if (core_if->en_multiple_tx_fifo == 0
4131                     && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
4132 #ifdef DEBUG
4133                         DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
4134 #endif
4135                         return;
4136                 }
4137
4138                 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
4139                 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
4140
4141                 if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
4142                         ep->xfer_len +=
4143                             (ep->maxxfer <
4144                              (ep->total_len -
4145                               ep->xfer_len)) ? ep->maxxfer : (ep->total_len -
4146                                                               ep->xfer_len);
4147                 else
4148                         ep->xfer_len +=
4149                             (MAX_PKT_CNT * ep->maxpacket <
4150                              (ep->total_len -
4151                               ep->xfer_len)) ? MAX_PKT_CNT *
4152                             ep->maxpacket : (ep->total_len - ep->xfer_len);
4153
4154                 /* Zero Length Packet? */
4155                 if ((ep->xfer_len - ep->xfer_count) == 0) {
4156                         deptsiz.b.xfersize = 0;
4157                         deptsiz.b.pktcnt = 1;
4158                 } else {
4159                         /* Program the transfer size and packet count
4160                          *      as follows: xfersize = N * maxpacket +
4161                          *      short_packet pktcnt = N + (short_packet
4162                          *      exist ? 1 : 0)
4163                          */
4164                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
4165                         deptsiz.b.pktcnt =
4166                             (ep->xfer_len - ep->xfer_count - 1 +
4167                              ep->maxpacket) / ep->maxpacket;
4168                         if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
4169                                 deptsiz.b.pktcnt = MAX_PKT_CNT;
4170                                 deptsiz.b.xfersize =
4171                                     deptsiz.b.pktcnt * ep->maxpacket;
4172                         }
4173                         if (ep->type == DWC_OTG_EP_TYPE_ISOC)
4174                                 deptsiz.b.mc = deptsiz.b.pktcnt;
4175                 }
4176
4177                 /* Write the DMA register */
4178                 if (core_if->dma_enable) {
4179                         if (core_if->dma_desc_enable == 0) {
4180                                 if (ep->type != DWC_OTG_EP_TYPE_ISOC)
4181                                         deptsiz.b.mc = 1;
4182                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
4183                                                 deptsiz.d32);
4184                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4185                                                 (uint32_t) ep->dma_addr);
4186                         } else {
4187 #ifdef DWC_UTE_CFI
4188                                 /* The descriptor chain should be
4189                                  * already initialized by now */
4190                                 if (ep->buff_mode != BM_STANDARD) {
4191                                         DWC_WRITE_REG32(&in_regs->diepdma,
4192                                                         ep->descs_dma_addr);
4193                                 } else {
4194 #endif
4195                                         init_dma_desc_chain(core_if, ep);
4196                                 /** DIEPDMAn Register write */
4197                                         DWC_WRITE_REG32(&in_regs->diepdma,
4198                                                         ep->dma_desc_addr);
4199 #ifdef DWC_UTE_CFI
4200                                 }
4201 #endif
4202                         }
4203                 } else {
4204                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4205                         if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
4206                                 /**
4207                                  * Enable the Non-Periodic Tx FIFO empty interrupt,
4208                                  * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
4209                                  * the data will be written into the fifo by the ISR.
4210                                  */
4211                                 if (core_if->en_multiple_tx_fifo == 0) {
4212                                         intr_mask.b.nptxfempty = 1;
4213                                         DWC_MODIFY_REG32
4214                                             (&core_if->core_global_regs->
4215                                              gintmsk, intr_mask.d32,
4216                                              intr_mask.d32);
4217                                 } else {
4218                                         /* Enable the Tx FIFO Empty Interrupt for this EP */
4219                                         if (ep->xfer_len > 0) {
4220                                                 uint32_t fifoemptymsk = 0;
4221                                                 fifoemptymsk = 1 << ep->num;
4222                                                 DWC_MODIFY_REG32
4223                                                     (&core_if->dev_if->
4224                                                      dev_global_regs->
4225                                                      dtknqr4_fifoemptymsk, 0,
4226                                                      fifoemptymsk);
4227
4228                                         }
4229                                 }
4230                         } else {
4231                                 write_isoc_tx_fifo(core_if, ep);
4232                         }
4233                 }
4234                 if (!core_if->core_params->en_multiple_tx_fifo
4235                     && core_if->dma_enable)
4236                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4237
4238                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
4239                         dsts_data_t dsts = {.d32 = 0 };
4240                         if (ep->bInterval == 1) {
4241                                 dsts.d32 =
4242                                     DWC_READ_REG32(&core_if->
4243                                                    dev_if->dev_global_regs->
4244                                                    dsts);
4245                                 ep->frame_num = dsts.b.soffn + ep->bInterval;
4246                                 if (ep->frame_num > 0x3FFF) {
4247                                         ep->frm_overrun = 1;
4248                                         ep->frame_num &= 0x3FFF;
4249                                 } else
4250                                         ep->frm_overrun = 0;
4251                                 if (ep->frame_num & 0x1)
4252                                         depctl.b.setd1pid = 1;
4253                                 else
4254                                         depctl.b.setd0pid = 1;
4255                         }
4256                 }
4257                 /* EP enable, IN data in FIFO */
4258                 depctl.b.cnak = 1;
4259                 depctl.b.epena = 1;
4260                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4261
4262         } else {
4263                 /* OUT endpoint */
4264                 dwc_otg_dev_out_ep_regs_t *out_regs =
4265                     core_if->dev_if->out_ep_regs[ep->num];
4266
4267                 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
4268                 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
4269
4270                 if (!core_if->dma_desc_enable) {
4271                         if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
4272                                 ep->xfer_len +=
4273                                     (ep->maxxfer <
4274                                      (ep->total_len -
4275                                       ep->xfer_len)) ? ep->maxxfer : (ep->
4276                                                                       total_len
4277                                                                       -
4278                                                                       ep->
4279                                                                       xfer_len);
4280                         else
4281                                 ep->xfer_len +=
4282                                     (MAX_PKT_CNT * ep->maxpacket <
4283                                      (ep->total_len -
4284                                       ep->xfer_len)) ? MAX_PKT_CNT *
4285                                     ep->maxpacket : (ep->total_len -
4286                                                      ep->xfer_len);
4287                 }
4288
4289                 /* Program the transfer size and packet count as follows:
4290                  *
4291                  *      pktcnt = N
4292                  *      xfersize = N * maxpacket
4293                  */
4294                 if ((ep->xfer_len - ep->xfer_count) == 0) {
4295                         /* Zero Length Packet */
4296                         deptsiz.b.xfersize = ep->maxpacket;
4297                         deptsiz.b.pktcnt = 1;
4298                 } else {
4299                         deptsiz.b.pktcnt =
4300                             (ep->xfer_len - ep->xfer_count +
4301                              (ep->maxpacket - 1)) / ep->maxpacket;
4302                         if (deptsiz.b.pktcnt > MAX_PKT_CNT)
4303                                 deptsiz.b.pktcnt = MAX_PKT_CNT;
4304                         if (!core_if->dma_desc_enable) {
4305                                 ep->xfer_len =
4306                                     deptsiz.b.pktcnt * ep->maxpacket +
4307                                     ep->xfer_count;
4308                         }
4309                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
4310                 }
4311
4312                 DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
4313                             ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
4314
4315                 if (core_if->dma_enable) {
4316                         if (!core_if->dma_desc_enable) {
4317                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
4318                                                 deptsiz.d32);
4319
4320                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4321                                                 (uint32_t) ep->dma_addr);
4322                         } else {
4323 #ifdef DWC_UTE_CFI
4324                                 /* The descriptor chain should be
4325                                  * already initialized by now */
4326                                 if (ep->buff_mode != BM_STANDARD) {
4327                                         DWC_WRITE_REG32(&out_regs->doepdma,
4328                                                         ep->descs_dma_addr);
4329                                 } else {
4330 #endif
4331                                         /* This is used for
4332                                          * interrupt out transfers*/
4333                                         if (!ep->xfer_len)
4334                                                 ep->xfer_len = ep->total_len;
4335                                         init_dma_desc_chain(core_if, ep);
4336
4337                                         if (core_if->core_params->dev_out_nak) {
4338                                                 if (ep->type ==
4339                                                     DWC_OTG_EP_TYPE_BULK) {
4340                                                         deptsiz.b.pktcnt =
4341                                                             (ep->total_len +
4342                                                              (ep->maxpacket -
4343                                                               1)) /
4344                                                             ep->maxpacket;
4345                                                         deptsiz.b.xfersize =
4346                                                             ep->total_len;
4347                                                         /* Remember initial value of doeptsiz */
4348                                                         core_if->
4349                                                             start_doeptsiz_val
4350                                                             [ep->num] =
4351                                                             deptsiz.d32;
4352                                                         DWC_WRITE_REG32
4353                                                             (&out_regs->
4354                                                              doeptsiz,
4355                                                              deptsiz.d32);
4356                                                 }
4357                                         }
4358                                 /** DOEPDMAn Register write */
4359                                         DWC_WRITE_REG32(&out_regs->doepdma,
4360                                                         ep->dma_desc_addr);
4361 #ifdef DWC_UTE_CFI
4362                                 }
4363 #endif
4364                         }
4365                 } else {
4366                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4367                 }
4368
4369                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
4370                         dsts_data_t dsts = {.d32 = 0 };
4371                         if (ep->bInterval == 1) {
4372                                 dsts.d32 =
4373                                     DWC_READ_REG32(&core_if->
4374                                                    dev_if->dev_global_regs->
4375                                                    dsts);
4376                                 ep->frame_num = dsts.b.soffn + ep->bInterval;
4377                                 if (ep->frame_num > 0x3FFF) {
4378                                         ep->frm_overrun = 1;
4379                                         ep->frame_num &= 0x3FFF;
4380                                 } else
4381                                         ep->frm_overrun = 0;
4382
4383                                 if (ep->frame_num & 0x1)
4384                                         depctl.b.setd1pid = 1;
4385                                 else
4386                                         depctl.b.setd0pid = 1;
4387                         }
4388                 }
4389
4390                 /* EP enable */
4391                 depctl.b.cnak = 1;
4392                 depctl.b.epena = 1;
4393
4394                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
4395
4396                 DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
4397                             DWC_READ_REG32(&out_regs->doepctl),
4398                             DWC_READ_REG32(&out_regs->doeptsiz));
4399                 DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
4400                             DWC_READ_REG32(&core_if->dev_if->
4401                                            dev_global_regs->daintmsk),
4402                             DWC_READ_REG32(&core_if->
4403                                            core_global_regs->gintmsk));
4404
4405                 /* Timer is scheduling only for out bulk transfers for
4406                  * "Device DDMA OUT NAK Enhancement" feature to inform user
4407                  * about received data payload in case of timeout
4408                  */
4409                 if (core_if->core_params->dev_out_nak) {
4410                         if (ep->type == DWC_OTG_EP_TYPE_BULK) {
4411                                 core_if->ep_xfer_info[ep->num].core_if =
4412                                     core_if;
4413                                 core_if->ep_xfer_info[ep->num].ep = ep;
4414                                 core_if->ep_xfer_info[ep->num].state = 1;
4415
4416                                 /* Start a timer for this transfer. */
4417                                 DWC_TIMER_SCHEDULE(core_if->
4418                                                    ep_xfer_timer[ep->num],
4419                                                    10000);
4420                         }
4421                 }
4422         }
4423 }
4424
4425 /**
4426  * This function setup a zero length transfer in Buffer DMA and
4427  * Slave modes for usb requests with zero field set
4428  *
4429  * @param core_if Programming view of DWC_otg controller.
4430  * @param ep The EP to start the transfer on.
4431  *
4432  */
4433 void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4434 {
4435
4436         depctl_data_t depctl;
4437         deptsiz_data_t deptsiz;
4438         gintmsk_data_t intr_mask = {.d32 = 0 };
4439
4440         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
4441         DWC_PRINTF("zero length transfer is called\n");
4442
4443         /* IN endpoint */
4444         if (ep->is_in == 1) {
4445                 dwc_otg_dev_in_ep_regs_t *in_regs =
4446                     core_if->dev_if->in_ep_regs[ep->num];
4447
4448                 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
4449                 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
4450
4451                 deptsiz.b.xfersize = 0;
4452                 deptsiz.b.pktcnt = 1;
4453
4454                 /* Write the DMA register */
4455                 if (core_if->dma_enable) {
4456                         if (core_if->dma_desc_enable == 0) {
4457                                 deptsiz.b.mc = 1;
4458                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
4459                                                 deptsiz.d32);
4460                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4461                                                 (uint32_t) ep->dma_addr);
4462                         }
4463                 } else {
4464                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4465                         /**
4466                          * Enable the Non-Periodic Tx FIFO empty interrupt,
4467                          * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
4468                          * the data will be written into the fifo by the ISR.
4469                          */
4470                         if (core_if->en_multiple_tx_fifo == 0) {
4471                                 intr_mask.b.nptxfempty = 1;
4472                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
4473                                                  gintmsk, intr_mask.d32,
4474                                                  intr_mask.d32);
4475                         } else {
4476                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
4477                                 if (ep->xfer_len > 0) {
4478                                         uint32_t fifoemptymsk = 0;
4479                                         fifoemptymsk = 1 << ep->num;
4480                                         DWC_MODIFY_REG32(&core_if->dev_if->
4481                                                          dev_global_regs->
4482                                                          dtknqr4_fifoemptymsk,
4483                                                          0, fifoemptymsk);
4484                                 }
4485                         }
4486                 }
4487
4488                 if (!core_if->core_params->en_multiple_tx_fifo
4489                     && core_if->dma_enable)
4490                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4491                 /* EP enable, IN data in FIFO */
4492                 depctl.b.cnak = 1;
4493                 depctl.b.epena = 1;
4494                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4495
4496         } else {
4497                 /* OUT endpoint */
4498                 dwc_otg_dev_out_ep_regs_t *out_regs =
4499                     core_if->dev_if->out_ep_regs[ep->num];
4500
4501                 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
4502                 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
4503
4504                 /* Zero Length Packet */
4505                 deptsiz.b.xfersize = ep->maxpacket;
4506                 deptsiz.b.pktcnt = 1;
4507
4508                 if (core_if->dma_enable) {
4509                         if (!core_if->dma_desc_enable) {
4510                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
4511                                                 deptsiz.d32);
4512
4513                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4514                                                 (uint32_t) ep->dma_addr);
4515                         }
4516                 } else {
4517                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4518                 }
4519
4520                 /* EP enable */
4521                 depctl.b.cnak = 1;
4522                 depctl.b.epena = 1;
4523
4524                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
4525
4526         }
4527 }
4528
4529 /**
4530  * This function does the setup for a data transfer for EP0 and starts
4531  * the transfer.  For an IN transfer, the packets will be loaded into
4532  * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
4533  * unloaded from the Rx FIFO in the ISR.
4534  *
4535  * @param core_if Programming view of DWC_otg controller.
4536  * @param ep The EP0 data.
4537  */
4538 void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4539 {
4540         depctl_data_t depctl;
4541         deptsiz0_data_t deptsiz;
4542         gintmsk_data_t intr_mask = {.d32 = 0 };
4543         dwc_otg_dev_dma_desc_t *dma_desc;
4544
4545         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
4546                     "xfer_buff=%p start_xfer_buff=%p \n",
4547                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
4548                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
4549
4550         ep->total_len = ep->xfer_len;
4551
4552         /* IN endpoint */
4553         if (ep->is_in == 1) {
4554                 dwc_otg_dev_in_ep_regs_t *in_regs =
4555                     core_if->dev_if->in_ep_regs[0];
4556
4557                 gnptxsts_data_t gtxstatus;
4558
4559                 if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
4560                         depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4561                         if (depctl.b.epena)
4562                                 return;
4563                 }
4564
4565                 gtxstatus.d32 =
4566                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
4567
4568                 /* If dedicated FIFO every time flush fifo before enable ep */
4569                 if (core_if->en_multiple_tx_fifo
4570                     && core_if->snpsid >= OTG_CORE_REV_3_00a)
4571                         dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
4572
4573                 if (core_if->en_multiple_tx_fifo == 0
4574                     && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
4575 #ifdef DEBUG
4576                         deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4577                         DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
4578                                     DWC_READ_REG32(&in_regs->diepctl));
4579                         DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
4580                                     deptsiz.d32,
4581                                     deptsiz.b.xfersize, deptsiz.b.pktcnt);
4582                         DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
4583                                    gtxstatus.d32);
4584 #endif
4585                         return;
4586                 }
4587
4588                 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4589                 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4590
4591                 /* Zero Length Packet? */
4592                 if (ep->xfer_len == 0) {
4593                         deptsiz.b.xfersize = 0;
4594                         deptsiz.b.pktcnt = 1;
4595                 } else {
4596                         /* Program the transfer size and packet count
4597                          *      as follows: xfersize = N * maxpacket +
4598                          *      short_packet pktcnt = N + (short_packet
4599                          *      exist ? 1 : 0)
4600                          */
4601                         if (ep->xfer_len > ep->maxpacket) {
4602                                 ep->xfer_len = ep->maxpacket;
4603                                 deptsiz.b.xfersize = ep->maxpacket;
4604                         } else {
4605                                 deptsiz.b.xfersize = ep->xfer_len;
4606                         }
4607                         deptsiz.b.pktcnt = 1;
4608
4609                 }
4610                 DWC_DEBUGPL(DBG_PCDV,
4611                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
4612                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4613                             deptsiz.d32);
4614
4615                 /* Write the DMA register */
4616                 if (core_if->dma_enable) {
4617                         if (core_if->dma_desc_enable == 0) {
4618                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
4619                                                 deptsiz.d32);
4620
4621                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4622                                                 (uint32_t) ep->dma_addr);
4623                         } else {
4624                                 dma_desc = core_if->dev_if->in_desc_addr;
4625
4626                                 /** DMA Descriptor Setup */
4627                                 dma_desc->status.b.bs = BS_HOST_BUSY;
4628                                 dma_desc->status.b.l = 1;
4629                                 dma_desc->status.b.ioc = 1;
4630                                 dma_desc->status.b.sp =
4631                                     (ep->xfer_len == ep->maxpacket) ? 0 : 1;
4632                                 dma_desc->status.b.bytes = ep->xfer_len;
4633                                 dma_desc->buf = ep->dma_addr;
4634                                 dma_desc->status.b.sts = 0;
4635                                 dma_desc->status.b.bs = BS_HOST_READY;
4636
4637                                 /** DIEPDMA0 Register write */
4638                                 DWC_WRITE_REG32(&in_regs->diepdma,
4639                                                 core_if->dev_if->
4640                                                 dma_in_desc_addr);
4641                         }
4642                 } else {
4643                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4644                 }
4645
4646                 if (!core_if->core_params->en_multiple_tx_fifo
4647                     && core_if->dma_enable)
4648                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4649                 /* EP enable, IN data in FIFO */
4650                 depctl.b.cnak = 1;
4651                 depctl.b.epena = 1;
4652                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4653
4654                 /**
4655                  * Enable the Non-Periodic Tx FIFO empty interrupt, the
4656                  * data will be written into the fifo by the ISR.
4657                  */
4658                 if (!core_if->dma_enable) {
4659                         if (core_if->en_multiple_tx_fifo == 0) {
4660                                 intr_mask.b.nptxfempty = 1;
4661                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
4662                                                  gintmsk, intr_mask.d32,
4663                                                  intr_mask.d32);
4664                         } else {
4665                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
4666                                 if (ep->xfer_len > 0) {
4667                                         uint32_t fifoemptymsk = 0;
4668                                         fifoemptymsk |= 1 << ep->num;
4669                                         DWC_MODIFY_REG32(&core_if->dev_if->
4670                                                          dev_global_regs->
4671                                                          dtknqr4_fifoemptymsk,
4672                                                          0, fifoemptymsk);
4673                                 }
4674                         }
4675                 }
4676         } else {
4677                 /* OUT endpoint */
4678                 dwc_otg_dev_out_ep_regs_t *out_regs =
4679                     core_if->dev_if->out_ep_regs[0];
4680
4681                 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
4682                 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
4683
4684                 /* Program the transfer size and packet count as follows:
4685                  *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
4686                  *      pktcnt = N                                                                                      */
4687                 /* Zero Length Packet */
4688                 deptsiz.b.xfersize = ep->maxpacket;
4689                 deptsiz.b.pktcnt = 1;
4690                 if (core_if->snpsid >= OTG_CORE_REV_3_00a)
4691                         deptsiz.b.supcnt = 1;
4692
4693                 DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
4694                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
4695
4696                 if (core_if->dma_enable) {
4697                         if (!core_if->dma_desc_enable) {
4698                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
4699                                                 deptsiz.d32);
4700
4701                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4702                                                 (uint32_t) ep->dma_addr);
4703                         } else {
4704                                 dma_desc = core_if->dev_if->out_desc_addr;
4705
4706                                 /** DMA Descriptor Setup */
4707                                 dma_desc->status.b.bs = BS_HOST_BUSY;
4708                                 if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
4709                                         dma_desc->status.b.mtrf = 0;
4710                                         dma_desc->status.b.sr = 0;
4711                                 }
4712                                 dma_desc->status.b.l = 1;
4713                                 dma_desc->status.b.ioc = 1;
4714                                 dma_desc->status.b.bytes = ep->maxpacket;
4715                                 dma_desc->buf = ep->dma_addr;
4716                                 dma_desc->status.b.sts = 0;
4717                                 dma_desc->status.b.bs = BS_HOST_READY;
4718
4719                                 /** DOEPDMA0 Register write */
4720                                 DWC_WRITE_REG32(&out_regs->doepdma,
4721                                                 core_if->
4722                                                 dev_if->dma_out_desc_addr);
4723                         }
4724                 } else {
4725                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4726                 }
4727
4728                 /* EP enable */
4729                 depctl.b.cnak = 1;
4730                 depctl.b.epena = 1;
4731                 DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
4732         }
4733 }
4734
4735 /**
4736  * This function continues control IN transfers started by
4737  * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
4738  * single packet.  NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
4739  * bit for the packet count.
4740  *
4741  * @param core_if Programming view of DWC_otg controller.
4742  * @param ep The EP0 data.
4743  */
4744 void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
4745 {
4746         depctl_data_t depctl;
4747         deptsiz0_data_t deptsiz;
4748         gintmsk_data_t intr_mask = {.d32 = 0 };
4749         dwc_otg_dev_dma_desc_t *dma_desc;
4750
4751         if (ep->is_in == 1) {
4752                 dwc_otg_dev_in_ep_regs_t *in_regs =
4753                     core_if->dev_if->in_ep_regs[0];
4754                 gnptxsts_data_t tx_status = {.d32 = 0 };
4755
4756                 tx_status.d32 =
4757                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
4758                 /** @todo Should there be check for room in the Tx
4759                  * Status Queue.  If not remove the code above this comment. */
4760
4761                 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4762                 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4763
4764                 /* Program the transfer size and packet count
4765                  *      as follows: xfersize = N * maxpacket +
4766                  *      short_packet pktcnt = N + (short_packet
4767                  *      exist ? 1 : 0)
4768                  */
4769
4770                 if (core_if->dma_desc_enable == 0) {
4771                         deptsiz.b.xfersize =
4772                             (ep->total_len - ep->xfer_count) >
4773                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
4774                                                              ep->xfer_count);
4775                         deptsiz.b.pktcnt = 1;
4776                         if (core_if->dma_enable == 0)
4777                                 ep->xfer_len += deptsiz.b.xfersize;
4778                         else
4779                                 ep->xfer_len = deptsiz.b.xfersize;
4780                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4781                 } else {
4782                         ep->xfer_len =
4783                             (ep->total_len - ep->xfer_count) >
4784                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
4785                                                              ep->xfer_count);
4786
4787                         dma_desc = core_if->dev_if->in_desc_addr;
4788
4789                         /** DMA Descriptor Setup */
4790                         dma_desc->status.b.bs = BS_HOST_BUSY;
4791                         dma_desc->status.b.l = 1;
4792                         dma_desc->status.b.ioc = 1;
4793                         dma_desc->status.b.sp =
4794                             (ep->xfer_len == ep->maxpacket) ? 0 : 1;
4795                         dma_desc->status.b.bytes = ep->xfer_len;
4796                         dma_desc->buf = ep->dma_addr;
4797                         dma_desc->status.b.sts = 0;
4798                         dma_desc->status.b.bs = BS_HOST_READY;
4799
4800                         /** DIEPDMA0 Register write */
4801                         DWC_WRITE_REG32(&in_regs->diepdma,
4802                                         core_if->dev_if->dma_in_desc_addr);
4803                 }
4804
4805                 DWC_DEBUGPL(DBG_PCDV,
4806                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
4807                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4808                             deptsiz.d32);
4809
4810                 /* Write the DMA register */
4811                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4812                         if (core_if->dma_desc_enable == 0)
4813                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4814                                                 (uint32_t) ep->dma_addr);
4815                 }
4816                 if (!core_if->core_params->en_multiple_tx_fifo
4817                     && core_if->dma_enable)
4818                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4819                 /* EP enable, IN data in FIFO */
4820                 depctl.b.cnak = 1;
4821                 depctl.b.epena = 1;
4822                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4823
4824                 /**
4825                  * Enable the Non-Periodic Tx FIFO empty interrupt, the
4826                  * data will be written into the fifo by the ISR.
4827                  */
4828                 if (!core_if->dma_enable) {
4829                         if (core_if->en_multiple_tx_fifo == 0) {
4830                                 /* First clear it from GINTSTS */
4831                                 intr_mask.b.nptxfempty = 1;
4832                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
4833                                                  gintmsk, intr_mask.d32,
4834                                                  intr_mask.d32);
4835
4836                         } else {
4837                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
4838                                 if (ep->xfer_len > 0) {
4839                                         uint32_t fifoemptymsk = 0;
4840                                         fifoemptymsk |= 1 << ep->num;
4841                                         DWC_MODIFY_REG32(&core_if->dev_if->
4842                                                          dev_global_regs->
4843                                                          dtknqr4_fifoemptymsk,
4844                                                          0, fifoemptymsk);
4845                                 }
4846                         }
4847                 }
4848         } else {
4849                 dwc_otg_dev_out_ep_regs_t *out_regs =
4850                     core_if->dev_if->out_ep_regs[0];
4851
4852                 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
4853                 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
4854
4855                 /* Program the transfer size and packet count
4856                  *      as follows: xfersize = N * maxpacket +
4857                  *      short_packet pktcnt = N + (short_packet
4858                  *      exist ? 1 : 0)
4859                  */
4860                 deptsiz.b.xfersize = ep->maxpacket;
4861                 deptsiz.b.pktcnt = 1;
4862
4863                 if (core_if->dma_desc_enable == 0) {
4864                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4865                 } else {
4866                         dma_desc = core_if->dev_if->out_desc_addr;
4867
4868                         /** DMA Descriptor Setup */
4869                         dma_desc->status.b.bs = BS_HOST_BUSY;
4870                         dma_desc->status.b.l = 1;
4871                         dma_desc->status.b.ioc = 1;
4872                         dma_desc->status.b.bytes = ep->maxpacket;
4873                         dma_desc->buf = ep->dma_addr;
4874                         dma_desc->status.b.sts = 0;
4875                         dma_desc->status.b.bs = BS_HOST_READY;
4876
4877                         /** DOEPDMA0 Register write */
4878                         DWC_WRITE_REG32(&out_regs->doepdma,
4879                                         core_if->dev_if->dma_out_desc_addr);
4880                 }
4881
4882                 DWC_DEBUGPL(DBG_PCDV,
4883                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
4884                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4885                             deptsiz.d32);
4886
4887                 /* Write the DMA register */
4888                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4889                         if (core_if->dma_desc_enable == 0)
4890                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4891                                                 (uint32_t) ep->dma_addr);
4892
4893                 }
4894
4895                 /* EP enable, IN data in FIFO */
4896                 depctl.b.cnak = 1;
4897                 depctl.b.epena = 1;
4898                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
4899
4900         }
4901 }
4902
4903 #ifdef DEBUG
4904 void dump_msg(const u8 *buf, unsigned int length)
4905 {
4906         unsigned int start, num, i;
4907         char line[52], *p;
4908
4909         if (length >= 512)
4910                 return;
4911         start = 0;
4912         while (length > 0) {
4913                 num = length < 16u ? length : 16u;
4914                 p = line;
4915                 for (i = 0; i < num; ++i) {
4916                         if (i == 8)
4917                                 *p++ = ' ';
4918                         DWC_SPRINTF(p, " %02x", buf[i]);
4919                         p += 3;
4920                 }
4921                 *p = 0;
4922                 DWC_PRINTF("%6x: %s\n", start, line);
4923                 buf += num;
4924                 start += num;
4925                 length -= num;
4926         }
4927 }
4928 #else
4929 static inline void dump_msg(const u8 *buf, unsigned int length)
4930 {
4931 }
4932 #endif
4933
4934 /**
4935  * This function writes a packet into the Tx FIFO associated with the
4936  * EP. For non-periodic EPs the non-periodic Tx FIFO is written.  For
4937  * periodic EPs the periodic Tx FIFO associated with the EP is written
4938  * with all packets for the next micro-frame.
4939  *
4940  * @param core_if Programming view of DWC_otg controller.
4941  * @param ep The EP to write packet for.
4942  * @param dma Indicates if DMA is being used.
4943  */
4944 void dwc_otg_ep_write_packet(dwc_otg_core_if_t *core_if, dwc_ep_t *ep,
4945                              int dma)
4946 {
4947         /**
4948          * The buffer is padded to DWORD on a per packet basis in
4949          * slave/dma mode if the MPS is not DWORD aligned. The last
4950          * packet, if short, is also padded to a multiple of DWORD.
4951          *
4952          * ep->xfer_buff always starts DWORD aligned in memory and is a
4953          * multiple of DWORD in length
4954          *
4955          * ep->xfer_len can be any number of bytes
4956          *
4957          * ep->xfer_count is a multiple of ep->maxpacket until the last
4958          *      packet
4959          *
4960          * FIFO access is DWORD */
4961
4962         uint32_t i;
4963         uint32_t byte_count;
4964         uint32_t dword_count;
4965         uint32_t *fifo;
4966         uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
4967
4968         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
4969                     ep);
4970         if (ep->xfer_count >= ep->xfer_len) {
4971                 DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
4972                 return;
4973         }
4974
4975         /* Find the byte length of the packet either short packet or MPS */
4976         if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket)
4977                 byte_count = ep->xfer_len - ep->xfer_count;
4978         else
4979                 byte_count = ep->maxpacket;
4980
4981         /* Find the DWORD length, padded by extra bytes as neccessary if MPS
4982          * is not a multiple of DWORD */
4983         dword_count = (byte_count + 3) / 4;
4984
4985 #ifdef VERBOSE
4986         dump_msg(ep->xfer_buff, byte_count);
4987 #endif
4988
4989         /**@todo NGS Where are the Periodic Tx FIFO addresses
4990          * intialized?  What should this be? */
4991
4992         fifo = core_if->data_fifo[ep->num];
4993
4994         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
4995                     fifo, data_buff, *data_buff, byte_count);
4996
4997         if (!dma) {
4998                 for (i = 0; i < dword_count; i++, data_buff++)
4999                         DWC_WRITE_REG32(fifo, *data_buff);
5000         }
5001
5002         ep->xfer_count += byte_count;
5003         ep->xfer_buff += byte_count;
5004         ep->dma_addr += byte_count;
5005 }
5006
5007 /**
5008  * Set the EP STALL.
5009  *
5010  * @param core_if Programming view of DWC_otg controller.
5011  * @param ep The EP to set the stall on.
5012  */
5013 void dwc_otg_ep_set_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5014 {
5015         depctl_data_t depctl;
5016         volatile uint32_t *depctl_addr;
5017
5018         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
5019                     (ep->is_in ? "IN" : "OUT"));
5020
5021         if (ep->is_in == 1) {
5022                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
5023                 depctl.d32 = DWC_READ_REG32(depctl_addr);
5024
5025                 /* set the disable and stall bits */
5026                 if (depctl.b.epena)
5027                         depctl.b.epdis = 1;
5028                 depctl.b.stall = 1;
5029                 DWC_WRITE_REG32(depctl_addr, depctl.d32);
5030         } else {
5031                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
5032                 depctl.d32 = DWC_READ_REG32(depctl_addr);
5033
5034                 /* set the stall bit */
5035                 depctl.b.stall = 1;
5036                 DWC_WRITE_REG32(depctl_addr, depctl.d32);
5037         }
5038
5039         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
5040
5041         return;
5042 }
5043
5044 /**
5045  * Clear the EP STALL.
5046  *
5047  * @param core_if Programming view of DWC_otg controller.
5048  * @param ep The EP to clear stall from.
5049  */
5050 void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5051 {
5052         depctl_data_t depctl;
5053         volatile uint32_t *depctl_addr;
5054
5055         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
5056                     (ep->is_in ? "IN" : "OUT"));
5057
5058         if (ep->is_in == 1)
5059                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
5060         else
5061                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
5062
5063         depctl.d32 = DWC_READ_REG32(depctl_addr);
5064
5065         /* clear the stall bits */
5066         depctl.b.stall = 0;
5067
5068         /*
5069          * USB Spec 9.4.5: For endpoints using data toggle, regardless
5070          * of whether an endpoint has the Halt feature set, a
5071          * ClearFeature(ENDPOINT_HALT) request always results in the
5072          * data toggle being reinitialized to DATA0.
5073          */
5074         if (ep->type == DWC_OTG_EP_TYPE_INTR ||
5075             ep->type == DWC_OTG_EP_TYPE_BULK) {
5076                 depctl.b.setd0pid = 1;  /* DATA0 */
5077         }
5078
5079         DWC_WRITE_REG32(depctl_addr, depctl.d32);
5080         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
5081         return;
5082 }
5083
5084 /**
5085  * This function reads a packet from the Rx FIFO into the destination
5086  * buffer. To read SETUP data use dwc_otg_read_setup_packet.
5087  *
5088  * @param core_if Programming view of DWC_otg controller.
5089  * @param dest    Destination buffer for the packet.
5090  * @param bytes  Number of bytes to copy to the destination.
5091  */
5092 void dwc_otg_read_packet(dwc_otg_core_if_t *core_if,
5093                          uint8_t *dest, uint16_t bytes)
5094 {
5095         int i;
5096         int word_count = (bytes + 3) / 4;
5097
5098         volatile uint32_t *fifo = core_if->data_fifo[0];
5099         uint32_t *data_buff = (uint32_t *) dest;
5100
5101         /**
5102          * @todo Account for the case where _dest is not dword aligned. This
5103          * requires reading data from the FIFO into a uint32_t temp buffer,
5104          * then moving it into the data buffer.
5105          */
5106
5107         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
5108                     core_if, dest, bytes);
5109
5110         for (i = 0; i < word_count; i++, data_buff++)
5111                 *data_buff = DWC_READ_REG32(fifo);
5112
5113         return;
5114 }
5115
5116 /**
5117  * This functions reads the device registers and prints them
5118  *
5119  * @param core_if Programming view of DWC_otg controller.
5120  */
5121 void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *core_if)
5122 {
5123         int i;
5124         volatile uint32_t *addr;
5125         uint32_t hwcfg1;
5126
5127         hwcfg1 = ~core_if->core_global_regs->ghwcfg1;
5128
5129         DWC_PRINTF("Device Global Registers\n");
5130         addr = &core_if->dev_if->dev_global_regs->dcfg;
5131         DWC_PRINTF("DCFG                 @0x%08lX : 0x%08X\n",
5132                    (unsigned long)addr, DWC_READ_REG32(addr));
5133         addr = &core_if->dev_if->dev_global_regs->dctl;
5134         DWC_PRINTF("DCTL                 @0x%08lX : 0x%08X\n",
5135                    (unsigned long)addr, DWC_READ_REG32(addr));
5136         addr = &core_if->dev_if->dev_global_regs->dsts;
5137         DWC_PRINTF("DSTS                 @0x%08lX : 0x%08X\n",
5138                    (unsigned long)addr, DWC_READ_REG32(addr));
5139         addr = &core_if->dev_if->dev_global_regs->diepmsk;
5140         DWC_PRINTF("DIEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5141                    DWC_READ_REG32(addr));
5142         addr = &core_if->dev_if->dev_global_regs->doepmsk;
5143         DWC_PRINTF("DOEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5144                    DWC_READ_REG32(addr));
5145         addr = &core_if->dev_if->dev_global_regs->daint;
5146         DWC_PRINTF("DAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5147                    DWC_READ_REG32(addr));
5148         addr = &core_if->dev_if->dev_global_regs->daintmsk;
5149         DWC_PRINTF("DAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5150                    DWC_READ_REG32(addr));
5151         addr = &core_if->dev_if->dev_global_regs->dtknqr1;
5152         DWC_PRINTF("DTKNQR1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5153                    DWC_READ_REG32(addr));
5154         if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
5155                 addr = &core_if->dev_if->dev_global_regs->dtknqr2;
5156                 DWC_PRINTF("DTKNQR2      @0x%08lX : 0x%08X\n",
5157                            (unsigned long)addr, DWC_READ_REG32(addr));
5158         }
5159
5160         addr = &core_if->dev_if->dev_global_regs->dvbusdis;
5161         DWC_PRINTF("DVBUSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5162                    DWC_READ_REG32(addr));
5163
5164         addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
5165         DWC_PRINTF("DVBUSPULSE  @0x%08lX : 0x%08X\n",
5166                    (unsigned long)addr, DWC_READ_REG32(addr));
5167
5168         addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
5169         DWC_PRINTF("DTKNQR3_DTHRCTL      @0x%08lX : 0x%08X\n",
5170                    (unsigned long)addr, DWC_READ_REG32(addr));
5171
5172         if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
5173                 addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
5174                 DWC_PRINTF("DTKNQR4      @0x%08lX : 0x%08X\n",
5175                            (unsigned long)addr, DWC_READ_REG32(addr));
5176         }
5177
5178         addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
5179         DWC_PRINTF("FIFOEMPMSK   @0x%08lX : 0x%08X\n", (unsigned long)addr,
5180                    DWC_READ_REG32(addr));
5181
5182         if (core_if->hwcfg2.b.multi_proc_int) {
5183
5184                 addr = &core_if->dev_if->dev_global_regs->deachint;
5185                 DWC_PRINTF("DEACHINT     @0x%08lX : 0x%08X\n",
5186                            (unsigned long)addr, DWC_READ_REG32(addr));
5187                 addr = &core_if->dev_if->dev_global_regs->deachintmsk;
5188                 DWC_PRINTF("DEACHINTMSK  @0x%08lX : 0x%08X\n",
5189                            (unsigned long)addr, DWC_READ_REG32(addr));
5190
5191                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
5192                         addr =
5193                             &core_if->dev_if->dev_global_regs->
5194                             diepeachintmsk[i];
5195                         DWC_PRINTF("DIEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
5196                                    i, (unsigned long)addr,
5197                                    DWC_READ_REG32(addr));
5198                 }
5199
5200                 for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
5201                         addr =
5202                             &core_if->dev_if->dev_global_regs->
5203                             doepeachintmsk[i];
5204                         DWC_PRINTF("DOEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
5205                                    i, (unsigned long)addr,
5206                                    DWC_READ_REG32(addr));
5207                 }
5208         }
5209
5210         for (i = 0; i <= core_if->core_params->dev_endpoints; i++) {
5211                 if (hwcfg1 & (2 << (i << 1))) {
5212                         DWC_PRINTF("Device IN EP %d Registers\n", i);
5213                         addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
5214                         DWC_PRINTF("DIEPCTL      @0x%08lX : 0x%08X\n",
5215                                    (unsigned long)addr, DWC_READ_REG32(addr));
5216                         addr = &core_if->dev_if->in_ep_regs[i]->diepint;
5217                         DWC_PRINTF("DIEPINT      @0x%08lX : 0x%08X\n",
5218                                    (unsigned long)addr, DWC_READ_REG32(addr));
5219                         addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
5220                         DWC_PRINTF("DIETSIZ      @0x%08lX : 0x%08X\n",
5221                                    (unsigned long)addr, DWC_READ_REG32(addr));
5222                         addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
5223                         DWC_PRINTF("DIEPDMA      @0x%08lX : 0x%08X\n",
5224                                    (unsigned long)addr, DWC_READ_REG32(addr));
5225                         addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
5226                         DWC_PRINTF("DTXFSTS      @0x%08lX : 0x%08X\n",
5227                                    (unsigned long)addr, DWC_READ_REG32(addr));
5228                         addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
5229                         DWC_PRINTF("DIEPDMAB     @0x%08lX : 0x%08X\n",
5230                                    (unsigned long)addr,
5231                                    0 /*DWC_READ_REG32(addr) */);
5232                 }
5233         }
5234
5235         for (i = 0; i <= core_if->core_params->dev_endpoints; i++) {
5236                 if (hwcfg1 & (1 << (i << 1))) {
5237                         DWC_PRINTF("Device OUT EP %d Registers\n", i);
5238                         addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
5239                         DWC_PRINTF("DOEPCTL      @0x%08lX : 0x%08X\n",
5240                                    (unsigned long)addr, DWC_READ_REG32(addr));
5241                         addr = &core_if->dev_if->out_ep_regs[i]->doepint;
5242                         DWC_PRINTF("DOEPINT      @0x%08lX : 0x%08X\n",
5243                                    (unsigned long)addr, DWC_READ_REG32(addr));
5244                         addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
5245                         DWC_PRINTF("DOETSIZ      @0x%08lX : 0x%08X\n",
5246                                    (unsigned long)addr, DWC_READ_REG32(addr));
5247                         addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
5248                         DWC_PRINTF("DOEPDMA      @0x%08lX : 0x%08X\n",
5249                                    (unsigned long)addr, DWC_READ_REG32(addr));
5250                         /* Don't access this register in SLAVE mode */
5251                         if (core_if->dma_enable) {
5252                                 addr =
5253                                     &core_if->dev_if->out_ep_regs[i]->doepdmab;
5254                                 DWC_PRINTF("DOEPDMAB     @0x%08lX : 0x%08X\n",
5255                                            (unsigned long)addr,
5256                                            DWC_READ_REG32(addr));
5257                         }
5258                 }
5259
5260         }
5261 }
5262
5263 /**
5264  * This functions reads the SPRAM and prints its content
5265  *
5266  * @param core_if Programming view of DWC_otg controller.
5267  */
5268 void dwc_otg_dump_spram(dwc_otg_core_if_t *core_if)
5269 {
5270         volatile uint8_t *addr, *start_addr, *end_addr;
5271
5272         DWC_PRINTF("SPRAM Data:\n");
5273         start_addr = (void *)core_if->core_global_regs;
5274         DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
5275         start_addr += 0x00028000;
5276         end_addr = (void *)core_if->core_global_regs;
5277         end_addr += 0x000280e0;
5278
5279         for (addr = start_addr; addr < end_addr; addr += 16) {
5280                 DWC_PRINTF
5281                     ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
5282                      (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
5283                      addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
5284                      addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
5285                     );
5286         }
5287
5288         return;
5289 }
5290
5291 /**
5292  * This function reads the host registers and prints them
5293  *
5294  * @param core_if Programming view of DWC_otg controller.
5295  */
5296 void dwc_otg_dump_host_registers(dwc_otg_core_if_t *core_if)
5297 {
5298         int i;
5299         volatile uint32_t *addr;
5300
5301         DWC_PRINTF("Host Global Registers\n");
5302         addr = &core_if->host_if->host_global_regs->hcfg;
5303         DWC_PRINTF("HCFG                 @0x%08lX : 0x%08X\n",
5304                    (unsigned long)addr, DWC_READ_REG32(addr));
5305         addr = &core_if->host_if->host_global_regs->hfir;
5306         DWC_PRINTF("HFIR                 @0x%08lX : 0x%08X\n",
5307                    (unsigned long)addr, DWC_READ_REG32(addr));
5308         addr = &core_if->host_if->host_global_regs->hfnum;
5309         DWC_PRINTF("HFNUM        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5310                    DWC_READ_REG32(addr));
5311         addr = &core_if->host_if->host_global_regs->hptxsts;
5312         DWC_PRINTF("HPTXSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5313                    DWC_READ_REG32(addr));
5314         addr = &core_if->host_if->host_global_regs->haint;
5315         DWC_PRINTF("HAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5316                    DWC_READ_REG32(addr));
5317         addr = &core_if->host_if->host_global_regs->haintmsk;
5318         DWC_PRINTF("HAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5319                    DWC_READ_REG32(addr));
5320         if (core_if->dma_desc_enable) {
5321                 addr = &core_if->host_if->host_global_regs->hflbaddr;
5322                 DWC_PRINTF("HFLBADDR     @0x%08lX : 0x%08X\n",
5323                            (unsigned long)addr, DWC_READ_REG32(addr));
5324         }
5325
5326         addr = core_if->host_if->hprt0;
5327         DWC_PRINTF("HPRT0        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5328                    DWC_READ_REG32(addr));
5329
5330         for (i = 0; i < core_if->core_params->host_channels; i++) {
5331                 DWC_PRINTF("Host Channel %d Specific Registers\n", i);
5332                 addr = &core_if->host_if->hc_regs[i]->hcchar;
5333                 DWC_PRINTF("HCCHAR       @0x%08lX : 0x%08X\n",
5334                            (unsigned long)addr, DWC_READ_REG32(addr));
5335                 addr = &core_if->host_if->hc_regs[i]->hcsplt;
5336                 DWC_PRINTF("HCSPLT       @0x%08lX : 0x%08X\n",
5337                            (unsigned long)addr, DWC_READ_REG32(addr));
5338                 addr = &core_if->host_if->hc_regs[i]->hcint;
5339                 DWC_PRINTF("HCINT        @0x%08lX : 0x%08X\n",
5340                            (unsigned long)addr, DWC_READ_REG32(addr));
5341                 addr = &core_if->host_if->hc_regs[i]->hcintmsk;
5342                 DWC_PRINTF("HCINTMSK     @0x%08lX : 0x%08X\n",
5343                            (unsigned long)addr, DWC_READ_REG32(addr));
5344                 addr = &core_if->host_if->hc_regs[i]->hctsiz;
5345                 DWC_PRINTF("HCTSIZ       @0x%08lX : 0x%08X\n",
5346                            (unsigned long)addr, DWC_READ_REG32(addr));
5347                 addr = &core_if->host_if->hc_regs[i]->hcdma;
5348                 DWC_PRINTF("HCDMA        @0x%08lX : 0x%08X\n",
5349                            (unsigned long)addr, DWC_READ_REG32(addr));
5350                 if (core_if->dma_desc_enable) {
5351                         addr = &core_if->host_if->hc_regs[i]->hcdmab;
5352                         DWC_PRINTF("HCDMAB       @0x%08lX : 0x%08X\n",
5353                                    (unsigned long)addr, DWC_READ_REG32(addr));
5354                 }
5355
5356         }
5357         return;
5358 }
5359
5360 /**
5361  * This function reads the core global registers and prints them
5362  *
5363  * @param core_if Programming view of DWC_otg controller.
5364  */
5365 void dwc_otg_dump_global_registers(dwc_otg_core_if_t *core_if)
5366 {
5367         int i, ep_num;
5368         volatile uint32_t *addr;
5369         char *txfsiz;
5370
5371         DWC_PRINTF("Core Global Registers\n");
5372         addr = &core_if->core_global_regs->gotgctl;
5373         DWC_PRINTF("GOTGCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5374                    DWC_READ_REG32(addr));
5375         addr = &core_if->core_global_regs->gotgint;
5376         DWC_PRINTF("GOTGINT      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5377                    DWC_READ_REG32(addr));
5378         addr = &core_if->core_global_regs->gahbcfg;
5379         DWC_PRINTF("GAHBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5380                    DWC_READ_REG32(addr));
5381         addr = &core_if->core_global_regs->gusbcfg;
5382         DWC_PRINTF("GUSBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5383                    DWC_READ_REG32(addr));
5384         addr = &core_if->core_global_regs->grstctl;
5385         DWC_PRINTF("GRSTCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5386                    DWC_READ_REG32(addr));
5387         addr = &core_if->core_global_regs->gintsts;
5388         DWC_PRINTF("GINTSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5389                    DWC_READ_REG32(addr));
5390         addr = &core_if->core_global_regs->gintmsk;
5391         DWC_PRINTF("GINTMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5392                    DWC_READ_REG32(addr));
5393         addr = &core_if->core_global_regs->grxstsr;
5394         DWC_PRINTF("GRXSTSR      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5395                    DWC_READ_REG32(addr));
5396         addr = &core_if->core_global_regs->grxfsiz;
5397         DWC_PRINTF("GRXFSIZ      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5398                    DWC_READ_REG32(addr));
5399         addr = &core_if->core_global_regs->gnptxfsiz;
5400         DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
5401                    DWC_READ_REG32(addr));
5402         addr = &core_if->core_global_regs->gnptxsts;
5403         DWC_PRINTF("GNPTXSTS     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5404                    DWC_READ_REG32(addr));
5405         addr = &core_if->core_global_regs->gi2cctl;
5406         DWC_PRINTF("GI2CCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5407                    DWC_READ_REG32(addr));
5408         addr = &core_if->core_global_regs->gpvndctl;
5409         DWC_PRINTF("GPVNDCTL     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5410                    DWC_READ_REG32(addr));
5411         addr = &core_if->core_global_regs->ggpio;
5412         DWC_PRINTF("GGPIO        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5413                    DWC_READ_REG32(addr));
5414         addr = &core_if->core_global_regs->guid;
5415         DWC_PRINTF("GUID                 @0x%08lX : 0x%08X\n",
5416                    (unsigned long)addr, DWC_READ_REG32(addr));
5417         addr = &core_if->core_global_regs->gsnpsid;
5418         DWC_PRINTF("GSNPSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5419                    DWC_READ_REG32(addr));
5420         addr = &core_if->core_global_regs->ghwcfg1;
5421         DWC_PRINTF("GHWCFG1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5422                    DWC_READ_REG32(addr));
5423         addr = &core_if->core_global_regs->ghwcfg2;
5424         DWC_PRINTF("GHWCFG2      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5425                    DWC_READ_REG32(addr));
5426         addr = &core_if->core_global_regs->ghwcfg3;
5427         DWC_PRINTF("GHWCFG3      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5428                    DWC_READ_REG32(addr));
5429         addr = &core_if->core_global_regs->ghwcfg4;
5430         DWC_PRINTF("GHWCFG4      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5431                    DWC_READ_REG32(addr));
5432         addr = &core_if->core_global_regs->glpmcfg;
5433         DWC_PRINTF("GLPMCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5434                    DWC_READ_REG32(addr));
5435         addr = &core_if->core_global_regs->gpwrdn;
5436         DWC_PRINTF("GPWRDN       @0x%08lX : 0x%08X\n", (unsigned long)addr,
5437                    DWC_READ_REG32(addr));
5438         addr = &core_if->core_global_regs->gdfifocfg;
5439         DWC_PRINTF("GDFIFOCFG    @0x%08lX : 0x%08X\n", (unsigned long)addr,
5440                    DWC_READ_REG32(addr));
5441         addr = &core_if->core_global_regs->hptxfsiz;
5442         DWC_PRINTF("HPTXFSIZ     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5443                    DWC_READ_REG32(addr));
5444
5445         if (core_if->en_multiple_tx_fifo == 0) {
5446                 ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
5447                 txfsiz = "DPTXFSIZ";
5448         } else {
5449                 ep_num = core_if->hwcfg4.b.num_in_eps;
5450                 txfsiz = "DIENPTXF";
5451         }
5452         for (i = 0; i < ep_num; i++) {
5453                 addr = &core_if->core_global_regs->dtxfsiz[i];
5454                 DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
5455                            (unsigned long)addr, DWC_READ_REG32(addr));
5456         }
5457         addr = core_if->pcgcctl;
5458         DWC_PRINTF("PCGCCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5459                    DWC_READ_REG32(addr));
5460 }
5461
5462 /**
5463  * Flush a Tx FIFO.
5464  *
5465  * @param core_if Programming view of DWC_otg controller.
5466  * @param num Tx FIFO to flush.
5467  */
5468 void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t *core_if, const int num)
5469 {
5470         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5471         volatile grstctl_t greset = {.d32 = 0 };
5472         int count = 0;
5473
5474         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
5475
5476         greset.b.txfflsh = 1;
5477         greset.b.txfnum = num;
5478         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5479
5480         do {
5481                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5482                 if (++count > 10000) {
5483                         DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
5484                                  __func__, greset.d32,
5485                                  DWC_READ_REG32(&global_regs->gnptxsts));
5486                         break;
5487                 }
5488                 dwc_udelay(1);
5489         } while (greset.b.txfflsh == 1);
5490
5491         /* Wait for 3 PHY Clocks */
5492         dwc_udelay(1);
5493 }
5494
5495 /**
5496  * Flush Rx FIFO.
5497  *
5498  * @param core_if Programming view of DWC_otg controller.
5499  */
5500 void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t *core_if)
5501 {
5502         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5503         volatile grstctl_t greset = {.d32 = 0 };
5504         int count = 0;
5505
5506         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
5507         /*
5508          *
5509          */
5510         greset.b.rxfflsh = 1;
5511         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5512
5513         do {
5514                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5515                 if (++count > 10000) {
5516                         DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
5517                                  greset.d32);
5518                         break;
5519                 }
5520                 dwc_udelay(1);
5521         } while (greset.b.rxfflsh == 1);
5522
5523         /* Wait for 3 PHY Clocks */
5524         dwc_udelay(1);
5525 }
5526
5527 /**
5528  * Do core a soft reset of the core.  Be careful with this because it
5529  * resets all the internal state machines of the core.
5530  */
5531 void dwc_otg_core_reset(dwc_otg_core_if_t *core_if)
5532 {
5533         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5534         volatile grstctl_t greset = {.d32 = 0 };
5535         volatile gusbcfg_data_t usbcfg = {.d32 = 0 };
5536         int count = 0;
5537
5538         DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
5539         /* Wait for AHB master IDLE state. */
5540         do {
5541                 dwc_udelay(10);
5542                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5543                 if (++count > 100000) {
5544                         DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
5545                                  greset.d32);
5546                         return;
5547                 }
5548         } while (greset.b.ahbidle == 0);
5549
5550         /* Core Soft Reset */
5551         count = 0;
5552         greset.b.csftrst = 1;
5553         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5554
5555         do {
5556                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5557                 if (++count > 10000) {
5558                         DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
5559                                  __func__, greset.d32);
5560                         break;
5561                 }
5562                 dwc_udelay(1);
5563         } while (greset.b.csftrst == 1);
5564
5565         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
5566         if (core_if->usb_mode == USB_MODE_FORCE_HOST) {
5567                 usbcfg.b.force_host_mode = 1;
5568                 usbcfg.b.force_dev_mode = 0;
5569         } else if (core_if->usb_mode == USB_MODE_FORCE_DEVICE) {
5570                 usbcfg.b.force_host_mode = 0;
5571                 usbcfg.b.force_dev_mode = 1;
5572         } else {
5573                 usbcfg.b.force_host_mode = 0;
5574                 usbcfg.b.force_dev_mode = 0;
5575         }
5576         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
5577
5578         /* Wait for 3 PHY Clocks */
5579         dwc_mdelay(100);
5580
5581 }
5582
5583 uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if)
5584 {
5585         return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
5586 }
5587
5588 uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if)
5589 {
5590         return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
5591 }
5592
5593 /**
5594  * Register HCD callbacks. The callbacks are used to start and stop
5595  * the HCD for interrupt processing.
5596  *
5597  * @param core_if Programming view of DWC_otg controller.
5598  * @param cb the HCD callback structure.
5599  * @param p pointer to be passed to callback function (usb_hcd*).
5600  */
5601 void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t *core_if,
5602                                         dwc_otg_cil_callbacks_t *cb, void *p)
5603 {
5604         core_if->hcd_cb = cb;
5605         /* cb->p = p; */
5606         core_if->hcd_cb_p = p;
5607 }
5608
5609 /**
5610  * Register PCD callbacks. The callbacks are used to start and stop
5611  * the PCD for interrupt processing.
5612  *
5613  * @param core_if Programming view of DWC_otg controller.
5614  * @param cb the PCD callback structure.
5615  * @param p pointer to be passed to callback function (pcd*).
5616  */
5617 void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t *core_if,
5618                                         dwc_otg_cil_callbacks_t *cb, void *p)
5619 {
5620         core_if->pcd_cb = cb;
5621         cb->p = p;
5622 }
5623
5624 #ifdef DWC_EN_ISOC
5625
5626 /**
5627  * This function writes isoc data per 1 (micro)frame into tx fifo
5628  *
5629  * @param core_if Programming view of DWC_otg controller.
5630  * @param ep The EP to start the transfer on.
5631  *
5632  */
5633 void write_isoc_frame_data(dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
5634 {
5635         dwc_otg_dev_in_ep_regs_t *ep_regs;
5636         dtxfsts_data_t txstatus = {.d32 = 0 };
5637         uint32_t len = 0;
5638         uint32_t dwords;
5639
5640         ep->xfer_len = ep->data_per_frame;
5641         ep->xfer_count = 0;
5642
5643         ep_regs = core_if->dev_if->in_ep_regs[ep->num];
5644
5645         len = ep->xfer_len - ep->xfer_count;
5646
5647         if (len > ep->maxpacket) {
5648                 len = ep->maxpacket;
5649         }
5650
5651         dwords = (len + 3) / 4;
5652
5653         /* While there is space in the queue and space in the FIFO and
5654          * More data to tranfer, Write packets to the Tx FIFO */
5655         txstatus.d32 =
5656             DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
5657         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
5658
5659         while (txstatus.b.txfspcavail > dwords &&
5660                ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
5661                 /* Write the FIFO */
5662                 dwc_otg_ep_write_packet(core_if, ep, 0);
5663
5664                 len = ep->xfer_len - ep->xfer_count;
5665                 if (len > ep->maxpacket) {
5666                         len = ep->maxpacket;
5667                 }
5668
5669                 dwords = (len + 3) / 4;
5670                 txstatus.d32 =
5671                     DWC_READ_REG32(&core_if->dev_if->
5672                                    in_ep_regs[ep->num]->dtxfsts);
5673                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
5674                             txstatus.d32);
5675         }
5676 }
5677
5678 /**
5679  * This function initializes a descriptor chain for Isochronous transfer
5680  *
5681  * @param core_if Programming view of DWC_otg controller.
5682  * @param ep The EP to start the transfer on.
5683  *
5684  */
5685 void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t *core_if,
5686                                        dwc_ep_t *ep)
5687 {
5688         deptsiz_data_t deptsiz = {.d32 = 0 };
5689         depctl_data_t depctl = {.d32 = 0 };
5690         dsts_data_t dsts = {.d32 = 0 };
5691         volatile uint32_t *addr;
5692
5693         if (ep->is_in)
5694                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
5695         else
5696                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
5697
5698         ep->xfer_len = ep->data_per_frame;
5699         ep->xfer_count = 0;
5700         ep->xfer_buff = ep->cur_pkt_addr;
5701         ep->dma_addr = ep->cur_pkt_dma_addr;
5702
5703         if (ep->is_in) {
5704                 /* Program the transfer size and packet count
5705                  *      as follows: xfersize = N * maxpacket +
5706                  *      short_packet pktcnt = N + (short_packet
5707                  *      exist ? 1 : 0)
5708                  */
5709                 deptsiz.b.xfersize = ep->xfer_len;
5710                 deptsiz.b.pktcnt =
5711                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
5712                 deptsiz.b.mc = deptsiz.b.pktcnt;
5713                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
5714                                 deptsiz.d32);
5715
5716                 /* Write the DMA register */
5717                 if (core_if->dma_enable) {
5718                         DWC_WRITE_REG32(&
5719                                         (core_if->dev_if->
5720                                          in_ep_regs[ep->num]->diepdma),
5721                                         (uint32_t) ep->dma_addr);
5722                 }
5723         } else {
5724                 deptsiz.b.pktcnt =
5725                     (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
5726                 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
5727
5728                 DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
5729                                 doeptsiz, deptsiz.d32);
5730
5731                 if (core_if->dma_enable) {
5732                         DWC_WRITE_REG32(&
5733                                         (core_if->dev_if->out_ep_regs[ep->num]->
5734                                          doepdma), (uint32_t) ep->dma_addr);
5735                 }
5736         }
5737
5738         /** Enable endpoint, clear nak  */
5739
5740         depctl.d32 = 0;
5741         if (ep->bInterval == 1) {
5742                 dsts.d32 =
5743                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
5744                 ep->next_frame = dsts.b.soffn + ep->bInterval;
5745
5746                 if (ep->next_frame & 0x1)
5747                         depctl.b.setd1pid = 1;
5748                 else
5749                         depctl.b.setd0pid = 1;
5750         } else {
5751                 ep->next_frame += ep->bInterval;
5752
5753                 if (ep->next_frame & 0x1)
5754                         depctl.b.setd1pid = 1;
5755                 else
5756                         depctl.b.setd0pid = 1;
5757         }
5758         depctl.b.epena = 1;
5759         depctl.b.cnak = 1;
5760
5761         DWC_MODIFY_REG32(addr, 0, depctl.d32);
5762         depctl.d32 = DWC_READ_REG32(addr);
5763
5764         if (ep->is_in && core_if->dma_enable == 0) {
5765                 write_isoc_frame_data(core_if, ep);
5766         }
5767
5768 }
5769 #endif /* DWC_EN_ISOC */
5770
5771 static void dwc_otg_set_uninitialized(int32_t *p, int size)
5772 {
5773         int i;
5774         for (i = 0; i < size; i++) {
5775                 p[i] = -1;
5776         }
5777 }
5778
5779 static int dwc_otg_param_initialized(int32_t val)
5780 {
5781         return val != -1;
5782 }
5783
5784 static int dwc_otg_setup_params(dwc_otg_core_if_t *core_if)
5785 {
5786         gintsts_data_t gintsts;
5787         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
5788
5789         core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
5790         if (!core_if->core_params)
5791                 return -DWC_E_NO_MEMORY;
5792         dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
5793                                   sizeof(*core_if->core_params) /
5794                                   sizeof(int32_t));
5795         DWC_PRINTF("Setting default values for core params\n");
5796         dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
5797         dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
5798         dwc_otg_set_param_dma_desc_enable(core_if,
5799                                           dwc_param_dma_desc_enable_default);
5800         dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
5801         dwc_otg_set_param_dma_burst_size(core_if,
5802                                          dwc_param_dma_burst_size_default);
5803         dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
5804                                                        dwc_param_host_support_fs_ls_low_power_default);
5805         dwc_otg_set_param_enable_dynamic_fifo(core_if,
5806                                               dwc_param_enable_dynamic_fifo_default);
5807         dwc_otg_set_param_data_fifo_size(core_if,
5808                                          dwc_param_data_fifo_size_default);
5809         dwc_otg_set_param_dev_rx_fifo_size(core_if,
5810                                            dwc_param_dev_rx_fifo_size_default);
5811         dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
5812                                                   dwc_param_dev_nperio_tx_fifo_size_default);
5813         dwc_otg_set_param_host_rx_fifo_size(core_if,
5814                                             dwc_param_host_rx_fifo_size_default);
5815         dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
5816                                                    dwc_param_host_nperio_tx_fifo_size_default);
5817         dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
5818                                                   dwc_param_host_perio_tx_fifo_size_default);
5819         dwc_otg_set_param_max_transfer_size(core_if,
5820                                             dwc_param_max_transfer_size_default);
5821         dwc_otg_set_param_max_packet_count(core_if,
5822                                            dwc_param_max_packet_count_default);
5823         dwc_otg_set_param_host_channels(core_if,
5824                                         dwc_param_host_channels_default);
5825         dwc_otg_set_param_dev_endpoints(core_if,
5826                                         dwc_param_dev_endpoints_default);
5827         dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
5828         dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
5829         dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
5830                                                     dwc_param_host_ls_low_power_phy_clk_default);
5831         dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
5832         dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
5833                                             dwc_param_phy_ulpi_ext_vbus_default);
5834         dwc_otg_set_param_phy_utmi_width(core_if,
5835                                          dwc_param_phy_utmi_width_default);
5836         dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
5837         dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
5838         dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
5839         dwc_otg_set_param_en_multiple_tx_fifo(core_if,
5840                                               dwc_param_en_multiple_tx_fifo_default);
5841
5842         /* do not set dev_perio_tx_fifo_size and dev_tx_fifo_size here
5843          * set validate parameter values in "set_parameters" later.
5844          */
5845 #if 0
5846         if (gintsts.b.curmode) {
5847                 /* Force device mode to get power-on values of device FIFOs */
5848                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
5849                 gusbcfg.d32 =
5850                     DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
5851                 gusbcfg.b.force_dev_mode = 1;
5852                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
5853                                 gusbcfg.d32);
5854                 dwc_mdelay(100);
5855                 for (i = 0; i < 15; i++) {
5856                         dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
5857                                                                  dwc_param_dev_perio_tx_fifo_size_default,
5858                                                                  i);
5859                 }
5860                 for (i = 0; i < 15; i++) {
5861                         dwc_otg_set_param_dev_tx_fifo_size(core_if,
5862                                                            dwc_param_dev_tx_fifo_size_default,
5863                                                            i);
5864                 }
5865                 gusbcfg.d32 =
5866                     DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
5867                 gusbcfg.b.force_dev_mode = 0;
5868                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
5869                                 gusbcfg.d32);
5870                 dwc_mdelay(100);
5871         } else {
5872                 for (i = 0; i < 15; i++) {
5873                         dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
5874                                                                  dwc_param_dev_perio_tx_fifo_size_default,
5875                                                                  i);
5876                 }
5877                 for (i = 0; i < 15; i++) {
5878                         dwc_otg_set_param_dev_tx_fifo_size(core_if,
5879                                                            dwc_param_dev_tx_fifo_size_default,
5880                                                            i);
5881                 }
5882         }
5883 #endif
5884         dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
5885         dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
5886         dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
5887         dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
5888
5889         dwc_otg_set_param_besl_enable(core_if, dwc_param_besl_enable_default);
5890         dwc_otg_set_param_baseline_besl(core_if,
5891                                         dwc_param_baseline_besl_default);
5892         dwc_otg_set_param_deep_besl(core_if, dwc_param_deep_besl_default);
5893
5894         dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
5895         dwc_otg_set_param_tx_thr_length(core_if,
5896                                         dwc_param_tx_thr_length_default);
5897         dwc_otg_set_param_rx_thr_length(core_if,
5898                                         dwc_param_rx_thr_length_default);
5899         dwc_otg_set_param_ahb_thr_ratio(core_if,
5900                                         dwc_param_ahb_thr_ratio_default);
5901         dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
5902         dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
5903         dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
5904         dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
5905         dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
5906         dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
5907         dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
5908         return 0;
5909 }
5910
5911 uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t *core_if)
5912 {
5913         return core_if->dma_enable;
5914 }
5915
5916 /* Checks if the parameter is outside of its valid range of values */
5917 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
5918                 (((_param_) < (_low_)) || \
5919                 ((_param_) > (_high_)))
5920
5921 /* Parameter access functions */
5922 int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t *core_if, int32_t val)
5923 {
5924         int valid;
5925         int retval = 0;
5926         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
5927                 DWC_WARN("Wrong value for otg_cap parameter\n");
5928                 DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
5929                 retval = -DWC_E_INVALID;
5930                 goto out;
5931         }
5932
5933         valid = 1;
5934         switch (val) {
5935         case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
5936                 if (core_if->hwcfg2.b.op_mode !=
5937                     DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5938                         valid = 0;
5939                 break;
5940         case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
5941                 if ((core_if->hwcfg2.b.op_mode !=
5942                      DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5943                     && (core_if->hwcfg2.b.op_mode !=
5944                         DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
5945                     && (core_if->hwcfg2.b.op_mode !=
5946                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
5947                     && (core_if->hwcfg2.b.op_mode !=
5948                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
5949                         valid = 0;
5950                 }
5951                 break;
5952         case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
5953                 /* always valid */
5954                 break;
5955         }
5956         if (!valid) {
5957                 if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
5958                         DWC_ERROR
5959                             ("%d invalid for otg_cap paremter. Check HW configuration.\n",
5960                              val);
5961                 }
5962                 val =
5963                     (((core_if->hwcfg2.b.op_mode ==
5964                        DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5965                       || (core_if->hwcfg2.b.op_mode ==
5966                           DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
5967                       || (core_if->hwcfg2.b.op_mode ==
5968                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
5969                       || (core_if->hwcfg2.b.op_mode ==
5970                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
5971                      DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
5972                      DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
5973                 retval = -DWC_E_INVALID;
5974         }
5975
5976         core_if->core_params->otg_cap = val;
5977 out:
5978         return retval;
5979 }
5980
5981 int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t *core_if)
5982 {
5983         return core_if->core_params->otg_cap;
5984 }
5985
5986 int dwc_otg_set_param_opt(dwc_otg_core_if_t *core_if, int32_t val)
5987 {
5988         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5989                 DWC_WARN("Wrong value for opt parameter\n");
5990                 return -DWC_E_INVALID;
5991         }
5992         core_if->core_params->opt = val;
5993         return 0;
5994 }
5995
5996 int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t *core_if)
5997 {
5998         return core_if->core_params->opt;
5999 }
6000
6001 int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t *core_if, int32_t val)
6002 {
6003         int retval = 0;
6004         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6005                 DWC_WARN("Wrong value for dma enable\n");
6006                 return -DWC_E_INVALID;
6007         }
6008
6009         if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
6010                 if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
6011                         DWC_ERROR
6012                             ("%d invalid for dma_enable paremter. Check HW configuration.\n",
6013                              val);
6014                 }
6015                 val = 0;
6016                 retval = -DWC_E_INVALID;
6017         }
6018
6019         core_if->core_params->dma_enable = val;
6020         if (val == 0) {
6021                 dwc_otg_set_param_dma_desc_enable(core_if, 0);
6022         }
6023         return retval;
6024 }
6025
6026 int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t *core_if)
6027 {
6028         return core_if->core_params->dma_enable;
6029 }
6030
6031 int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t *core_if, int32_t val)
6032 {
6033         int retval = 0;
6034         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6035                 DWC_WARN("Wrong value for dma_enable\n");
6036                 DWC_WARN("dma_desc_enable must be 0 or 1\n");
6037                 return -DWC_E_INVALID;
6038         }
6039
6040         if ((val == 1)
6041             && ((dwc_otg_get_param_dma_enable(core_if) == 0)
6042                 || (core_if->hwcfg4.b.desc_dma == 0))) {
6043                 if (dwc_otg_param_initialized
6044                     (core_if->core_params->dma_desc_enable)) {
6045                         DWC_ERROR
6046                             ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
6047                              val);
6048                 }
6049                 val = 0;
6050                 retval = -DWC_E_INVALID;
6051         }
6052         core_if->core_params->dma_desc_enable = val;
6053         return retval;
6054 }
6055
6056 int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t *core_if)
6057 {
6058         return core_if->core_params->dma_desc_enable;
6059 }
6060
6061 int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *core_if,
6062                                                    int32_t val)
6063 {
6064         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6065                 DWC_WARN("Wrong value for host_support_fs_low_power\n");
6066                 DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
6067                 return -DWC_E_INVALID;
6068         }
6069         core_if->core_params->host_support_fs_ls_low_power = val;
6070         return 0;
6071 }
6072
6073 int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
6074                                                        *core_if)
6075 {
6076         return core_if->core_params->host_support_fs_ls_low_power;
6077 }
6078
6079 int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t *core_if,
6080                                           int32_t val)
6081 {
6082         int retval = 0;
6083         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6084                 DWC_WARN("Wrong value for enable_dynamic_fifo\n");
6085                 DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
6086                 return -DWC_E_INVALID;
6087         }
6088
6089         if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
6090                 if (dwc_otg_param_initialized
6091                     (core_if->core_params->enable_dynamic_fifo)) {
6092                         DWC_ERROR
6093                             ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
6094                              val);
6095                 }
6096                 val = 0;
6097                 retval = -DWC_E_INVALID;
6098         }
6099         core_if->core_params->enable_dynamic_fifo = val;
6100         return retval;
6101 }
6102
6103 int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *core_if)
6104 {
6105         return core_if->core_params->enable_dynamic_fifo;
6106 }
6107
6108 int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t *core_if, int32_t val)
6109 {
6110         int retval = 0;
6111         if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
6112                 DWC_WARN("Wrong value for data_fifo_size\n");
6113                 DWC_WARN("data_fifo_size must be 32-32768\n");
6114                 return -DWC_E_INVALID;
6115         }
6116
6117         if (val > core_if->hwcfg3.b.dfifo_depth) {
6118                 if (dwc_otg_param_initialized
6119                     (core_if->core_params->data_fifo_size)) {
6120                         DWC_ERROR
6121                             ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
6122                              val);
6123                 }
6124                 val = core_if->hwcfg3.b.dfifo_depth;
6125                 retval = -DWC_E_INVALID;
6126         }
6127
6128         core_if->core_params->data_fifo_size = val;
6129         return retval;
6130 }
6131
6132 int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t *core_if)
6133 {
6134         return core_if->core_params->data_fifo_size;
6135 }
6136
6137 int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t *core_if, int32_t val)
6138 {
6139         int retval = 0;
6140         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6141                 DWC_WARN("Wrong value for dev_rx_fifo_size\n");
6142                 DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
6143                 return -DWC_E_INVALID;
6144         }
6145
6146         if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
6147                 if (dwc_otg_param_initialized
6148                     (core_if->core_params->dev_rx_fifo_size)) {
6149                         DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n",
6150                                  val);
6151                 }
6152                 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
6153                 retval = -DWC_E_INVALID;
6154         }
6155
6156         core_if->core_params->dev_rx_fifo_size = val;
6157         return retval;
6158 }
6159
6160 int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t *core_if)
6161 {
6162         return core_if->core_params->dev_rx_fifo_size;
6163 }
6164
6165 int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if,
6166                                               int32_t val)
6167 {
6168         int retval = 0;
6169
6170         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6171                 DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
6172                 DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
6173                 return -DWC_E_INVALID;
6174         }
6175
6176         if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
6177                 if (dwc_otg_param_initialized
6178                     (core_if->core_params->dev_nperio_tx_fifo_size)) {
6179                         DWC_ERROR
6180                             ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
6181                              val);
6182                 }
6183                 val =
6184                     (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
6185                      16);
6186                 retval = -DWC_E_INVALID;
6187         }
6188
6189         core_if->core_params->dev_nperio_tx_fifo_size = val;
6190         return retval;
6191 }
6192
6193 int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if)
6194 {
6195         return core_if->core_params->dev_nperio_tx_fifo_size;
6196 }
6197
6198 int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t *core_if,
6199                                         int32_t val)
6200 {
6201         int retval = 0;
6202
6203         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6204                 DWC_WARN("Wrong value for host_rx_fifo_size\n");
6205                 DWC_WARN("host_rx_fifo_size must be 16-32768\n");
6206                 return -DWC_E_INVALID;
6207         }
6208
6209         if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
6210                 if (dwc_otg_param_initialized
6211                     (core_if->core_params->host_rx_fifo_size)) {
6212                         DWC_ERROR
6213                             ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
6214                              val);
6215                 }
6216                 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
6217                 retval = -DWC_E_INVALID;
6218         }
6219
6220         core_if->core_params->host_rx_fifo_size = val;
6221         return retval;
6222
6223 }
6224
6225 int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t *core_if)
6226 {
6227         return core_if->core_params->host_rx_fifo_size;
6228 }
6229
6230 int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if,
6231                                                int32_t val)
6232 {
6233         int retval = 0;
6234
6235         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6236                 DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
6237                 DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
6238                 return -DWC_E_INVALID;
6239         }
6240
6241         if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
6242                 if (dwc_otg_param_initialized
6243                     (core_if->core_params->host_nperio_tx_fifo_size)) {
6244                         DWC_ERROR
6245                             ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
6246                              val);
6247                 }
6248                 val =
6249                     (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
6250                      16);
6251                 retval = -DWC_E_INVALID;
6252         }
6253
6254         core_if->core_params->host_nperio_tx_fifo_size = val;
6255         return retval;
6256 }
6257
6258 int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *core_if)
6259 {
6260         return core_if->core_params->host_nperio_tx_fifo_size;
6261 }
6262
6263 int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *core_if,
6264                                               int32_t val)
6265 {
6266         int retval = 0;
6267         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6268                 DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
6269                 DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
6270                 return -DWC_E_INVALID;
6271         }
6272
6273         if (val > ((core_if->hptxfsiz.d32) >> 16)) {
6274                 if (dwc_otg_param_initialized
6275                     (core_if->core_params->host_perio_tx_fifo_size)) {
6276                         DWC_ERROR
6277                             ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
6278                              val);
6279                 }
6280                 val = (core_if->hptxfsiz.d32) >> 16;
6281                 retval = -DWC_E_INVALID;
6282         }
6283
6284         core_if->core_params->host_perio_tx_fifo_size = val;
6285         return retval;
6286 }
6287
6288 int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *core_if)
6289 {
6290         return core_if->core_params->host_perio_tx_fifo_size;
6291 }
6292
6293 int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t *core_if,
6294                                         int32_t val)
6295 {
6296         int retval = 0;
6297
6298         if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
6299                 DWC_WARN("Wrong value for max_transfer_size\n");
6300                 DWC_WARN("max_transfer_size must be 2047-524288\n");
6301                 return -DWC_E_INVALID;
6302         }
6303
6304         if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
6305                 if (dwc_otg_param_initialized
6306                     (core_if->core_params->max_transfer_size)) {
6307                         DWC_ERROR
6308                             ("%d invalid for max_transfer_size. Check HW configuration.\n",
6309                              val);
6310                 }
6311                 val =
6312                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
6313                      1);
6314                 retval = -DWC_E_INVALID;
6315         }
6316
6317         core_if->core_params->max_transfer_size = val;
6318         return retval;
6319 }
6320
6321 int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t *core_if)
6322 {
6323         return core_if->core_params->max_transfer_size;
6324 }
6325
6326 int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t *core_if, int32_t val)
6327 {
6328         int retval = 0;
6329
6330         if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
6331                 DWC_WARN("Wrong value for max_packet_count\n");
6332                 DWC_WARN("max_packet_count must be 15-511\n");
6333                 return -DWC_E_INVALID;
6334         }
6335
6336         if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
6337                 if (dwc_otg_param_initialized
6338                     (core_if->core_params->max_packet_count)) {
6339                         DWC_ERROR
6340                             ("%d invalid for max_packet_count. Check HW configuration.\n",
6341                              val);
6342                 }
6343                 val =
6344                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
6345                 retval = -DWC_E_INVALID;
6346         }
6347
6348         core_if->core_params->max_packet_count = val;
6349         return retval;
6350 }
6351
6352 int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t *core_if)
6353 {
6354         return core_if->core_params->max_packet_count;
6355 }
6356
6357 int dwc_otg_set_param_host_channels(dwc_otg_core_if_t *core_if, int32_t val)
6358 {
6359         int retval = 0;
6360
6361         if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
6362                 DWC_WARN("Wrong value for host_channels\n");
6363                 DWC_WARN("host_channels must be 1-16\n");
6364                 return -DWC_E_INVALID;
6365         }
6366
6367         if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
6368                 if (dwc_otg_param_initialized
6369                     (core_if->core_params->host_channels)) {
6370                         DWC_ERROR
6371                             ("%d invalid for host_channels. Check HW configurations.\n",
6372                              val);
6373                 }
6374                 val = (core_if->hwcfg2.b.num_host_chan + 1);
6375                 retval = -DWC_E_INVALID;
6376         }
6377
6378         core_if->core_params->host_channels = val;
6379         return retval;
6380 }
6381
6382 int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t *core_if)
6383 {
6384         return core_if->core_params->host_channels;
6385 }
6386
6387 int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t *core_if, int32_t val)
6388 {
6389         int retval = 0;
6390
6391         if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
6392                 DWC_WARN("Wrong value for dev_endpoints\n");
6393                 DWC_WARN("dev_endpoints must be 1-15\n");
6394                 return -DWC_E_INVALID;
6395         }
6396
6397         if (val > (core_if->hwcfg2.b.num_dev_ep)) {
6398                 if (dwc_otg_param_initialized
6399                     (core_if->core_params->dev_endpoints)) {
6400                         DWC_ERROR
6401                             ("%d invalid for dev_endpoints. Check HW configurations.\n",
6402                              val);
6403                 }
6404                 val = core_if->hwcfg2.b.num_dev_ep;
6405                 retval = -DWC_E_INVALID;
6406         }
6407
6408         core_if->core_params->dev_endpoints = val;
6409         return retval;
6410 }
6411
6412 int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t *core_if)
6413 {
6414         return core_if->core_params->dev_endpoints;
6415 }
6416
6417 int dwc_otg_set_param_phy_type(dwc_otg_core_if_t *core_if, int32_t val)
6418 {
6419         int retval = 0;
6420         int valid = 0;
6421
6422         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
6423                 DWC_WARN("Wrong value for phy_type\n");
6424                 DWC_WARN("phy_type must be 0,1 or 2\n");
6425                 return -DWC_E_INVALID;
6426         }
6427 #ifndef NO_FS_PHY_HW_CHECKS
6428         if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
6429             ((core_if->hwcfg2.b.hs_phy_type == 1) ||
6430              (core_if->hwcfg2.b.hs_phy_type == 3))) {
6431                 valid = 1;
6432         } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
6433                    ((core_if->hwcfg2.b.hs_phy_type == 2) ||
6434                     (core_if->hwcfg2.b.hs_phy_type == 3))) {
6435                 valid = 1;
6436         } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
6437                    (core_if->hwcfg2.b.fs_phy_type == 1)) {
6438                 valid = 1;
6439         }
6440         if (!valid) {
6441                 if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
6442                         DWC_ERROR
6443                             ("%d invalid for phy_type. Check HW configurations.\n",
6444                              val);
6445                 }
6446                 if (core_if->hwcfg2.b.hs_phy_type) {
6447                         if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
6448                             (core_if->hwcfg2.b.hs_phy_type == 1)) {
6449                                 val = DWC_PHY_TYPE_PARAM_UTMI;
6450                         } else {
6451                                 val = DWC_PHY_TYPE_PARAM_ULPI;
6452                         }
6453                 }
6454                 retval = -DWC_E_INVALID;
6455         }
6456 #endif
6457         core_if->core_params->phy_type = val;
6458         return retval;
6459 }
6460
6461 int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t *core_if)
6462 {
6463         return core_if->core_params->phy_type;
6464 }
6465
6466 int dwc_otg_set_param_speed(dwc_otg_core_if_t *core_if, int32_t val)
6467 {
6468         int retval = 0;
6469         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6470                 DWC_WARN("Wrong value for speed parameter\n");
6471                 DWC_WARN("max_speed parameter must be 0 or 1\n");
6472                 return -DWC_E_INVALID;
6473         }
6474         if ((val == 0)
6475             && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
6476                 if (dwc_otg_param_initialized(core_if->core_params->speed)) {
6477                         DWC_ERROR
6478                             ("%d invalid for speed paremter. Check HW configuration.\n",
6479                              val);
6480                 }
6481                 val =
6482                     (dwc_otg_get_param_phy_type(core_if) ==
6483                      DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
6484                 retval = -DWC_E_INVALID;
6485         }
6486         core_if->core_params->speed = val;
6487         return retval;
6488 }
6489
6490 int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t *core_if)
6491 {
6492         return core_if->core_params->speed;
6493 }
6494
6495 int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *core_if,
6496                                                 int32_t val)
6497 {
6498         int retval = 0;
6499
6500         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6501                 DWC_WARN
6502                     ("Wrong value for host_ls_low_power_phy_clk parameter\n");
6503                 DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
6504                 return -DWC_E_INVALID;
6505         }
6506
6507         if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
6508             && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
6509                 if (dwc_otg_param_initialized
6510                     (core_if->core_params->host_ls_low_power_phy_clk)) {
6511                         DWC_ERROR
6512                             ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
6513                              val);
6514                 }
6515                 val =
6516                     (dwc_otg_get_param_phy_type(core_if) ==
6517                      DWC_PHY_TYPE_PARAM_FS) ?
6518                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
6519                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
6520                 retval = -DWC_E_INVALID;
6521         }
6522
6523         core_if->core_params->host_ls_low_power_phy_clk = val;
6524         return retval;
6525 }
6526
6527 int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *core_if)
6528 {
6529         return core_if->core_params->host_ls_low_power_phy_clk;
6530 }
6531
6532 int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t *core_if, int32_t val)
6533 {
6534         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6535                 DWC_WARN("Wrong value for phy_ulpi_ddr\n");
6536                 DWC_WARN("phy_upli_ddr must be 0 or 1\n");
6537                 return -DWC_E_INVALID;
6538         }
6539
6540         core_if->core_params->phy_ulpi_ddr = val;
6541         return 0;
6542 }
6543
6544 int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t *core_if)
6545 {
6546         return core_if->core_params->phy_ulpi_ddr;
6547 }
6548
6549 int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t *core_if,
6550                                         int32_t val)
6551 {
6552         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6553                 DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
6554                 DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
6555                 return -DWC_E_INVALID;
6556         }
6557
6558         core_if->core_params->phy_ulpi_ext_vbus = val;
6559         return 0;
6560 }
6561
6562 int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t *core_if)
6563 {
6564         return core_if->core_params->phy_ulpi_ext_vbus;
6565 }
6566
6567 int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t *core_if, int32_t val)
6568 {
6569         if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
6570                 DWC_WARN("Wrong valaue for phy_utmi_width\n");
6571                 DWC_WARN("phy_utmi_width must be 8 or 16\n");
6572                 return -DWC_E_INVALID;
6573         }
6574
6575         core_if->core_params->phy_utmi_width = val;
6576         return 0;
6577 }
6578
6579 int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t *core_if)
6580 {
6581         return core_if->core_params->phy_utmi_width;
6582 }
6583
6584 int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t *core_if, int32_t val)
6585 {
6586         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6587                 DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
6588                 DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
6589                 return -DWC_E_INVALID;
6590         }
6591
6592         core_if->core_params->ulpi_fs_ls = val;
6593         return 0;
6594 }
6595
6596 int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t *core_if)
6597 {
6598         return core_if->core_params->ulpi_fs_ls;
6599 }
6600
6601 int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t *core_if, int32_t val)
6602 {
6603         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6604                 DWC_WARN("Wrong valaue for ts_dline\n");
6605                 DWC_WARN("ts_dline must be 0 or 1\n");
6606                 return -DWC_E_INVALID;
6607         }
6608
6609         core_if->core_params->ts_dline = val;
6610         return 0;
6611 }
6612
6613 int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t *core_if)
6614 {
6615         return core_if->core_params->ts_dline;
6616 }
6617
6618 int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t *core_if, int32_t val)
6619 {
6620         int retval = 0;
6621         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6622                 DWC_WARN("Wrong valaue for i2c_enable\n");
6623                 DWC_WARN("i2c_enable must be 0 or 1\n");
6624                 return -DWC_E_INVALID;
6625         }
6626 #ifndef NO_FS_PHY_HW_CHECK
6627         if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
6628                 if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
6629                         DWC_ERROR
6630                             ("%d invalid for i2c_enable. Check HW configuration.\n",
6631                              val);
6632                 }
6633                 val = 0;
6634                 retval = -DWC_E_INVALID;
6635         }
6636 #endif
6637
6638         core_if->core_params->i2c_enable = val;
6639         return retval;
6640 }
6641
6642 int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t *core_if)
6643 {
6644         return core_if->core_params->i2c_enable;
6645 }
6646
6647 int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *core_if,
6648                                              int32_t val, int fifo_num)
6649 {
6650         int retval = 0;
6651         gintsts_data_t gintsts;
6652         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
6653
6654         if (core_if->hwcfg4.b.ded_fifo_en == 0) {
6655                 if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
6656                         DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
6657                         DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
6658                         return -DWC_E_INVALID;
6659                 }
6660
6661                 if (val >
6662                     (DWC_READ_REG32
6663                      (&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16)) {
6664                         printk("%d   ",
6665                                DWC_READ_REG32(&core_if->core_global_regs->
6666                                               dtxfsiz[fifo_num]) >> 16);
6667                         printk("val = %d fifo_num = %d\n", val, fifo_num);
6668                         DWC_WARN("Value is larger then power-on FIFO size\n");
6669                         if (dwc_otg_param_initialized
6670                             (core_if->core_params->
6671                              dev_perio_tx_fifo_size[fifo_num])) {
6672                                 DWC_ERROR
6673                                     ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
6674                                      val, fifo_num);
6675                         }
6676                         val =
6677                             (DWC_READ_REG32
6678                              (&core_if->core_global_regs->
6679                               dtxfsiz[fifo_num]) >> 16);
6680                         retval = -DWC_E_INVALID;
6681                 }
6682
6683                 core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
6684         }
6685         return retval;
6686 }
6687
6688 int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *core_if,
6689                                                  int fifo_num)
6690 {
6691         return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
6692 }
6693
6694 int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t *core_if,
6695                                           int32_t val)
6696 {
6697         int retval = 0;
6698         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6699                 DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
6700                 DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
6701                 return -DWC_E_INVALID;
6702         }
6703
6704         if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
6705                 if (dwc_otg_param_initialized
6706                     (core_if->core_params->en_multiple_tx_fifo)) {
6707                         DWC_ERROR
6708                             ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
6709                              val);
6710                 }
6711                 val = 0;
6712                 retval = -DWC_E_INVALID;
6713         }
6714
6715         core_if->core_params->en_multiple_tx_fifo = val;
6716         return retval;
6717 }
6718
6719 int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *core_if)
6720 {
6721         return core_if->core_params->en_multiple_tx_fifo;
6722 }
6723
6724 int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t *core_if, int32_t val,
6725                                        int fifo_num)
6726 {
6727         int retval = 0;
6728         fifosize_data_t txfifosize;
6729         txfifosize.d32 =
6730             DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]);
6731
6732         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6733                 DWC_WARN("Wrong value for dev_tx_fifo_size\n");
6734                 DWC_WARN("dev_tx_fifo_size must be 16-32768\n");
6735                 return -DWC_E_INVALID;
6736         }
6737
6738         core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
6739         return retval;
6740 }
6741
6742 int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t *core_if,
6743                                            int fifo_num)
6744 {
6745         return core_if->core_params->dev_tx_fifo_size[fifo_num];
6746 }
6747
6748 int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t *core_if, int32_t val)
6749 {
6750         int retval = 0;
6751
6752         if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
6753                 DWC_WARN("Wrong value for thr_ctl\n");
6754                 DWC_WARN("thr_ctl must be 0-7\n");
6755                 return -DWC_E_INVALID;
6756         }
6757
6758         if ((val != 0) &&
6759             (!dwc_otg_get_param_dma_enable(core_if) ||
6760              !core_if->hwcfg4.b.ded_fifo_en)) {
6761                 if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
6762                         DWC_ERROR
6763                             ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
6764                              val);
6765                 }
6766                 val = 0;
6767                 retval = -DWC_E_INVALID;
6768         }
6769
6770         core_if->core_params->thr_ctl = val;
6771         return retval;
6772 }
6773
6774 int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t *core_if)
6775 {
6776         return core_if->core_params->thr_ctl;
6777 }
6778
6779 int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t *core_if, int32_t val)
6780 {
6781         int retval = 0;
6782
6783         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6784                 DWC_WARN("Wrong value for lpm_enable\n");
6785                 DWC_WARN("lpm_enable must be 0 or 1\n");
6786                 return -DWC_E_INVALID;
6787         }
6788
6789         if (val && !core_if->hwcfg3.b.otg_lpm_en) {
6790                 if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
6791                         DWC_ERROR
6792                             ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
6793                              val);
6794                 }
6795                 val = 0;
6796                 retval = -DWC_E_INVALID;
6797         }
6798
6799         core_if->core_params->lpm_enable = val;
6800         return retval;
6801 }
6802
6803 int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t *core_if)
6804 {
6805         return core_if->core_params->lpm_enable;
6806 }
6807
6808 int dwc_otg_set_param_besl_enable(dwc_otg_core_if_t *core_if, int32_t val)
6809 {
6810         int retval = 0;
6811
6812         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6813                 DWC_WARN("Wrong value for besl_enable\n");
6814                 DWC_WARN("besl_enable must be 0 or 1\n");
6815                 return -DWC_E_INVALID;
6816         }
6817
6818         core_if->core_params->besl_enable = val;
6819
6820         if (val) {
6821                 retval += dwc_otg_set_param_lpm_enable(core_if, val);
6822         }
6823
6824         return retval;
6825 }
6826
6827 int32_t dwc_otg_get_param_besl_enable(dwc_otg_core_if_t *core_if)
6828 {
6829         return core_if->core_params->besl_enable;
6830 }
6831
6832 int dwc_otg_set_param_baseline_besl(dwc_otg_core_if_t *core_if, int32_t val)
6833 {
6834         int retval = 0;
6835
6836         if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
6837                 DWC_WARN("Wrong value for baseline_besl\n");
6838                 DWC_WARN("baseline_besl must be 0-15\n");
6839                 return -DWC_E_INVALID;
6840         }
6841
6842         core_if->core_params->baseline_besl = val;
6843         return retval;
6844 }
6845
6846 int32_t dwc_otg_get_param_baseline_besl(dwc_otg_core_if_t *core_if)
6847 {
6848         return core_if->core_params->baseline_besl;
6849 }
6850
6851 int dwc_otg_set_param_deep_besl(dwc_otg_core_if_t *core_if, int32_t val)
6852 {
6853         int retval = 0;
6854
6855         if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
6856                 DWC_WARN("Wrong value for deep_besl\n");
6857                 DWC_WARN("deep_besl must be 0-15\n");
6858                 return -DWC_E_INVALID;
6859         }
6860
6861         core_if->core_params->deep_besl = val;
6862         return retval;
6863 }
6864
6865 int32_t dwc_otg_get_param_deep_besl(dwc_otg_core_if_t *core_if)
6866 {
6867         return core_if->core_params->deep_besl;
6868 }
6869
6870 int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t *core_if, int32_t val)
6871 {
6872         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
6873                 DWC_WARN("Wrong valaue for tx_thr_length\n");
6874                 DWC_WARN("tx_thr_length must be 8 - 128\n");
6875                 return -DWC_E_INVALID;
6876         }
6877
6878         core_if->core_params->tx_thr_length = val;
6879         return 0;
6880 }
6881
6882 int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t *core_if)
6883 {
6884         return core_if->core_params->tx_thr_length;
6885 }
6886
6887 int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t *core_if, int32_t val)
6888 {
6889         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
6890                 DWC_WARN("Wrong valaue for rx_thr_length\n");
6891                 DWC_WARN("rx_thr_length must be 8 - 128\n");
6892                 return -DWC_E_INVALID;
6893         }
6894
6895         core_if->core_params->rx_thr_length = val;
6896         return 0;
6897 }
6898
6899 int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t *core_if)
6900 {
6901         return core_if->core_params->rx_thr_length;
6902 }
6903
6904 int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t *core_if, int32_t val)
6905 {
6906         if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
6907             DWC_OTG_PARAM_TEST(val, 4, 4) &&
6908             DWC_OTG_PARAM_TEST(val, 8, 8) &&
6909             DWC_OTG_PARAM_TEST(val, 16, 16) &&
6910             DWC_OTG_PARAM_TEST(val, 32, 32) &&
6911             DWC_OTG_PARAM_TEST(val, 64, 64) &&
6912             DWC_OTG_PARAM_TEST(val, 128, 128) &&
6913             DWC_OTG_PARAM_TEST(val, 256, 256)) {
6914                 DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
6915                 return -DWC_E_INVALID;
6916         }
6917         core_if->core_params->dma_burst_size = val;
6918         return 0;
6919 }
6920
6921 int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t *core_if)
6922 {
6923         return core_if->core_params->dma_burst_size;
6924 }
6925
6926 int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t *core_if, int32_t val)
6927 {
6928         int retval = 0;
6929         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6930                 DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
6931                 return -DWC_E_INVALID;
6932         }
6933         if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
6934                 if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
6935                         DWC_ERROR
6936                             ("%d invalid for parameter pti_enable. Check HW configuration.\n",
6937                              val);
6938                 }
6939                 retval = -DWC_E_INVALID;
6940                 val = 0;
6941         }
6942         core_if->core_params->pti_enable = val;
6943         return retval;
6944 }
6945
6946 int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t *core_if)
6947 {
6948         return core_if->core_params->pti_enable;
6949 }
6950
6951 int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t *core_if, int32_t val)
6952 {
6953         int retval = 0;
6954         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6955                 DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
6956                 return -DWC_E_INVALID;
6957         }
6958         if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
6959                 if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
6960                         DWC_ERROR
6961                             ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
6962                              val);
6963                 }
6964                 retval = -DWC_E_INVALID;
6965                 val = 0;
6966         }
6967         core_if->core_params->mpi_enable = val;
6968         return retval;
6969 }
6970
6971 int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t *core_if)
6972 {
6973         return core_if->core_params->mpi_enable;
6974 }
6975
6976 int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t *core_if, int32_t val)
6977 {
6978         int retval = 0;
6979         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6980                 DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
6981                 return -DWC_E_INVALID;
6982         }
6983         if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
6984                 if (dwc_otg_param_initialized
6985                     (core_if->core_params->adp_supp_enable)) {
6986                         DWC_ERROR
6987                             ("%d invalid for parameter adp_enable. Check HW configuration.\n",
6988                              val);
6989                 }
6990                 retval = -DWC_E_INVALID;
6991                 val = 0;
6992         }
6993         core_if->core_params->adp_supp_enable = val;
6994         /* Set OTG version 2.0 in case of enabling ADP */
6995         if (val)
6996                 dwc_otg_set_param_otg_ver(core_if, 1);
6997
6998         return retval;
6999 }
7000
7001 int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t *core_if)
7002 {
7003         return core_if->core_params->adp_supp_enable;
7004 }
7005
7006 int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t *core_if, int32_t val)
7007 {
7008         int retval = 0;
7009         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7010                 DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
7011                 DWC_WARN("ic_usb_cap must be 0 or 1\n");
7012                 return -DWC_E_INVALID;
7013         }
7014
7015         if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
7016                 if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
7017                         DWC_ERROR
7018                             ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
7019                              val);
7020                 }
7021                 retval = -DWC_E_INVALID;
7022                 val = 0;
7023         }
7024         core_if->core_params->ic_usb_cap = val;
7025         return retval;
7026 }
7027
7028 int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t *core_if)
7029 {
7030         return core_if->core_params->ic_usb_cap;
7031 }
7032
7033 int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t *core_if, int32_t val)
7034 {
7035         int retval = 0;
7036         int valid = 1;
7037
7038         if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
7039                 DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
7040                 DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
7041                 return -DWC_E_INVALID;
7042         }
7043
7044         if (val
7045             && (core_if->snpsid < OTG_CORE_REV_2_81a
7046                 || !dwc_otg_get_param_thr_ctl(core_if))) {
7047                 valid = 0;
7048         } else if (val
7049                    && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
7050                        4)) {
7051                 valid = 0;
7052         }
7053         if (valid == 0) {
7054                 if (dwc_otg_param_initialized
7055                     (core_if->core_params->ahb_thr_ratio)) {
7056                         DWC_ERROR
7057                             ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
7058                              val);
7059                 }
7060                 retval = -DWC_E_INVALID;
7061                 val = 0;
7062         }
7063
7064         core_if->core_params->ahb_thr_ratio = val;
7065         return retval;
7066 }
7067
7068 int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t *core_if)
7069 {
7070         return core_if->core_params->ahb_thr_ratio;
7071 }
7072
7073 int dwc_otg_set_param_power_down(dwc_otg_core_if_t *core_if, int32_t val)
7074 {
7075         int retval = 0;
7076         int valid = 1;
7077         hwcfg4_data_t hwcfg4 = {.d32 = 0 };
7078         hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
7079
7080         if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
7081                 DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
7082                 DWC_WARN("power_down must be 0 - 2\n");
7083                 return -DWC_E_INVALID;
7084         }
7085
7086         if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
7087                 valid = 0;
7088         }
7089         if ((val == 3)
7090             && ((core_if->snpsid < OTG_CORE_REV_3_00a)
7091                 || (hwcfg4.b.xhiber == 0))) {
7092                 valid = 0;
7093         }
7094         if (valid == 0) {
7095                 if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
7096                         DWC_ERROR
7097                             ("%d invalid for parameter power_down. Check HW configuration.\n",
7098                              val);
7099                 }
7100                 retval = -DWC_E_INVALID;
7101                 val = 0;
7102         }
7103         core_if->core_params->power_down = val;
7104         return retval;
7105 }
7106
7107 int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t *core_if)
7108 {
7109         return core_if->core_params->power_down;
7110 }
7111
7112 int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t *core_if, int32_t val)
7113 {
7114         int retval = 0;
7115         int valid = 1;
7116
7117         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7118                 DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
7119                 DWC_WARN("reload_ctl must be 0 or 1\n");
7120                 return -DWC_E_INVALID;
7121         }
7122
7123         if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
7124                 valid = 0;
7125         }
7126         if (valid == 0) {
7127                 if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
7128                         DWC_ERROR("%d invalid for parameter reload_ctl."
7129                                   "Check HW configuration.\n", val);
7130                 }
7131                 retval = -DWC_E_INVALID;
7132                 val = 0;
7133         }
7134         core_if->core_params->reload_ctl = val;
7135         return retval;
7136 }
7137
7138 int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t *core_if)
7139 {
7140         return core_if->core_params->reload_ctl;
7141 }
7142
7143 int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t *core_if, int32_t val)
7144 {
7145         int retval = 0;
7146         int valid = 1;
7147
7148         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7149                 DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
7150                 DWC_WARN("dev_out_nak must be 0 or 1\n");
7151                 return -DWC_E_INVALID;
7152         }
7153
7154         if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
7155                            !(core_if->core_params->dma_desc_enable))) {
7156                 valid = 0;
7157         }
7158         if (valid == 0) {
7159                 if (dwc_otg_param_initialized
7160                     (core_if->core_params->dev_out_nak)) {
7161                         DWC_ERROR("%d invalid for parameter dev_out_nak."
7162                                   "Check HW configuration.\n", val);
7163                 }
7164                 retval = -DWC_E_INVALID;
7165                 val = 0;
7166         }
7167         core_if->core_params->dev_out_nak = val;
7168         return retval;
7169 }
7170
7171 int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t *core_if)
7172 {
7173         return core_if->core_params->dev_out_nak;
7174 }
7175
7176 int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t *core_if, int32_t val)
7177 {
7178         int retval = 0;
7179         int valid = 1;
7180
7181         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7182                 DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
7183                 DWC_WARN("cont_on_bna must be 0 or 1\n");
7184                 return -DWC_E_INVALID;
7185         }
7186
7187         if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
7188                            !(core_if->core_params->dma_desc_enable))) {
7189                 valid = 0;
7190         }
7191         if (valid == 0) {
7192                 if (dwc_otg_param_initialized
7193                     (core_if->core_params->cont_on_bna)) {
7194                         DWC_ERROR("%d invalid for parameter cont_on_bna."
7195                                   "Check HW configuration.\n", val);
7196                 }
7197                 retval = -DWC_E_INVALID;
7198                 val = 0;
7199         }
7200         core_if->core_params->cont_on_bna = val;
7201         return retval;
7202 }
7203
7204 int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t *core_if)
7205 {
7206         return core_if->core_params->cont_on_bna;
7207 }
7208
7209 int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t *core_if, int32_t val)
7210 {
7211         int retval = 0;
7212         int valid = 1;
7213
7214         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7215                 DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
7216                 DWC_WARN("ahb_single must be 0 or 1\n");
7217                 return -DWC_E_INVALID;
7218         }
7219
7220         if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
7221                 valid = 0;
7222         }
7223         if (valid == 0) {
7224                 if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
7225                         DWC_ERROR("%d invalid for parameter ahb_single."
7226                                   "Check HW configuration.\n", val);
7227                 }
7228                 retval = -DWC_E_INVALID;
7229                 val = 0;
7230         }
7231         core_if->core_params->ahb_single = val;
7232         return retval;
7233 }
7234
7235 int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t *core_if)
7236 {
7237         return core_if->core_params->ahb_single;
7238 }
7239
7240 int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t *core_if, int32_t val)
7241 {
7242         int retval = 0;
7243
7244         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
7245                 DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
7246                 DWC_WARN
7247                     ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
7248                 return -DWC_E_INVALID;
7249         }
7250
7251         core_if->core_params->otg_ver = val;
7252         return retval;
7253 }
7254
7255 int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t *core_if)
7256 {
7257         return core_if->core_params->otg_ver;
7258 }
7259
7260 uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t *core_if)
7261 {
7262         gotgctl_data_t otgctl;
7263         otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
7264         return otgctl.b.hstnegscs;
7265 }
7266
7267 uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t *core_if)
7268 {
7269         gotgctl_data_t otgctl;
7270         otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
7271         return otgctl.b.sesreqscs;
7272 }
7273
7274 void dwc_otg_set_hnpreq(dwc_otg_core_if_t *core_if, uint32_t val)
7275 {
7276         if (core_if->otg_ver == 0) {
7277                 gotgctl_data_t otgctl;
7278                 otgctl.d32 =
7279                     DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
7280                 otgctl.b.hnpreq = val;
7281                 DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl,
7282                                 otgctl.d32);
7283         } else {
7284                 core_if->otg_sts = val;
7285         }
7286 }
7287
7288 uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t *core_if)
7289 {
7290         return core_if->snpsid;
7291 }
7292
7293 uint32_t dwc_otg_get_mode(dwc_otg_core_if_t *core_if)
7294 {
7295         gintsts_data_t gintsts;
7296         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
7297         return gintsts.b.curmode;
7298 }
7299
7300 uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t *core_if)
7301 {
7302         gusbcfg_data_t usbcfg;
7303         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7304         return usbcfg.b.hnpcap;
7305 }
7306
7307 void dwc_otg_set_hnpcapable(dwc_otg_core_if_t *core_if, uint32_t val)
7308 {
7309         gusbcfg_data_t usbcfg;
7310         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7311         usbcfg.b.hnpcap = val;
7312         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
7313 }
7314
7315 uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t *core_if)
7316 {
7317         gusbcfg_data_t usbcfg;
7318         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7319         return usbcfg.b.srpcap;
7320 }
7321
7322 void dwc_otg_set_srpcapable(dwc_otg_core_if_t *core_if, uint32_t val)
7323 {
7324         gusbcfg_data_t usbcfg;
7325         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7326         usbcfg.b.srpcap = val;
7327         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
7328 }
7329
7330 uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t *core_if)
7331 {
7332         dcfg_data_t dcfg;
7333         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
7334         return dcfg.b.devspd;
7335 }
7336
7337 void dwc_otg_set_devspeed(dwc_otg_core_if_t *core_if, uint32_t val)
7338 {
7339         dcfg_data_t dcfg;
7340         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
7341         dcfg.b.devspd = val;
7342         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
7343 }
7344
7345 uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t *core_if)
7346 {
7347         hprt0_data_t hprt0;
7348         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
7349         return hprt0.b.prtconnsts;
7350 }
7351
7352 uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t *core_if)
7353 {
7354         dsts_data_t dsts;
7355         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
7356         return dsts.b.enumspd;
7357 }
7358
7359 uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t *core_if)
7360 {
7361         hprt0_data_t hprt0;
7362         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
7363         return hprt0.b.prtpwr;
7364
7365 }
7366
7367 uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t *core_if)
7368 {
7369         return core_if->hibernation_suspend;
7370 }
7371
7372 void dwc_otg_set_prtpower(dwc_otg_core_if_t *core_if, uint32_t val)
7373 {
7374         hprt0_data_t hprt0;
7375         hprt0.d32 = dwc_otg_read_hprt0(core_if);
7376         hprt0.b.prtpwr = val;
7377         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
7378 }
7379
7380 uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t *core_if)
7381 {
7382         hprt0_data_t hprt0;
7383         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
7384         return hprt0.b.prtsusp;
7385
7386 }
7387
7388 void dwc_otg_set_prtsuspend(dwc_otg_core_if_t *core_if, uint32_t val)
7389 {
7390         hprt0_data_t hprt0;
7391         hprt0.d32 = dwc_otg_read_hprt0(core_if);
7392         hprt0.b.prtsusp = val;
7393         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
7394 }
7395
7396 uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t *core_if)
7397 {
7398         hfir_data_t hfir;
7399         hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
7400         return hfir.b.frint;
7401
7402 }
7403
7404 void dwc_otg_set_fr_interval(dwc_otg_core_if_t *core_if, uint32_t val)
7405 {
7406         hfir_data_t hfir;
7407         uint32_t fram_int;
7408         fram_int = calc_frame_interval(core_if);
7409         hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
7410         if (!core_if->core_params->reload_ctl) {
7411                 DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
7412                          "not set to 1.\nShould load driver with reload_ctl=1"
7413                          " module parameter\n");
7414                 return;
7415         }
7416         switch (fram_int) {
7417         case 3750:
7418                 if ((val < 3350) || (val > 4150)) {
7419                         DWC_WARN("HFIR interval for HS core and 30 MHz"
7420                                  "clock freq should be from 3350 to 4150\n");
7421                         return;
7422                 }
7423                 break;
7424         case 30000:
7425                 if ((val < 26820) || (val > 33180)) {
7426                         DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
7427                                  "clock freq should be from 26820 to 33180\n");
7428                         return;
7429                 }
7430                 break;
7431         case 6000:
7432                 if ((val < 5360) || (val > 6640)) {
7433                         DWC_WARN("HFIR interval for HS core and 48 MHz"
7434                                  "clock freq should be from 5360 to 6640\n");
7435                         return;
7436                 }
7437                 break;
7438         case 48000:
7439                 if ((val < 42912) || (val > 53088)) {
7440                         DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
7441                                  "clock freq should be from 42912 to 53088\n");
7442                         return;
7443                 }
7444                 break;
7445         case 7500:
7446                 if ((val < 6700) || (val > 8300)) {
7447                         DWC_WARN("HFIR interval for HS core and 60 MHz"
7448                                  "clock freq should be from 6700 to 8300\n");
7449                         return;
7450                 }
7451                 break;
7452         case 60000:
7453                 if ((val < 53640) || (val > 65536)) {
7454                         DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
7455                                  "clock freq should be from 53640 to 65536\n");
7456                         return;
7457                 }
7458                 break;
7459         default:
7460                 DWC_WARN("Unknown frame interval\n");
7461                 return;
7462                 break;
7463
7464         }
7465         hfir.b.frint = val;
7466         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
7467 }
7468
7469 uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t *core_if)
7470 {
7471         hcfg_data_t hcfg;
7472         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
7473         return hcfg.b.modechtimen;
7474
7475 }
7476
7477 void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t *core_if, uint32_t val)
7478 {
7479         hcfg_data_t hcfg;
7480         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
7481         hcfg.b.modechtimen = val;
7482         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
7483 }
7484
7485 void dwc_otg_set_prtresume(dwc_otg_core_if_t *core_if, uint32_t val)
7486 {
7487         hprt0_data_t hprt0;
7488         hprt0.d32 = dwc_otg_read_hprt0(core_if);
7489         hprt0.b.prtres = val;
7490         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
7491 }
7492
7493 uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t *core_if)
7494 {
7495         dctl_data_t dctl;
7496         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7497         return dctl.b.rmtwkupsig;
7498 }
7499
7500 uint32_t dwc_otg_get_beslreject(dwc_otg_core_if_t *core_if)
7501 {
7502         dctl_data_t dctl;
7503         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7504         return dctl.b.besl_reject;
7505 }
7506
7507 void dwc_otg_set_beslreject(dwc_otg_core_if_t *core_if, uint32_t val)
7508 {
7509         dctl_data_t dctl;
7510         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7511         dctl.b.besl_reject = val;
7512         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
7513 }
7514
7515 uint32_t dwc_otg_get_hirdthresh(dwc_otg_core_if_t *core_if)
7516 {
7517         glpmcfg_data_t lpmcfg;
7518         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7519         return lpmcfg.b.hird_thres;
7520 }
7521
7522 void dwc_otg_set_hirdthresh(dwc_otg_core_if_t *core_if, uint32_t val)
7523 {
7524         glpmcfg_data_t lpmcfg;
7525
7526         if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
7527                 DWC_WARN("Wrong valaue for hird_thres\n");
7528                 DWC_WARN("hird_thres must be 0-f\n");
7529                 return;
7530         }
7531
7532         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7533         lpmcfg.b.hird_thres |= val;
7534         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7535 }
7536
7537 uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t *core_if)
7538 {
7539         glpmcfg_data_t lpmcfg;
7540         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7541
7542         DWC_ASSERT(!
7543                    ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
7544                    "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
7545                    core_if->lx_state, lpmcfg.b.prt_sleep_sts);
7546
7547         return lpmcfg.b.prt_sleep_sts;
7548 }
7549
7550 uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t *core_if)
7551 {
7552         glpmcfg_data_t lpmcfg;
7553         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7554         return lpmcfg.b.rem_wkup_en;
7555 }
7556
7557 uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t *core_if)
7558 {
7559         glpmcfg_data_t lpmcfg;
7560         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7561         return lpmcfg.b.appl_resp;
7562 }
7563
7564 void dwc_otg_set_lpmresponse(dwc_otg_core_if_t *core_if, uint32_t val)
7565 {
7566         glpmcfg_data_t lpmcfg;
7567         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7568         lpmcfg.b.appl_resp = val;
7569         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7570 }
7571
7572 uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t *core_if)
7573 {
7574         glpmcfg_data_t lpmcfg;
7575         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7576         return lpmcfg.b.hsic_connect;
7577 }
7578
7579 void dwc_otg_set_hsic_connect(dwc_otg_core_if_t *core_if, uint32_t val)
7580 {
7581         glpmcfg_data_t lpmcfg;
7582         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7583         lpmcfg.b.hsic_connect = val;
7584         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7585 }
7586
7587 uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t *core_if)
7588 {
7589         glpmcfg_data_t lpmcfg;
7590         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7591         return lpmcfg.b.inv_sel_hsic;
7592
7593 }
7594
7595 void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t *core_if, uint32_t val)
7596 {
7597         glpmcfg_data_t lpmcfg;
7598         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7599         lpmcfg.b.inv_sel_hsic = val;
7600         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7601 }
7602
7603 uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t *core_if)
7604 {
7605         return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
7606 }
7607
7608 void dwc_otg_set_gotgctl(dwc_otg_core_if_t *core_if, uint32_t val)
7609 {
7610         DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
7611 }
7612
7613 uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t *core_if)
7614 {
7615         return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7616 }
7617
7618 void dwc_otg_set_gusbcfg(dwc_otg_core_if_t *core_if, uint32_t val)
7619 {
7620         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
7621 }
7622
7623 uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t *core_if)
7624 {
7625         return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
7626 }
7627
7628 void dwc_otg_set_grxfsiz(dwc_otg_core_if_t *core_if, uint32_t val)
7629 {
7630         DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
7631 }
7632
7633 uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t *core_if)
7634 {
7635         return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
7636 }
7637
7638 void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t *core_if, uint32_t val)
7639 {
7640         DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
7641 }
7642
7643 uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t *core_if)
7644 {
7645         return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
7646 }
7647
7648 void dwc_otg_set_gpvndctl(dwc_otg_core_if_t *core_if, uint32_t val)
7649 {
7650         DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
7651 }
7652
7653 uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t *core_if)
7654 {
7655         return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
7656 }
7657
7658 void dwc_otg_set_ggpio(dwc_otg_core_if_t *core_if, uint32_t val)
7659 {
7660         DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
7661 }
7662
7663 uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t *core_if)
7664 {
7665         return DWC_READ_REG32(core_if->host_if->hprt0);
7666
7667 }
7668
7669 void dwc_otg_set_hprt0(dwc_otg_core_if_t *core_if, uint32_t val)
7670 {
7671         DWC_WRITE_REG32(core_if->host_if->hprt0, val);
7672 }
7673
7674 uint32_t dwc_otg_get_guid(dwc_otg_core_if_t *core_if)
7675 {
7676         return DWC_READ_REG32(&core_if->core_global_regs->guid);
7677 }
7678
7679 void dwc_otg_set_guid(dwc_otg_core_if_t *core_if, uint32_t val)
7680 {
7681         DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
7682 }
7683
7684 uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t *core_if)
7685 {
7686         return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
7687 }
7688
7689 uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t *core_if)
7690 {
7691         return ((core_if->otg_ver ==
7692                  1) ? (uint16_t) 0x0200 : (uint16_t) 0x0103);
7693 }
7694
7695 /**
7696  * Start the SRP timer to detect when the SRP does not complete within
7697  * 6 seconds.
7698  *
7699  * @param core_if the pointer to core_if strucure.
7700  */
7701 void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t *core_if)
7702 {
7703         core_if->srp_timer_started = 1;
7704         DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */);
7705 }
7706
7707 void dwc_otg_initiate_srp(void *p)
7708 {
7709         dwc_otg_core_if_t *core_if = p;
7710         uint32_t *addr = (uint32_t *)&(core_if->core_global_regs->gotgctl);
7711         gotgctl_data_t mem;
7712         gotgctl_data_t val;
7713
7714         val.d32 = DWC_READ_REG32(addr);
7715         if (val.b.sesreq) {
7716                 DWC_ERROR("Session Request Already active!\n");
7717                 return;
7718         }
7719
7720         DWC_INFO("Session Request Initated\n");
7721         mem.d32 = DWC_READ_REG32(addr);
7722         mem.b.sesreq = 1;
7723         DWC_WRITE_REG32(addr, mem.d32);
7724
7725         /* Start the SRP timer */
7726         dwc_otg_pcd_start_srp_timer(core_if);
7727         return;
7728 }
7729
7730 int dwc_otg_check_haps_status(dwc_otg_core_if_t *core_if)
7731 {
7732         int retval = 0;
7733
7734         if (DWC_READ_REG32(&core_if->core_global_regs->gsnpsid) == 0xffffffff) {
7735                 return -1;
7736         } else {
7737                 return retval;
7738         }
7739
7740 }
7741
7742 void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode)
7743 {
7744         gusbcfg_data_t usbcfg = {.d32 = 0 };
7745
7746         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7747         switch (mode) {
7748         case USB_MODE_FORCE_HOST:
7749                 usbcfg.b.force_host_mode = 1;
7750                 usbcfg.b.force_dev_mode = 0;
7751                 break;
7752         case USB_MODE_FORCE_DEVICE:
7753                 usbcfg.b.force_host_mode = 0;
7754                 usbcfg.b.force_dev_mode = 1;
7755                 break;
7756         case USB_MODE_NORMAL:
7757                 usbcfg.b.force_host_mode = 0;
7758                 usbcfg.b.force_dev_mode = 0;
7759                 break;
7760         }
7761         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
7762 }