drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 /**
 149  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 150  * @dwc: pointer to our context structure
 151  *
 152  * This function will a best effort FIFO allocation in order
 153  * to improve FIFO usage and throughput, while still allowing
 154  * us to enable as many endpoints as possible.
 155  *
 156  * Keep in mind that this operation will be highly dependent
 157  * on the configured size for RAM1 - which contains TxFifo -,
 158  * the amount of endpoints enabled on coreConsultant tool, and
 159  * the width of the Master Bus.
 160  *
 161  * In the ideal world, we would always be able to satisfy the
 162  * following equation:
 163  *
 164  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 165  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 166  *
 167  * Unfortunately, due to many variables that's not always the case.
 168  */
 169 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 170 {
 171         int             last_fifo_depth = 0;
 172         int             ram1_depth;
 173         int             fifo_size;
 174         int             mdwidth;
 175         int             num;
 176
 177         if (!dwc->needs_fifo_resize)
 178                 return 0;
 179
 180         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 181         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 182
 183         /* MDWIDTH is represented in bits, we need it in bytes */
 184         mdwidth >>= 3;
 185
 186         /*
 187          * FIXME For now we will only allocate 1 wMaxPacketSize space
 188          * for each enabled endpoint, later patches will come to
 189          * improve this algorithm so that we better use the internal
 190          * FIFO space
 191          */
 192         for (num = 0; num < dwc->num_in_eps; num++) {
 193                 /* bit0 indicates direction; 1 means IN ep */
 194                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 195                 int             mult = 1;
 196                 int             tmp;
 197
 198                 if (!(dep->flags & DWC3_EP_ENABLED))
 199                         continue;
 200
 201                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 202                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 203                         mult = 3;
 204
 205                 /*
 206                  * REVISIT: the following assumes we will always have enough
 207                  * space available on the FIFO RAM for all possible use cases.
 208                  * Make sure that's true somehow and change FIFO allocation
 209                  * accordingly.
 210                  *
 211                  * If we have Bulk or Isochronous endpoints, we want
 212                  * them to be able to be very, very fast. So we're giving
 213                  * those endpoints a fifo_size which is enough for 3 full
 214                  * packets
 215                  */
 216                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 217                 tmp += mdwidth;
 218
 219                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 220
 221                 fifo_size |= (last_fifo_depth << 16);
 222
 223                 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
 224                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 225
 226                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 227
 228                 last_fifo_depth += (fifo_size & 0xffff);
 229         }
 230
 231         return 0;
 232 }
 233
 234 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 235                 int status)
 236 {
 237         struct dwc3                     *dwc = dep->dwc;
 238         int                             i;
 239
 240         if (req->queued) {
 241                 i = 0;
 242                 do {
 243                         dep->busy_slot++;
 244                         /*
 245                          * Skip LINK TRB. We can't use req->trb and check for
 246                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 247                          * just completed (not the LINK TRB).
 248                          */
 249                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 250                                 DWC3_TRB_NUM- 1) &&
 251                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 252                                 dep->busy_slot++;
 253                 } while(++i < req->request.num_mapped_sgs);
 254                 req->queued = false;
 255         }
 256         list_del(&req->list);
 257         req->trb = NULL;
 258
 259         if (req->request.status == -EINPROGRESS)
 260                 req->request.status = status;
 261
 262         if (dwc->ep0_bounced && dep->number == 0)
 263                 dwc->ep0_bounced = false;
 264         else
 265                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 266                                 req->direction);
 267
 268         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 269                         req, dep->name, req->request.actual,
 270                         req->request.length, status);
 271         trace_dwc3_gadget_giveback(req);
 272
 273         spin_unlock(&dwc->lock);
 274         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 275         spin_lock(&dwc->lock);
 276 }
 277
 278 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 279 {
 280         u32             timeout = 500;
 281         u32             reg;
 282
 283         trace_dwc3_gadget_generic_cmd(cmd, param);
 284
 285         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 286         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 287
 288         do {
 289                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 290                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 291                         dwc3_trace(trace_dwc3_gadget,
 292                                         "Command Complete --> %d",
 293                                         DWC3_DGCMD_STATUS(reg));
 294                         if (DWC3_DGCMD_STATUS(reg))
 295                                 return -EINVAL;
 296                         return 0;
 297                 }
 298
 299                 /*
 300                  * We can't sleep here, because it's also called from
 301                  * interrupt context.
 302                  */
 303                 timeout--;
 304                 if (!timeout) {
 305                         dwc3_trace(trace_dwc3_gadget,
 306                                         "Command Timed Out");
 307                         return -ETIMEDOUT;
 308                 }
 309                 udelay(1);
 310         } while (1);
 311 }
 312
 313 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 314                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 315 {
 316         struct dwc3_ep          *dep = dwc->eps[ep];
 317         u32                     timeout = 500;
 318         u32                     reg;
 319
 320         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 321
 322         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 323         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 324         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 325
 326         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 327         do {
 328                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 329                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 330                         dwc3_trace(trace_dwc3_gadget,
 331                                         "Command Complete --> %d",
 332                                         DWC3_DEPCMD_STATUS(reg));
 333                         if (DWC3_DEPCMD_STATUS(reg))
 334                                 return -EINVAL;
 335                         return 0;
 336                 }
 337
 338                 /*
 339                  * We can't sleep here, because it is also called from
 340                  * interrupt context.
 341                  */
 342                 timeout--;
 343                 if (!timeout) {
 344                         dwc3_trace(trace_dwc3_gadget,
 345                                         "Command Timed Out");
 346                         return -ETIMEDOUT;
 347                 }
 348
 349                 udelay(1);
 350         } while (1);
 351 }
 352
 353 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 354                 struct dwc3_trb *trb)
 355 {
 356         u32             offset = (char *) trb - (char *) dep->trb_pool;
 357
 358         return dep->trb_pool_dma + offset;
 359 }
 360
 361 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 362 {
 363         struct dwc3             *dwc = dep->dwc;
 364
 365         if (dep->trb_pool)
 366                 return 0;
 367
 368         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 369                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 370                         &dep->trb_pool_dma, GFP_KERNEL);
 371         if (!dep->trb_pool) {
 372                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 373                                 dep->name);
 374                 return -ENOMEM;
 375         }
 376
 377         return 0;
 378 }
 379
 380 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 381 {
 382         struct dwc3             *dwc = dep->dwc;
 383
 384         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 385                         dep->trb_pool, dep->trb_pool_dma);
 386
 387         dep->trb_pool = NULL;
 388         dep->trb_pool_dma = 0;
 389 }
 390
 391 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 392
 393 /**
 394  * dwc3_gadget_start_config - Configure EP resources
 395  * @dwc: pointer to our controller context structure
 396  * @dep: endpoint that is being enabled
 397  *
 398  * The assignment of transfer resources cannot perfectly follow the
 399  * data book due to the fact that the controller driver does not have
 400  * all knowledge of the configuration in advance. It is given this
 401  * information piecemeal by the composite gadget framework after every
 402  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 403  * programming model in this scenario can cause errors. For two
 404  * reasons:
 405  *
 406  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 407  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 408  * multiple interfaces.
 409  *
 410  * 2) The databook does not mention doing more DEPXFERCFG for new
 411  * endpoint on alt setting (8.1.6).
 412  *
 413  * The following simplified method is used instead:
 414  *
 415  * All hardware endpoints can be assigned a transfer resource and this
 416  * setting will stay persistent until either a core reset or
 417  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 418  * do DEPXFERCFG for every hardware endpoint as well. We are
 419  * guaranteed that there are as many transfer resources as endpoints.
 420  *
 421  * This function is called for each endpoint when it is being enabled
 422  * but is triggered only when called for EP0-out, which always happens
 423  * first, and which should only happen in one of the above conditions.
 424  */
 425 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 426 {
 427         struct dwc3_gadget_ep_cmd_params params;
 428         u32                     cmd;
 429         int                     i;
 430         int                     ret;
 431
 432         if (dep->number)
 433                 return 0;
 434
 435         memset(&params, 0x00, sizeof(params));
 436         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 437
 438         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 439         if (ret)
 440                 return ret;
 441
 442         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 443                 struct dwc3_ep *dep = dwc->eps[i];
 444
 445                 if (!dep)
 446                         continue;
 447
 448                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 449                 if (ret)
 450                         return ret;
 451         }
 452
 453         return 0;
 454 }
 455
 456 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 457                 const struct usb_endpoint_descriptor *desc,
 458                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 459                 bool ignore, bool restore)
 460 {
 461         struct dwc3_gadget_ep_cmd_params params;
 462
 463         memset(&params, 0x00, sizeof(params));
 464
 465         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 466                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 467
 468         /* Burst size is only needed in SuperSpeed mode */
 469         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 470                 u32 burst = dep->endpoint.maxburst - 1;
 471
 472                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 473         }
 474
 475         if (ignore)
 476                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 477
 478         if (restore) {
 479                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 480                 params.param2 |= dep->saved_state;
 481         }
 482
 483         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 484                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 485
 486         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 487                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 488                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 489                 dep->stream_capable = true;
 490         }
 491
 492         if (!usb_endpoint_xfer_control(desc))
 493                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 494
 495         /*
 496          * We are doing 1:1 mapping for endpoints, meaning
 497          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 498          * so on. We consider the direction bit as part of the physical
 499          * endpoint number. So USB endpoint 0x81 is 0x03.
 500          */
 501         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 502
 503         /*
 504          * We must use the lower 16 TX FIFOs even though
 505          * HW might have more
 506          */
 507         if (dep->direction)
 508                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 509
 510         if (desc->bInterval) {
 511                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 512                 dep->interval = 1 << (desc->bInterval - 1);
 513         }
 514
 515         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 516                         DWC3_DEPCMD_SETEPCONFIG, &params);
 517 }
 518
 519 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 520 {
 521         struct dwc3_gadget_ep_cmd_params params;
 522
 523         memset(&params, 0x00, sizeof(params));
 524
 525         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 526
 527         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 528                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 529 }
 530
 531 /**
 532  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 533  * @dep: endpoint to be initialized
 534  * @desc: USB Endpoint Descriptor
 535  *
 536  * Caller should take care of locking
 537  */
 538 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 539                 const struct usb_endpoint_descriptor *desc,
 540                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 541                 bool ignore, bool restore)
 542 {
 543         struct dwc3             *dwc = dep->dwc;
 544         u32                     reg;
 545         int                     ret;
 546
 547         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 548
 549         if (!(dep->flags & DWC3_EP_ENABLED)) {
 550                 ret = dwc3_gadget_start_config(dwc, dep);
 551                 if (ret)
 552                         return ret;
 553         }
 554
 555         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 556                         restore);
 557         if (ret)
 558                 return ret;
 559
 560         if (!(dep->flags & DWC3_EP_ENABLED)) {
 561                 struct dwc3_trb *trb_st_hw;
 562                 struct dwc3_trb *trb_link;
 563
 564                 dep->endpoint.desc = desc;
 565                 dep->comp_desc = comp_desc;
 566                 dep->type = usb_endpoint_type(desc);
 567                 dep->flags |= DWC3_EP_ENABLED;
 568
 569                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 570                 reg |= DWC3_DALEPENA_EP(dep->number);
 571                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 572
 573                 if (!usb_endpoint_xfer_isoc(desc))
 574                         return 0;
 575
 576                 /* Link TRB for ISOC. The HWO bit is never reset */
 577                 trb_st_hw = &dep->trb_pool[0];
 578
 579                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 580                 memset(trb_link, 0, sizeof(*trb_link));
 581
 582                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 583                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 584                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 585                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 586         }
 587
 588         switch (usb_endpoint_type(desc)) {
 589         case USB_ENDPOINT_XFER_CONTROL:
 590                 strlcat(dep->name, "-control", sizeof(dep->name));
 591                 break;
 592         case USB_ENDPOINT_XFER_ISOC:
 593                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 594                 break;
 595         case USB_ENDPOINT_XFER_BULK:
 596                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 597                 break;
 598         case USB_ENDPOINT_XFER_INT:
 599                 strlcat(dep->name, "-int", sizeof(dep->name));
 600                 break;
 601         default:
 602                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 603         }
 604
 605         return 0;
 606 }
 607
 608 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 609 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 610 {
 611         struct dwc3_request             *req;
 612
 613         if (!list_empty(&dep->req_queued)) {
 614                 dwc3_stop_active_transfer(dwc, dep->number, true);
 615
 616                 /* - giveback all requests to gadget driver */
 617                 while (!list_empty(&dep->req_queued)) {
 618                         req = next_request(&dep->req_queued);
 619
 620                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 621                 }
 622         }
 623
 624         while (!list_empty(&dep->request_list)) {
 625                 req = next_request(&dep->request_list);
 626
 627                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 628         }
 629 }
 630
 631 /**
 632  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 633  * @dep: the endpoint to disable
 634  *
 635  * This function also removes requests which are currently processed ny the
 636  * hardware and those which are not yet scheduled.
 637  * Caller should take care of locking.
 638  */
 639 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 640 {
 641         struct dwc3             *dwc = dep->dwc;
 642         u32                     reg;
 643
 644         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 645
 646         dwc3_remove_requests(dwc, dep);
 647
 648         /* make sure HW endpoint isn't stalled */
 649         if (dep->flags & DWC3_EP_STALL)
 650                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 651
 652         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 653         reg &= ~DWC3_DALEPENA_EP(dep->number);
 654         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 655
 656         dep->stream_capable = false;
 657         dep->endpoint.desc = NULL;
 658         dep->comp_desc = NULL;
 659         dep->type = 0;
 660         dep->flags = 0;
 661
 662         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 663                         dep->number >> 1,
 664                         (dep->number & 1) ? "in" : "out");
 665
 666         return 0;
 667 }
 668
 669 /* -------------------------------------------------------------------------- */
 670
 671 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 672                 const struct usb_endpoint_descriptor *desc)
 673 {
 674         return -EINVAL;
 675 }
 676
 677 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 678 {
 679         return -EINVAL;
 680 }
 681
 682 /* -------------------------------------------------------------------------- */
 683
 684 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 685                 const struct usb_endpoint_descriptor *desc)
 686 {
 687         struct dwc3_ep                  *dep;
 688         struct dwc3                     *dwc;
 689         unsigned long                   flags;
 690         int                             ret;
 691
 692         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 693                 pr_debug("dwc3: invalid parameters\n");
 694                 return -EINVAL;
 695         }
 696
 697         if (!desc->wMaxPacketSize) {
 698                 pr_debug("dwc3: missing wMaxPacketSize\n");
 699                 return -EINVAL;
 700         }
 701
 702         dep = to_dwc3_ep(ep);
 703         dwc = dep->dwc;
 704
 705         if (dep->flags & DWC3_EP_ENABLED) {
 706                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 707                                 dep->name);
 708                 return 0;
 709         }
 710
 711         spin_lock_irqsave(&dwc->lock, flags);
 712         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 713         spin_unlock_irqrestore(&dwc->lock, flags);
 714
 715         return ret;
 716 }
 717
 718 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 719 {
 720         struct dwc3_ep                  *dep;
 721         struct dwc3                     *dwc;
 722         unsigned long                   flags;
 723         int                             ret;
 724
 725         if (!ep) {
 726                 pr_debug("dwc3: invalid parameters\n");
 727                 return -EINVAL;
 728         }
 729
 730         dep = to_dwc3_ep(ep);
 731         dwc = dep->dwc;
 732
 733         if (!(dep->flags & DWC3_EP_ENABLED)) {
 734                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 735                                 dep->name);
 736                 return 0;
 737         }
 738
 739         spin_lock_irqsave(&dwc->lock, flags);
 740         ret = __dwc3_gadget_ep_disable(dep);
 741         spin_unlock_irqrestore(&dwc->lock, flags);
 742
 743         return ret;
 744 }
 745
 746 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 747         gfp_t gfp_flags)
 748 {
 749         struct dwc3_request             *req;
 750         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 751
 752         req = kzalloc(sizeof(*req), gfp_flags);
 753         if (!req)
 754                 return NULL;
 755
 756         req->epnum      = dep->number;
 757         req->dep        = dep;
 758
 759         trace_dwc3_alloc_request(req);
 760
 761         return &req->request;
 762 }
 763
 764 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 765                 struct usb_request *request)
 766 {
 767         struct dwc3_request             *req = to_dwc3_request(request);
 768
 769         trace_dwc3_free_request(req);
 770         kfree(req);
 771 }
 772
 773 /**
 774  * dwc3_prepare_one_trb - setup one TRB from one request
 775  * @dep: endpoint for which this request is prepared
 776  * @req: dwc3_request pointer
 777  */
 778 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 779                 struct dwc3_request *req, dma_addr_t dma,
 780                 unsigned length, unsigned last, unsigned chain, unsigned node)
 781 {
 782         struct dwc3_trb         *trb;
 783
 784         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 785                         dep->name, req, (unsigned long long) dma,
 786                         length, last ? " last" : "",
 787                         chain ? " chain" : "");
 788
 789
 790         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 791
 792         if (!req->trb) {
 793                 dwc3_gadget_move_request_queued(req);
 794                 req->trb = trb;
 795                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 796                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 797         }
 798
 799         dep->free_slot++;
 800         /* Skip the LINK-TRB on ISOC */
 801         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 802                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 803                 dep->free_slot++;
 804
 805         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 806         trb->bpl = lower_32_bits(dma);
 807         trb->bph = upper_32_bits(dma);
 808
 809         switch (usb_endpoint_type(dep->endpoint.desc)) {
 810         case USB_ENDPOINT_XFER_CONTROL:
 811                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 812                 break;
 813
 814         case USB_ENDPOINT_XFER_ISOC:
 815                 if (!node)
 816                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 817                 else
 818                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 819                 break;
 820
 821         case USB_ENDPOINT_XFER_BULK:
 822         case USB_ENDPOINT_XFER_INT:
 823                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 824                 break;
 825         default:
 826                 /*
 827                  * This is only possible with faulty memory because we
 828                  * checked it already :)
 829                  */
 830                 BUG();
 831         }
 832
 833         if (!req->request.no_interrupt && !chain)
 834                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 835
 836         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 837                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 838                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 839         } else if (last) {
 840                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 841         }
 842
 843         if (chain)
 844                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 845
 846         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 847                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 848
 849         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 850
 851         trace_dwc3_prepare_trb(dep, trb);
 852 }
 853
 854 /*
 855  * dwc3_prepare_trbs - setup TRBs from requests
 856  * @dep: endpoint for which requests are being prepared
 857  * @starting: true if the endpoint is idle and no requests are queued.
 858  *
 859  * The function goes through the requests list and sets up TRBs for the
 860  * transfers. The function returns once there are no more TRBs available or
 861  * it runs out of requests.
 862  */
 863 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 864 {
 865         struct dwc3_request     *req, *n;
 866         u32                     trbs_left;
 867         u32                     max;
 868         unsigned int            last_one = 0;
 869
 870         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 871
 872         /* the first request must not be queued */
 873         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 874
 875         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 876         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 877                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 878                 if (trbs_left > max)
 879                         trbs_left = max;
 880         }
 881
 882         /*
 883          * If busy & slot are equal than it is either full or empty. If we are
 884          * starting to process requests then we are empty. Otherwise we are
 885          * full and don't do anything
 886          */
 887         if (!trbs_left) {
 888                 if (!starting)
 889                         return;
 890                 trbs_left = DWC3_TRB_NUM;
 891                 /*
 892                  * In case we start from scratch, we queue the ISOC requests
 893                  * starting from slot 1. This is done because we use ring
 894                  * buffer and have no LST bit to stop us. Instead, we place
 895                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 896                  * after the first request so we start at slot 1 and have
 897                  * 7 requests proceed before we hit the first IOC.
 898                  * Other transfer types don't use the ring buffer and are
 899                  * processed from the first TRB until the last one. Since we
 900                  * don't wrap around we have to start at the beginning.
 901                  */
 902                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 903                         dep->busy_slot = 1;
 904                         dep->free_slot = 1;
 905                 } else {
 906                         dep->busy_slot = 0;
 907                         dep->free_slot = 0;
 908                 }
 909         }
 910
 911         /* The last TRB is a link TRB, not used for xfer */
 912         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 913                 return;
 914
 915         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 916                 unsigned        length;
 917                 dma_addr_t      dma;
 918                 last_one = false;
 919
 920                 if (req->request.num_mapped_sgs > 0) {
 921                         struct usb_request *request = &req->request;
 922                         struct scatterlist *sg = request->sg;
 923                         struct scatterlist *s;
 924                         int             i;
 925
 926                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 927                                 unsigned chain = true;
 928
 929                                 length = sg_dma_len(s);
 930                                 dma = sg_dma_address(s);
 931
 932                                 if (i == (request->num_mapped_sgs - 1) ||
 933                                                 sg_is_last(s)) {
 934                                         if (list_empty(&dep->request_list))
 935                                                 last_one = true;
 936                                         chain = false;
 937                                 }
 938
 939                                 trbs_left--;
 940                                 if (!trbs_left)
 941                                         last_one = true;
 942
 943                                 if (last_one)
 944                                         chain = false;
 945
 946                                 dwc3_prepare_one_trb(dep, req, dma, length,
 947                                                 last_one, chain, i);
 948
 949                                 if (last_one)
 950                                         break;
 951                         }
 952
 953                         if (last_one)
 954                                 break;
 955                 } else {
 956                         dma = req->request.dma;
 957                         length = req->request.length;
 958                         trbs_left--;
 959
 960                         if (!trbs_left)
 961                                 last_one = 1;
 962
 963                         /* Is this the last request? */
 964                         if (list_is_last(&req->list, &dep->request_list))
 965                                 last_one = 1;
 966
 967                         dwc3_prepare_one_trb(dep, req, dma, length,
 968                                         last_one, false, 0);
 969
 970                         if (last_one)
 971                                 break;
 972                 }
 973         }
 974 }
 975
 976 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 977                 int start_new)
 978 {
 979         struct dwc3_gadget_ep_cmd_params params;
 980         struct dwc3_request             *req;
 981         struct dwc3                     *dwc = dep->dwc;
 982         int                             ret;
 983         u32                             cmd;
 984
 985         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 986                 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
 987                 return -EBUSY;
 988         }
 989
 990         /*
 991          * If we are getting here after a short-out-packet we don't enqueue any
 992          * new requests as we try to set the IOC bit only on the last request.
 993          */
 994         if (start_new) {
 995                 if (list_empty(&dep->req_queued))
 996                         dwc3_prepare_trbs(dep, start_new);
 997
 998                 /* req points to the first request which will be sent */
 999                 req = next_request(&dep->req_queued);
1000         } else {
1001                 dwc3_prepare_trbs(dep, start_new);
1002
1003                 /*
1004                  * req points to the first request where HWO changed from 0 to 1
1005                  */
1006                 req = next_request(&dep->req_queued);
1007         }
1008         if (!req) {
1009                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1010                 return 0;
1011         }
1012
1013         memset(&params, 0, sizeof(params));
1014
1015         if (start_new) {
1016                 params.param0 = upper_32_bits(req->trb_dma);
1017                 params.param1 = lower_32_bits(req->trb_dma);
1018                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1019         } else {
1020                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1021         }
1022
1023         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1024         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1025         if (ret < 0) {
1026                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1027
1028                 /*
1029                  * FIXME we need to iterate over the list of requests
1030                  * here and stop, unmap, free and del each of the linked
1031                  * requests instead of what we do now.
1032                  */
1033                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1034                                 req->direction);
1035                 list_del(&req->list);
1036                 return ret;
1037         }
1038
1039         dep->flags |= DWC3_EP_BUSY;
1040
1041         if (start_new) {
1042                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1043                                 dep->number);
1044                 WARN_ON_ONCE(!dep->resource_index);
1045         }
1046
1047         return 0;
1048 }
1049
1050 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1051                 struct dwc3_ep *dep, u32 cur_uf)
1052 {
1053         u32 uf;
1054
1055         if (list_empty(&dep->request_list)) {
1056                 dwc3_trace(trace_dwc3_gadget,
1057                                 "ISOC ep %s run out for requests",
1058                                 dep->name);
1059                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1060                 return;
1061         }
1062
1063         /* 4 micro frames in the future */
1064         uf = cur_uf + dep->interval * 4;
1065
1066         __dwc3_gadget_kick_transfer(dep, uf, 1);
1067 }
1068
1069 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1070                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1071 {
1072         u32 cur_uf, mask;
1073
1074         mask = ~(dep->interval - 1);
1075         cur_uf = event->parameters & mask;
1076
1077         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1078 }
1079
1080 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1081 {
1082         struct dwc3             *dwc = dep->dwc;
1083         int                     ret;
1084
1085         req->request.actual     = 0;
1086         req->request.status     = -EINPROGRESS;
1087         req->direction          = dep->direction;
1088         req->epnum              = dep->number;
1089
1090         trace_dwc3_ep_queue(req);
1091
1092         /*
1093          * We only add to our list of requests now and
1094          * start consuming the list once we get XferNotReady
1095          * IRQ.
1096          *
1097          * That way, we avoid doing anything that we don't need
1098          * to do now and defer it until the point we receive a
1099          * particular token from the Host side.
1100          *
1101          * This will also avoid Host cancelling URBs due to too
1102          * many NAKs.
1103          */
1104         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1105                         dep->direction);
1106         if (ret)
1107                 return ret;
1108
1109         list_add_tail(&req->list, &dep->request_list);
1110
1111         /*
1112          * If there are no pending requests and the endpoint isn't already
1113          * busy, we will just start the request straight away.
1114          *
1115          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1116          * little bit faster.
1117          */
1118         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1119                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1120                         !(dep->flags & DWC3_EP_BUSY)) {
1121                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1122                 goto out;
1123         }
1124
1125         /*
1126          * There are a few special cases:
1127          *
1128          * 1. XferNotReady with empty list of requests. We need to kick the
1129          *    transfer here in that situation, otherwise we will be NAKing
1130          *    forever. If we get XferNotReady before gadget driver has a
1131          *    chance to queue a request, we will ACK the IRQ but won't be
1132          *    able to receive the data until the next request is queued.
1133          *    The following code is handling exactly that.
1134          *
1135          */
1136         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1137                 /*
1138                  * If xfernotready is already elapsed and it is a case
1139                  * of isoc transfer, then issue END TRANSFER, so that
1140                  * you can receive xfernotready again and can have
1141                  * notion of current microframe.
1142                  */
1143                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1144                         if (list_empty(&dep->req_queued)) {
1145                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1146                                 dep->flags = DWC3_EP_ENABLED;
1147                         }
1148                         return 0;
1149                 }
1150
1151                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1152                 if (!ret)
1153                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1154
1155                 goto out;
1156         }
1157
1158         /*
1159          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1160          *    kick the transfer here after queuing a request, otherwise the
1161          *    core may not see the modified TRB(s).
1162          */
1163         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1164                         (dep->flags & DWC3_EP_BUSY) &&
1165                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1166                 WARN_ON_ONCE(!dep->resource_index);
1167                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1168                                 false);
1169                 goto out;
1170         }
1171
1172         /*
1173          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1174          * right away, otherwise host will not know we have streams to be
1175          * handled.
1176          */
1177         if (dep->stream_capable)
1178                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1179
1180 out:
1181         if (ret && ret != -EBUSY)
1182                 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1183                                 dep->name);
1184         if (ret == -EBUSY)
1185                 ret = 0;
1186
1187         return ret;
1188 }
1189
1190 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1191         gfp_t gfp_flags)
1192 {
1193         struct dwc3_request             *req = to_dwc3_request(request);
1194         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1195         struct dwc3                     *dwc = dep->dwc;
1196
1197         unsigned long                   flags;
1198
1199         int                             ret;
1200
1201         spin_lock_irqsave(&dwc->lock, flags);
1202         if (!dep->endpoint.desc) {
1203                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1204                                 request, ep->name);
1205                 ret = -ESHUTDOWN;
1206                 goto out;
1207         }
1208
1209         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1210                                 request, req->dep->name)) {
1211                 ret = -EINVAL;
1212                 goto out;
1213         }
1214
1215         ret = __dwc3_gadget_ep_queue(dep, req);
1216
1217 out:
1218         spin_unlock_irqrestore(&dwc->lock, flags);
1219
1220         return ret;
1221 }
1222
1223 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1224                 struct usb_request *request)
1225 {
1226         struct dwc3_request             *req = to_dwc3_request(request);
1227         struct dwc3_request             *r = NULL;
1228
1229         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1230         struct dwc3                     *dwc = dep->dwc;
1231
1232         unsigned long                   flags;
1233         int                             ret = 0;
1234
1235         trace_dwc3_ep_dequeue(req);
1236
1237         spin_lock_irqsave(&dwc->lock, flags);
1238
1239         list_for_each_entry(r, &dep->request_list, list) {
1240                 if (r == req)
1241                         break;
1242         }
1243
1244         if (r != req) {
1245                 list_for_each_entry(r, &dep->req_queued, list) {
1246                         if (r == req)
1247                                 break;
1248                 }
1249                 if (r == req) {
1250                         /* wait until it is processed */
1251                         dwc3_stop_active_transfer(dwc, dep->number, true);
1252                         goto out1;
1253                 }
1254                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1255                                 request, ep->name);
1256                 ret = -EINVAL;
1257                 goto out0;
1258         }
1259
1260 out1:
1261         /* giveback the request */
1262         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1263
1264 out0:
1265         spin_unlock_irqrestore(&dwc->lock, flags);
1266
1267         return ret;
1268 }
1269
1270 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1271 {
1272         struct dwc3_gadget_ep_cmd_params        params;
1273         struct dwc3                             *dwc = dep->dwc;
1274         int                                     ret;
1275
1276         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1277                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1278                 return -EINVAL;
1279         }
1280
1281         memset(&params, 0x00, sizeof(params));
1282
1283         if (value) {
1284                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1285                                 (!list_empty(&dep->req_queued) ||
1286                                  !list_empty(&dep->request_list)))) {
1287                         dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1288                                         dep->name);
1289                         return -EAGAIN;
1290                 }
1291
1292                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1293                         DWC3_DEPCMD_SETSTALL, &params);
1294                 if (ret)
1295                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1296                                         dep->name);
1297                 else
1298                         dep->flags |= DWC3_EP_STALL;
1299         } else {
1300                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1301                         DWC3_DEPCMD_CLEARSTALL, &params);
1302                 if (ret)
1303                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1304                                         dep->name);
1305                 else
1306                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1307         }
1308
1309         return ret;
1310 }
1311
1312 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1313 {
1314         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1315         struct dwc3                     *dwc = dep->dwc;
1316
1317         unsigned long                   flags;
1318
1319         int                             ret;
1320
1321         spin_lock_irqsave(&dwc->lock, flags);
1322         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1323         spin_unlock_irqrestore(&dwc->lock, flags);
1324
1325         return ret;
1326 }
1327
1328 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1329 {
1330         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1331         struct dwc3                     *dwc = dep->dwc;
1332         unsigned long                   flags;
1333         int                             ret;
1334
1335         spin_lock_irqsave(&dwc->lock, flags);
1336         dep->flags |= DWC3_EP_WEDGE;
1337
1338         if (dep->number == 0 || dep->number == 1)
1339                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1340         else
1341                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1342         spin_unlock_irqrestore(&dwc->lock, flags);
1343
1344         return ret;
1345 }
1346
1347 /* -------------------------------------------------------------------------- */
1348
1349 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1350         .bLength        = USB_DT_ENDPOINT_SIZE,
1351         .bDescriptorType = USB_DT_ENDPOINT,
1352         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1353 };
1354
1355 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1356         .enable         = dwc3_gadget_ep0_enable,
1357         .disable        = dwc3_gadget_ep0_disable,
1358         .alloc_request  = dwc3_gadget_ep_alloc_request,
1359         .free_request   = dwc3_gadget_ep_free_request,
1360         .queue          = dwc3_gadget_ep0_queue,
1361         .dequeue        = dwc3_gadget_ep_dequeue,
1362         .set_halt       = dwc3_gadget_ep0_set_halt,
1363         .set_wedge      = dwc3_gadget_ep_set_wedge,
1364 };
1365
1366 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1367         .enable         = dwc3_gadget_ep_enable,
1368         .disable        = dwc3_gadget_ep_disable,
1369         .alloc_request  = dwc3_gadget_ep_alloc_request,
1370         .free_request   = dwc3_gadget_ep_free_request,
1371         .queue          = dwc3_gadget_ep_queue,
1372         .dequeue        = dwc3_gadget_ep_dequeue,
1373         .set_halt       = dwc3_gadget_ep_set_halt,
1374         .set_wedge      = dwc3_gadget_ep_set_wedge,
1375 };
1376
1377 /* -------------------------------------------------------------------------- */
1378
1379 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1380 {
1381         struct dwc3             *dwc = gadget_to_dwc(g);
1382         u32                     reg;
1383
1384         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1385         return DWC3_DSTS_SOFFN(reg);
1386 }
1387
1388 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1389 {
1390         struct dwc3             *dwc = gadget_to_dwc(g);
1391
1392         unsigned long           timeout;
1393         unsigned long           flags;
1394
1395         u32                     reg;
1396
1397         int                     ret = 0;
1398
1399         u8                      link_state;
1400         u8                      speed;
1401
1402         spin_lock_irqsave(&dwc->lock, flags);
1403
1404         /*
1405          * According to the Databook Remote wakeup request should
1406          * be issued only when the device is in early suspend state.
1407          *
1408          * We can check that via USB Link State bits in DSTS register.
1409          */
1410         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1411
1412         speed = reg & DWC3_DSTS_CONNECTSPD;
1413         if (speed == DWC3_DSTS_SUPERSPEED) {
1414                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1415                 ret = -EINVAL;
1416                 goto out;
1417         }
1418
1419         link_state = DWC3_DSTS_USBLNKST(reg);
1420
1421         switch (link_state) {
1422         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1423         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1424                 break;
1425         default:
1426                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1427                                 link_state);
1428                 ret = -EINVAL;
1429                 goto out;
1430         }
1431
1432         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1433         if (ret < 0) {
1434                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1435                 goto out;
1436         }
1437
1438         /* Recent versions do this automatically */
1439         if (dwc->revision < DWC3_REVISION_194A) {
1440                 /* write zeroes to Link Change Request */
1441                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1442                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1443                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1444         }
1445
1446         /* poll until Link State changes to ON */
1447         timeout = jiffies + msecs_to_jiffies(100);
1448
1449         while (!time_after(jiffies, timeout)) {
1450                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1451
1452                 /* in HS, means ON */
1453                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1454                         break;
1455         }
1456
1457         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1458                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1459                 ret = -EINVAL;
1460         }
1461
1462 out:
1463         spin_unlock_irqrestore(&dwc->lock, flags);
1464
1465         return ret;
1466 }
1467
1468 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1469                 int is_selfpowered)
1470 {
1471         struct dwc3             *dwc = gadget_to_dwc(g);
1472         unsigned long           flags;
1473
1474         spin_lock_irqsave(&dwc->lock, flags);
1475         g->is_selfpowered = !!is_selfpowered;
1476         spin_unlock_irqrestore(&dwc->lock, flags);
1477
1478         return 0;
1479 }
1480
1481 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1482 {
1483         u32                     reg;
1484         u32                     timeout = 500;
1485
1486         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1487         if (is_on) {
1488                 if (dwc->revision <= DWC3_REVISION_187A) {
1489                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1490                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1491                 }
1492
1493                 if (dwc->revision >= DWC3_REVISION_194A)
1494                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1495                 reg |= DWC3_DCTL_RUN_STOP;
1496
1497                 if (dwc->has_hibernation)
1498                         reg |= DWC3_DCTL_KEEP_CONNECT;
1499
1500                 dwc->pullups_connected = true;
1501         } else {
1502                 reg &= ~DWC3_DCTL_RUN_STOP;
1503
1504                 if (dwc->has_hibernation && !suspend)
1505                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1506
1507                 dwc->pullups_connected = false;
1508         }
1509
1510         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1511
1512         do {
1513                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1514                 if (is_on) {
1515                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1516                                 break;
1517                 } else {
1518                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1519                                 break;
1520                 }
1521                 timeout--;
1522                 if (!timeout)
1523                         return -ETIMEDOUT;
1524                 udelay(1);
1525         } while (1);
1526
1527         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1528                         dwc->gadget_driver
1529                         ? dwc->gadget_driver->function : "no-function",
1530                         is_on ? "connect" : "disconnect");
1531
1532         return 0;
1533 }
1534
1535 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1536 {
1537         struct dwc3             *dwc = gadget_to_dwc(g);
1538         unsigned long           flags;
1539         int                     ret;
1540
1541         is_on = !!is_on;
1542
1543         spin_lock_irqsave(&dwc->lock, flags);
1544         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1545         spin_unlock_irqrestore(&dwc->lock, flags);
1546
1547         return ret;
1548 }
1549
1550 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1551 {
1552         u32                     reg;
1553
1554         /* Enable all but Start and End of Frame IRQs */
1555         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1556                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1557                         DWC3_DEVTEN_CMDCMPLTEN |
1558                         DWC3_DEVTEN_ERRTICERREN |
1559                         DWC3_DEVTEN_WKUPEVTEN |
1560                         DWC3_DEVTEN_ULSTCNGEN |
1561                         DWC3_DEVTEN_CONNECTDONEEN |
1562                         DWC3_DEVTEN_USBRSTEN |
1563                         DWC3_DEVTEN_DISCONNEVTEN);
1564
1565         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1566 }
1567
1568 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1569 {
1570         /* mask all interrupts */
1571         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1572 }
1573
1574 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1575 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1576
1577 static int dwc3_gadget_start(struct usb_gadget *g,
1578                 struct usb_gadget_driver *driver)
1579 {
1580         struct dwc3             *dwc = gadget_to_dwc(g);
1581         struct dwc3_ep          *dep;
1582         unsigned long           flags;
1583         int                     ret = 0;
1584         int                     irq;
1585         u32                     reg;
1586
1587         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1588         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1589                         IRQF_SHARED, "dwc3", dwc);
1590         if (ret) {
1591                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1592                                 irq, ret);
1593                 goto err0;
1594         }
1595
1596         spin_lock_irqsave(&dwc->lock, flags);
1597
1598         if (dwc->gadget_driver) {
1599                 dev_err(dwc->dev, "%s is already bound to %s\n",
1600                                 dwc->gadget.name,
1601                                 dwc->gadget_driver->driver.name);
1602                 ret = -EBUSY;
1603                 goto err1;
1604         }
1605
1606         dwc->gadget_driver      = driver;
1607
1608         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1609         reg &= ~(DWC3_DCFG_SPEED_MASK);
1610
1611         /**
1612          * WORKAROUND: DWC3 revision < 2.20a have an issue
1613          * which would cause metastability state on Run/Stop
1614          * bit if we try to force the IP to USB2-only mode.
1615          *
1616          * Because of that, we cannot configure the IP to any
1617          * speed other than the SuperSpeed
1618          *
1619          * Refers to:
1620          *
1621          * STAR#9000525659: Clock Domain Crossing on DCTL in
1622          * USB 2.0 Mode
1623          */
1624         if (dwc->revision < DWC3_REVISION_220A) {
1625                 reg |= DWC3_DCFG_SUPERSPEED;
1626         } else {
1627                 switch (dwc->maximum_speed) {
1628                 case USB_SPEED_LOW:
1629                         reg |= DWC3_DSTS_LOWSPEED;
1630                         break;
1631                 case USB_SPEED_FULL:
1632                         reg |= DWC3_DSTS_FULLSPEED1;
1633                         break;
1634                 case USB_SPEED_HIGH:
1635                         reg |= DWC3_DSTS_HIGHSPEED;
1636                         break;
1637                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1638                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1639                 default:
1640                         reg |= DWC3_DSTS_SUPERSPEED;
1641                 }
1642         }
1643         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1644
1645         /* Start with SuperSpeed Default */
1646         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1647
1648         dep = dwc->eps[0];
1649         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1650                         false);
1651         if (ret) {
1652                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1653                 goto err2;
1654         }
1655
1656         dep = dwc->eps[1];
1657         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1658                         false);
1659         if (ret) {
1660                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1661                 goto err3;
1662         }
1663
1664         /* begin to receive SETUP packets */
1665         dwc->ep0state = EP0_SETUP_PHASE;
1666         dwc3_ep0_out_start(dwc);
1667
1668         dwc3_gadget_enable_irq(dwc);
1669
1670         spin_unlock_irqrestore(&dwc->lock, flags);
1671
1672         return 0;
1673
1674 err3:
1675         __dwc3_gadget_ep_disable(dwc->eps[0]);
1676
1677 err2:
1678         dwc->gadget_driver = NULL;
1679
1680 err1:
1681         spin_unlock_irqrestore(&dwc->lock, flags);
1682
1683         free_irq(irq, dwc);
1684
1685 err0:
1686         return ret;
1687 }
1688
1689 static int dwc3_gadget_stop(struct usb_gadget *g)
1690 {
1691         struct dwc3             *dwc = gadget_to_dwc(g);
1692         unsigned long           flags;
1693         int                     irq;
1694
1695         spin_lock_irqsave(&dwc->lock, flags);
1696
1697         dwc3_gadget_disable_irq(dwc);
1698         __dwc3_gadget_ep_disable(dwc->eps[0]);
1699         __dwc3_gadget_ep_disable(dwc->eps[1]);
1700
1701         dwc->gadget_driver      = NULL;
1702
1703         spin_unlock_irqrestore(&dwc->lock, flags);
1704
1705         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1706         free_irq(irq, dwc);
1707
1708         return 0;
1709 }
1710
1711 static const struct usb_gadget_ops dwc3_gadget_ops = {
1712         .get_frame              = dwc3_gadget_get_frame,
1713         .wakeup                 = dwc3_gadget_wakeup,
1714         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1715         .pullup                 = dwc3_gadget_pullup,
1716         .udc_start              = dwc3_gadget_start,
1717         .udc_stop               = dwc3_gadget_stop,
1718 };
1719
1720 /* -------------------------------------------------------------------------- */
1721
1722 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1723                 u8 num, u32 direction)
1724 {
1725         struct dwc3_ep                  *dep;
1726         u8                              i;
1727
1728         for (i = 0; i < num; i++) {
1729                 u8 epnum = (i << 1) | (!!direction);
1730
1731                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1732                 if (!dep)
1733                         return -ENOMEM;
1734
1735                 dep->dwc = dwc;
1736                 dep->number = epnum;
1737                 dep->direction = !!direction;
1738                 dwc->eps[epnum] = dep;
1739
1740                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1741                                 (epnum & 1) ? "in" : "out");
1742
1743                 dep->endpoint.name = dep->name;
1744
1745                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1746
1747                 if (epnum == 0 || epnum == 1) {
1748                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1749                         dep->endpoint.maxburst = 1;
1750                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1751                         if (!epnum)
1752                                 dwc->gadget.ep0 = &dep->endpoint;
1753                 } else {
1754                         int             ret;
1755
1756                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1757                         dep->endpoint.max_streams = 15;
1758                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1759                         list_add_tail(&dep->endpoint.ep_list,
1760                                         &dwc->gadget.ep_list);
1761
1762                         ret = dwc3_alloc_trb_pool(dep);
1763                         if (ret)
1764                                 return ret;
1765                 }
1766
1767                 if (epnum == 0 || epnum == 1) {
1768                         dep->endpoint.caps.type_control = true;
1769                 } else {
1770                         dep->endpoint.caps.type_iso = true;
1771                         dep->endpoint.caps.type_bulk = true;
1772                         dep->endpoint.caps.type_int = true;
1773                 }
1774
1775                 dep->endpoint.caps.dir_in = !!direction;
1776                 dep->endpoint.caps.dir_out = !direction;
1777
1778                 INIT_LIST_HEAD(&dep->request_list);
1779                 INIT_LIST_HEAD(&dep->req_queued);
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1786 {
1787         int                             ret;
1788
1789         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1790
1791         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1792         if (ret < 0) {
1793                 dwc3_trace(trace_dwc3_gadget,
1794                                 "failed to allocate OUT endpoints");
1795                 return ret;
1796         }
1797
1798         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1799         if (ret < 0) {
1800                 dwc3_trace(trace_dwc3_gadget,
1801                                 "failed to allocate IN endpoints");
1802                 return ret;
1803         }
1804
1805         return 0;
1806 }
1807
1808 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1809 {
1810         struct dwc3_ep                  *dep;
1811         u8                              epnum;
1812
1813         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1814                 dep = dwc->eps[epnum];
1815                 if (!dep)
1816                         continue;
1817                 /*
1818                  * Physical endpoints 0 and 1 are special; they form the
1819                  * bi-directional USB endpoint 0.
1820                  *
1821                  * For those two physical endpoints, we don't allocate a TRB
1822                  * pool nor do we add them the endpoints list. Due to that, we
1823                  * shouldn't do these two operations otherwise we would end up
1824                  * with all sorts of bugs when removing dwc3.ko.
1825                  */
1826                 if (epnum != 0 && epnum != 1) {
1827                         dwc3_free_trb_pool(dep);
1828                         list_del(&dep->endpoint.ep_list);
1829                 }
1830
1831                 kfree(dep);
1832         }
1833 }
1834
1835 /* -------------------------------------------------------------------------- */
1836
1837 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1838                 struct dwc3_request *req, struct dwc3_trb *trb,
1839                 const struct dwc3_event_depevt *event, int status)
1840 {
1841         unsigned int            count;
1842         unsigned int            s_pkt = 0;
1843         unsigned int            trb_status;
1844
1845         trace_dwc3_complete_trb(dep, trb);
1846
1847         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1848                 /*
1849                  * We continue despite the error. There is not much we
1850                  * can do. If we don't clean it up we loop forever. If
1851                  * we skip the TRB then it gets overwritten after a
1852                  * while since we use them in a ring buffer. A BUG()
1853                  * would help. Lets hope that if this occurs, someone
1854                  * fixes the root cause instead of looking away :)
1855                  */
1856                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1857                                 dep->name, trb);
1858         count = trb->size & DWC3_TRB_SIZE_MASK;
1859
1860         if (dep->direction) {
1861                 if (count) {
1862                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1863                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1864                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1865                                                 dep->name);
1866                                 /*
1867                                  * If missed isoc occurred and there is
1868                                  * no request queued then issue END
1869                                  * TRANSFER, so that core generates
1870                                  * next xfernotready and we will issue
1871                                  * a fresh START TRANSFER.
1872                                  * If there are still queued request
1873                                  * then wait, do not issue either END
1874                                  * or UPDATE TRANSFER, just attach next
1875                                  * request in request_list during
1876                                  * giveback.If any future queued request
1877                                  * is successfully transferred then we
1878                                  * will issue UPDATE TRANSFER for all
1879                                  * request in the request_list.
1880                                  */
1881                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1882                         } else {
1883                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1884                                                 dep->name);
1885                                 status = -ECONNRESET;
1886                         }
1887                 } else {
1888                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1889                 }
1890         } else {
1891                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1892                         s_pkt = 1;
1893         }
1894
1895         /*
1896          * We assume here we will always receive the entire data block
1897          * which we should receive. Meaning, if we program RX to
1898          * receive 4K but we receive only 2K, we assume that's all we
1899          * should receive and we simply bounce the request back to the
1900          * gadget driver for further processing.
1901          */
1902         req->request.actual += req->request.length - count;
1903         if (s_pkt)
1904                 return 1;
1905         if ((event->status & DEPEVT_STATUS_LST) &&
1906                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1907                                 DWC3_TRB_CTRL_HWO)))
1908                 return 1;
1909         if ((event->status & DEPEVT_STATUS_IOC) &&
1910                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1911                 return 1;
1912         return 0;
1913 }
1914
1915 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1916                 const struct dwc3_event_depevt *event, int status)
1917 {
1918         struct dwc3_request     *req;
1919         struct dwc3_trb         *trb;
1920         unsigned int            slot;
1921         unsigned int            i;
1922         int                     ret;
1923
1924         do {
1925                 req = next_request(&dep->req_queued);
1926                 if (!req) {
1927                         WARN_ON_ONCE(1);
1928                         return 1;
1929                 }
1930                 i = 0;
1931                 do {
1932                         slot = req->start_slot + i;
1933                         if ((slot == DWC3_TRB_NUM - 1) &&
1934                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1935                                 slot++;
1936                         slot %= DWC3_TRB_NUM;
1937                         trb = &dep->trb_pool[slot];
1938
1939                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1940                                         event, status);
1941                         if (ret)
1942                                 break;
1943                 } while (++i < req->request.num_mapped_sgs);
1944
1945                 dwc3_gadget_giveback(dep, req, status);
1946
1947                 if (ret)
1948                         break;
1949         } while (1);
1950
1951         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1952                         list_empty(&dep->req_queued)) {
1953                 if (list_empty(&dep->request_list)) {
1954                         /*
1955                          * If there is no entry in request list then do
1956                          * not issue END TRANSFER now. Just set PENDING
1957                          * flag, so that END TRANSFER is issued when an
1958                          * entry is added into request list.
1959                          */
1960                         dep->flags = DWC3_EP_PENDING_REQUEST;
1961                 } else {
1962                         dwc3_stop_active_transfer(dwc, dep->number, true);
1963                         dep->flags = DWC3_EP_ENABLED;
1964                 }
1965                 return 1;
1966         }
1967
1968         if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1969                 if ((event->status & DEPEVT_STATUS_IOC) &&
1970                                 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1971                         return 0;
1972         return 1;
1973 }
1974
1975 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1976                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1977 {
1978         unsigned                status = 0;
1979         int                     clean_busy;
1980         u32                     is_xfer_complete;
1981
1982         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
1983
1984         if (event->status & DEPEVT_STATUS_BUSERR)
1985                 status = -ECONNRESET;
1986
1987         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1988         if (clean_busy && (is_xfer_complete ||
1989                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
1990                 dep->flags &= ~DWC3_EP_BUSY;
1991
1992         /*
1993          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1994          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1995          */
1996         if (dwc->revision < DWC3_REVISION_183A) {
1997                 u32             reg;
1998                 int             i;
1999
2000                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2001                         dep = dwc->eps[i];
2002
2003                         if (!(dep->flags & DWC3_EP_ENABLED))
2004                                 continue;
2005
2006                         if (!list_empty(&dep->req_queued))
2007                                 return;
2008                 }
2009
2010                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2011                 reg |= dwc->u1u2;
2012                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2013
2014                 dwc->u1u2 = 0;
2015         }
2016
2017         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2018                 int ret;
2019
2020                 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2021                 if (!ret || ret == -EBUSY)
2022                         return;
2023         }
2024 }
2025
2026 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2027                 const struct dwc3_event_depevt *event)
2028 {
2029         struct dwc3_ep          *dep;
2030         u8                      epnum = event->endpoint_number;
2031
2032         dep = dwc->eps[epnum];
2033
2034         if (!(dep->flags & DWC3_EP_ENABLED))
2035                 return;
2036
2037         if (epnum == 0 || epnum == 1) {
2038                 dwc3_ep0_interrupt(dwc, event);
2039                 return;
2040         }
2041
2042         switch (event->endpoint_event) {
2043         case DWC3_DEPEVT_XFERCOMPLETE:
2044                 dep->resource_index = 0;
2045
2046                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2047                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
2048                                         dep->name);
2049                         return;
2050                 }
2051
2052                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2053                 break;
2054         case DWC3_DEPEVT_XFERINPROGRESS:
2055                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2056                 break;
2057         case DWC3_DEPEVT_XFERNOTREADY:
2058                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2059                         dwc3_gadget_start_isoc(dwc, dep, event);
2060                 } else {
2061                         int active;
2062                         int ret;
2063
2064                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2065
2066                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2067                                         dep->name, active ? "Transfer Active"
2068                                         : "Transfer Not Active");
2069
2070                         ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2071                         if (!ret || ret == -EBUSY)
2072                                 return;
2073
2074                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
2075                                         dep->name);
2076                 }
2077
2078                 break;
2079         case DWC3_DEPEVT_STREAMEVT:
2080                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2081                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2082                                         dep->name);
2083                         return;
2084                 }
2085
2086                 switch (event->status) {
2087                 case DEPEVT_STREAMEVT_FOUND:
2088                         dwc3_trace(trace_dwc3_gadget,
2089                                         "Stream %d found and started",
2090                                         event->parameters);
2091
2092                         break;
2093                 case DEPEVT_STREAMEVT_NOTFOUND:
2094                         /* FALLTHROUGH */
2095                 default:
2096                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2097                 }
2098                 break;
2099         case DWC3_DEPEVT_RXTXFIFOEVT:
2100                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2101                 break;
2102         case DWC3_DEPEVT_EPCMDCMPLT:
2103                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2104                 break;
2105         }
2106 }
2107
2108 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2109 {
2110         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2111                 spin_unlock(&dwc->lock);
2112                 dwc->gadget_driver->disconnect(&dwc->gadget);
2113                 spin_lock(&dwc->lock);
2114         }
2115 }
2116
2117 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2118 {
2119         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2120                 spin_unlock(&dwc->lock);
2121                 dwc->gadget_driver->suspend(&dwc->gadget);
2122                 spin_lock(&dwc->lock);
2123         }
2124 }
2125
2126 static void dwc3_resume_gadget(struct dwc3 *dwc)
2127 {
2128         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2129                 spin_unlock(&dwc->lock);
2130                 dwc->gadget_driver->resume(&dwc->gadget);
2131                 spin_lock(&dwc->lock);
2132         }
2133 }
2134
2135 static void dwc3_reset_gadget(struct dwc3 *dwc)
2136 {
2137         if (!dwc->gadget_driver)
2138                 return;
2139
2140         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2141                 spin_unlock(&dwc->lock);
2142                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2143                 spin_lock(&dwc->lock);
2144         }
2145 }
2146
2147 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2148 {
2149         struct dwc3_ep *dep;
2150         struct dwc3_gadget_ep_cmd_params params;
2151         u32 cmd;
2152         int ret;
2153
2154         dep = dwc->eps[epnum];
2155
2156         if (!dep->resource_index)
2157                 return;
2158
2159         /*
2160          * NOTICE: We are violating what the Databook says about the
2161          * EndTransfer command. Ideally we would _always_ wait for the
2162          * EndTransfer Command Completion IRQ, but that's causing too
2163          * much trouble synchronizing between us and gadget driver.
2164          *
2165          * We have discussed this with the IP Provider and it was
2166          * suggested to giveback all requests here, but give HW some
2167          * extra time to synchronize with the interconnect. We're using
2168          * an arbitrary 100us delay for that.
2169          *
2170          * Note also that a similar handling was tested by Synopsys
2171          * (thanks a lot Paul) and nothing bad has come out of it.
2172          * In short, what we're doing is:
2173          *
2174          * - Issue EndTransfer WITH CMDIOC bit set
2175          * - Wait 100us
2176          */
2177
2178         cmd = DWC3_DEPCMD_ENDTRANSFER;
2179         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2180         cmd |= DWC3_DEPCMD_CMDIOC;
2181         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2182         memset(&params, 0, sizeof(params));
2183         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2184         WARN_ON_ONCE(ret);
2185         dep->resource_index = 0;
2186         dep->flags &= ~DWC3_EP_BUSY;
2187         udelay(100);
2188 }
2189
2190 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2191 {
2192         u32 epnum;
2193
2194         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2195                 struct dwc3_ep *dep;
2196
2197                 dep = dwc->eps[epnum];
2198                 if (!dep)
2199                         continue;
2200
2201                 if (!(dep->flags & DWC3_EP_ENABLED))
2202                         continue;
2203
2204                 dwc3_remove_requests(dwc, dep);
2205         }
2206 }
2207
2208 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2209 {
2210         u32 epnum;
2211
2212         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2213                 struct dwc3_ep *dep;
2214                 struct dwc3_gadget_ep_cmd_params params;
2215                 int ret;
2216
2217                 dep = dwc->eps[epnum];
2218                 if (!dep)
2219                         continue;
2220
2221                 if (!(dep->flags & DWC3_EP_STALL))
2222                         continue;
2223
2224                 dep->flags &= ~DWC3_EP_STALL;
2225
2226                 memset(&params, 0, sizeof(params));
2227                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2228                                 DWC3_DEPCMD_CLEARSTALL, &params);
2229                 WARN_ON_ONCE(ret);
2230         }
2231 }
2232
2233 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2234 {
2235         int                     reg;
2236
2237         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2238         reg &= ~DWC3_DCTL_INITU1ENA;
2239         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2240
2241         reg &= ~DWC3_DCTL_INITU2ENA;
2242         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2243
2244         dwc3_disconnect_gadget(dwc);
2245
2246         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2247         dwc->setup_packet_pending = false;
2248         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2249 }
2250
2251 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2252 {
2253         u32                     reg;
2254
2255         /*
2256          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2257          * would cause a missing Disconnect Event if there's a
2258          * pending Setup Packet in the FIFO.
2259          *
2260          * There's no suggested workaround on the official Bug
2261          * report, which states that "unless the driver/application
2262          * is doing any special handling of a disconnect event,
2263          * there is no functional issue".
2264          *
2265          * Unfortunately, it turns out that we _do_ some special
2266          * handling of a disconnect event, namely complete all
2267          * pending transfers, notify gadget driver of the
2268          * disconnection, and so on.
2269          *
2270          * Our suggested workaround is to follow the Disconnect
2271          * Event steps here, instead, based on a setup_packet_pending
2272          * flag. Such flag gets set whenever we have a XferNotReady
2273          * event on EP0 and gets cleared on XferComplete for the
2274          * same endpoint.
2275          *
2276          * Refers to:
2277          *
2278          * STAR#9000466709: RTL: Device : Disconnect event not
2279          * generated if setup packet pending in FIFO
2280          */
2281         if (dwc->revision < DWC3_REVISION_188A) {
2282                 if (dwc->setup_packet_pending)
2283                         dwc3_gadget_disconnect_interrupt(dwc);
2284         }
2285
2286         dwc3_reset_gadget(dwc);
2287
2288         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2289         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2290         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2291         dwc->test_mode = false;
2292
2293         dwc3_stop_active_transfers(dwc);
2294         dwc3_clear_stall_all_ep(dwc);
2295
2296         /* Reset device address to zero */
2297         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2298         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2299         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2300 }
2301
2302 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2303 {
2304         u32 reg;
2305         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2306
2307         /*
2308          * We change the clock only at SS but I dunno why I would want to do
2309          * this. Maybe it becomes part of the power saving plan.
2310          */
2311
2312         if (speed != DWC3_DSTS_SUPERSPEED)
2313                 return;
2314
2315         /*
2316          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2317          * each time on Connect Done.
2318          */
2319         if (!usb30_clock)
2320                 return;
2321
2322         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2323         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2324         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2325 }
2326
2327 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2328 {
2329         struct dwc3_ep          *dep;
2330         int                     ret;
2331         u32                     reg;
2332         u8                      speed;
2333
2334         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2335         speed = reg & DWC3_DSTS_CONNECTSPD;
2336         dwc->speed = speed;
2337
2338         dwc3_update_ram_clk_sel(dwc, speed);
2339
2340         switch (speed) {
2341         case DWC3_DCFG_SUPERSPEED:
2342                 /*
2343                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2344                  * would cause a missing USB3 Reset event.
2345                  *
2346                  * In such situations, we should force a USB3 Reset
2347                  * event by calling our dwc3_gadget_reset_interrupt()
2348                  * routine.
2349                  *
2350                  * Refers to:
2351                  *
2352                  * STAR#9000483510: RTL: SS : USB3 reset event may
2353                  * not be generated always when the link enters poll
2354                  */
2355                 if (dwc->revision < DWC3_REVISION_190A)
2356                         dwc3_gadget_reset_interrupt(dwc);
2357
2358                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2359                 dwc->gadget.ep0->maxpacket = 512;
2360                 dwc->gadget.speed = USB_SPEED_SUPER;
2361                 break;
2362         case DWC3_DCFG_HIGHSPEED:
2363                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2364                 dwc->gadget.ep0->maxpacket = 64;
2365                 dwc->gadget.speed = USB_SPEED_HIGH;
2366                 break;
2367         case DWC3_DCFG_FULLSPEED2:
2368         case DWC3_DCFG_FULLSPEED1:
2369                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2370                 dwc->gadget.ep0->maxpacket = 64;
2371                 dwc->gadget.speed = USB_SPEED_FULL;
2372                 break;
2373         case DWC3_DCFG_LOWSPEED:
2374                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2375                 dwc->gadget.ep0->maxpacket = 8;
2376                 dwc->gadget.speed = USB_SPEED_LOW;
2377                 break;
2378         }
2379
2380         /* Enable USB2 LPM Capability */
2381
2382         if ((dwc->revision > DWC3_REVISION_194A)
2383                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2384                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2385                 reg |= DWC3_DCFG_LPM_CAP;
2386                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2387
2388                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2389                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2390
2391                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2392
2393                 /*
2394                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2395                  * DCFG.LPMCap is set, core responses with an ACK and the
2396                  * BESL value in the LPM token is less than or equal to LPM
2397                  * NYET threshold.
2398                  */
2399                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2400                                 && dwc->has_lpm_erratum,
2401                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2402
2403                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2404                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2405
2406                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2407         } else {
2408                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2409                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2410                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2411         }
2412
2413         dep = dwc->eps[0];
2414         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2415                         false);
2416         if (ret) {
2417                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2418                 return;
2419         }
2420
2421         dep = dwc->eps[1];
2422         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2423                         false);
2424         if (ret) {
2425                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2426                 return;
2427         }
2428
2429         /*
2430          * Configure PHY via GUSB3PIPECTLn if required.
2431          *
2432          * Update GTXFIFOSIZn
2433          *
2434          * In both cases reset values should be sufficient.
2435          */
2436 }
2437
2438 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2439 {
2440         /*
2441          * TODO take core out of low power mode when that's
2442          * implemented.
2443          */
2444
2445         dwc->gadget_driver->resume(&dwc->gadget);
2446 }
2447
2448 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2449                 unsigned int evtinfo)
2450 {
2451         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2452         unsigned int            pwropt;
2453
2454         /*
2455          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2456          * Hibernation mode enabled which would show up when device detects
2457          * host-initiated U3 exit.
2458          *
2459          * In that case, device will generate a Link State Change Interrupt
2460          * from U3 to RESUME which is only necessary if Hibernation is
2461          * configured in.
2462          *
2463          * There are no functional changes due to such spurious event and we
2464          * just need to ignore it.
2465          *
2466          * Refers to:
2467          *
2468          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2469          * operational mode
2470          */
2471         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2472         if ((dwc->revision < DWC3_REVISION_250A) &&
2473                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2474                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2475                                 (next == DWC3_LINK_STATE_RESUME)) {
2476                         dwc3_trace(trace_dwc3_gadget,
2477                                         "ignoring transition U3 -> Resume");
2478                         return;
2479                 }
2480         }
2481
2482         /*
2483          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2484          * on the link partner, the USB session might do multiple entry/exit
2485          * of low power states before a transfer takes place.
2486          *
2487          * Due to this problem, we might experience lower throughput. The
2488          * suggested workaround is to disable DCTL[12:9] bits if we're
2489          * transitioning from U1/U2 to U0 and enable those bits again
2490          * after a transfer completes and there are no pending transfers
2491          * on any of the enabled endpoints.
2492          *
2493          * This is the first half of that workaround.
2494          *
2495          * Refers to:
2496          *
2497          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2498          * core send LGO_Ux entering U0
2499          */
2500         if (dwc->revision < DWC3_REVISION_183A) {
2501                 if (next == DWC3_LINK_STATE_U0) {
2502                         u32     u1u2;
2503                         u32     reg;
2504
2505                         switch (dwc->link_state) {
2506                         case DWC3_LINK_STATE_U1:
2507                         case DWC3_LINK_STATE_U2:
2508                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2509                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2510                                                 | DWC3_DCTL_ACCEPTU2ENA
2511                                                 | DWC3_DCTL_INITU1ENA
2512                                                 | DWC3_DCTL_ACCEPTU1ENA);
2513
2514                                 if (!dwc->u1u2)
2515                                         dwc->u1u2 = reg & u1u2;
2516
2517                                 reg &= ~u1u2;
2518
2519                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2520                                 break;
2521                         default:
2522                                 /* do nothing */
2523                                 break;
2524                         }
2525                 }
2526         }
2527
2528         switch (next) {
2529         case DWC3_LINK_STATE_U1:
2530                 if (dwc->speed == USB_SPEED_SUPER)
2531                         dwc3_suspend_gadget(dwc);
2532                 break;
2533         case DWC3_LINK_STATE_U2:
2534         case DWC3_LINK_STATE_U3:
2535                 dwc3_suspend_gadget(dwc);
2536                 break;
2537         case DWC3_LINK_STATE_RESUME:
2538                 dwc3_resume_gadget(dwc);
2539                 break;
2540         default:
2541                 /* do nothing */
2542                 break;
2543         }
2544
2545         dwc->link_state = next;
2546 }
2547
2548 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2549                 unsigned int evtinfo)
2550 {
2551         unsigned int is_ss = evtinfo & BIT(4);
2552
2553         /**
2554          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2555          * have a known issue which can cause USB CV TD.9.23 to fail
2556          * randomly.
2557          *
2558          * Because of this issue, core could generate bogus hibernation
2559          * events which SW needs to ignore.
2560          *
2561          * Refers to:
2562          *
2563          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2564          * Device Fallback from SuperSpeed
2565          */
2566         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2567                 return;
2568
2569         /* enter hibernation here */
2570 }
2571
2572 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2573                 const struct dwc3_event_devt *event)
2574 {
2575         switch (event->type) {
2576         case DWC3_DEVICE_EVENT_DISCONNECT:
2577                 dwc3_gadget_disconnect_interrupt(dwc);
2578                 break;
2579         case DWC3_DEVICE_EVENT_RESET:
2580                 dwc3_gadget_reset_interrupt(dwc);
2581                 break;
2582         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2583                 dwc3_gadget_conndone_interrupt(dwc);
2584                 break;
2585         case DWC3_DEVICE_EVENT_WAKEUP:
2586                 dwc3_gadget_wakeup_interrupt(dwc);
2587                 break;
2588         case DWC3_DEVICE_EVENT_HIBER_REQ:
2589                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2590                                         "unexpected hibernation event\n"))
2591                         break;
2592
2593                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2594                 break;
2595         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2596                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2597                 break;
2598         case DWC3_DEVICE_EVENT_EOPF:
2599                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2600                 break;
2601         case DWC3_DEVICE_EVENT_SOF:
2602                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2603                 break;
2604         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2605                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2606                 break;
2607         case DWC3_DEVICE_EVENT_CMD_CMPL:
2608                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2609                 break;
2610         case DWC3_DEVICE_EVENT_OVERFLOW:
2611                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2612                 break;
2613         default:
2614                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2615         }
2616 }
2617
2618 static void dwc3_process_event_entry(struct dwc3 *dwc,
2619                 const union dwc3_event *event)
2620 {
2621         trace_dwc3_event(event->raw);
2622
2623         /* Endpoint IRQ, handle it and return early */
2624         if (event->type.is_devspec == 0) {
2625                 /* depevt */
2626                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2627         }
2628
2629         switch (event->type.type) {
2630         case DWC3_EVENT_TYPE_DEV:
2631                 dwc3_gadget_interrupt(dwc, &event->devt);
2632                 break;
2633         /* REVISIT what to do with Carkit and I2C events ? */
2634         default:
2635                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2636         }
2637 }
2638
2639 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2640 {
2641         struct dwc3_event_buffer *evt;
2642         irqreturn_t ret = IRQ_NONE;
2643         int left;
2644         u32 reg;
2645
2646         evt = dwc->ev_buffs[buf];
2647         left = evt->count;
2648
2649         if (!(evt->flags & DWC3_EVENT_PENDING))
2650                 return IRQ_NONE;
2651
2652         while (left > 0) {
2653                 union dwc3_event event;
2654
2655                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2656
2657                 dwc3_process_event_entry(dwc, &event);
2658
2659                 /*
2660                  * FIXME we wrap around correctly to the next entry as
2661                  * almost all entries are 4 bytes in size. There is one
2662                  * entry which has 12 bytes which is a regular entry
2663                  * followed by 8 bytes data. ATM I don't know how
2664                  * things are organized if we get next to the a
2665                  * boundary so I worry about that once we try to handle
2666                  * that.
2667                  */
2668                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2669                 left -= 4;
2670
2671                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2672         }
2673
2674         evt->count = 0;
2675         evt->flags &= ~DWC3_EVENT_PENDING;
2676         ret = IRQ_HANDLED;
2677
2678         /* Unmask interrupt */
2679         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2680         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2681         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2682
2683         return ret;
2684 }
2685
2686 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2687 {
2688         struct dwc3 *dwc = _dwc;
2689         unsigned long flags;
2690         irqreturn_t ret = IRQ_NONE;
2691         int i;
2692
2693         spin_lock_irqsave(&dwc->lock, flags);
2694
2695         for (i = 0; i < dwc->num_event_buffers; i++)
2696                 ret |= dwc3_process_event_buf(dwc, i);
2697
2698         spin_unlock_irqrestore(&dwc->lock, flags);
2699
2700         return ret;
2701 }
2702
2703 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2704 {
2705         struct dwc3_event_buffer *evt;
2706         u32 count;
2707         u32 reg;
2708
2709         evt = dwc->ev_buffs[buf];
2710
2711         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2712         count &= DWC3_GEVNTCOUNT_MASK;
2713         if (!count)
2714                 return IRQ_NONE;
2715
2716         evt->count = count;
2717         evt->flags |= DWC3_EVENT_PENDING;
2718
2719         /* Mask interrupt */
2720         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2721         reg |= DWC3_GEVNTSIZ_INTMASK;
2722         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2723
2724         return IRQ_WAKE_THREAD;
2725 }
2726
2727 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2728 {
2729         struct dwc3                     *dwc = _dwc;
2730         int                             i;
2731         irqreturn_t                     ret = IRQ_NONE;
2732
2733         for (i = 0; i < dwc->num_event_buffers; i++) {
2734                 irqreturn_t status;
2735
2736                 status = dwc3_check_event_buf(dwc, i);
2737                 if (status == IRQ_WAKE_THREAD)
2738                         ret = status;
2739         }
2740
2741         return ret;
2742 }
2743
2744 /**
2745  * dwc3_gadget_init - Initializes gadget related registers
2746  * @dwc: pointer to our controller context structure
2747  *
2748  * Returns 0 on success otherwise negative errno.
2749  */
2750 int dwc3_gadget_init(struct dwc3 *dwc)
2751 {
2752         int                                     ret;
2753
2754         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2755                         &dwc->ctrl_req_addr, GFP_KERNEL);
2756         if (!dwc->ctrl_req) {
2757                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2758                 ret = -ENOMEM;
2759                 goto err0;
2760         }
2761
2762         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2763                         &dwc->ep0_trb_addr, GFP_KERNEL);
2764         if (!dwc->ep0_trb) {
2765                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2766                 ret = -ENOMEM;
2767                 goto err1;
2768         }
2769
2770         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2771         if (!dwc->setup_buf) {
2772                 ret = -ENOMEM;
2773                 goto err2;
2774         }
2775
2776         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2777                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2778                         GFP_KERNEL);
2779         if (!dwc->ep0_bounce) {
2780                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2781                 ret = -ENOMEM;
2782                 goto err3;
2783         }
2784
2785         dwc->gadget.ops                 = &dwc3_gadget_ops;
2786         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2787         dwc->gadget.sg_supported        = true;
2788         dwc->gadget.name                = "dwc3-gadget";
2789
2790         /*
2791          * FIXME We might be setting max_speed to <SUPER, however versions
2792          * <2.20a of dwc3 have an issue with metastability (documented
2793          * elsewhere in this driver) which tells us we can't set max speed to
2794          * anything lower than SUPER.
2795          *
2796          * Because gadget.max_speed is only used by composite.c and function
2797          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2798          * to happen so we avoid sending SuperSpeed Capability descriptor
2799          * together with our BOS descriptor as that could confuse host into
2800          * thinking we can handle super speed.
2801          *
2802          * Note that, in fact, we won't even support GetBOS requests when speed
2803          * is less than super speed because we don't have means, yet, to tell
2804          * composite.c that we are USB 2.0 + LPM ECN.
2805          */
2806         if (dwc->revision < DWC3_REVISION_220A)
2807                 dwc3_trace(trace_dwc3_gadget,
2808                                 "Changing max_speed on rev %08x\n",
2809                                 dwc->revision);
2810
2811         dwc->gadget.max_speed           = dwc->maximum_speed;
2812
2813         /*
2814          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2815          * on ep out.
2816          */
2817         dwc->gadget.quirk_ep_out_aligned_size = true;
2818
2819         /*
2820          * REVISIT: Here we should clear all pending IRQs to be
2821          * sure we're starting from a well known location.
2822          */
2823
2824         ret = dwc3_gadget_init_endpoints(dwc);
2825         if (ret)
2826                 goto err4;
2827
2828         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2829         if (ret) {
2830                 dev_err(dwc->dev, "failed to register udc\n");
2831                 goto err4;
2832         }
2833
2834         return 0;
2835
2836 err4:
2837         dwc3_gadget_free_endpoints(dwc);
2838         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2839                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2840
2841 err3:
2842         kfree(dwc->setup_buf);
2843
2844 err2:
2845         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2846                         dwc->ep0_trb, dwc->ep0_trb_addr);
2847
2848 err1:
2849         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2850                         dwc->ctrl_req, dwc->ctrl_req_addr);
2851
2852 err0:
2853         return ret;
2854 }
2855
2856 /* -------------------------------------------------------------------------- */
2857
2858 void dwc3_gadget_exit(struct dwc3 *dwc)
2859 {
2860         usb_del_gadget_udc(&dwc->gadget);
2861
2862         dwc3_gadget_free_endpoints(dwc);
2863
2864         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2865                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2866
2867         kfree(dwc->setup_buf);
2868
2869         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2870                         dwc->ep0_trb, dwc->ep0_trb_addr);
2871
2872         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2873                         dwc->ctrl_req, dwc->ctrl_req_addr);
2874 }
2875
2876 int dwc3_gadget_suspend(struct dwc3 *dwc)
2877 {
2878         if (dwc->pullups_connected) {
2879                 dwc3_gadget_disable_irq(dwc);
2880                 dwc3_gadget_run_stop(dwc, true, true);
2881         }
2882
2883         __dwc3_gadget_ep_disable(dwc->eps[0]);
2884         __dwc3_gadget_ep_disable(dwc->eps[1]);
2885
2886         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2887
2888         return 0;
2889 }
2890
2891 int dwc3_gadget_resume(struct dwc3 *dwc)
2892 {
2893         struct dwc3_ep          *dep;
2894         int                     ret;
2895
2896         /* Start with SuperSpeed Default */
2897         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2898
2899         dep = dwc->eps[0];
2900         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2901                         false);
2902         if (ret)
2903                 goto err0;
2904
2905         dep = dwc->eps[1];
2906         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2907                         false);
2908         if (ret)
2909                 goto err1;
2910
2911         /* begin to receive SETUP packets */
2912         dwc->ep0state = EP0_SETUP_PHASE;
2913         dwc3_ep0_out_start(dwc);
2914
2915         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2916
2917         if (dwc->pullups_connected) {
2918                 dwc3_gadget_enable_irq(dwc);
2919                 dwc3_gadget_run_stop(dwc, true, false);
2920         }
2921
2922         return 0;
2923
2924 err1:
2925         __dwc3_gadget_ep_disable(dwc->eps[0]);
2926
2927 err0:
2928         return ret;
2929 }