drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 149                 int status)
 150 {
 151         struct dwc3                     *dwc = dep->dwc;
 152         int                             i;
 153
 154         if (req->started) {
 155                 i = 0;
 156                 do {
 157                         dep->trb_dequeue++;
 158                         /*
 159                          * Skip LINK TRB. We can't use req->trb and check for
 160                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 161                          * just completed (not the LINK TRB).
 162                          */
 163                         if (((dep->trb_dequeue & DWC3_TRB_MASK) ==
 164                                 DWC3_TRB_NUM- 1) &&
 165                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 166                                 dep->trb_dequeue++;
 167                 } while(++i < req->request.num_mapped_sgs);
 168                 req->started = false;
 169         }
 170         list_del(&req->list);
 171         req->trb = NULL;
 172
 173         if (req->request.status == -EINPROGRESS)
 174                 req->request.status = status;
 175
 176         if (dwc->ep0_bounced && dep->number == 0)
 177                 dwc->ep0_bounced = false;
 178         else
 179                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 180                                 req->direction);
 181
 182         trace_dwc3_gadget_giveback(req);
 183
 184         spin_unlock(&dwc->lock);
 185         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 186         spin_lock(&dwc->lock);
 187 }
 188
 189 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 190 {
 191         u32             timeout = 500;
 192         u32             reg;
 193
 194         trace_dwc3_gadget_generic_cmd(cmd, param);
 195
 196         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 197         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 198
 199         do {
 200                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 201                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 202                         dwc3_trace(trace_dwc3_gadget,
 203                                         "Command Complete --> %d",
 204                                         DWC3_DGCMD_STATUS(reg));
 205                         if (DWC3_DGCMD_STATUS(reg))
 206                                 return -EINVAL;
 207                         return 0;
 208                 }
 209
 210                 /*
 211                  * We can't sleep here, because it's also called from
 212                  * interrupt context.
 213                  */
 214                 timeout--;
 215                 if (!timeout) {
 216                         dwc3_trace(trace_dwc3_gadget,
 217                                         "Command Timed Out");
 218                         return -ETIMEDOUT;
 219                 }
 220                 udelay(1);
 221         } while (1);
 222 }
 223
 224 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 225
 226 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 227                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 228 {
 229         struct dwc3_ep          *dep = dwc->eps[ep];
 230         u32                     timeout = 500;
 231         u32                     reg;
 232
 233         int                     susphy = false;
 234         int                     ret = -EINVAL;
 235
 236         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 237
 238         /*
 239          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 240          * we're issuing an endpoint command, we must check if
 241          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 242          *
 243          * We will also set SUSPHY bit to what it was before returning as stated
 244          * by the same section on Synopsys databook.
 245          */
 246         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 247         if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 248                 susphy = true;
 249                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 250                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 251         }
 252
 253         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 254                 int             needs_wakeup;
 255
 256                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 257                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 258                                 dwc->link_state == DWC3_LINK_STATE_U3);
 259
 260                 if (unlikely(needs_wakeup)) {
 261                         ret = __dwc3_gadget_wakeup(dwc);
 262                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 263                                         ret);
 264                 }
 265         }
 266
 267         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 268         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 269         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 270
 271         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 272         do {
 273                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 274                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 275                         dwc3_trace(trace_dwc3_gadget,
 276                                         "Command Complete --> %d",
 277                                         DWC3_DEPCMD_STATUS(reg));
 278                         if (DWC3_DEPCMD_STATUS(reg))
 279                                 break;
 280                         ret = 0;
 281                         break;
 282                 }
 283
 284                 /*
 285                  * We can't sleep here, because it is also called from
 286                  * interrupt context.
 287                  */
 288                 timeout--;
 289                 if (!timeout) {
 290                         dwc3_trace(trace_dwc3_gadget,
 291                                         "Command Timed Out");
 292                         ret = -ETIMEDOUT;
 293                         break;
 294                 }
 295
 296                 udelay(1);
 297         } while (1);
 298
 299         if (unlikely(susphy)) {
 300                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 301                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 302                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 303         }
 304
 305         return ret;
 306 }
 307
 308 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 309                 struct dwc3_trb *trb)
 310 {
 311         u32             offset = (char *) trb - (char *) dep->trb_pool;
 312
 313         return dep->trb_pool_dma + offset;
 314 }
 315
 316 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 317 {
 318         struct dwc3             *dwc = dep->dwc;
 319
 320         if (dep->trb_pool)
 321                 return 0;
 322
 323         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 324                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 325                         &dep->trb_pool_dma, GFP_KERNEL);
 326         if (!dep->trb_pool) {
 327                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 328                                 dep->name);
 329                 return -ENOMEM;
 330         }
 331
 332         return 0;
 333 }
 334
 335 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 336 {
 337         struct dwc3             *dwc = dep->dwc;
 338
 339         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 340                         dep->trb_pool, dep->trb_pool_dma);
 341
 342         dep->trb_pool = NULL;
 343         dep->trb_pool_dma = 0;
 344 }
 345
 346 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 347
 348 /**
 349  * dwc3_gadget_start_config - Configure EP resources
 350  * @dwc: pointer to our controller context structure
 351  * @dep: endpoint that is being enabled
 352  *
 353  * The assignment of transfer resources cannot perfectly follow the
 354  * data book due to the fact that the controller driver does not have
 355  * all knowledge of the configuration in advance. It is given this
 356  * information piecemeal by the composite gadget framework after every
 357  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 358  * programming model in this scenario can cause errors. For two
 359  * reasons:
 360  *
 361  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 362  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 363  * multiple interfaces.
 364  *
 365  * 2) The databook does not mention doing more DEPXFERCFG for new
 366  * endpoint on alt setting (8.1.6).
 367  *
 368  * The following simplified method is used instead:
 369  *
 370  * All hardware endpoints can be assigned a transfer resource and this
 371  * setting will stay persistent until either a core reset or
 372  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 373  * do DEPXFERCFG for every hardware endpoint as well. We are
 374  * guaranteed that there are as many transfer resources as endpoints.
 375  *
 376  * This function is called for each endpoint when it is being enabled
 377  * but is triggered only when called for EP0-out, which always happens
 378  * first, and which should only happen in one of the above conditions.
 379  */
 380 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 381 {
 382         struct dwc3_gadget_ep_cmd_params params;
 383         u32                     cmd;
 384         int                     i;
 385         int                     ret;
 386
 387         if (dep->number)
 388                 return 0;
 389
 390         memset(&params, 0x00, sizeof(params));
 391         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 392
 393         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 394         if (ret)
 395                 return ret;
 396
 397         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 398                 struct dwc3_ep *dep = dwc->eps[i];
 399
 400                 if (!dep)
 401                         continue;
 402
 403                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 404                 if (ret)
 405                         return ret;
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 412                 const struct usb_endpoint_descriptor *desc,
 413                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 414                 bool ignore, bool restore)
 415 {
 416         struct dwc3_gadget_ep_cmd_params params;
 417
 418         memset(&params, 0x00, sizeof(params));
 419
 420         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 421                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 422
 423         /* Burst size is only needed in SuperSpeed mode */
 424         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 425                 u32 burst = dep->endpoint.maxburst - 1;
 426
 427                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 428         }
 429
 430         if (ignore)
 431                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 432
 433         if (restore) {
 434                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 435                 params.param2 |= dep->saved_state;
 436         }
 437
 438         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 439                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 440
 441         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 442                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 443                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 444                 dep->stream_capable = true;
 445         }
 446
 447         if (!usb_endpoint_xfer_control(desc))
 448                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 449
 450         /*
 451          * We are doing 1:1 mapping for endpoints, meaning
 452          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 453          * so on. We consider the direction bit as part of the physical
 454          * endpoint number. So USB endpoint 0x81 is 0x03.
 455          */
 456         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 457
 458         /*
 459          * We must use the lower 16 TX FIFOs even though
 460          * HW might have more
 461          */
 462         if (dep->direction)
 463                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 464
 465         if (desc->bInterval) {
 466                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 467                 dep->interval = 1 << (desc->bInterval - 1);
 468         }
 469
 470         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 471                         DWC3_DEPCMD_SETEPCONFIG, &params);
 472 }
 473
 474 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 475 {
 476         struct dwc3_gadget_ep_cmd_params params;
 477
 478         memset(&params, 0x00, sizeof(params));
 479
 480         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 481
 482         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 483                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 484 }
 485
 486 /**
 487  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 488  * @dep: endpoint to be initialized
 489  * @desc: USB Endpoint Descriptor
 490  *
 491  * Caller should take care of locking
 492  */
 493 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 494                 const struct usb_endpoint_descriptor *desc,
 495                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 496                 bool ignore, bool restore)
 497 {
 498         struct dwc3             *dwc = dep->dwc;
 499         u32                     reg;
 500         int                     ret;
 501
 502         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 503
 504         if (!(dep->flags & DWC3_EP_ENABLED)) {
 505                 ret = dwc3_gadget_start_config(dwc, dep);
 506                 if (ret)
 507                         return ret;
 508         }
 509
 510         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 511                         restore);
 512         if (ret)
 513                 return ret;
 514
 515         if (!(dep->flags & DWC3_EP_ENABLED)) {
 516                 struct dwc3_trb *trb_st_hw;
 517                 struct dwc3_trb *trb_link;
 518
 519                 dep->endpoint.desc = desc;
 520                 dep->comp_desc = comp_desc;
 521                 dep->type = usb_endpoint_type(desc);
 522                 dep->flags |= DWC3_EP_ENABLED;
 523
 524                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 525                 reg |= DWC3_DALEPENA_EP(dep->number);
 526                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 527
 528                 if (!usb_endpoint_xfer_isoc(desc))
 529                         goto out;
 530
 531                 /* Link TRB for ISOC. The HWO bit is never reset */
 532                 trb_st_hw = &dep->trb_pool[0];
 533
 534                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 535                 memset(trb_link, 0, sizeof(*trb_link));
 536
 537                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 538                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 539                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 540                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 541         }
 542
 543 out:
 544         switch (usb_endpoint_type(desc)) {
 545         case USB_ENDPOINT_XFER_CONTROL:
 546                 /* don't change name */
 547                 break;
 548         case USB_ENDPOINT_XFER_ISOC:
 549                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 550                 break;
 551         case USB_ENDPOINT_XFER_BULK:
 552                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 553                 break;
 554         case USB_ENDPOINT_XFER_INT:
 555                 strlcat(dep->name, "-int", sizeof(dep->name));
 556                 break;
 557         default:
 558                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 559         }
 560
 561         return 0;
 562 }
 563
 564 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 565 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 566 {
 567         struct dwc3_request             *req;
 568
 569         if (!list_empty(&dep->started_list)) {
 570                 dwc3_stop_active_transfer(dwc, dep->number, true);
 571
 572                 /* - giveback all requests to gadget driver */
 573                 while (!list_empty(&dep->started_list)) {
 574                         req = next_request(&dep->started_list);
 575
 576                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 577                 }
 578         }
 579
 580         while (!list_empty(&dep->pending_list)) {
 581                 req = next_request(&dep->pending_list);
 582
 583                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 584         }
 585 }
 586
 587 /**
 588  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 589  * @dep: the endpoint to disable
 590  *
 591  * This function also removes requests which are currently processed ny the
 592  * hardware and those which are not yet scheduled.
 593  * Caller should take care of locking.
 594  */
 595 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 596 {
 597         struct dwc3             *dwc = dep->dwc;
 598         u32                     reg;
 599
 600         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 601
 602         dwc3_remove_requests(dwc, dep);
 603
 604         /* make sure HW endpoint isn't stalled */
 605         if (dep->flags & DWC3_EP_STALL)
 606                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 607
 608         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 609         reg &= ~DWC3_DALEPENA_EP(dep->number);
 610         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 611
 612         dep->stream_capable = false;
 613         dep->endpoint.desc = NULL;
 614         dep->comp_desc = NULL;
 615         dep->type = 0;
 616         dep->flags = 0;
 617
 618         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 619                         dep->number >> 1,
 620                         (dep->number & 1) ? "in" : "out");
 621
 622         return 0;
 623 }
 624
 625 /* -------------------------------------------------------------------------- */
 626
 627 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 628                 const struct usb_endpoint_descriptor *desc)
 629 {
 630         return -EINVAL;
 631 }
 632
 633 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 634 {
 635         return -EINVAL;
 636 }
 637
 638 /* -------------------------------------------------------------------------- */
 639
 640 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 641                 const struct usb_endpoint_descriptor *desc)
 642 {
 643         struct dwc3_ep                  *dep;
 644         struct dwc3                     *dwc;
 645         unsigned long                   flags;
 646         int                             ret;
 647
 648         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 649                 pr_debug("dwc3: invalid parameters\n");
 650                 return -EINVAL;
 651         }
 652
 653         if (!desc->wMaxPacketSize) {
 654                 pr_debug("dwc3: missing wMaxPacketSize\n");
 655                 return -EINVAL;
 656         }
 657
 658         dep = to_dwc3_ep(ep);
 659         dwc = dep->dwc;
 660
 661         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 662                                         "%s is already enabled\n",
 663                                         dep->name))
 664                 return 0;
 665
 666         spin_lock_irqsave(&dwc->lock, flags);
 667         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 668         spin_unlock_irqrestore(&dwc->lock, flags);
 669
 670         return ret;
 671 }
 672
 673 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 674 {
 675         struct dwc3_ep                  *dep;
 676         struct dwc3                     *dwc;
 677         unsigned long                   flags;
 678         int                             ret;
 679
 680         if (!ep) {
 681                 pr_debug("dwc3: invalid parameters\n");
 682                 return -EINVAL;
 683         }
 684
 685         dep = to_dwc3_ep(ep);
 686         dwc = dep->dwc;
 687
 688         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 689                                         "%s is already disabled\n",
 690                                         dep->name))
 691                 return 0;
 692
 693         spin_lock_irqsave(&dwc->lock, flags);
 694         ret = __dwc3_gadget_ep_disable(dep);
 695         spin_unlock_irqrestore(&dwc->lock, flags);
 696
 697         return ret;
 698 }
 699
 700 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 701         gfp_t gfp_flags)
 702 {
 703         struct dwc3_request             *req;
 704         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 705
 706         req = kzalloc(sizeof(*req), gfp_flags);
 707         if (!req)
 708                 return NULL;
 709
 710         req->epnum      = dep->number;
 711         req->dep        = dep;
 712
 713         trace_dwc3_alloc_request(req);
 714
 715         return &req->request;
 716 }
 717
 718 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 719                 struct usb_request *request)
 720 {
 721         struct dwc3_request             *req = to_dwc3_request(request);
 722
 723         trace_dwc3_free_request(req);
 724         kfree(req);
 725 }
 726
 727 /**
 728  * dwc3_prepare_one_trb - setup one TRB from one request
 729  * @dep: endpoint for which this request is prepared
 730  * @req: dwc3_request pointer
 731  */
 732 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 733                 struct dwc3_request *req, dma_addr_t dma,
 734                 unsigned length, unsigned last, unsigned chain, unsigned node)
 735 {
 736         struct dwc3_trb         *trb;
 737
 738         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 739                         dep->name, req, (unsigned long long) dma,
 740                         length, last ? " last" : "",
 741                         chain ? " chain" : "");
 742
 743
 744         trb = &dep->trb_pool[dep->trb_enqueue & DWC3_TRB_MASK];
 745
 746         if (!req->trb) {
 747                 dwc3_gadget_move_started_request(req);
 748                 req->trb = trb;
 749                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 750                 req->first_trb_index = dep->trb_enqueue & DWC3_TRB_MASK;
 751         }
 752
 753         dep->trb_enqueue++;
 754         /* Skip the LINK-TRB on ISOC */
 755         if (((dep->trb_enqueue & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 756                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 757                 dep->trb_enqueue++;
 758
 759         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 760         trb->bpl = lower_32_bits(dma);
 761         trb->bph = upper_32_bits(dma);
 762
 763         switch (usb_endpoint_type(dep->endpoint.desc)) {
 764         case USB_ENDPOINT_XFER_CONTROL:
 765                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 766                 break;
 767
 768         case USB_ENDPOINT_XFER_ISOC:
 769                 if (!node)
 770                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 771                 else
 772                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 773
 774                 /* always enable Interrupt on Missed ISOC */
 775                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 776                 break;
 777
 778         case USB_ENDPOINT_XFER_BULK:
 779         case USB_ENDPOINT_XFER_INT:
 780                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 781                 break;
 782         default:
 783                 /*
 784                  * This is only possible with faulty memory because we
 785                  * checked it already :)
 786                  */
 787                 BUG();
 788         }
 789
 790         /* always enable Continue on Short Packet */
 791         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 792
 793         if (!req->request.no_interrupt)
 794                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 795
 796         if (last)
 797                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 798
 799         if (chain)
 800                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 801
 802         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 803                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 804
 805         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 806
 807         trace_dwc3_prepare_trb(dep, trb);
 808 }
 809
 810 /*
 811  * dwc3_prepare_trbs - setup TRBs from requests
 812  * @dep: endpoint for which requests are being prepared
 813  * @starting: true if the endpoint is idle and no requests are queued.
 814  *
 815  * The function goes through the requests list and sets up TRBs for the
 816  * transfers. The function returns once there are no more TRBs available or
 817  * it runs out of requests.
 818  */
 819 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 820 {
 821         struct dwc3_request     *req, *n;
 822         u32                     trbs_left;
 823         u32                     max;
 824         unsigned int            last_one = 0;
 825
 826         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 827
 828         /* the first request must not be queued */
 829         trbs_left = (dep->trb_dequeue - dep->trb_enqueue) & DWC3_TRB_MASK;
 830
 831         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 832         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 833                 max = DWC3_TRB_NUM - (dep->trb_enqueue & DWC3_TRB_MASK);
 834                 if (trbs_left > max)
 835                         trbs_left = max;
 836         }
 837
 838         /*
 839          * If busy & slot are equal than it is either full or empty. If we are
 840          * starting to process requests then we are empty. Otherwise we are
 841          * full and don't do anything
 842          */
 843         if (!trbs_left) {
 844                 if (!starting)
 845                         return;
 846                 trbs_left = DWC3_TRB_NUM;
 847                 /*
 848                  * In case we start from scratch, we queue the ISOC requests
 849                  * starting from slot 1. This is done because we use ring
 850                  * buffer and have no LST bit to stop us. Instead, we place
 851                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 852                  * after the first request so we start at slot 1 and have
 853                  * 7 requests proceed before we hit the first IOC.
 854                  * Other transfer types don't use the ring buffer and are
 855                  * processed from the first TRB until the last one. Since we
 856                  * don't wrap around we have to start at the beginning.
 857                  */
 858                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 859                         dep->trb_dequeue = 1;
 860                         dep->trb_enqueue = 1;
 861                 } else {
 862                         dep->trb_dequeue = 0;
 863                         dep->trb_enqueue = 0;
 864                 }
 865         }
 866
 867         /* The last TRB is a link TRB, not used for xfer */
 868         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 869                 return;
 870
 871         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 872                 unsigned        length;
 873                 dma_addr_t      dma;
 874                 last_one = false;
 875
 876                 if (req->request.num_mapped_sgs > 0) {
 877                         struct usb_request *request = &req->request;
 878                         struct scatterlist *sg = request->sg;
 879                         struct scatterlist *s;
 880                         int             i;
 881
 882                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 883                                 unsigned chain = true;
 884
 885                                 length = sg_dma_len(s);
 886                                 dma = sg_dma_address(s);
 887
 888                                 if (i == (request->num_mapped_sgs - 1) ||
 889                                                 sg_is_last(s)) {
 890                                         if (list_empty(&dep->pending_list))
 891                                                 last_one = true;
 892                                         chain = false;
 893                                 }
 894
 895                                 trbs_left--;
 896                                 if (!trbs_left)
 897                                         last_one = true;
 898
 899                                 if (last_one)
 900                                         chain = false;
 901
 902                                 dwc3_prepare_one_trb(dep, req, dma, length,
 903                                                 last_one, chain, i);
 904
 905                                 if (last_one)
 906                                         break;
 907                         }
 908
 909                         if (last_one)
 910                                 break;
 911                 } else {
 912                         dma = req->request.dma;
 913                         length = req->request.length;
 914                         trbs_left--;
 915
 916                         if (!trbs_left)
 917                                 last_one = 1;
 918
 919                         /* Is this the last request? */
 920                         if (list_is_last(&req->list, &dep->pending_list))
 921                                 last_one = 1;
 922
 923                         dwc3_prepare_one_trb(dep, req, dma, length,
 924                                         last_one, false, 0);
 925
 926                         if (last_one)
 927                                 break;
 928                 }
 929         }
 930 }
 931
 932 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 933                 int start_new)
 934 {
 935         struct dwc3_gadget_ep_cmd_params params;
 936         struct dwc3_request             *req;
 937         struct dwc3                     *dwc = dep->dwc;
 938         int                             ret;
 939         u32                             cmd;
 940
 941         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 942                 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
 943                 return -EBUSY;
 944         }
 945
 946         /*
 947          * If we are getting here after a short-out-packet we don't enqueue any
 948          * new requests as we try to set the IOC bit only on the last request.
 949          */
 950         if (start_new) {
 951                 if (list_empty(&dep->started_list))
 952                         dwc3_prepare_trbs(dep, start_new);
 953
 954                 /* req points to the first request which will be sent */
 955                 req = next_request(&dep->started_list);
 956         } else {
 957                 dwc3_prepare_trbs(dep, start_new);
 958
 959                 /*
 960                  * req points to the first request where HWO changed from 0 to 1
 961                  */
 962                 req = next_request(&dep->started_list);
 963         }
 964         if (!req) {
 965                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 966                 return 0;
 967         }
 968
 969         memset(&params, 0, sizeof(params));
 970
 971         if (start_new) {
 972                 params.param0 = upper_32_bits(req->trb_dma);
 973                 params.param1 = lower_32_bits(req->trb_dma);
 974                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 975         } else {
 976                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 977         }
 978
 979         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 980         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 981         if (ret < 0) {
 982                 /*
 983                  * FIXME we need to iterate over the list of requests
 984                  * here and stop, unmap, free and del each of the linked
 985                  * requests instead of what we do now.
 986                  */
 987                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 988                                 req->direction);
 989                 list_del(&req->list);
 990                 return ret;
 991         }
 992
 993         dep->flags |= DWC3_EP_BUSY;
 994
 995         if (start_new) {
 996                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 997                                 dep->number);
 998                 WARN_ON_ONCE(!dep->resource_index);
 999         }
1000
1001         return 0;
1002 }
1003
1004 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1005                 struct dwc3_ep *dep, u32 cur_uf)
1006 {
1007         u32 uf;
1008
1009         if (list_empty(&dep->pending_list)) {
1010                 dwc3_trace(trace_dwc3_gadget,
1011                                 "ISOC ep %s run out for requests",
1012                                 dep->name);
1013                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1014                 return;
1015         }
1016
1017         /* 4 micro frames in the future */
1018         uf = cur_uf + dep->interval * 4;
1019
1020         __dwc3_gadget_kick_transfer(dep, uf, 1);
1021 }
1022
1023 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1024                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1025 {
1026         u32 cur_uf, mask;
1027
1028         mask = ~(dep->interval - 1);
1029         cur_uf = event->parameters & mask;
1030
1031         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1032 }
1033
1034 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1035 {
1036         struct dwc3             *dwc = dep->dwc;
1037         int                     ret;
1038
1039         if (!dep->endpoint.desc) {
1040                 dwc3_trace(trace_dwc3_gadget,
1041                                 "trying to queue request %p to disabled %s\n",
1042                                 &req->request, dep->endpoint.name);
1043                 return -ESHUTDOWN;
1044         }
1045
1046         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1047                                 &req->request, req->dep->name)) {
1048                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1049                                 &req->request, req->dep->name);
1050                 return -EINVAL;
1051         }
1052
1053         req->request.actual     = 0;
1054         req->request.status     = -EINPROGRESS;
1055         req->direction          = dep->direction;
1056         req->epnum              = dep->number;
1057
1058         trace_dwc3_ep_queue(req);
1059
1060         /*
1061          * Per databook, the total size of buffer must be a multiple
1062          * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1063          * configed for endpoints in dwc3_gadget_set_ep_config(),
1064          * set to usb_endpoint_descriptor->wMaxPacketSize.
1065          */
1066         if (dep->direction == 0 &&
1067             req->request.length % dep->endpoint.desc->wMaxPacketSize)
1068                 req->request.length = roundup(req->request.length,
1069                                         dep->endpoint.desc->wMaxPacketSize);
1070
1071         /*
1072          * We only add to our list of requests now and
1073          * start consuming the list once we get XferNotReady
1074          * IRQ.
1075          *
1076          * That way, we avoid doing anything that we don't need
1077          * to do now and defer it until the point we receive a
1078          * particular token from the Host side.
1079          *
1080          * This will also avoid Host cancelling URBs due to too
1081          * many NAKs.
1082          */
1083         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1084                         dep->direction);
1085         if (ret)
1086                 return ret;
1087
1088         list_add_tail(&req->list, &dep->pending_list);
1089
1090         /*
1091          * If there are no pending requests and the endpoint isn't already
1092          * busy, we will just start the request straight away.
1093          *
1094          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1095          * little bit faster.
1096          */
1097         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1098                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1099                         !(dep->flags & DWC3_EP_BUSY)) {
1100                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1101                 goto out;
1102         }
1103
1104         /*
1105          * There are a few special cases:
1106          *
1107          * 1. XferNotReady with empty list of requests. We need to kick the
1108          *    transfer here in that situation, otherwise we will be NAKing
1109          *    forever. If we get XferNotReady before gadget driver has a
1110          *    chance to queue a request, we will ACK the IRQ but won't be
1111          *    able to receive the data until the next request is queued.
1112          *    The following code is handling exactly that.
1113          *
1114          */
1115         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1116                 /*
1117                  * If xfernotready is already elapsed and it is a case
1118                  * of isoc transfer, then issue END TRANSFER, so that
1119                  * you can receive xfernotready again and can have
1120                  * notion of current microframe.
1121                  */
1122                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1123                         if (list_empty(&dep->started_list)) {
1124                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1125                                 dep->flags = DWC3_EP_ENABLED;
1126                         }
1127                         return 0;
1128                 }
1129
1130                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1131                 if (!ret)
1132                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1133
1134                 goto out;
1135         }
1136
1137         /*
1138          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1139          *    kick the transfer here after queuing a request, otherwise the
1140          *    core may not see the modified TRB(s).
1141          */
1142         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1143                         (dep->flags & DWC3_EP_BUSY) &&
1144                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1145                 WARN_ON_ONCE(!dep->resource_index);
1146                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1147                                 false);
1148                 goto out;
1149         }
1150
1151         /*
1152          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1153          * right away, otherwise host will not know we have streams to be
1154          * handled.
1155          */
1156         if (dep->stream_capable)
1157                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1158
1159 out:
1160         if (ret && ret != -EBUSY)
1161                 dwc3_trace(trace_dwc3_gadget,
1162                                 "%s: failed to kick transfers\n",
1163                                 dep->name);
1164         if (ret == -EBUSY)
1165                 ret = 0;
1166
1167         return ret;
1168 }
1169
1170 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1171                 struct usb_request *request)
1172 {
1173         dwc3_gadget_ep_free_request(ep, request);
1174 }
1175
1176 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1177 {
1178         struct dwc3_request             *req;
1179         struct usb_request              *request;
1180         struct usb_ep                   *ep = &dep->endpoint;
1181
1182         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1183         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1184         if (!request)
1185                 return -ENOMEM;
1186
1187         request->length = 0;
1188         request->buf = dwc->zlp_buf;
1189         request->complete = __dwc3_gadget_ep_zlp_complete;
1190
1191         req = to_dwc3_request(request);
1192
1193         return __dwc3_gadget_ep_queue(dep, req);
1194 }
1195
1196 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1197         gfp_t gfp_flags)
1198 {
1199         struct dwc3_request             *req = to_dwc3_request(request);
1200         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1201         struct dwc3                     *dwc = dep->dwc;
1202
1203         unsigned long                   flags;
1204
1205         int                             ret;
1206
1207         spin_lock_irqsave(&dwc->lock, flags);
1208         ret = __dwc3_gadget_ep_queue(dep, req);
1209
1210         /*
1211          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1212          * setting request->zero, instead of doing magic, we will just queue an
1213          * extra usb_request ourselves so that it gets handled the same way as
1214          * any other request.
1215          */
1216         if (ret == 0 && request->zero && request->length &&
1217             (request->length % ep->desc->wMaxPacketSize == 0))
1218                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1219
1220         spin_unlock_irqrestore(&dwc->lock, flags);
1221
1222         return ret;
1223 }
1224
1225 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1226                 struct usb_request *request)
1227 {
1228         struct dwc3_request             *req = to_dwc3_request(request);
1229         struct dwc3_request             *r = NULL;
1230
1231         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1232         struct dwc3                     *dwc = dep->dwc;
1233
1234         unsigned long                   flags;
1235         int                             ret = 0;
1236
1237         trace_dwc3_ep_dequeue(req);
1238
1239         spin_lock_irqsave(&dwc->lock, flags);
1240
1241         list_for_each_entry(r, &dep->pending_list, list) {
1242                 if (r == req)
1243                         break;
1244         }
1245
1246         if (r != req) {
1247                 list_for_each_entry(r, &dep->started_list, list) {
1248                         if (r == req)
1249                                 break;
1250                 }
1251                 if (r == req) {
1252                         /* wait until it is processed */
1253                         dwc3_stop_active_transfer(dwc, dep->number, true);
1254                         goto out1;
1255                 }
1256                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1257                                 request, ep->name);
1258                 ret = -EINVAL;
1259                 goto out0;
1260         }
1261
1262 out1:
1263         /* giveback the request */
1264         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1265
1266 out0:
1267         spin_unlock_irqrestore(&dwc->lock, flags);
1268
1269         return ret;
1270 }
1271
1272 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1273 {
1274         struct dwc3_gadget_ep_cmd_params        params;
1275         struct dwc3                             *dwc = dep->dwc;
1276         int                                     ret;
1277
1278         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1279                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1280                 return -EINVAL;
1281         }
1282
1283         memset(&params, 0x00, sizeof(params));
1284
1285         if (value) {
1286                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1287                                 (!list_empty(&dep->started_list) ||
1288                                  !list_empty(&dep->pending_list)))) {
1289                         dwc3_trace(trace_dwc3_gadget,
1290                                         "%s: pending request, cannot halt\n",
1291                                         dep->name);
1292                         return -EAGAIN;
1293                 }
1294
1295                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1296                         DWC3_DEPCMD_SETSTALL, &params);
1297                 if (ret)
1298                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1299                                         dep->name);
1300                 else
1301                         dep->flags |= DWC3_EP_STALL;
1302         } else {
1303                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1304                         DWC3_DEPCMD_CLEARSTALL, &params);
1305                 if (ret)
1306                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1307                                         dep->name);
1308                 else
1309                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1310         }
1311
1312         return ret;
1313 }
1314
1315 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1316 {
1317         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1318         struct dwc3                     *dwc = dep->dwc;
1319
1320         unsigned long                   flags;
1321
1322         int                             ret;
1323
1324         spin_lock_irqsave(&dwc->lock, flags);
1325         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1326         spin_unlock_irqrestore(&dwc->lock, flags);
1327
1328         return ret;
1329 }
1330
1331 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1332 {
1333         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1334         struct dwc3                     *dwc = dep->dwc;
1335         unsigned long                   flags;
1336         int                             ret;
1337
1338         spin_lock_irqsave(&dwc->lock, flags);
1339         dep->flags |= DWC3_EP_WEDGE;
1340
1341         if (dep->number == 0 || dep->number == 1)
1342                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1343         else
1344                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1345         spin_unlock_irqrestore(&dwc->lock, flags);
1346
1347         return ret;
1348 }
1349
1350 /* -------------------------------------------------------------------------- */
1351
1352 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1353         .bLength        = USB_DT_ENDPOINT_SIZE,
1354         .bDescriptorType = USB_DT_ENDPOINT,
1355         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1356 };
1357
1358 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1359         .enable         = dwc3_gadget_ep0_enable,
1360         .disable        = dwc3_gadget_ep0_disable,
1361         .alloc_request  = dwc3_gadget_ep_alloc_request,
1362         .free_request   = dwc3_gadget_ep_free_request,
1363         .queue          = dwc3_gadget_ep0_queue,
1364         .dequeue        = dwc3_gadget_ep_dequeue,
1365         .set_halt       = dwc3_gadget_ep0_set_halt,
1366         .set_wedge      = dwc3_gadget_ep_set_wedge,
1367 };
1368
1369 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1370         .enable         = dwc3_gadget_ep_enable,
1371         .disable        = dwc3_gadget_ep_disable,
1372         .alloc_request  = dwc3_gadget_ep_alloc_request,
1373         .free_request   = dwc3_gadget_ep_free_request,
1374         .queue          = dwc3_gadget_ep_queue,
1375         .dequeue        = dwc3_gadget_ep_dequeue,
1376         .set_halt       = dwc3_gadget_ep_set_halt,
1377         .set_wedge      = dwc3_gadget_ep_set_wedge,
1378 };
1379
1380 /* -------------------------------------------------------------------------- */
1381
1382 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1383 {
1384         struct dwc3             *dwc = gadget_to_dwc(g);
1385         u32                     reg;
1386
1387         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1388         return DWC3_DSTS_SOFFN(reg);
1389 }
1390
1391 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1392 {
1393         unsigned long           timeout;
1394
1395         int                     ret;
1396         u32                     reg;
1397
1398         u8                      link_state;
1399         u8                      speed;
1400
1401         /*
1402          * According to the Databook Remote wakeup request should
1403          * be issued only when the device is in early suspend state.
1404          *
1405          * We can check that via USB Link State bits in DSTS register.
1406          */
1407         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1408
1409         speed = reg & DWC3_DSTS_CONNECTSPD;
1410         if (speed == DWC3_DSTS_SUPERSPEED) {
1411                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1412                 return -EINVAL;
1413         }
1414
1415         link_state = DWC3_DSTS_USBLNKST(reg);
1416
1417         switch (link_state) {
1418         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1419         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1420                 break;
1421         default:
1422                 dwc3_trace(trace_dwc3_gadget,
1423                                 "can't wakeup from '%s'\n",
1424                                 dwc3_gadget_link_string(link_state));
1425                 return -EINVAL;
1426         }
1427
1428         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1429         if (ret < 0) {
1430                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1431                 return ret;
1432         }
1433
1434         /* Recent versions do this automatically */
1435         if (dwc->revision < DWC3_REVISION_194A) {
1436                 /* write zeroes to Link Change Request */
1437                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1438                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1439                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1440         }
1441
1442         /* poll until Link State changes to ON */
1443         timeout = jiffies + msecs_to_jiffies(100);
1444
1445         while (!time_after(jiffies, timeout)) {
1446                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1447
1448                 /* in HS, means ON */
1449                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1450                         break;
1451         }
1452
1453         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1454                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1455                 return -EINVAL;
1456         }
1457
1458         return 0;
1459 }
1460
1461 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1462 {
1463         struct dwc3             *dwc = gadget_to_dwc(g);
1464         unsigned long           flags;
1465         int                     ret;
1466
1467         spin_lock_irqsave(&dwc->lock, flags);
1468         ret = __dwc3_gadget_wakeup(dwc);
1469         spin_unlock_irqrestore(&dwc->lock, flags);
1470
1471         return ret;
1472 }
1473
1474 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1475                 int is_selfpowered)
1476 {
1477         struct dwc3             *dwc = gadget_to_dwc(g);
1478         unsigned long           flags;
1479
1480         spin_lock_irqsave(&dwc->lock, flags);
1481         g->is_selfpowered = !!is_selfpowered;
1482         spin_unlock_irqrestore(&dwc->lock, flags);
1483
1484         return 0;
1485 }
1486
1487 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1488 {
1489         u32                     reg;
1490         u32                     timeout = 500;
1491
1492         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1493         if (is_on) {
1494                 if (dwc->revision <= DWC3_REVISION_187A) {
1495                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1496                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1497                 }
1498
1499                 if (dwc->revision >= DWC3_REVISION_194A)
1500                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1501                 reg |= DWC3_DCTL_RUN_STOP;
1502
1503                 if (dwc->has_hibernation)
1504                         reg |= DWC3_DCTL_KEEP_CONNECT;
1505
1506                 dwc->pullups_connected = true;
1507         } else {
1508                 reg &= ~DWC3_DCTL_RUN_STOP;
1509
1510                 if (dwc->has_hibernation && !suspend)
1511                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1512
1513                 dwc->pullups_connected = false;
1514         }
1515
1516         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1517
1518         do {
1519                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1520                 if (is_on) {
1521                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1522                                 break;
1523                 } else {
1524                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1525                                 break;
1526                 }
1527                 timeout--;
1528                 if (!timeout)
1529                         return -ETIMEDOUT;
1530                 udelay(1);
1531         } while (1);
1532
1533         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1534                         dwc->gadget_driver
1535                         ? dwc->gadget_driver->function : "no-function",
1536                         is_on ? "connect" : "disconnect");
1537
1538         return 0;
1539 }
1540
1541 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1542 {
1543         struct dwc3             *dwc = gadget_to_dwc(g);
1544         unsigned long           flags;
1545         int                     ret;
1546
1547         is_on = !!is_on;
1548
1549         spin_lock_irqsave(&dwc->lock, flags);
1550         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1551         spin_unlock_irqrestore(&dwc->lock, flags);
1552
1553         return ret;
1554 }
1555
1556 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1557 {
1558         u32                     reg;
1559
1560         /* Enable all but Start and End of Frame IRQs */
1561         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1562                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1563                         DWC3_DEVTEN_CMDCMPLTEN |
1564                         DWC3_DEVTEN_ERRTICERREN |
1565                         DWC3_DEVTEN_WKUPEVTEN |
1566                         DWC3_DEVTEN_ULSTCNGEN |
1567                         DWC3_DEVTEN_CONNECTDONEEN |
1568                         DWC3_DEVTEN_USBRSTEN |
1569                         DWC3_DEVTEN_DISCONNEVTEN);
1570
1571         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1572 }
1573
1574 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1575 {
1576         /* mask all interrupts */
1577         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1578 }
1579
1580 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1581 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1582
1583 static int dwc3_gadget_start(struct usb_gadget *g,
1584                 struct usb_gadget_driver *driver)
1585 {
1586         struct dwc3             *dwc = gadget_to_dwc(g);
1587         struct dwc3_ep          *dep;
1588         unsigned long           flags;
1589         int                     ret = 0;
1590         int                     irq;
1591         u32                     reg;
1592
1593         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1594         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1595                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1596         if (ret) {
1597                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1598                                 irq, ret);
1599                 goto err0;
1600         }
1601
1602         spin_lock_irqsave(&dwc->lock, flags);
1603
1604         if (dwc->gadget_driver) {
1605                 dev_err(dwc->dev, "%s is already bound to %s\n",
1606                                 dwc->gadget.name,
1607                                 dwc->gadget_driver->driver.name);
1608                 ret = -EBUSY;
1609                 goto err1;
1610         }
1611
1612         dwc->gadget_driver      = driver;
1613
1614         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1615         reg &= ~(DWC3_DCFG_SPEED_MASK);
1616
1617         /**
1618          * WORKAROUND: DWC3 revision < 2.20a have an issue
1619          * which would cause metastability state on Run/Stop
1620          * bit if we try to force the IP to USB2-only mode.
1621          *
1622          * Because of that, we cannot configure the IP to any
1623          * speed other than the SuperSpeed
1624          *
1625          * Refers to:
1626          *
1627          * STAR#9000525659: Clock Domain Crossing on DCTL in
1628          * USB 2.0 Mode
1629          */
1630         if (dwc->revision < DWC3_REVISION_220A) {
1631                 reg |= DWC3_DCFG_SUPERSPEED;
1632         } else {
1633                 switch (dwc->maximum_speed) {
1634                 case USB_SPEED_LOW:
1635                         reg |= DWC3_DSTS_LOWSPEED;
1636                         break;
1637                 case USB_SPEED_FULL:
1638                         reg |= DWC3_DSTS_FULLSPEED1;
1639                         break;
1640                 case USB_SPEED_HIGH:
1641                         reg |= DWC3_DSTS_HIGHSPEED;
1642                         break;
1643                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1644                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1645                 default:
1646                         reg |= DWC3_DSTS_SUPERSPEED;
1647                 }
1648         }
1649         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1650
1651         /* Start with SuperSpeed Default */
1652         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1653
1654         dep = dwc->eps[0];
1655         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1656                         false);
1657         if (ret) {
1658                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1659                 goto err2;
1660         }
1661
1662         dep = dwc->eps[1];
1663         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1664                         false);
1665         if (ret) {
1666                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1667                 goto err3;
1668         }
1669
1670         /* begin to receive SETUP packets */
1671         dwc->ep0state = EP0_SETUP_PHASE;
1672         dwc3_ep0_out_start(dwc);
1673
1674         dwc3_gadget_enable_irq(dwc);
1675
1676         spin_unlock_irqrestore(&dwc->lock, flags);
1677
1678         return 0;
1679
1680 err3:
1681         __dwc3_gadget_ep_disable(dwc->eps[0]);
1682
1683 err2:
1684         dwc->gadget_driver = NULL;
1685
1686 err1:
1687         spin_unlock_irqrestore(&dwc->lock, flags);
1688
1689         free_irq(irq, dwc->ev_buf);
1690
1691 err0:
1692         return ret;
1693 }
1694
1695 static int dwc3_gadget_stop(struct usb_gadget *g)
1696 {
1697         struct dwc3             *dwc = gadget_to_dwc(g);
1698         unsigned long           flags;
1699         int                     irq;
1700
1701         spin_lock_irqsave(&dwc->lock, flags);
1702
1703         dwc3_gadget_disable_irq(dwc);
1704         __dwc3_gadget_ep_disable(dwc->eps[0]);
1705         __dwc3_gadget_ep_disable(dwc->eps[1]);
1706
1707         dwc->gadget_driver      = NULL;
1708
1709         spin_unlock_irqrestore(&dwc->lock, flags);
1710
1711         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1712         free_irq(irq, dwc->ev_buf);
1713
1714         return 0;
1715 }
1716
1717 static const struct usb_gadget_ops dwc3_gadget_ops = {
1718         .get_frame              = dwc3_gadget_get_frame,
1719         .wakeup                 = dwc3_gadget_wakeup,
1720         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1721         .pullup                 = dwc3_gadget_pullup,
1722         .udc_start              = dwc3_gadget_start,
1723         .udc_stop               = dwc3_gadget_stop,
1724 };
1725
1726 /* -------------------------------------------------------------------------- */
1727
1728 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1729                 u8 num, u32 direction)
1730 {
1731         struct dwc3_ep                  *dep;
1732         u8                              i;
1733
1734         for (i = 0; i < num; i++) {
1735                 u8 epnum = (i << 1) | (!!direction);
1736
1737                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1738                 if (!dep)
1739                         return -ENOMEM;
1740
1741                 dep->dwc = dwc;
1742                 dep->number = epnum;
1743                 dep->direction = !!direction;
1744                 dwc->eps[epnum] = dep;
1745
1746                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1747                                 (epnum & 1) ? "in" : "out");
1748
1749                 dep->endpoint.name = dep->name;
1750
1751                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1752
1753                 if (epnum == 0 || epnum == 1) {
1754                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1755                         dep->endpoint.maxburst = 1;
1756                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1757                         if (!epnum)
1758                                 dwc->gadget.ep0 = &dep->endpoint;
1759                 } else {
1760                         int             ret;
1761
1762                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1763                         dep->endpoint.max_streams = 15;
1764                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1765                         list_add_tail(&dep->endpoint.ep_list,
1766                                         &dwc->gadget.ep_list);
1767
1768                         ret = dwc3_alloc_trb_pool(dep);
1769                         if (ret)
1770                                 return ret;
1771                 }
1772
1773                 if (epnum == 0 || epnum == 1) {
1774                         dep->endpoint.caps.type_control = true;
1775                 } else {
1776                         dep->endpoint.caps.type_iso = true;
1777                         dep->endpoint.caps.type_bulk = true;
1778                         dep->endpoint.caps.type_int = true;
1779                 }
1780
1781                 dep->endpoint.caps.dir_in = !!direction;
1782                 dep->endpoint.caps.dir_out = !direction;
1783
1784                 INIT_LIST_HEAD(&dep->pending_list);
1785                 INIT_LIST_HEAD(&dep->started_list);
1786         }
1787
1788         return 0;
1789 }
1790
1791 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1792 {
1793         int                             ret;
1794
1795         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1796
1797         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1798         if (ret < 0) {
1799                 dwc3_trace(trace_dwc3_gadget,
1800                                 "failed to allocate OUT endpoints");
1801                 return ret;
1802         }
1803
1804         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1805         if (ret < 0) {
1806                 dwc3_trace(trace_dwc3_gadget,
1807                                 "failed to allocate IN endpoints");
1808                 return ret;
1809         }
1810
1811         return 0;
1812 }
1813
1814 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1815 {
1816         struct dwc3_ep                  *dep;
1817         u8                              epnum;
1818
1819         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1820                 dep = dwc->eps[epnum];
1821                 if (!dep)
1822                         continue;
1823                 /*
1824                  * Physical endpoints 0 and 1 are special; they form the
1825                  * bi-directional USB endpoint 0.
1826                  *
1827                  * For those two physical endpoints, we don't allocate a TRB
1828                  * pool nor do we add them the endpoints list. Due to that, we
1829                  * shouldn't do these two operations otherwise we would end up
1830                  * with all sorts of bugs when removing dwc3.ko.
1831                  */
1832                 if (epnum != 0 && epnum != 1) {
1833                         dwc3_free_trb_pool(dep);
1834                         list_del(&dep->endpoint.ep_list);
1835                 }
1836
1837                 kfree(dep);
1838         }
1839 }
1840
1841 /* -------------------------------------------------------------------------- */
1842
1843 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1844                 struct dwc3_request *req, struct dwc3_trb *trb,
1845                 const struct dwc3_event_depevt *event, int status)
1846 {
1847         unsigned int            count;
1848         unsigned int            s_pkt = 0;
1849         unsigned int            trb_status;
1850
1851         trace_dwc3_complete_trb(dep, trb);
1852
1853         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1854                 /*
1855                  * We continue despite the error. There is not much we
1856                  * can do. If we don't clean it up we loop forever. If
1857                  * we skip the TRB then it gets overwritten after a
1858                  * while since we use them in a ring buffer. A BUG()
1859                  * would help. Lets hope that if this occurs, someone
1860                  * fixes the root cause instead of looking away :)
1861                  */
1862                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1863                                 dep->name, trb);
1864         count = trb->size & DWC3_TRB_SIZE_MASK;
1865
1866         if (dep->direction) {
1867                 if (count) {
1868                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1869                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1870                                 dwc3_trace(trace_dwc3_gadget,
1871                                                 "%s: incomplete IN transfer\n",
1872                                                 dep->name);
1873                                 /*
1874                                  * If missed isoc occurred and there is
1875                                  * no request queued then issue END
1876                                  * TRANSFER, so that core generates
1877                                  * next xfernotready and we will issue
1878                                  * a fresh START TRANSFER.
1879                                  * If there are still queued request
1880                                  * then wait, do not issue either END
1881                                  * or UPDATE TRANSFER, just attach next
1882                                  * request in pending_list during
1883                                  * giveback.If any future queued request
1884                                  * is successfully transferred then we
1885                                  * will issue UPDATE TRANSFER for all
1886                                  * request in the pending_list.
1887                                  */
1888                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1889                         } else {
1890                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1891                                                 dep->name);
1892                                 status = -ECONNRESET;
1893                         }
1894                 } else {
1895                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1896                 }
1897         } else {
1898                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1899                         s_pkt = 1;
1900         }
1901
1902         /*
1903          * We assume here we will always receive the entire data block
1904          * which we should receive. Meaning, if we program RX to
1905          * receive 4K but we receive only 2K, we assume that's all we
1906          * should receive and we simply bounce the request back to the
1907          * gadget driver for further processing.
1908          */
1909         req->request.actual += req->request.length - count;
1910         if (s_pkt)
1911                 return 1;
1912         if ((event->status & DEPEVT_STATUS_LST) &&
1913                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1914                                 DWC3_TRB_CTRL_HWO)))
1915                 return 1;
1916         if ((event->status & DEPEVT_STATUS_IOC) &&
1917                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1918                 return 1;
1919         return 0;
1920 }
1921
1922 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1923                 const struct dwc3_event_depevt *event, int status)
1924 {
1925         struct dwc3_request     *req;
1926         struct dwc3_trb         *trb;
1927         unsigned int            slot;
1928         unsigned int            i;
1929         int                     ret;
1930
1931         do {
1932                 req = next_request(&dep->started_list);
1933                 if (WARN_ON_ONCE(!req))
1934                         return 1;
1935
1936                 i = 0;
1937                 do {
1938                         slot = req->first_trb_index + i;
1939                         if ((slot == DWC3_TRB_NUM - 1) &&
1940                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1941                                 slot++;
1942                         slot %= DWC3_TRB_NUM;
1943                         trb = &dep->trb_pool[slot];
1944
1945                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1946                                         event, status);
1947                         if (ret)
1948                                 break;
1949                 } while (++i < req->request.num_mapped_sgs);
1950
1951                 dwc3_gadget_giveback(dep, req, status);
1952
1953                 if (ret)
1954                         break;
1955         } while (1);
1956
1957         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1958                         list_empty(&dep->started_list)) {
1959                 if (list_empty(&dep->pending_list)) {
1960                         /*
1961                          * If there is no entry in request list then do
1962                          * not issue END TRANSFER now. Just set PENDING
1963                          * flag, so that END TRANSFER is issued when an
1964                          * entry is added into request list.
1965                          */
1966                         dep->flags = DWC3_EP_PENDING_REQUEST;
1967                 } else {
1968                         dwc3_stop_active_transfer(dwc, dep->number, true);
1969                         dep->flags = DWC3_EP_ENABLED;
1970                 }
1971                 return 1;
1972         }
1973
1974         return 1;
1975 }
1976
1977 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1978                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1979 {
1980         unsigned                status = 0;
1981         int                     clean_busy;
1982         u32                     is_xfer_complete;
1983
1984         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
1985
1986         if (event->status & DEPEVT_STATUS_BUSERR)
1987                 status = -ECONNRESET;
1988
1989         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1990         if (clean_busy && (is_xfer_complete ||
1991                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
1992                 dep->flags &= ~DWC3_EP_BUSY;
1993
1994         /*
1995          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1996          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1997          */
1998         if (dwc->revision < DWC3_REVISION_183A) {
1999                 u32             reg;
2000                 int             i;
2001
2002                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2003                         dep = dwc->eps[i];
2004
2005                         if (!(dep->flags & DWC3_EP_ENABLED))
2006                                 continue;
2007
2008                         if (!list_empty(&dep->started_list))
2009                                 return;
2010                 }
2011
2012                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2013                 reg |= dwc->u1u2;
2014                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2015
2016                 dwc->u1u2 = 0;
2017         }
2018
2019         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2020                 int ret;
2021
2022                 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2023                 if (!ret || ret == -EBUSY)
2024                         return;
2025         }
2026 }
2027
2028 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2029                 const struct dwc3_event_depevt *event)
2030 {
2031         struct dwc3_ep          *dep;
2032         u8                      epnum = event->endpoint_number;
2033
2034         dep = dwc->eps[epnum];
2035
2036         if (!(dep->flags & DWC3_EP_ENABLED))
2037                 return;
2038
2039         if (epnum == 0 || epnum == 1) {
2040                 dwc3_ep0_interrupt(dwc, event);
2041                 return;
2042         }
2043
2044         switch (event->endpoint_event) {
2045         case DWC3_DEPEVT_XFERCOMPLETE:
2046                 dep->resource_index = 0;
2047
2048                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2049                         dwc3_trace(trace_dwc3_gadget,
2050                                         "%s is an Isochronous endpoint\n",
2051                                         dep->name);
2052                         return;
2053                 }
2054
2055                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2056                 break;
2057         case DWC3_DEPEVT_XFERINPROGRESS:
2058                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2059                 break;
2060         case DWC3_DEPEVT_XFERNOTREADY:
2061                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2062                         dwc3_gadget_start_isoc(dwc, dep, event);
2063                 } else {
2064                         int active;
2065                         int ret;
2066
2067                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2068
2069                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2070                                         dep->name, active ? "Transfer Active"
2071                                         : "Transfer Not Active");
2072
2073                         ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2074                         if (!ret || ret == -EBUSY)
2075                                 return;
2076
2077                         dwc3_trace(trace_dwc3_gadget,
2078                                         "%s: failed to kick transfers\n",
2079                                         dep->name);
2080                 }
2081
2082                 break;
2083         case DWC3_DEPEVT_STREAMEVT:
2084                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2085                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2086                                         dep->name);
2087                         return;
2088                 }
2089
2090                 switch (event->status) {
2091                 case DEPEVT_STREAMEVT_FOUND:
2092                         dwc3_trace(trace_dwc3_gadget,
2093                                         "Stream %d found and started",
2094                                         event->parameters);
2095
2096                         break;
2097                 case DEPEVT_STREAMEVT_NOTFOUND:
2098                         /* FALLTHROUGH */
2099                 default:
2100                         dwc3_trace(trace_dwc3_gadget,
2101                                         "unable to find suitable stream\n");
2102                 }
2103                 break;
2104         case DWC3_DEPEVT_RXTXFIFOEVT:
2105                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2106                 break;
2107         case DWC3_DEPEVT_EPCMDCMPLT:
2108                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2109                 break;
2110         }
2111 }
2112
2113 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2114 {
2115         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2116                 spin_unlock(&dwc->lock);
2117                 dwc->gadget_driver->disconnect(&dwc->gadget);
2118                 spin_lock(&dwc->lock);
2119         }
2120 }
2121
2122 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2123 {
2124         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2125                 spin_unlock(&dwc->lock);
2126                 dwc->gadget_driver->suspend(&dwc->gadget);
2127                 spin_lock(&dwc->lock);
2128         }
2129 }
2130
2131 static void dwc3_resume_gadget(struct dwc3 *dwc)
2132 {
2133         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2134                 spin_unlock(&dwc->lock);
2135                 dwc->gadget_driver->resume(&dwc->gadget);
2136                 spin_lock(&dwc->lock);
2137         }
2138 }
2139
2140 static void dwc3_reset_gadget(struct dwc3 *dwc)
2141 {
2142         if (!dwc->gadget_driver)
2143                 return;
2144
2145         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2146                 spin_unlock(&dwc->lock);
2147                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2148                 spin_lock(&dwc->lock);
2149         }
2150 }
2151
2152 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2153 {
2154         struct dwc3_ep *dep;
2155         struct dwc3_gadget_ep_cmd_params params;
2156         u32 cmd;
2157         int ret;
2158
2159         dep = dwc->eps[epnum];
2160
2161         if (!dep->resource_index)
2162                 return;
2163
2164         /*
2165          * NOTICE: We are violating what the Databook says about the
2166          * EndTransfer command. Ideally we would _always_ wait for the
2167          * EndTransfer Command Completion IRQ, but that's causing too
2168          * much trouble synchronizing between us and gadget driver.
2169          *
2170          * We have discussed this with the IP Provider and it was
2171          * suggested to giveback all requests here, but give HW some
2172          * extra time to synchronize with the interconnect. We're using
2173          * an arbitrary 100us delay for that.
2174          *
2175          * Note also that a similar handling was tested by Synopsys
2176          * (thanks a lot Paul) and nothing bad has come out of it.
2177          * In short, what we're doing is:
2178          *
2179          * - Issue EndTransfer WITH CMDIOC bit set
2180          * - Wait 100us
2181          */
2182
2183         cmd = DWC3_DEPCMD_ENDTRANSFER;
2184         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2185         cmd |= DWC3_DEPCMD_CMDIOC;
2186         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2187         memset(&params, 0, sizeof(params));
2188         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2189         WARN_ON_ONCE(ret);
2190         dep->resource_index = 0;
2191         dep->flags &= ~DWC3_EP_BUSY;
2192         udelay(100);
2193 }
2194
2195 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2196 {
2197         u32 epnum;
2198
2199         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2200                 struct dwc3_ep *dep;
2201
2202                 dep = dwc->eps[epnum];
2203                 if (!dep)
2204                         continue;
2205
2206                 if (!(dep->flags & DWC3_EP_ENABLED))
2207                         continue;
2208
2209                 dwc3_remove_requests(dwc, dep);
2210         }
2211 }
2212
2213 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2214 {
2215         u32 epnum;
2216
2217         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2218                 struct dwc3_ep *dep;
2219                 struct dwc3_gadget_ep_cmd_params params;
2220                 int ret;
2221
2222                 dep = dwc->eps[epnum];
2223                 if (!dep)
2224                         continue;
2225
2226                 if (!(dep->flags & DWC3_EP_STALL))
2227                         continue;
2228
2229                 dep->flags &= ~DWC3_EP_STALL;
2230
2231                 memset(&params, 0, sizeof(params));
2232                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2233                                 DWC3_DEPCMD_CLEARSTALL, &params);
2234                 WARN_ON_ONCE(ret);
2235         }
2236 }
2237
2238 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2239 {
2240         int                     reg;
2241
2242         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2243         reg &= ~DWC3_DCTL_INITU1ENA;
2244         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2245
2246         reg &= ~DWC3_DCTL_INITU2ENA;
2247         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2248
2249         dwc3_disconnect_gadget(dwc);
2250
2251         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2252         dwc->setup_packet_pending = false;
2253         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2254 }
2255
2256 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2257 {
2258         u32                     reg;
2259
2260         /*
2261          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2262          * would cause a missing Disconnect Event if there's a
2263          * pending Setup Packet in the FIFO.
2264          *
2265          * There's no suggested workaround on the official Bug
2266          * report, which states that "unless the driver/application
2267          * is doing any special handling of a disconnect event,
2268          * there is no functional issue".
2269          *
2270          * Unfortunately, it turns out that we _do_ some special
2271          * handling of a disconnect event, namely complete all
2272          * pending transfers, notify gadget driver of the
2273          * disconnection, and so on.
2274          *
2275          * Our suggested workaround is to follow the Disconnect
2276          * Event steps here, instead, based on a setup_packet_pending
2277          * flag. Such flag gets set whenever we have a SETUP_PENDING
2278          * status for EP0 TRBs and gets cleared on XferComplete for the
2279          * same endpoint.
2280          *
2281          * Refers to:
2282          *
2283          * STAR#9000466709: RTL: Device : Disconnect event not
2284          * generated if setup packet pending in FIFO
2285          */
2286         if (dwc->revision < DWC3_REVISION_188A) {
2287                 if (dwc->setup_packet_pending)
2288                         dwc3_gadget_disconnect_interrupt(dwc);
2289         }
2290
2291         dwc3_reset_gadget(dwc);
2292
2293         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2294         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2295         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2296         dwc->test_mode = false;
2297
2298         dwc3_stop_active_transfers(dwc);
2299         dwc3_clear_stall_all_ep(dwc);
2300
2301         /* Reset device address to zero */
2302         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2303         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2304         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2305 }
2306
2307 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2308 {
2309         u32 reg;
2310         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2311
2312         /*
2313          * We change the clock only at SS but I dunno why I would want to do
2314          * this. Maybe it becomes part of the power saving plan.
2315          */
2316
2317         if (speed != DWC3_DSTS_SUPERSPEED)
2318                 return;
2319
2320         /*
2321          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2322          * each time on Connect Done.
2323          */
2324         if (!usb30_clock)
2325                 return;
2326
2327         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2328         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2329         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2330 }
2331
2332 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2333 {
2334         struct dwc3_ep          *dep;
2335         int                     ret;
2336         u32                     reg;
2337         u8                      speed;
2338
2339         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2340         speed = reg & DWC3_DSTS_CONNECTSPD;
2341         dwc->speed = speed;
2342
2343         dwc3_update_ram_clk_sel(dwc, speed);
2344
2345         switch (speed) {
2346         case DWC3_DCFG_SUPERSPEED:
2347                 /*
2348                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2349                  * would cause a missing USB3 Reset event.
2350                  *
2351                  * In such situations, we should force a USB3 Reset
2352                  * event by calling our dwc3_gadget_reset_interrupt()
2353                  * routine.
2354                  *
2355                  * Refers to:
2356                  *
2357                  * STAR#9000483510: RTL: SS : USB3 reset event may
2358                  * not be generated always when the link enters poll
2359                  */
2360                 if (dwc->revision < DWC3_REVISION_190A)
2361                         dwc3_gadget_reset_interrupt(dwc);
2362
2363                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2364                 dwc->gadget.ep0->maxpacket = 512;
2365                 dwc->gadget.speed = USB_SPEED_SUPER;
2366                 break;
2367         case DWC3_DCFG_HIGHSPEED:
2368                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2369                 dwc->gadget.ep0->maxpacket = 64;
2370                 dwc->gadget.speed = USB_SPEED_HIGH;
2371                 break;
2372         case DWC3_DCFG_FULLSPEED2:
2373         case DWC3_DCFG_FULLSPEED1:
2374                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2375                 dwc->gadget.ep0->maxpacket = 64;
2376                 dwc->gadget.speed = USB_SPEED_FULL;
2377                 break;
2378         case DWC3_DCFG_LOWSPEED:
2379                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2380                 dwc->gadget.ep0->maxpacket = 8;
2381                 dwc->gadget.speed = USB_SPEED_LOW;
2382                 break;
2383         }
2384
2385         /* Enable USB2 LPM Capability */
2386
2387         if ((dwc->revision > DWC3_REVISION_194A)
2388                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2389                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2390                 reg |= DWC3_DCFG_LPM_CAP;
2391                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2392
2393                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2394                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2395
2396                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2397
2398                 /*
2399                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2400                  * DCFG.LPMCap is set, core responses with an ACK and the
2401                  * BESL value in the LPM token is less than or equal to LPM
2402                  * NYET threshold.
2403                  */
2404                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2405                                 && dwc->has_lpm_erratum,
2406                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2407
2408                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2409                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2410
2411                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2412         } else {
2413                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2414                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2415                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2416         }
2417
2418         dep = dwc->eps[0];
2419         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2420                         false);
2421         if (ret) {
2422                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2423                 return;
2424         }
2425
2426         dep = dwc->eps[1];
2427         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2428                         false);
2429         if (ret) {
2430                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2431                 return;
2432         }
2433
2434         /*
2435          * Configure PHY via GUSB3PIPECTLn if required.
2436          *
2437          * Update GTXFIFOSIZn
2438          *
2439          * In both cases reset values should be sufficient.
2440          */
2441 }
2442
2443 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2444 {
2445         /*
2446          * TODO take core out of low power mode when that's
2447          * implemented.
2448          */
2449
2450         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2451                 spin_unlock(&dwc->lock);
2452                 dwc->gadget_driver->resume(&dwc->gadget);
2453                 spin_lock(&dwc->lock);
2454         }
2455 }
2456
2457 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2458                 unsigned int evtinfo)
2459 {
2460         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2461         unsigned int            pwropt;
2462
2463         /*
2464          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2465          * Hibernation mode enabled which would show up when device detects
2466          * host-initiated U3 exit.
2467          *
2468          * In that case, device will generate a Link State Change Interrupt
2469          * from U3 to RESUME which is only necessary if Hibernation is
2470          * configured in.
2471          *
2472          * There are no functional changes due to such spurious event and we
2473          * just need to ignore it.
2474          *
2475          * Refers to:
2476          *
2477          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2478          * operational mode
2479          */
2480         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2481         if ((dwc->revision < DWC3_REVISION_250A) &&
2482                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2483                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2484                                 (next == DWC3_LINK_STATE_RESUME)) {
2485                         dwc3_trace(trace_dwc3_gadget,
2486                                         "ignoring transition U3 -> Resume");
2487                         return;
2488                 }
2489         }
2490
2491         /*
2492          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2493          * on the link partner, the USB session might do multiple entry/exit
2494          * of low power states before a transfer takes place.
2495          *
2496          * Due to this problem, we might experience lower throughput. The
2497          * suggested workaround is to disable DCTL[12:9] bits if we're
2498          * transitioning from U1/U2 to U0 and enable those bits again
2499          * after a transfer completes and there are no pending transfers
2500          * on any of the enabled endpoints.
2501          *
2502          * This is the first half of that workaround.
2503          *
2504          * Refers to:
2505          *
2506          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2507          * core send LGO_Ux entering U0
2508          */
2509         if (dwc->revision < DWC3_REVISION_183A) {
2510                 if (next == DWC3_LINK_STATE_U0) {
2511                         u32     u1u2;
2512                         u32     reg;
2513
2514                         switch (dwc->link_state) {
2515                         case DWC3_LINK_STATE_U1:
2516                         case DWC3_LINK_STATE_U2:
2517                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2518                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2519                                                 | DWC3_DCTL_ACCEPTU2ENA
2520                                                 | DWC3_DCTL_INITU1ENA
2521                                                 | DWC3_DCTL_ACCEPTU1ENA);
2522
2523                                 if (!dwc->u1u2)
2524                                         dwc->u1u2 = reg & u1u2;
2525
2526                                 reg &= ~u1u2;
2527
2528                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2529                                 break;
2530                         default:
2531                                 /* do nothing */
2532                                 break;
2533                         }
2534                 }
2535         }
2536
2537         switch (next) {
2538         case DWC3_LINK_STATE_U1:
2539                 if (dwc->speed == USB_SPEED_SUPER)
2540                         dwc3_suspend_gadget(dwc);
2541                 break;
2542         case DWC3_LINK_STATE_U2:
2543         case DWC3_LINK_STATE_U3:
2544                 dwc3_suspend_gadget(dwc);
2545                 break;
2546         case DWC3_LINK_STATE_RESUME:
2547                 dwc3_resume_gadget(dwc);
2548                 break;
2549         default:
2550                 /* do nothing */
2551                 break;
2552         }
2553
2554         dwc->link_state = next;
2555 }
2556
2557 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2558                 unsigned int evtinfo)
2559 {
2560         unsigned int is_ss = evtinfo & BIT(4);
2561
2562         /**
2563          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2564          * have a known issue which can cause USB CV TD.9.23 to fail
2565          * randomly.
2566          *
2567          * Because of this issue, core could generate bogus hibernation
2568          * events which SW needs to ignore.
2569          *
2570          * Refers to:
2571          *
2572          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2573          * Device Fallback from SuperSpeed
2574          */
2575         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2576                 return;
2577
2578         /* enter hibernation here */
2579 }
2580
2581 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2582                 const struct dwc3_event_devt *event)
2583 {
2584         switch (event->type) {
2585         case DWC3_DEVICE_EVENT_DISCONNECT:
2586                 dwc3_gadget_disconnect_interrupt(dwc);
2587                 break;
2588         case DWC3_DEVICE_EVENT_RESET:
2589                 dwc3_gadget_reset_interrupt(dwc);
2590                 break;
2591         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2592                 dwc3_gadget_conndone_interrupt(dwc);
2593                 break;
2594         case DWC3_DEVICE_EVENT_WAKEUP:
2595                 dwc3_gadget_wakeup_interrupt(dwc);
2596                 break;
2597         case DWC3_DEVICE_EVENT_HIBER_REQ:
2598                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2599                                         "unexpected hibernation event\n"))
2600                         break;
2601
2602                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2603                 break;
2604         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2605                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2606                 break;
2607         case DWC3_DEVICE_EVENT_EOPF:
2608                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2609                 break;
2610         case DWC3_DEVICE_EVENT_SOF:
2611                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2612                 break;
2613         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2614                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2615                 break;
2616         case DWC3_DEVICE_EVENT_CMD_CMPL:
2617                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2618                 break;
2619         case DWC3_DEVICE_EVENT_OVERFLOW:
2620                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2621                 break;
2622         default:
2623                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2624         }
2625 }
2626
2627 static void dwc3_process_event_entry(struct dwc3 *dwc,
2628                 const union dwc3_event *event)
2629 {
2630         trace_dwc3_event(event->raw);
2631
2632         /* Endpoint IRQ, handle it and return early */
2633         if (event->type.is_devspec == 0) {
2634                 /* depevt */
2635                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2636         }
2637
2638         switch (event->type.type) {
2639         case DWC3_EVENT_TYPE_DEV:
2640                 dwc3_gadget_interrupt(dwc, &event->devt);
2641                 break;
2642         /* REVISIT what to do with Carkit and I2C events ? */
2643         default:
2644                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2645         }
2646 }
2647
2648 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2649 {
2650         struct dwc3 *dwc = evt->dwc;
2651         irqreturn_t ret = IRQ_NONE;
2652         int left;
2653         u32 reg;
2654
2655         left = evt->count;
2656
2657         if (!(evt->flags & DWC3_EVENT_PENDING))
2658                 return IRQ_NONE;
2659
2660         while (left > 0) {
2661                 union dwc3_event event;
2662
2663                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2664
2665                 dwc3_process_event_entry(dwc, &event);
2666
2667                 /*
2668                  * FIXME we wrap around correctly to the next entry as
2669                  * almost all entries are 4 bytes in size. There is one
2670                  * entry which has 12 bytes which is a regular entry
2671                  * followed by 8 bytes data. ATM I don't know how
2672                  * things are organized if we get next to the a
2673                  * boundary so I worry about that once we try to handle
2674                  * that.
2675                  */
2676                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2677                 left -= 4;
2678
2679                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2680         }
2681
2682         evt->count = 0;
2683         evt->flags &= ~DWC3_EVENT_PENDING;
2684         ret = IRQ_HANDLED;
2685
2686         /* Unmask interrupt */
2687         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2688         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2689         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2690
2691         return ret;
2692 }
2693
2694 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2695 {
2696         struct dwc3_event_buffer *evt = _evt;
2697         struct dwc3 *dwc = evt->dwc;
2698         unsigned long flags;
2699         irqreturn_t ret = IRQ_NONE;
2700
2701         spin_lock_irqsave(&dwc->lock, flags);
2702         ret = dwc3_process_event_buf(evt);
2703         spin_unlock_irqrestore(&dwc->lock, flags);
2704
2705         return ret;
2706 }
2707
2708 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2709 {
2710         struct dwc3 *dwc = evt->dwc;
2711         u32 count;
2712         u32 reg;
2713
2714         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2715         count &= DWC3_GEVNTCOUNT_MASK;
2716         if (!count)
2717                 return IRQ_NONE;
2718
2719         evt->count = count;
2720         evt->flags |= DWC3_EVENT_PENDING;
2721
2722         /* Mask interrupt */
2723         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2724         reg |= DWC3_GEVNTSIZ_INTMASK;
2725         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2726
2727         return IRQ_WAKE_THREAD;
2728 }
2729
2730 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2731 {
2732         struct dwc3_event_buffer        *evt = _evt;
2733
2734         return dwc3_check_event_buf(evt);
2735 }
2736
2737 /**
2738  * dwc3_gadget_init - Initializes gadget related registers
2739  * @dwc: pointer to our controller context structure
2740  *
2741  * Returns 0 on success otherwise negative errno.
2742  */
2743 int dwc3_gadget_init(struct dwc3 *dwc)
2744 {
2745         int                                     ret;
2746
2747         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2748                         &dwc->ctrl_req_addr, GFP_KERNEL);
2749         if (!dwc->ctrl_req) {
2750                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2751                 ret = -ENOMEM;
2752                 goto err0;
2753         }
2754
2755         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2756                         &dwc->ep0_trb_addr, GFP_KERNEL);
2757         if (!dwc->ep0_trb) {
2758                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2759                 ret = -ENOMEM;
2760                 goto err1;
2761         }
2762
2763         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2764         if (!dwc->setup_buf) {
2765                 ret = -ENOMEM;
2766                 goto err2;
2767         }
2768
2769         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2770                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2771                         GFP_KERNEL);
2772         if (!dwc->ep0_bounce) {
2773                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2774                 ret = -ENOMEM;
2775                 goto err3;
2776         }
2777
2778         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2779         if (!dwc->zlp_buf) {
2780                 ret = -ENOMEM;
2781                 goto err4;
2782         }
2783
2784         dwc->gadget.ops                 = &dwc3_gadget_ops;
2785         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2786         dwc->gadget.sg_supported        = true;
2787         dwc->gadget.name                = "dwc3-gadget";
2788         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2789
2790         /*
2791          * FIXME We might be setting max_speed to <SUPER, however versions
2792          * <2.20a of dwc3 have an issue with metastability (documented
2793          * elsewhere in this driver) which tells us we can't set max speed to
2794          * anything lower than SUPER.
2795          *
2796          * Because gadget.max_speed is only used by composite.c and function
2797          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2798          * to happen so we avoid sending SuperSpeed Capability descriptor
2799          * together with our BOS descriptor as that could confuse host into
2800          * thinking we can handle super speed.
2801          *
2802          * Note that, in fact, we won't even support GetBOS requests when speed
2803          * is less than super speed because we don't have means, yet, to tell
2804          * composite.c that we are USB 2.0 + LPM ECN.
2805          */
2806         if (dwc->revision < DWC3_REVISION_220A)
2807                 dwc3_trace(trace_dwc3_gadget,
2808                                 "Changing max_speed on rev %08x\n",
2809                                 dwc->revision);
2810
2811         dwc->gadget.max_speed           = dwc->maximum_speed;
2812
2813         /*
2814          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2815          * on ep out.
2816          */
2817         dwc->gadget.quirk_ep_out_aligned_size = true;
2818
2819         /*
2820          * REVISIT: Here we should clear all pending IRQs to be
2821          * sure we're starting from a well known location.
2822          */
2823
2824         ret = dwc3_gadget_init_endpoints(dwc);
2825         if (ret)
2826                 goto err5;
2827
2828         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2829         if (ret) {
2830                 dev_err(dwc->dev, "failed to register udc\n");
2831                 goto err5;
2832         }
2833
2834         return 0;
2835
2836 err5:
2837         kfree(dwc->zlp_buf);
2838
2839 err4:
2840         dwc3_gadget_free_endpoints(dwc);
2841         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2842                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2843
2844 err3:
2845         kfree(dwc->setup_buf);
2846
2847 err2:
2848         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2849                         dwc->ep0_trb, dwc->ep0_trb_addr);
2850
2851 err1:
2852         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2853                         dwc->ctrl_req, dwc->ctrl_req_addr);
2854
2855 err0:
2856         return ret;
2857 }
2858
2859 /* -------------------------------------------------------------------------- */
2860
2861 void dwc3_gadget_exit(struct dwc3 *dwc)
2862 {
2863         usb_del_gadget_udc(&dwc->gadget);
2864
2865         dwc3_gadget_free_endpoints(dwc);
2866
2867         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2868                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2869
2870         kfree(dwc->setup_buf);
2871         kfree(dwc->zlp_buf);
2872
2873         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2874                         dwc->ep0_trb, dwc->ep0_trb_addr);
2875
2876         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2877                         dwc->ctrl_req, dwc->ctrl_req_addr);
2878 }
2879
2880 int dwc3_gadget_suspend(struct dwc3 *dwc)
2881 {
2882         if (!dwc->gadget_driver)
2883                 return 0;
2884
2885         if (dwc->pullups_connected) {
2886                 dwc3_gadget_disable_irq(dwc);
2887                 dwc3_gadget_run_stop(dwc, true, true);
2888         }
2889
2890         __dwc3_gadget_ep_disable(dwc->eps[0]);
2891         __dwc3_gadget_ep_disable(dwc->eps[1]);
2892
2893         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2894
2895         return 0;
2896 }
2897
2898 int dwc3_gadget_resume(struct dwc3 *dwc)
2899 {
2900         struct dwc3_ep          *dep;
2901         int                     ret;
2902
2903         if (!dwc->gadget_driver)
2904                 return 0;
2905
2906         /* Start with SuperSpeed Default */
2907         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2908
2909         dep = dwc->eps[0];
2910         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2911                         false);
2912         if (ret)
2913                 goto err0;
2914
2915         dep = dwc->eps[1];
2916         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2917                         false);
2918         if (ret)
2919                 goto err1;
2920
2921         /* begin to receive SETUP packets */
2922         dwc->ep0state = EP0_SETUP_PHASE;
2923         dwc3_ep0_out_start(dwc);
2924
2925         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2926
2927         if (dwc->pullups_connected) {
2928                 dwc3_gadget_enable_irq(dwc);
2929                 dwc3_gadget_run_stop(dwc, true, false);
2930         }
2931
2932         return 0;
2933
2934 err1:
2935         __dwc3_gadget_ep_disable(dwc->eps[0]);
2936
2937 err0:
2938         return ret;
2939 }