drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 149 {
 150         dep->trb_enqueue++;
 151         dep->trb_enqueue %= DWC3_TRB_NUM;
 152 }
 153
 154 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 155 {
 156         dep->trb_dequeue++;
 157         dep->trb_dequeue %= DWC3_TRB_NUM;
 158 }
 159
 160 static int dwc3_ep_is_last_trb(unsigned int index)
 161 {
 162         return index == DWC3_TRB_NUM - 1;
 163 }
 164
 165 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 166                 int status)
 167 {
 168         struct dwc3                     *dwc = dep->dwc;
 169         int                             i;
 170
 171         if (req->started) {
 172                 i = 0;
 173                 do {
 174                         dwc3_ep_inc_deq(dep);
 175                         /*
 176                          * Skip LINK TRB. We can't use req->trb and check for
 177                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 178                          * just completed (not the LINK TRB).
 179                          */
 180                         if (dwc3_ep_is_last_trb(dep->trb_dequeue))
 181                                 dwc3_ep_inc_deq(dep);
 182                 } while(++i < req->request.num_mapped_sgs);
 183                 req->started = false;
 184         }
 185         list_del(&req->list);
 186         req->trb = NULL;
 187
 188         if (req->request.status == -EINPROGRESS)
 189                 req->request.status = status;
 190
 191         if (dwc->ep0_bounced && dep->number == 0)
 192                 dwc->ep0_bounced = false;
 193         else
 194                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 195                                 req->direction);
 196
 197         trace_dwc3_gadget_giveback(req);
 198
 199         spin_unlock(&dwc->lock);
 200         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 201         spin_lock(&dwc->lock);
 202 }
 203
 204 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 205 {
 206         u32             timeout = 500;
 207         u32             reg;
 208
 209         trace_dwc3_gadget_generic_cmd(cmd, param);
 210
 211         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 212         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 213
 214         do {
 215                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 216                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 217                         dwc3_trace(trace_dwc3_gadget,
 218                                         "Command Complete --> %d",
 219                                         DWC3_DGCMD_STATUS(reg));
 220                         if (DWC3_DGCMD_STATUS(reg))
 221                                 return -EINVAL;
 222                         return 0;
 223                 }
 224
 225                 /*
 226                  * We can't sleep here, because it's also called from
 227                  * interrupt context.
 228                  */
 229                 timeout--;
 230                 if (!timeout) {
 231                         dwc3_trace(trace_dwc3_gadget,
 232                                         "Command Timed Out");
 233                         return -ETIMEDOUT;
 234                 }
 235                 udelay(1);
 236         } while (1);
 237 }
 238
 239 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 240
 241 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 242                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 243 {
 244         struct dwc3_ep          *dep = dwc->eps[ep];
 245         u32                     timeout = 500;
 246         u32                     reg;
 247
 248         int                     susphy = false;
 249         int                     ret = -EINVAL;
 250
 251         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 252
 253         /*
 254          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 255          * we're issuing an endpoint command, we must check if
 256          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 257          *
 258          * We will also set SUSPHY bit to what it was before returning as stated
 259          * by the same section on Synopsys databook.
 260          */
 261         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 262         if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 263                 susphy = true;
 264                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 265                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 266         }
 267
 268         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 269                 int             needs_wakeup;
 270
 271                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 272                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 273                                 dwc->link_state == DWC3_LINK_STATE_U3);
 274
 275                 if (unlikely(needs_wakeup)) {
 276                         ret = __dwc3_gadget_wakeup(dwc);
 277                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 278                                         ret);
 279                 }
 280         }
 281
 282         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 283         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 284         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 285
 286         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 287         do {
 288                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 289                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 290                         int cmd_status = DWC3_DEPCMD_STATUS(reg);
 291
 292                         dwc3_trace(trace_dwc3_gadget,
 293                                         "Command Complete --> %d",
 294                                         cmd_status);
 295
 296                         switch (cmd_status) {
 297                         case 0:
 298                                 ret = 0;
 299                                 break;
 300                         case DEPEVT_TRANSFER_NO_RESOURCE:
 301                                 dwc3_trace(trace_dwc3_gadget, "%s: no resource available");
 302                                 ret = -EINVAL;
 303                                 break;
 304                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 305                                 /*
 306                                  * SW issues START TRANSFER command to
 307                                  * isochronous ep with future frame interval. If
 308                                  * future interval time has already passed when
 309                                  * core receives the command, it will respond
 310                                  * with an error status of 'Bus Expiry'.
 311                                  *
 312                                  * Instead of always returning -EINVAL, let's
 313                                  * give a hint to the gadget driver that this is
 314                                  * the case by returning -EAGAIN.
 315                                  */
 316                                 dwc3_trace(trace_dwc3_gadget, "%s: bus expiry");
 317                                 ret = -EAGAIN;
 318                                 break;
 319                         default:
 320                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 321                         }
 322
 323                         break;
 324                 }
 325
 326                 /*
 327                  * We can't sleep here, because it is also called from
 328                  * interrupt context.
 329                  */
 330                 timeout--;
 331                 if (!timeout) {
 332                         dwc3_trace(trace_dwc3_gadget,
 333                                         "Command Timed Out");
 334                         ret = -ETIMEDOUT;
 335                         break;
 336                 }
 337
 338                 udelay(1);
 339         } while (1);
 340
 341         if (unlikely(susphy)) {
 342                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 343                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 344                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 345         }
 346
 347         return ret;
 348 }
 349
 350 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 351 {
 352         struct dwc3 *dwc = dep->dwc;
 353         struct dwc3_gadget_ep_cmd_params params;
 354         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 355
 356         /*
 357          * As of core revision 2.60a the recommended programming model
 358          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 359          * command for IN endpoints. This is to prevent an issue where
 360          * some (non-compliant) hosts may not send ACK TPs for pending
 361          * IN transfers due to a mishandled error condition. Synopsys
 362          * STAR 9000614252.
 363          */
 364         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
 365                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 366
 367         memset(&params, 0, sizeof(params));
 368
 369         return dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 370 }
 371
 372 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 373                 struct dwc3_trb *trb)
 374 {
 375         u32             offset = (char *) trb - (char *) dep->trb_pool;
 376
 377         return dep->trb_pool_dma + offset;
 378 }
 379
 380 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 381 {
 382         struct dwc3             *dwc = dep->dwc;
 383
 384         if (dep->trb_pool)
 385                 return 0;
 386
 387         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 388                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 389                         &dep->trb_pool_dma, GFP_KERNEL);
 390         if (!dep->trb_pool) {
 391                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 392                                 dep->name);
 393                 return -ENOMEM;
 394         }
 395
 396         return 0;
 397 }
 398
 399 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 400 {
 401         struct dwc3             *dwc = dep->dwc;
 402
 403         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 404                         dep->trb_pool, dep->trb_pool_dma);
 405
 406         dep->trb_pool = NULL;
 407         dep->trb_pool_dma = 0;
 408 }
 409
 410 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 411
 412 /**
 413  * dwc3_gadget_start_config - Configure EP resources
 414  * @dwc: pointer to our controller context structure
 415  * @dep: endpoint that is being enabled
 416  *
 417  * The assignment of transfer resources cannot perfectly follow the
 418  * data book due to the fact that the controller driver does not have
 419  * all knowledge of the configuration in advance. It is given this
 420  * information piecemeal by the composite gadget framework after every
 421  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 422  * programming model in this scenario can cause errors. For two
 423  * reasons:
 424  *
 425  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 426  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 427  * multiple interfaces.
 428  *
 429  * 2) The databook does not mention doing more DEPXFERCFG for new
 430  * endpoint on alt setting (8.1.6).
 431  *
 432  * The following simplified method is used instead:
 433  *
 434  * All hardware endpoints can be assigned a transfer resource and this
 435  * setting will stay persistent until either a core reset or
 436  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 437  * do DEPXFERCFG for every hardware endpoint as well. We are
 438  * guaranteed that there are as many transfer resources as endpoints.
 439  *
 440  * This function is called for each endpoint when it is being enabled
 441  * but is triggered only when called for EP0-out, which always happens
 442  * first, and which should only happen in one of the above conditions.
 443  */
 444 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 445 {
 446         struct dwc3_gadget_ep_cmd_params params;
 447         u32                     cmd;
 448         int                     i;
 449         int                     ret;
 450
 451         if (dep->number)
 452                 return 0;
 453
 454         memset(&params, 0x00, sizeof(params));
 455         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 456
 457         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 458         if (ret)
 459                 return ret;
 460
 461         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 462                 struct dwc3_ep *dep = dwc->eps[i];
 463
 464                 if (!dep)
 465                         continue;
 466
 467                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 468                 if (ret)
 469                         return ret;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 476                 const struct usb_endpoint_descriptor *desc,
 477                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 478                 bool ignore, bool restore)
 479 {
 480         struct dwc3_gadget_ep_cmd_params params;
 481
 482         memset(&params, 0x00, sizeof(params));
 483
 484         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 485                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 486
 487         /* Burst size is only needed in SuperSpeed mode */
 488         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 489                 u32 burst = dep->endpoint.maxburst;
 490                 u32 nump;
 491                 u32 reg;
 492
 493                 /* update NumP */
 494                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 495                 nump = DWC3_DCFG_NUMP(reg);
 496                 nump = max(nump, burst);
 497                 reg &= ~DWC3_DCFG_NUMP_MASK;
 498                 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
 499                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 500
 501                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 502         }
 503
 504         if (ignore)
 505                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 506
 507         if (restore) {
 508                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 509                 params.param2 |= dep->saved_state;
 510         }
 511
 512         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 513                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 514
 515         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 516                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 517                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 518                 dep->stream_capable = true;
 519         }
 520
 521         if (!usb_endpoint_xfer_control(desc))
 522                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 523
 524         /*
 525          * We are doing 1:1 mapping for endpoints, meaning
 526          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 527          * so on. We consider the direction bit as part of the physical
 528          * endpoint number. So USB endpoint 0x81 is 0x03.
 529          */
 530         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 531
 532         /*
 533          * We must use the lower 16 TX FIFOs even though
 534          * HW might have more
 535          */
 536         if (dep->direction)
 537                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 538
 539         if (desc->bInterval) {
 540                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 541                 dep->interval = 1 << (desc->bInterval - 1);
 542         }
 543
 544         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 545                         DWC3_DEPCMD_SETEPCONFIG, &params);
 546 }
 547
 548 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 549 {
 550         struct dwc3_gadget_ep_cmd_params params;
 551
 552         memset(&params, 0x00, sizeof(params));
 553
 554         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 555
 556         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 557                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 558 }
 559
 560 /**
 561  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 562  * @dep: endpoint to be initialized
 563  * @desc: USB Endpoint Descriptor
 564  *
 565  * Caller should take care of locking
 566  */
 567 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 568                 const struct usb_endpoint_descriptor *desc,
 569                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 570                 bool ignore, bool restore)
 571 {
 572         struct dwc3             *dwc = dep->dwc;
 573         u32                     reg;
 574         int                     ret;
 575
 576         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 577
 578         if (!(dep->flags & DWC3_EP_ENABLED)) {
 579                 ret = dwc3_gadget_start_config(dwc, dep);
 580                 if (ret)
 581                         return ret;
 582         }
 583
 584         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 585                         restore);
 586         if (ret)
 587                 return ret;
 588
 589         if (!(dep->flags & DWC3_EP_ENABLED)) {
 590                 struct dwc3_trb *trb_st_hw;
 591                 struct dwc3_trb *trb_link;
 592
 593                 dep->endpoint.desc = desc;
 594                 dep->comp_desc = comp_desc;
 595                 dep->type = usb_endpoint_type(desc);
 596                 dep->flags |= DWC3_EP_ENABLED;
 597
 598                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 599                 reg |= DWC3_DALEPENA_EP(dep->number);
 600                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 601
 602                 if (usb_endpoint_xfer_control(desc))
 603                         goto out;
 604
 605                 /* Link TRB. The HWO bit is never reset */
 606                 trb_st_hw = &dep->trb_pool[0];
 607
 608                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 609                 memset(trb_link, 0, sizeof(*trb_link));
 610
 611                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 612                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 613                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 614                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 615         }
 616
 617 out:
 618         switch (usb_endpoint_type(desc)) {
 619         case USB_ENDPOINT_XFER_CONTROL:
 620                 /* don't change name */
 621                 break;
 622         case USB_ENDPOINT_XFER_ISOC:
 623                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 624                 break;
 625         case USB_ENDPOINT_XFER_BULK:
 626                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 627                 break;
 628         case USB_ENDPOINT_XFER_INT:
 629                 strlcat(dep->name, "-int", sizeof(dep->name));
 630                 break;
 631         default:
 632                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 633         }
 634
 635         return 0;
 636 }
 637
 638 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 639 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 640 {
 641         struct dwc3_request             *req;
 642
 643         if (!list_empty(&dep->started_list)) {
 644                 dwc3_stop_active_transfer(dwc, dep->number, true);
 645
 646                 /* - giveback all requests to gadget driver */
 647                 while (!list_empty(&dep->started_list)) {
 648                         req = next_request(&dep->started_list);
 649
 650                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 651                 }
 652         }
 653
 654         while (!list_empty(&dep->pending_list)) {
 655                 req = next_request(&dep->pending_list);
 656
 657                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 658         }
 659 }
 660
 661 /**
 662  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 663  * @dep: the endpoint to disable
 664  *
 665  * This function also removes requests which are currently processed ny the
 666  * hardware and those which are not yet scheduled.
 667  * Caller should take care of locking.
 668  */
 669 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 670 {
 671         struct dwc3             *dwc = dep->dwc;
 672         u32                     reg;
 673
 674         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 675
 676         dwc3_remove_requests(dwc, dep);
 677
 678         /* make sure HW endpoint isn't stalled */
 679         if (dep->flags & DWC3_EP_STALL)
 680                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 681
 682         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 683         reg &= ~DWC3_DALEPENA_EP(dep->number);
 684         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 685
 686         dep->stream_capable = false;
 687         dep->endpoint.desc = NULL;
 688         dep->comp_desc = NULL;
 689         dep->type = 0;
 690         dep->flags = 0;
 691
 692         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 693                         dep->number >> 1,
 694                         (dep->number & 1) ? "in" : "out");
 695
 696         return 0;
 697 }
 698
 699 /* -------------------------------------------------------------------------- */
 700
 701 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 702                 const struct usb_endpoint_descriptor *desc)
 703 {
 704         return -EINVAL;
 705 }
 706
 707 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 708 {
 709         return -EINVAL;
 710 }
 711
 712 /* -------------------------------------------------------------------------- */
 713
 714 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 715                 const struct usb_endpoint_descriptor *desc)
 716 {
 717         struct dwc3_ep                  *dep;
 718         struct dwc3                     *dwc;
 719         unsigned long                   flags;
 720         int                             ret;
 721
 722         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 723                 pr_debug("dwc3: invalid parameters\n");
 724                 return -EINVAL;
 725         }
 726
 727         if (!desc->wMaxPacketSize) {
 728                 pr_debug("dwc3: missing wMaxPacketSize\n");
 729                 return -EINVAL;
 730         }
 731
 732         dep = to_dwc3_ep(ep);
 733         dwc = dep->dwc;
 734
 735         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 736                                         "%s is already enabled\n",
 737                                         dep->name))
 738                 return 0;
 739
 740         spin_lock_irqsave(&dwc->lock, flags);
 741         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 742         spin_unlock_irqrestore(&dwc->lock, flags);
 743
 744         return ret;
 745 }
 746
 747 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 748 {
 749         struct dwc3_ep                  *dep;
 750         struct dwc3                     *dwc;
 751         unsigned long                   flags;
 752         int                             ret;
 753
 754         if (!ep) {
 755                 pr_debug("dwc3: invalid parameters\n");
 756                 return -EINVAL;
 757         }
 758
 759         dep = to_dwc3_ep(ep);
 760         dwc = dep->dwc;
 761
 762         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 763                                         "%s is already disabled\n",
 764                                         dep->name))
 765                 return 0;
 766
 767         spin_lock_irqsave(&dwc->lock, flags);
 768         ret = __dwc3_gadget_ep_disable(dep);
 769         spin_unlock_irqrestore(&dwc->lock, flags);
 770
 771         return ret;
 772 }
 773
 774 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 775         gfp_t gfp_flags)
 776 {
 777         struct dwc3_request             *req;
 778         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 779
 780         req = kzalloc(sizeof(*req), gfp_flags);
 781         if (!req)
 782                 return NULL;
 783
 784         req->epnum      = dep->number;
 785         req->dep        = dep;
 786
 787         trace_dwc3_alloc_request(req);
 788
 789         return &req->request;
 790 }
 791
 792 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 793                 struct usb_request *request)
 794 {
 795         struct dwc3_request             *req = to_dwc3_request(request);
 796
 797         trace_dwc3_free_request(req);
 798         kfree(req);
 799 }
 800
 801 /**
 802  * dwc3_prepare_one_trb - setup one TRB from one request
 803  * @dep: endpoint for which this request is prepared
 804  * @req: dwc3_request pointer
 805  */
 806 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 807                 struct dwc3_request *req, dma_addr_t dma,
 808                 unsigned length, unsigned last, unsigned chain, unsigned node)
 809 {
 810         struct dwc3_trb         *trb;
 811
 812         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 813                         dep->name, req, (unsigned long long) dma,
 814                         length, last ? " last" : "",
 815                         chain ? " chain" : "");
 816
 817
 818         trb = &dep->trb_pool[dep->trb_enqueue];
 819
 820         if (!req->trb) {
 821                 dwc3_gadget_move_started_request(req);
 822                 req->trb = trb;
 823                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 824                 req->first_trb_index = dep->trb_enqueue;
 825         }
 826
 827         dwc3_ep_inc_enq(dep);
 828         /* Skip the LINK-TRB */
 829         if (dwc3_ep_is_last_trb(dep->trb_enqueue))
 830                 dwc3_ep_inc_enq(dep);
 831
 832         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 833         trb->bpl = lower_32_bits(dma);
 834         trb->bph = upper_32_bits(dma);
 835
 836         switch (usb_endpoint_type(dep->endpoint.desc)) {
 837         case USB_ENDPOINT_XFER_CONTROL:
 838                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 839                 break;
 840
 841         case USB_ENDPOINT_XFER_ISOC:
 842                 if (!node)
 843                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 844                 else
 845                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 846
 847                 /* always enable Interrupt on Missed ISOC */
 848                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 849                 break;
 850
 851         case USB_ENDPOINT_XFER_BULK:
 852         case USB_ENDPOINT_XFER_INT:
 853                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 854                 break;
 855         default:
 856                 /*
 857                  * This is only possible with faulty memory because we
 858                  * checked it already :)
 859                  */
 860                 BUG();
 861         }
 862
 863         /* always enable Continue on Short Packet */
 864         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 865
 866         if (!req->request.no_interrupt && !chain)
 867                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 868
 869         if (last)
 870                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 871
 872         if (chain)
 873                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 874
 875         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 876                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 877
 878         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 879
 880         trace_dwc3_prepare_trb(dep, trb);
 881 }
 882
 883 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 884 {
 885         struct dwc3_trb         *tmp;
 886
 887         /*
 888          * If enqueue & dequeue are equal than it is either full or empty.
 889          *
 890          * One way to know for sure is if the TRB right before us has HWO bit
 891          * set or not. If it has, then we're definitely full and can't fit any
 892          * more transfers in our ring.
 893          */
 894         if (dep->trb_enqueue == dep->trb_dequeue) {
 895                 /* If we're full, enqueue/dequeue are > 0 */
 896                 if (dep->trb_enqueue) {
 897                         tmp = &dep->trb_pool[dep->trb_enqueue - 1];
 898                         if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 899                                 return 0;
 900                 }
 901
 902                 return DWC3_TRB_NUM - 1;
 903         }
 904
 905         return dep->trb_dequeue - dep->trb_enqueue;
 906 }
 907
 908 /*
 909  * dwc3_prepare_trbs - setup TRBs from requests
 910  * @dep: endpoint for which requests are being prepared
 911  *
 912  * The function goes through the requests list and sets up TRBs for the
 913  * transfers. The function returns once there are no more TRBs available or
 914  * it runs out of requests.
 915  */
 916 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
 917 {
 918         struct dwc3_request     *req, *n;
 919         u32                     trbs_left;
 920         unsigned int            last_one = 0;
 921
 922         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 923
 924         trbs_left = dwc3_calc_trbs_left(dep);
 925
 926         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 927                 unsigned        length;
 928                 dma_addr_t      dma;
 929                 last_one = false;
 930
 931                 if (req->request.num_mapped_sgs > 0) {
 932                         struct usb_request *request = &req->request;
 933                         struct scatterlist *sg = request->sg;
 934                         struct scatterlist *s;
 935                         int             i;
 936
 937                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 938                                 unsigned chain = true;
 939
 940                                 length = sg_dma_len(s);
 941                                 dma = sg_dma_address(s);
 942
 943                                 if (i == (request->num_mapped_sgs - 1) ||
 944                                                 sg_is_last(s)) {
 945                                         if (list_empty(&dep->pending_list))
 946                                                 last_one = true;
 947                                         chain = false;
 948                                 }
 949
 950                                 trbs_left--;
 951                                 if (!trbs_left)
 952                                         last_one = true;
 953
 954                                 if (last_one)
 955                                         chain = false;
 956
 957                                 dwc3_prepare_one_trb(dep, req, dma, length,
 958                                                 last_one, chain, i);
 959
 960                                 if (last_one)
 961                                         break;
 962                         }
 963
 964                         if (last_one)
 965                                 break;
 966                 } else {
 967                         dma = req->request.dma;
 968                         length = req->request.length;
 969                         trbs_left--;
 970
 971                         if (!trbs_left)
 972                                 last_one = 1;
 973
 974                         /* Is this the last request? */
 975                         if (list_is_last(&req->list, &dep->pending_list))
 976                                 last_one = 1;
 977
 978                         dwc3_prepare_one_trb(dep, req, dma, length,
 979                                         last_one, false, 0);
 980
 981                         if (last_one)
 982                                 break;
 983                 }
 984         }
 985 }
 986
 987 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
 988 {
 989         struct dwc3_gadget_ep_cmd_params params;
 990         struct dwc3_request             *req;
 991         struct dwc3                     *dwc = dep->dwc;
 992         int                             starting;
 993         int                             ret;
 994         u32                             cmd;
 995
 996         starting = !(dep->flags & DWC3_EP_BUSY);
 997
 998         dwc3_prepare_trbs(dep);
 999         req = next_request(&dep->started_list);
1000         if (!req) {
1001                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1002                 return 0;
1003         }
1004
1005         memset(&params, 0, sizeof(params));
1006
1007         if (starting) {
1008                 params.param0 = upper_32_bits(req->trb_dma);
1009                 params.param1 = lower_32_bits(req->trb_dma);
1010                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1011         } else {
1012                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1013         }
1014
1015         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1016         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1017         if (ret < 0) {
1018                 /*
1019                  * FIXME we need to iterate over the list of requests
1020                  * here and stop, unmap, free and del each of the linked
1021                  * requests instead of what we do now.
1022                  */
1023                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1024                                 req->direction);
1025                 list_del(&req->list);
1026                 return ret;
1027         }
1028
1029         dep->flags |= DWC3_EP_BUSY;
1030
1031         if (starting) {
1032                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1033                                 dep->number);
1034                 WARN_ON_ONCE(!dep->resource_index);
1035         }
1036
1037         return 0;
1038 }
1039
1040 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1041                 struct dwc3_ep *dep, u32 cur_uf)
1042 {
1043         u32 uf;
1044
1045         if (list_empty(&dep->pending_list)) {
1046                 dwc3_trace(trace_dwc3_gadget,
1047                                 "ISOC ep %s run out for requests",
1048                                 dep->name);
1049                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1050                 return;
1051         }
1052
1053         /* 4 micro frames in the future */
1054         uf = cur_uf + dep->interval * 4;
1055
1056         __dwc3_gadget_kick_transfer(dep, uf);
1057 }
1058
1059 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1060                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1061 {
1062         u32 cur_uf, mask;
1063
1064         mask = ~(dep->interval - 1);
1065         cur_uf = event->parameters & mask;
1066
1067         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1068 }
1069
1070 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1071 {
1072         struct dwc3             *dwc = dep->dwc;
1073         int                     ret;
1074
1075         if (!dep->endpoint.desc) {
1076                 dwc3_trace(trace_dwc3_gadget,
1077                                 "trying to queue request %p to disabled %s\n",
1078                                 &req->request, dep->endpoint.name);
1079                 return -ESHUTDOWN;
1080         }
1081
1082         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1083                                 &req->request, req->dep->name)) {
1084                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1085                                 &req->request, req->dep->name);
1086                 return -EINVAL;
1087         }
1088
1089         req->request.actual     = 0;
1090         req->request.status     = -EINPROGRESS;
1091         req->direction          = dep->direction;
1092         req->epnum              = dep->number;
1093
1094         trace_dwc3_ep_queue(req);
1095
1096         /*
1097          * Per databook, the total size of buffer must be a multiple
1098          * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1099          * configed for endpoints in dwc3_gadget_set_ep_config(),
1100          * set to usb_endpoint_descriptor->wMaxPacketSize.
1101          */
1102         if (dep->direction == 0 &&
1103             req->request.length % dep->endpoint.desc->wMaxPacketSize)
1104                 req->request.length = roundup(req->request.length,
1105                                         dep->endpoint.desc->wMaxPacketSize);
1106
1107         /*
1108          * We only add to our list of requests now and
1109          * start consuming the list once we get XferNotReady
1110          * IRQ.
1111          *
1112          * That way, we avoid doing anything that we don't need
1113          * to do now and defer it until the point we receive a
1114          * particular token from the Host side.
1115          *
1116          * This will also avoid Host cancelling URBs due to too
1117          * many NAKs.
1118          */
1119         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1120                         dep->direction);
1121         if (ret)
1122                 return ret;
1123
1124         list_add_tail(&req->list, &dep->pending_list);
1125
1126         /*
1127          * If there are no pending requests and the endpoint isn't already
1128          * busy, we will just start the request straight away.
1129          *
1130          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1131          * little bit faster.
1132          */
1133         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1134                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1135                         !(dep->flags & DWC3_EP_BUSY)) {
1136                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1137                 goto out;
1138         }
1139
1140         /*
1141          * There are a few special cases:
1142          *
1143          * 1. XferNotReady with empty list of requests. We need to kick the
1144          *    transfer here in that situation, otherwise we will be NAKing
1145          *    forever. If we get XferNotReady before gadget driver has a
1146          *    chance to queue a request, we will ACK the IRQ but won't be
1147          *    able to receive the data until the next request is queued.
1148          *    The following code is handling exactly that.
1149          *
1150          */
1151         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1152                 /*
1153                  * If xfernotready is already elapsed and it is a case
1154                  * of isoc transfer, then issue END TRANSFER, so that
1155                  * you can receive xfernotready again and can have
1156                  * notion of current microframe.
1157                  */
1158                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1159                         if (list_empty(&dep->started_list)) {
1160                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1161                                 dep->flags = DWC3_EP_ENABLED;
1162                         }
1163                         return 0;
1164                 }
1165
1166                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1167                 if (!ret)
1168                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1169
1170                 goto out;
1171         }
1172
1173         /*
1174          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1175          *    kick the transfer here after queuing a request, otherwise the
1176          *    core may not see the modified TRB(s).
1177          */
1178         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1179                         (dep->flags & DWC3_EP_BUSY) &&
1180                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1181                 WARN_ON_ONCE(!dep->resource_index);
1182                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1183                 goto out;
1184         }
1185
1186         /*
1187          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1188          * right away, otherwise host will not know we have streams to be
1189          * handled.
1190          */
1191         if (dep->stream_capable)
1192                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1193
1194 out:
1195         if (ret && ret != -EBUSY)
1196                 dwc3_trace(trace_dwc3_gadget,
1197                                 "%s: failed to kick transfers\n",
1198                                 dep->name);
1199         if (ret == -EBUSY)
1200                 ret = 0;
1201
1202         return ret;
1203 }
1204
1205 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1206                 struct usb_request *request)
1207 {
1208         dwc3_gadget_ep_free_request(ep, request);
1209 }
1210
1211 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1212 {
1213         struct dwc3_request             *req;
1214         struct usb_request              *request;
1215         struct usb_ep                   *ep = &dep->endpoint;
1216
1217         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1218         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1219         if (!request)
1220                 return -ENOMEM;
1221
1222         request->length = 0;
1223         request->buf = dwc->zlp_buf;
1224         request->complete = __dwc3_gadget_ep_zlp_complete;
1225
1226         req = to_dwc3_request(request);
1227
1228         return __dwc3_gadget_ep_queue(dep, req);
1229 }
1230
1231 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1232         gfp_t gfp_flags)
1233 {
1234         struct dwc3_request             *req = to_dwc3_request(request);
1235         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1236         struct dwc3                     *dwc = dep->dwc;
1237
1238         unsigned long                   flags;
1239
1240         int                             ret;
1241
1242         spin_lock_irqsave(&dwc->lock, flags);
1243         ret = __dwc3_gadget_ep_queue(dep, req);
1244
1245         /*
1246          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1247          * setting request->zero, instead of doing magic, we will just queue an
1248          * extra usb_request ourselves so that it gets handled the same way as
1249          * any other request.
1250          */
1251         if (ret == 0 && request->zero && request->length &&
1252             (request->length % ep->desc->wMaxPacketSize == 0))
1253                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1254
1255         spin_unlock_irqrestore(&dwc->lock, flags);
1256
1257         return ret;
1258 }
1259
1260 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1261                 struct usb_request *request)
1262 {
1263         struct dwc3_request             *req = to_dwc3_request(request);
1264         struct dwc3_request             *r = NULL;
1265
1266         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1267         struct dwc3                     *dwc = dep->dwc;
1268
1269         unsigned long                   flags;
1270         int                             ret = 0;
1271
1272         trace_dwc3_ep_dequeue(req);
1273
1274         spin_lock_irqsave(&dwc->lock, flags);
1275
1276         list_for_each_entry(r, &dep->pending_list, list) {
1277                 if (r == req)
1278                         break;
1279         }
1280
1281         if (r != req) {
1282                 list_for_each_entry(r, &dep->started_list, list) {
1283                         if (r == req)
1284                                 break;
1285                 }
1286                 if (r == req) {
1287                         /* wait until it is processed */
1288                         dwc3_stop_active_transfer(dwc, dep->number, true);
1289                         goto out1;
1290                 }
1291                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1292                                 request, ep->name);
1293                 ret = -EINVAL;
1294                 goto out0;
1295         }
1296
1297 out1:
1298         /* giveback the request */
1299         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1300
1301 out0:
1302         spin_unlock_irqrestore(&dwc->lock, flags);
1303
1304         return ret;
1305 }
1306
1307 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1308 {
1309         struct dwc3_gadget_ep_cmd_params        params;
1310         struct dwc3                             *dwc = dep->dwc;
1311         int                                     ret;
1312
1313         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1314                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1315                 return -EINVAL;
1316         }
1317
1318         memset(&params, 0x00, sizeof(params));
1319
1320         if (value) {
1321                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1322                                 (!list_empty(&dep->started_list) ||
1323                                  !list_empty(&dep->pending_list)))) {
1324                         dwc3_trace(trace_dwc3_gadget,
1325                                         "%s: pending request, cannot halt",
1326                                         dep->name);
1327                         return -EAGAIN;
1328                 }
1329
1330                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1331                         DWC3_DEPCMD_SETSTALL, &params);
1332                 if (ret)
1333                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1334                                         dep->name);
1335                 else
1336                         dep->flags |= DWC3_EP_STALL;
1337         } else {
1338                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1339                 if (ret)
1340                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1341                                         dep->name);
1342                 else
1343                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1344         }
1345
1346         return ret;
1347 }
1348
1349 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1350 {
1351         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1352         struct dwc3                     *dwc = dep->dwc;
1353
1354         unsigned long                   flags;
1355
1356         int                             ret;
1357
1358         spin_lock_irqsave(&dwc->lock, flags);
1359         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1360         spin_unlock_irqrestore(&dwc->lock, flags);
1361
1362         return ret;
1363 }
1364
1365 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1366 {
1367         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1368         struct dwc3                     *dwc = dep->dwc;
1369         unsigned long                   flags;
1370         int                             ret;
1371
1372         spin_lock_irqsave(&dwc->lock, flags);
1373         dep->flags |= DWC3_EP_WEDGE;
1374
1375         if (dep->number == 0 || dep->number == 1)
1376                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1377         else
1378                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1379         spin_unlock_irqrestore(&dwc->lock, flags);
1380
1381         return ret;
1382 }
1383
1384 /* -------------------------------------------------------------------------- */
1385
1386 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1387         .bLength        = USB_DT_ENDPOINT_SIZE,
1388         .bDescriptorType = USB_DT_ENDPOINT,
1389         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1390 };
1391
1392 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1393         .enable         = dwc3_gadget_ep0_enable,
1394         .disable        = dwc3_gadget_ep0_disable,
1395         .alloc_request  = dwc3_gadget_ep_alloc_request,
1396         .free_request   = dwc3_gadget_ep_free_request,
1397         .queue          = dwc3_gadget_ep0_queue,
1398         .dequeue        = dwc3_gadget_ep_dequeue,
1399         .set_halt       = dwc3_gadget_ep0_set_halt,
1400         .set_wedge      = dwc3_gadget_ep_set_wedge,
1401 };
1402
1403 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1404         .enable         = dwc3_gadget_ep_enable,
1405         .disable        = dwc3_gadget_ep_disable,
1406         .alloc_request  = dwc3_gadget_ep_alloc_request,
1407         .free_request   = dwc3_gadget_ep_free_request,
1408         .queue          = dwc3_gadget_ep_queue,
1409         .dequeue        = dwc3_gadget_ep_dequeue,
1410         .set_halt       = dwc3_gadget_ep_set_halt,
1411         .set_wedge      = dwc3_gadget_ep_set_wedge,
1412 };
1413
1414 /* -------------------------------------------------------------------------- */
1415
1416 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1417 {
1418         struct dwc3             *dwc = gadget_to_dwc(g);
1419         u32                     reg;
1420
1421         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1422         return DWC3_DSTS_SOFFN(reg);
1423 }
1424
1425 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1426 {
1427         unsigned long           timeout;
1428
1429         int                     ret;
1430         u32                     reg;
1431
1432         u8                      link_state;
1433         u8                      speed;
1434
1435         /*
1436          * According to the Databook Remote wakeup request should
1437          * be issued only when the device is in early suspend state.
1438          *
1439          * We can check that via USB Link State bits in DSTS register.
1440          */
1441         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1442
1443         speed = reg & DWC3_DSTS_CONNECTSPD;
1444         if (speed == DWC3_DSTS_SUPERSPEED) {
1445                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1446                 return -EINVAL;
1447         }
1448
1449         link_state = DWC3_DSTS_USBLNKST(reg);
1450
1451         switch (link_state) {
1452         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1453         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1454                 break;
1455         default:
1456                 dwc3_trace(trace_dwc3_gadget,
1457                                 "can't wakeup from '%s'\n",
1458                                 dwc3_gadget_link_string(link_state));
1459                 return -EINVAL;
1460         }
1461
1462         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1463         if (ret < 0) {
1464                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1465                 return ret;
1466         }
1467
1468         /* Recent versions do this automatically */
1469         if (dwc->revision < DWC3_REVISION_194A) {
1470                 /* write zeroes to Link Change Request */
1471                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1472                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1473                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1474         }
1475
1476         /* poll until Link State changes to ON */
1477         timeout = jiffies + msecs_to_jiffies(100);
1478
1479         while (!time_after(jiffies, timeout)) {
1480                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1481
1482                 /* in HS, means ON */
1483                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1484                         break;
1485         }
1486
1487         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1488                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1489                 return -EINVAL;
1490         }
1491
1492         return 0;
1493 }
1494
1495 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1496 {
1497         struct dwc3             *dwc = gadget_to_dwc(g);
1498         unsigned long           flags;
1499         int                     ret;
1500
1501         spin_lock_irqsave(&dwc->lock, flags);
1502         ret = __dwc3_gadget_wakeup(dwc);
1503         spin_unlock_irqrestore(&dwc->lock, flags);
1504
1505         return ret;
1506 }
1507
1508 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1509                 int is_selfpowered)
1510 {
1511         struct dwc3             *dwc = gadget_to_dwc(g);
1512         unsigned long           flags;
1513
1514         spin_lock_irqsave(&dwc->lock, flags);
1515         g->is_selfpowered = !!is_selfpowered;
1516         spin_unlock_irqrestore(&dwc->lock, flags);
1517
1518         return 0;
1519 }
1520
1521 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1522 {
1523         u32                     reg;
1524         u32                     timeout = 500;
1525
1526         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1527         if (is_on) {
1528                 if (dwc->revision <= DWC3_REVISION_187A) {
1529                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1530                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1531                 }
1532
1533                 if (dwc->revision >= DWC3_REVISION_194A)
1534                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1535                 reg |= DWC3_DCTL_RUN_STOP;
1536
1537                 if (dwc->has_hibernation)
1538                         reg |= DWC3_DCTL_KEEP_CONNECT;
1539
1540                 dwc->pullups_connected = true;
1541         } else {
1542                 reg &= ~DWC3_DCTL_RUN_STOP;
1543
1544                 if (dwc->has_hibernation && !suspend)
1545                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1546
1547                 dwc->pullups_connected = false;
1548         }
1549
1550         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1551
1552         do {
1553                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1554                 if (is_on) {
1555                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1556                                 break;
1557                 } else {
1558                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1559                                 break;
1560                 }
1561                 timeout--;
1562                 if (!timeout)
1563                         return -ETIMEDOUT;
1564                 udelay(1);
1565         } while (1);
1566
1567         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1568                         dwc->gadget_driver
1569                         ? dwc->gadget_driver->function : "no-function",
1570                         is_on ? "connect" : "disconnect");
1571
1572         return 0;
1573 }
1574
1575 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1576 {
1577         struct dwc3             *dwc = gadget_to_dwc(g);
1578         unsigned long           flags;
1579         int                     ret;
1580
1581         is_on = !!is_on;
1582
1583         spin_lock_irqsave(&dwc->lock, flags);
1584         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1585         spin_unlock_irqrestore(&dwc->lock, flags);
1586
1587         return ret;
1588 }
1589
1590 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1591 {
1592         u32                     reg;
1593
1594         /* Enable all but Start and End of Frame IRQs */
1595         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1596                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1597                         DWC3_DEVTEN_CMDCMPLTEN |
1598                         DWC3_DEVTEN_ERRTICERREN |
1599                         DWC3_DEVTEN_WKUPEVTEN |
1600                         DWC3_DEVTEN_ULSTCNGEN |
1601                         DWC3_DEVTEN_CONNECTDONEEN |
1602                         DWC3_DEVTEN_USBRSTEN |
1603                         DWC3_DEVTEN_DISCONNEVTEN);
1604
1605         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1606 }
1607
1608 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1609 {
1610         /* mask all interrupts */
1611         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1612 }
1613
1614 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1615 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1616
1617 static int __dwc3_gadget_start(struct dwc3 *dwc)
1618 {
1619         struct dwc3_ep          *dep;
1620         int                     ret = 0;
1621         u32                     reg;
1622
1623         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1624         reg &= ~(DWC3_DCFG_SPEED_MASK);
1625
1626         /**
1627          * WORKAROUND: DWC3 revision < 2.20a have an issue
1628          * which would cause metastability state on Run/Stop
1629          * bit if we try to force the IP to USB2-only mode.
1630          *
1631          * Because of that, we cannot configure the IP to any
1632          * speed other than the SuperSpeed
1633          *
1634          * Refers to:
1635          *
1636          * STAR#9000525659: Clock Domain Crossing on DCTL in
1637          * USB 2.0 Mode
1638          */
1639         if (dwc->revision < DWC3_REVISION_220A) {
1640                 reg |= DWC3_DCFG_SUPERSPEED;
1641         } else {
1642                 switch (dwc->maximum_speed) {
1643                 case USB_SPEED_LOW:
1644                         reg |= DWC3_DSTS_LOWSPEED;
1645                         break;
1646                 case USB_SPEED_FULL:
1647                         reg |= DWC3_DSTS_FULLSPEED1;
1648                         break;
1649                 case USB_SPEED_HIGH:
1650                         reg |= DWC3_DSTS_HIGHSPEED;
1651                         break;
1652                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1653                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1654                 default:
1655                         reg |= DWC3_DSTS_SUPERSPEED;
1656                 }
1657         }
1658         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1659
1660         /*
1661          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1662          * field instead of letting dwc3 itself calculate that automatically.
1663          *
1664          * This way, we maximize the chances that we'll be able to get several
1665          * bursts of data without going through any sort of endpoint throttling.
1666          */
1667         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1668         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1669         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1670
1671         /* Start with SuperSpeed Default */
1672         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1673
1674         dep = dwc->eps[0];
1675         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1676                         false);
1677         if (ret) {
1678                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1679                 goto err0;
1680         }
1681
1682         dep = dwc->eps[1];
1683         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1684                         false);
1685         if (ret) {
1686                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1687                 goto err1;
1688         }
1689
1690         /* begin to receive SETUP packets */
1691         dwc->ep0state = EP0_SETUP_PHASE;
1692         dwc3_ep0_out_start(dwc);
1693
1694         dwc3_gadget_enable_irq(dwc);
1695
1696         return 0;
1697
1698 err1:
1699         __dwc3_gadget_ep_disable(dwc->eps[0]);
1700
1701 err0:
1702         return ret;
1703 }
1704
1705 static int dwc3_gadget_start(struct usb_gadget *g,
1706                 struct usb_gadget_driver *driver)
1707 {
1708         struct dwc3             *dwc = gadget_to_dwc(g);
1709         unsigned long           flags;
1710         int                     ret = 0;
1711         int                     irq;
1712
1713         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1714         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1715                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1716         if (ret) {
1717                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1718                                 irq, ret);
1719                 goto err0;
1720         }
1721
1722         spin_lock_irqsave(&dwc->lock, flags);
1723         if (dwc->gadget_driver) {
1724                 dev_err(dwc->dev, "%s is already bound to %s\n",
1725                                 dwc->gadget.name,
1726                                 dwc->gadget_driver->driver.name);
1727                 ret = -EBUSY;
1728                 goto err1;
1729         }
1730
1731         dwc->gadget_driver      = driver;
1732
1733         __dwc3_gadget_start(dwc);
1734         spin_unlock_irqrestore(&dwc->lock, flags);
1735
1736         return 0;
1737
1738 err1:
1739         spin_unlock_irqrestore(&dwc->lock, flags);
1740         free_irq(irq, dwc);
1741
1742 err0:
1743         return ret;
1744 }
1745
1746 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1747 {
1748         dwc3_gadget_disable_irq(dwc);
1749         __dwc3_gadget_ep_disable(dwc->eps[0]);
1750         __dwc3_gadget_ep_disable(dwc->eps[1]);
1751 }
1752
1753 static int dwc3_gadget_stop(struct usb_gadget *g)
1754 {
1755         struct dwc3             *dwc = gadget_to_dwc(g);
1756         unsigned long           flags;
1757         int                     irq;
1758
1759         spin_lock_irqsave(&dwc->lock, flags);
1760         __dwc3_gadget_stop(dwc);
1761         dwc->gadget_driver      = NULL;
1762         spin_unlock_irqrestore(&dwc->lock, flags);
1763
1764         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1765         free_irq(irq, dwc->ev_buf);
1766
1767         return 0;
1768 }
1769
1770 static const struct usb_gadget_ops dwc3_gadget_ops = {
1771         .get_frame              = dwc3_gadget_get_frame,
1772         .wakeup                 = dwc3_gadget_wakeup,
1773         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1774         .pullup                 = dwc3_gadget_pullup,
1775         .udc_start              = dwc3_gadget_start,
1776         .udc_stop               = dwc3_gadget_stop,
1777 };
1778
1779 /* -------------------------------------------------------------------------- */
1780
1781 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1782                 u8 num, u32 direction)
1783 {
1784         struct dwc3_ep                  *dep;
1785         u8                              i;
1786
1787         for (i = 0; i < num; i++) {
1788                 u8 epnum = (i << 1) | (!!direction);
1789
1790                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1791                 if (!dep)
1792                         return -ENOMEM;
1793
1794                 dep->dwc = dwc;
1795                 dep->number = epnum;
1796                 dep->direction = !!direction;
1797                 dwc->eps[epnum] = dep;
1798
1799                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1800                                 (epnum & 1) ? "in" : "out");
1801
1802                 dep->endpoint.name = dep->name;
1803
1804                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1805
1806                 if (epnum == 0 || epnum == 1) {
1807                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1808                         dep->endpoint.maxburst = 1;
1809                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1810                         if (!epnum)
1811                                 dwc->gadget.ep0 = &dep->endpoint;
1812                 } else {
1813                         int             ret;
1814
1815                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1816                         dep->endpoint.max_streams = 15;
1817                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1818                         list_add_tail(&dep->endpoint.ep_list,
1819                                         &dwc->gadget.ep_list);
1820
1821                         ret = dwc3_alloc_trb_pool(dep);
1822                         if (ret)
1823                                 return ret;
1824                 }
1825
1826                 if (epnum == 0 || epnum == 1) {
1827                         dep->endpoint.caps.type_control = true;
1828                 } else {
1829                         dep->endpoint.caps.type_iso = true;
1830                         dep->endpoint.caps.type_bulk = true;
1831                         dep->endpoint.caps.type_int = true;
1832                 }
1833
1834                 dep->endpoint.caps.dir_in = !!direction;
1835                 dep->endpoint.caps.dir_out = !direction;
1836
1837                 INIT_LIST_HEAD(&dep->pending_list);
1838                 INIT_LIST_HEAD(&dep->started_list);
1839         }
1840
1841         return 0;
1842 }
1843
1844 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1845 {
1846         int                             ret;
1847
1848         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1849
1850         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1851         if (ret < 0) {
1852                 dwc3_trace(trace_dwc3_gadget,
1853                                 "failed to allocate OUT endpoints");
1854                 return ret;
1855         }
1856
1857         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1858         if (ret < 0) {
1859                 dwc3_trace(trace_dwc3_gadget,
1860                                 "failed to allocate IN endpoints");
1861                 return ret;
1862         }
1863
1864         return 0;
1865 }
1866
1867 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1868 {
1869         struct dwc3_ep                  *dep;
1870         u8                              epnum;
1871
1872         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1873                 dep = dwc->eps[epnum];
1874                 if (!dep)
1875                         continue;
1876                 /*
1877                  * Physical endpoints 0 and 1 are special; they form the
1878                  * bi-directional USB endpoint 0.
1879                  *
1880                  * For those two physical endpoints, we don't allocate a TRB
1881                  * pool nor do we add them the endpoints list. Due to that, we
1882                  * shouldn't do these two operations otherwise we would end up
1883                  * with all sorts of bugs when removing dwc3.ko.
1884                  */
1885                 if (epnum != 0 && epnum != 1) {
1886                         dwc3_free_trb_pool(dep);
1887                         list_del(&dep->endpoint.ep_list);
1888                 }
1889
1890                 kfree(dep);
1891         }
1892 }
1893
1894 /* -------------------------------------------------------------------------- */
1895
1896 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1897                 struct dwc3_request *req, struct dwc3_trb *trb,
1898                 const struct dwc3_event_depevt *event, int status)
1899 {
1900         unsigned int            count;
1901         unsigned int            s_pkt = 0;
1902         unsigned int            trb_status;
1903
1904         trace_dwc3_complete_trb(dep, trb);
1905
1906         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1907                 /*
1908                  * We continue despite the error. There is not much we
1909                  * can do. If we don't clean it up we loop forever. If
1910                  * we skip the TRB then it gets overwritten after a
1911                  * while since we use them in a ring buffer. A BUG()
1912                  * would help. Lets hope that if this occurs, someone
1913                  * fixes the root cause instead of looking away :)
1914                  */
1915                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1916                                 dep->name, trb);
1917         count = trb->size & DWC3_TRB_SIZE_MASK;
1918
1919         if (dep->direction) {
1920                 if (count) {
1921                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1922                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1923                                 dwc3_trace(trace_dwc3_gadget,
1924                                                 "%s: incomplete IN transfer\n",
1925                                                 dep->name);
1926                                 /*
1927                                  * If missed isoc occurred and there is
1928                                  * no request queued then issue END
1929                                  * TRANSFER, so that core generates
1930                                  * next xfernotready and we will issue
1931                                  * a fresh START TRANSFER.
1932                                  * If there are still queued request
1933                                  * then wait, do not issue either END
1934                                  * or UPDATE TRANSFER, just attach next
1935                                  * request in pending_list during
1936                                  * giveback.If any future queued request
1937                                  * is successfully transferred then we
1938                                  * will issue UPDATE TRANSFER for all
1939                                  * request in the pending_list.
1940                                  */
1941                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1942                         } else {
1943                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1944                                                 dep->name);
1945                                 status = -ECONNRESET;
1946                         }
1947                 } else {
1948                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1949                 }
1950         } else {
1951                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1952                         s_pkt = 1;
1953         }
1954
1955         /*
1956          * We assume here we will always receive the entire data block
1957          * which we should receive. Meaning, if we program RX to
1958          * receive 4K but we receive only 2K, we assume that's all we
1959          * should receive and we simply bounce the request back to the
1960          * gadget driver for further processing.
1961          */
1962         req->request.actual += req->request.length - count;
1963         if (s_pkt)
1964                 return 1;
1965         if ((event->status & DEPEVT_STATUS_LST) &&
1966                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1967                                 DWC3_TRB_CTRL_HWO)))
1968                 return 1;
1969         if ((event->status & DEPEVT_STATUS_IOC) &&
1970                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1971                 return 1;
1972         return 0;
1973 }
1974
1975 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1976                 const struct dwc3_event_depevt *event, int status)
1977 {
1978         struct dwc3_request     *req;
1979         struct dwc3_trb         *trb;
1980         unsigned int            slot;
1981         unsigned int            i;
1982         int                     ret;
1983
1984         do {
1985                 req = next_request(&dep->started_list);
1986                 if (WARN_ON_ONCE(!req))
1987                         return 1;
1988
1989                 i = 0;
1990                 do {
1991                         slot = req->first_trb_index + i;
1992                         if (slot == DWC3_TRB_NUM - 1)
1993                                 slot++;
1994                         slot %= DWC3_TRB_NUM;
1995                         trb = &dep->trb_pool[slot];
1996
1997                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1998                                         event, status);
1999                         if (ret)
2000                                 break;
2001                 } while (++i < req->request.num_mapped_sgs);
2002
2003                 dwc3_gadget_giveback(dep, req, status);
2004
2005                 if (ret)
2006                         break;
2007         } while (1);
2008
2009         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2010                         list_empty(&dep->started_list)) {
2011                 if (list_empty(&dep->pending_list)) {
2012                         /*
2013                          * If there is no entry in request list then do
2014                          * not issue END TRANSFER now. Just set PENDING
2015                          * flag, so that END TRANSFER is issued when an
2016                          * entry is added into request list.
2017                          */
2018                         dep->flags = DWC3_EP_PENDING_REQUEST;
2019                 } else {
2020                         dwc3_stop_active_transfer(dwc, dep->number, true);
2021                         dep->flags = DWC3_EP_ENABLED;
2022                 }
2023                 return 1;
2024         }
2025
2026         return 1;
2027 }
2028
2029 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2030                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2031 {
2032         unsigned                status = 0;
2033         int                     clean_busy;
2034         u32                     is_xfer_complete;
2035
2036         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2037
2038         if (event->status & DEPEVT_STATUS_BUSERR)
2039                 status = -ECONNRESET;
2040
2041         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2042         if (clean_busy && (is_xfer_complete ||
2043                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2044                 dep->flags &= ~DWC3_EP_BUSY;
2045
2046         /*
2047          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2048          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2049          */
2050         if (dwc->revision < DWC3_REVISION_183A) {
2051                 u32             reg;
2052                 int             i;
2053
2054                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2055                         dep = dwc->eps[i];
2056
2057                         if (!(dep->flags & DWC3_EP_ENABLED))
2058                                 continue;
2059
2060                         if (!list_empty(&dep->started_list))
2061                                 return;
2062                 }
2063
2064                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2065                 reg |= dwc->u1u2;
2066                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2067
2068                 dwc->u1u2 = 0;
2069         }
2070
2071         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2072                 int ret;
2073
2074                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2075                 if (!ret || ret == -EBUSY)
2076                         return;
2077         }
2078 }
2079
2080 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2081                 const struct dwc3_event_depevt *event)
2082 {
2083         struct dwc3_ep          *dep;
2084         u8                      epnum = event->endpoint_number;
2085
2086         dep = dwc->eps[epnum];
2087
2088         if (!(dep->flags & DWC3_EP_ENABLED))
2089                 return;
2090
2091         if (epnum == 0 || epnum == 1) {
2092                 dwc3_ep0_interrupt(dwc, event);
2093                 return;
2094         }
2095
2096         switch (event->endpoint_event) {
2097         case DWC3_DEPEVT_XFERCOMPLETE:
2098                 dep->resource_index = 0;
2099
2100                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2101                         dwc3_trace(trace_dwc3_gadget,
2102                                         "%s is an Isochronous endpoint\n",
2103                                         dep->name);
2104                         return;
2105                 }
2106
2107                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2108                 break;
2109         case DWC3_DEPEVT_XFERINPROGRESS:
2110                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2111                 break;
2112         case DWC3_DEPEVT_XFERNOTREADY:
2113                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2114                         dwc3_gadget_start_isoc(dwc, dep, event);
2115                 } else {
2116                         int active;
2117                         int ret;
2118
2119                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2120
2121                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2122                                         dep->name, active ? "Transfer Active"
2123                                         : "Transfer Not Active");
2124
2125                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2126                         if (!ret || ret == -EBUSY)
2127                                 return;
2128
2129                         dwc3_trace(trace_dwc3_gadget,
2130                                         "%s: failed to kick transfers\n",
2131                                         dep->name);
2132                 }
2133
2134                 break;
2135         case DWC3_DEPEVT_STREAMEVT:
2136                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2137                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2138                                         dep->name);
2139                         return;
2140                 }
2141
2142                 switch (event->status) {
2143                 case DEPEVT_STREAMEVT_FOUND:
2144                         dwc3_trace(trace_dwc3_gadget,
2145                                         "Stream %d found and started",
2146                                         event->parameters);
2147
2148                         break;
2149                 case DEPEVT_STREAMEVT_NOTFOUND:
2150                         /* FALLTHROUGH */
2151                 default:
2152                         dwc3_trace(trace_dwc3_gadget,
2153                                         "unable to find suitable stream\n");
2154                 }
2155                 break;
2156         case DWC3_DEPEVT_RXTXFIFOEVT:
2157                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2158                 break;
2159         case DWC3_DEPEVT_EPCMDCMPLT:
2160                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2161                 break;
2162         }
2163 }
2164
2165 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2166 {
2167         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2168                 spin_unlock(&dwc->lock);
2169                 dwc->gadget_driver->disconnect(&dwc->gadget);
2170                 spin_lock(&dwc->lock);
2171         }
2172 }
2173
2174 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2175 {
2176         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2177                 spin_unlock(&dwc->lock);
2178                 dwc->gadget_driver->suspend(&dwc->gadget);
2179                 spin_lock(&dwc->lock);
2180         }
2181 }
2182
2183 static void dwc3_resume_gadget(struct dwc3 *dwc)
2184 {
2185         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2186                 spin_unlock(&dwc->lock);
2187                 dwc->gadget_driver->resume(&dwc->gadget);
2188                 spin_lock(&dwc->lock);
2189         }
2190 }
2191
2192 static void dwc3_reset_gadget(struct dwc3 *dwc)
2193 {
2194         if (!dwc->gadget_driver)
2195                 return;
2196
2197         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2198                 spin_unlock(&dwc->lock);
2199                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2200                 spin_lock(&dwc->lock);
2201         }
2202 }
2203
2204 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2205 {
2206         struct dwc3_ep *dep;
2207         struct dwc3_gadget_ep_cmd_params params;
2208         u32 cmd;
2209         int ret;
2210
2211         dep = dwc->eps[epnum];
2212
2213         if (!dep->resource_index)
2214                 return;
2215
2216         /*
2217          * NOTICE: We are violating what the Databook says about the
2218          * EndTransfer command. Ideally we would _always_ wait for the
2219          * EndTransfer Command Completion IRQ, but that's causing too
2220          * much trouble synchronizing between us and gadget driver.
2221          *
2222          * We have discussed this with the IP Provider and it was
2223          * suggested to giveback all requests here, but give HW some
2224          * extra time to synchronize with the interconnect. We're using
2225          * an arbitrary 100us delay for that.
2226          *
2227          * Note also that a similar handling was tested by Synopsys
2228          * (thanks a lot Paul) and nothing bad has come out of it.
2229          * In short, what we're doing is:
2230          *
2231          * - Issue EndTransfer WITH CMDIOC bit set
2232          * - Wait 100us
2233          */
2234
2235         cmd = DWC3_DEPCMD_ENDTRANSFER;
2236         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2237         cmd |= DWC3_DEPCMD_CMDIOC;
2238         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2239         memset(&params, 0, sizeof(params));
2240         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2241         WARN_ON_ONCE(ret);
2242         dep->resource_index = 0;
2243         dep->flags &= ~DWC3_EP_BUSY;
2244         udelay(100);
2245 }
2246
2247 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2248 {
2249         u32 epnum;
2250
2251         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2252                 struct dwc3_ep *dep;
2253
2254                 dep = dwc->eps[epnum];
2255                 if (!dep)
2256                         continue;
2257
2258                 if (!(dep->flags & DWC3_EP_ENABLED))
2259                         continue;
2260
2261                 dwc3_remove_requests(dwc, dep);
2262         }
2263 }
2264
2265 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2266 {
2267         u32 epnum;
2268
2269         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2270                 struct dwc3_ep *dep;
2271                 int ret;
2272
2273                 dep = dwc->eps[epnum];
2274                 if (!dep)
2275                         continue;
2276
2277                 if (!(dep->flags & DWC3_EP_STALL))
2278                         continue;
2279
2280                 dep->flags &= ~DWC3_EP_STALL;
2281
2282                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2283                 WARN_ON_ONCE(ret);
2284         }
2285 }
2286
2287 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2288 {
2289         int                     reg;
2290
2291         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2292         reg &= ~DWC3_DCTL_INITU1ENA;
2293         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2294
2295         reg &= ~DWC3_DCTL_INITU2ENA;
2296         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2297
2298         dwc3_disconnect_gadget(dwc);
2299
2300         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2301         dwc->setup_packet_pending = false;
2302         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2303 }
2304
2305 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2306 {
2307         u32                     reg;
2308
2309         /*
2310          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2311          * would cause a missing Disconnect Event if there's a
2312          * pending Setup Packet in the FIFO.
2313          *
2314          * There's no suggested workaround on the official Bug
2315          * report, which states that "unless the driver/application
2316          * is doing any special handling of a disconnect event,
2317          * there is no functional issue".
2318          *
2319          * Unfortunately, it turns out that we _do_ some special
2320          * handling of a disconnect event, namely complete all
2321          * pending transfers, notify gadget driver of the
2322          * disconnection, and so on.
2323          *
2324          * Our suggested workaround is to follow the Disconnect
2325          * Event steps here, instead, based on a setup_packet_pending
2326          * flag. Such flag gets set whenever we have a SETUP_PENDING
2327          * status for EP0 TRBs and gets cleared on XferComplete for the
2328          * same endpoint.
2329          *
2330          * Refers to:
2331          *
2332          * STAR#9000466709: RTL: Device : Disconnect event not
2333          * generated if setup packet pending in FIFO
2334          */
2335         if (dwc->revision < DWC3_REVISION_188A) {
2336                 if (dwc->setup_packet_pending)
2337                         dwc3_gadget_disconnect_interrupt(dwc);
2338         }
2339
2340         dwc3_reset_gadget(dwc);
2341
2342         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2343         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2344         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2345         dwc->test_mode = false;
2346
2347         dwc3_stop_active_transfers(dwc);
2348         dwc3_clear_stall_all_ep(dwc);
2349
2350         /* Reset device address to zero */
2351         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2352         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2353         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2354 }
2355
2356 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2357 {
2358         u32 reg;
2359         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2360
2361         /*
2362          * We change the clock only at SS but I dunno why I would want to do
2363          * this. Maybe it becomes part of the power saving plan.
2364          */
2365
2366         if (speed != DWC3_DSTS_SUPERSPEED)
2367                 return;
2368
2369         /*
2370          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2371          * each time on Connect Done.
2372          */
2373         if (!usb30_clock)
2374                 return;
2375
2376         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2377         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2378         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2379 }
2380
2381 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2382 {
2383         struct dwc3_ep          *dep;
2384         int                     ret;
2385         u32                     reg;
2386         u8                      speed;
2387
2388         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2389         speed = reg & DWC3_DSTS_CONNECTSPD;
2390         dwc->speed = speed;
2391
2392         dwc3_update_ram_clk_sel(dwc, speed);
2393
2394         switch (speed) {
2395         case DWC3_DCFG_SUPERSPEED:
2396                 /*
2397                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2398                  * would cause a missing USB3 Reset event.
2399                  *
2400                  * In such situations, we should force a USB3 Reset
2401                  * event by calling our dwc3_gadget_reset_interrupt()
2402                  * routine.
2403                  *
2404                  * Refers to:
2405                  *
2406                  * STAR#9000483510: RTL: SS : USB3 reset event may
2407                  * not be generated always when the link enters poll
2408                  */
2409                 if (dwc->revision < DWC3_REVISION_190A)
2410                         dwc3_gadget_reset_interrupt(dwc);
2411
2412                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2413                 dwc->gadget.ep0->maxpacket = 512;
2414                 dwc->gadget.speed = USB_SPEED_SUPER;
2415                 break;
2416         case DWC3_DCFG_HIGHSPEED:
2417                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2418                 dwc->gadget.ep0->maxpacket = 64;
2419                 dwc->gadget.speed = USB_SPEED_HIGH;
2420                 break;
2421         case DWC3_DCFG_FULLSPEED2:
2422         case DWC3_DCFG_FULLSPEED1:
2423                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2424                 dwc->gadget.ep0->maxpacket = 64;
2425                 dwc->gadget.speed = USB_SPEED_FULL;
2426                 break;
2427         case DWC3_DCFG_LOWSPEED:
2428                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2429                 dwc->gadget.ep0->maxpacket = 8;
2430                 dwc->gadget.speed = USB_SPEED_LOW;
2431                 break;
2432         }
2433
2434         /* Enable USB2 LPM Capability */
2435
2436         if ((dwc->revision > DWC3_REVISION_194A)
2437                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2438                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2439                 reg |= DWC3_DCFG_LPM_CAP;
2440                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2441
2442                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2443                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2444
2445                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2446
2447                 /*
2448                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2449                  * DCFG.LPMCap is set, core responses with an ACK and the
2450                  * BESL value in the LPM token is less than or equal to LPM
2451                  * NYET threshold.
2452                  */
2453                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2454                                 && dwc->has_lpm_erratum,
2455                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2456
2457                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2458                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2459
2460                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2461         } else {
2462                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2463                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2464                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2465         }
2466
2467         dep = dwc->eps[0];
2468         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2469                         false);
2470         if (ret) {
2471                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2472                 return;
2473         }
2474
2475         dep = dwc->eps[1];
2476         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2477                         false);
2478         if (ret) {
2479                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2480                 return;
2481         }
2482
2483         /*
2484          * Configure PHY via GUSB3PIPECTLn if required.
2485          *
2486          * Update GTXFIFOSIZn
2487          *
2488          * In both cases reset values should be sufficient.
2489          */
2490 }
2491
2492 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2493 {
2494         /*
2495          * TODO take core out of low power mode when that's
2496          * implemented.
2497          */
2498
2499         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2500                 spin_unlock(&dwc->lock);
2501                 dwc->gadget_driver->resume(&dwc->gadget);
2502                 spin_lock(&dwc->lock);
2503         }
2504 }
2505
2506 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2507                 unsigned int evtinfo)
2508 {
2509         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2510         unsigned int            pwropt;
2511
2512         /*
2513          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2514          * Hibernation mode enabled which would show up when device detects
2515          * host-initiated U3 exit.
2516          *
2517          * In that case, device will generate a Link State Change Interrupt
2518          * from U3 to RESUME which is only necessary if Hibernation is
2519          * configured in.
2520          *
2521          * There are no functional changes due to such spurious event and we
2522          * just need to ignore it.
2523          *
2524          * Refers to:
2525          *
2526          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2527          * operational mode
2528          */
2529         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2530         if ((dwc->revision < DWC3_REVISION_250A) &&
2531                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2532                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2533                                 (next == DWC3_LINK_STATE_RESUME)) {
2534                         dwc3_trace(trace_dwc3_gadget,
2535                                         "ignoring transition U3 -> Resume");
2536                         return;
2537                 }
2538         }
2539
2540         /*
2541          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2542          * on the link partner, the USB session might do multiple entry/exit
2543          * of low power states before a transfer takes place.
2544          *
2545          * Due to this problem, we might experience lower throughput. The
2546          * suggested workaround is to disable DCTL[12:9] bits if we're
2547          * transitioning from U1/U2 to U0 and enable those bits again
2548          * after a transfer completes and there are no pending transfers
2549          * on any of the enabled endpoints.
2550          *
2551          * This is the first half of that workaround.
2552          *
2553          * Refers to:
2554          *
2555          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2556          * core send LGO_Ux entering U0
2557          */
2558         if (dwc->revision < DWC3_REVISION_183A) {
2559                 if (next == DWC3_LINK_STATE_U0) {
2560                         u32     u1u2;
2561                         u32     reg;
2562
2563                         switch (dwc->link_state) {
2564                         case DWC3_LINK_STATE_U1:
2565                         case DWC3_LINK_STATE_U2:
2566                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2567                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2568                                                 | DWC3_DCTL_ACCEPTU2ENA
2569                                                 | DWC3_DCTL_INITU1ENA
2570                                                 | DWC3_DCTL_ACCEPTU1ENA);
2571
2572                                 if (!dwc->u1u2)
2573                                         dwc->u1u2 = reg & u1u2;
2574
2575                                 reg &= ~u1u2;
2576
2577                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2578                                 break;
2579                         default:
2580                                 /* do nothing */
2581                                 break;
2582                         }
2583                 }
2584         }
2585
2586         switch (next) {
2587         case DWC3_LINK_STATE_U1:
2588                 if (dwc->speed == USB_SPEED_SUPER)
2589                         dwc3_suspend_gadget(dwc);
2590                 break;
2591         case DWC3_LINK_STATE_U2:
2592         case DWC3_LINK_STATE_U3:
2593                 dwc3_suspend_gadget(dwc);
2594                 break;
2595         case DWC3_LINK_STATE_RESUME:
2596                 dwc3_resume_gadget(dwc);
2597                 break;
2598         default:
2599                 /* do nothing */
2600                 break;
2601         }
2602
2603         dwc->link_state = next;
2604 }
2605
2606 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2607                 unsigned int evtinfo)
2608 {
2609         unsigned int is_ss = evtinfo & BIT(4);
2610
2611         /**
2612          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2613          * have a known issue which can cause USB CV TD.9.23 to fail
2614          * randomly.
2615          *
2616          * Because of this issue, core could generate bogus hibernation
2617          * events which SW needs to ignore.
2618          *
2619          * Refers to:
2620          *
2621          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2622          * Device Fallback from SuperSpeed
2623          */
2624         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2625                 return;
2626
2627         /* enter hibernation here */
2628 }
2629
2630 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2631                 const struct dwc3_event_devt *event)
2632 {
2633         switch (event->type) {
2634         case DWC3_DEVICE_EVENT_DISCONNECT:
2635                 dwc3_gadget_disconnect_interrupt(dwc);
2636                 break;
2637         case DWC3_DEVICE_EVENT_RESET:
2638                 dwc3_gadget_reset_interrupt(dwc);
2639                 break;
2640         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2641                 dwc3_gadget_conndone_interrupt(dwc);
2642                 break;
2643         case DWC3_DEVICE_EVENT_WAKEUP:
2644                 dwc3_gadget_wakeup_interrupt(dwc);
2645                 break;
2646         case DWC3_DEVICE_EVENT_HIBER_REQ:
2647                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2648                                         "unexpected hibernation event\n"))
2649                         break;
2650
2651                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2652                 break;
2653         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2654                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2655                 break;
2656         case DWC3_DEVICE_EVENT_EOPF:
2657                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2658                 break;
2659         case DWC3_DEVICE_EVENT_SOF:
2660                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2661                 break;
2662         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2663                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2664                 break;
2665         case DWC3_DEVICE_EVENT_CMD_CMPL:
2666                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2667                 break;
2668         case DWC3_DEVICE_EVENT_OVERFLOW:
2669                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2670                 break;
2671         default:
2672                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2673         }
2674 }
2675
2676 static void dwc3_process_event_entry(struct dwc3 *dwc,
2677                 const union dwc3_event *event)
2678 {
2679         trace_dwc3_event(event->raw);
2680
2681         /* Endpoint IRQ, handle it and return early */
2682         if (event->type.is_devspec == 0) {
2683                 /* depevt */
2684                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2685         }
2686
2687         switch (event->type.type) {
2688         case DWC3_EVENT_TYPE_DEV:
2689                 dwc3_gadget_interrupt(dwc, &event->devt);
2690                 break;
2691         /* REVISIT what to do with Carkit and I2C events ? */
2692         default:
2693                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2694         }
2695 }
2696
2697 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2698 {
2699         struct dwc3 *dwc = evt->dwc;
2700         irqreturn_t ret = IRQ_NONE;
2701         int left;
2702         u32 reg;
2703
2704         left = evt->count;
2705
2706         if (!(evt->flags & DWC3_EVENT_PENDING))
2707                 return IRQ_NONE;
2708
2709         while (left > 0) {
2710                 union dwc3_event event;
2711
2712                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2713
2714                 dwc3_process_event_entry(dwc, &event);
2715
2716                 /*
2717                  * FIXME we wrap around correctly to the next entry as
2718                  * almost all entries are 4 bytes in size. There is one
2719                  * entry which has 12 bytes which is a regular entry
2720                  * followed by 8 bytes data. ATM I don't know how
2721                  * things are organized if we get next to the a
2722                  * boundary so I worry about that once we try to handle
2723                  * that.
2724                  */
2725                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2726                 left -= 4;
2727
2728                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2729         }
2730
2731         evt->count = 0;
2732         evt->flags &= ~DWC3_EVENT_PENDING;
2733         ret = IRQ_HANDLED;
2734
2735         /* Unmask interrupt */
2736         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2737         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2738         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2739
2740         return ret;
2741 }
2742
2743 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2744 {
2745         struct dwc3_event_buffer *evt = _evt;
2746         struct dwc3 *dwc = evt->dwc;
2747         unsigned long flags;
2748         irqreturn_t ret = IRQ_NONE;
2749
2750         spin_lock_irqsave(&dwc->lock, flags);
2751         ret = dwc3_process_event_buf(evt);
2752         spin_unlock_irqrestore(&dwc->lock, flags);
2753
2754         return ret;
2755 }
2756
2757 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2758 {
2759         struct dwc3 *dwc = evt->dwc;
2760         u32 count;
2761         u32 reg;
2762
2763         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2764         count &= DWC3_GEVNTCOUNT_MASK;
2765         if (!count)
2766                 return IRQ_NONE;
2767
2768         evt->count = count;
2769         evt->flags |= DWC3_EVENT_PENDING;
2770
2771         /* Mask interrupt */
2772         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2773         reg |= DWC3_GEVNTSIZ_INTMASK;
2774         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2775
2776         return IRQ_WAKE_THREAD;
2777 }
2778
2779 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2780 {
2781         struct dwc3_event_buffer        *evt = _evt;
2782
2783         return dwc3_check_event_buf(evt);
2784 }
2785
2786 /**
2787  * dwc3_gadget_init - Initializes gadget related registers
2788  * @dwc: pointer to our controller context structure
2789  *
2790  * Returns 0 on success otherwise negative errno.
2791  */
2792 int dwc3_gadget_init(struct dwc3 *dwc)
2793 {
2794         int                                     ret;
2795
2796         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2797                         &dwc->ctrl_req_addr, GFP_KERNEL);
2798         if (!dwc->ctrl_req) {
2799                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2800                 ret = -ENOMEM;
2801                 goto err0;
2802         }
2803
2804         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2805                         &dwc->ep0_trb_addr, GFP_KERNEL);
2806         if (!dwc->ep0_trb) {
2807                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2808                 ret = -ENOMEM;
2809                 goto err1;
2810         }
2811
2812         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2813         if (!dwc->setup_buf) {
2814                 ret = -ENOMEM;
2815                 goto err2;
2816         }
2817
2818         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2819                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2820                         GFP_KERNEL);
2821         if (!dwc->ep0_bounce) {
2822                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2823                 ret = -ENOMEM;
2824                 goto err3;
2825         }
2826
2827         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2828         if (!dwc->zlp_buf) {
2829                 ret = -ENOMEM;
2830                 goto err4;
2831         }
2832
2833         dwc->gadget.ops                 = &dwc3_gadget_ops;
2834         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2835         dwc->gadget.sg_supported        = true;
2836         dwc->gadget.name                = "dwc3-gadget";
2837         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2838
2839         /*
2840          * FIXME We might be setting max_speed to <SUPER, however versions
2841          * <2.20a of dwc3 have an issue with metastability (documented
2842          * elsewhere in this driver) which tells us we can't set max speed to
2843          * anything lower than SUPER.
2844          *
2845          * Because gadget.max_speed is only used by composite.c and function
2846          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2847          * to happen so we avoid sending SuperSpeed Capability descriptor
2848          * together with our BOS descriptor as that could confuse host into
2849          * thinking we can handle super speed.
2850          *
2851          * Note that, in fact, we won't even support GetBOS requests when speed
2852          * is less than super speed because we don't have means, yet, to tell
2853          * composite.c that we are USB 2.0 + LPM ECN.
2854          */
2855         if (dwc->revision < DWC3_REVISION_220A)
2856                 dwc3_trace(trace_dwc3_gadget,
2857                                 "Changing max_speed on rev %08x\n",
2858                                 dwc->revision);
2859
2860         dwc->gadget.max_speed           = dwc->maximum_speed;
2861
2862         /*
2863          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2864          * on ep out.
2865          */
2866         dwc->gadget.quirk_ep_out_aligned_size = true;
2867
2868         /*
2869          * REVISIT: Here we should clear all pending IRQs to be
2870          * sure we're starting from a well known location.
2871          */
2872
2873         ret = dwc3_gadget_init_endpoints(dwc);
2874         if (ret)
2875                 goto err5;
2876
2877         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2878         if (ret) {
2879                 dev_err(dwc->dev, "failed to register udc\n");
2880                 goto err5;
2881         }
2882
2883         return 0;
2884
2885 err5:
2886         kfree(dwc->zlp_buf);
2887
2888 err4:
2889         dwc3_gadget_free_endpoints(dwc);
2890         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2891                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2892
2893 err3:
2894         kfree(dwc->setup_buf);
2895
2896 err2:
2897         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2898                         dwc->ep0_trb, dwc->ep0_trb_addr);
2899
2900 err1:
2901         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2902                         dwc->ctrl_req, dwc->ctrl_req_addr);
2903
2904 err0:
2905         return ret;
2906 }
2907
2908 /* -------------------------------------------------------------------------- */
2909
2910 void dwc3_gadget_exit(struct dwc3 *dwc)
2911 {
2912         usb_del_gadget_udc(&dwc->gadget);
2913
2914         dwc3_gadget_free_endpoints(dwc);
2915
2916         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2917                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2918
2919         kfree(dwc->setup_buf);
2920         kfree(dwc->zlp_buf);
2921
2922         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2923                         dwc->ep0_trb, dwc->ep0_trb_addr);
2924
2925         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2926                         dwc->ctrl_req, dwc->ctrl_req_addr);
2927 }
2928
2929 int dwc3_gadget_suspend(struct dwc3 *dwc)
2930 {
2931         int ret;
2932
2933         if (!dwc->gadget_driver)
2934                 return 0;
2935
2936         ret = dwc3_gadget_run_stop(dwc, false, false);
2937         if (ret < 0)
2938                 return ret;
2939
2940         dwc3_disconnect_gadget(dwc);
2941         __dwc3_gadget_stop(dwc);
2942
2943         return 0;
2944 }
2945
2946 int dwc3_gadget_resume(struct dwc3 *dwc)
2947 {
2948         int                     ret;
2949
2950         if (!dwc->gadget_driver)
2951                 return 0;
2952
2953         ret = __dwc3_gadget_start(dwc);
2954         if (ret < 0)
2955                 goto err0;
2956
2957         ret = dwc3_gadget_run_stop(dwc, true, false);
2958         if (ret < 0)
2959                 goto err1;
2960
2961         return 0;
2962
2963 err1:
2964         __dwc3_gadget_stop(dwc);
2965
2966 err0:
2967         return ret;
2968 }