drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/io.h>
  46 #include <linux/list.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <linux/usb/ch9.h>
  50 #include <linux/usb/gadget.h>
  51 #include <linux/usb/composite.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  58 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  59                 struct dwc3_ep *dep, struct dwc3_request *req);
  60
  61 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  62 {
  63         switch (state) {
  64         case EP0_UNCONNECTED:
  65                 return "Unconnected";
  66         case EP0_SETUP_PHASE:
  67                 return "Setup Phase";
  68         case EP0_DATA_PHASE:
  69                 return "Data Phase";
  70         case EP0_STATUS_PHASE:
  71                 return "Status Phase";
  72         default:
  73                 return "UNKNOWN";
  74         }
  75 }
  76
  77 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  78                 u32 len, u32 type)
  79 {
  80         struct dwc3_gadget_ep_cmd_params params;
  81         struct dwc3_trb                 *trb;
  82         struct dwc3_ep                  *dep;
  83
  84         int                             ret;
  85
  86         dep = dwc->eps[epnum];
  87         if (dep->flags & DWC3_EP_BUSY) {
  88                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  89                 return 0;
  90         }
  91
  92         trb = dwc->ep0_trb;
  93
  94         trb->bpl = lower_32_bits(buf_dma);
  95         trb->bph = upper_32_bits(buf_dma);
  96         trb->size = len;
  97         trb->ctrl = type;
  98
  99         trb->ctrl |= (DWC3_TRB_CTRL_HWO
 100                         | DWC3_TRB_CTRL_LST
 101                         | DWC3_TRB_CTRL_IOC
 102                         | DWC3_TRB_CTRL_ISP_IMI);
 103
 104         memset(&params, 0, sizeof(params));
 105         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 106         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 107
 108         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 109                         DWC3_DEPCMD_STARTTRANSFER, &params);
 110         if (ret < 0) {
 111                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 112                 return ret;
 113         }
 114
 115         dep->flags |= DWC3_EP_BUSY;
 116         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 117                         dep->number);
 118
 119         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 120
 121         return 0;
 122 }
 123
 124 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 125                 struct dwc3_request *req)
 126 {
 127         struct dwc3             *dwc = dep->dwc;
 128
 129         req->request.actual     = 0;
 130         req->request.status     = -EINPROGRESS;
 131         req->epnum              = dep->number;
 132
 133         list_add_tail(&req->list, &dep->request_list);
 134
 135         /*
 136          * Gadget driver might not be quick enough to queue a request
 137          * before we get a Transfer Not Ready event on this endpoint.
 138          *
 139          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 140          * flag is set, it's telling us that as soon as Gadget queues the
 141          * required request, we should kick the transfer here because the
 142          * IRQ we were waiting for is long gone.
 143          */
 144         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 145                 unsigned        direction;
 146
 147                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 148
 149                 if (dwc->ep0state != EP0_DATA_PHASE) {
 150                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 151                         return 0;
 152                 }
 153
 154                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 155
 156                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 157                                 DWC3_EP0_DIR_IN);
 158
 159                 return 0;
 160         }
 161
 162         /*
 163          * In case gadget driver asked us to delay the STATUS phase,
 164          * handle it here.
 165          */
 166         if (dwc->delayed_status) {
 167                 unsigned        direction;
 168
 169                 direction = !dwc->ep0_expect_in;
 170                 dwc->delayed_status = false;
 171
 172                 if (dwc->ep0state == EP0_STATUS_PHASE)
 173                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 174                 else
 175                         dev_dbg(dwc->dev, "too early for delayed status\n");
 176
 177                 return 0;
 178         }
 179
 180         /*
 181          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 182          *
 183          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 184          * come before issueing Start Transfer command, but if we do, we will
 185          * miss situations where the host starts another SETUP phase instead of
 186          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 187          * Layer Compliance Suite.
 188          *
 189          * The problem surfaces due to the fact that in case of back-to-back
 190          * SETUP packets there will be no XferNotReady(DATA) generated and we
 191          * will be stuck waiting for XferNotReady(DATA) forever.
 192          *
 193          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 194          * it tells us to start Data Phase right away. It also mentions that if
 195          * we receive a SETUP phase instead of the DATA phase, core will issue
 196          * XferComplete for the DATA phase, before actually initiating it in
 197          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 198          * can only be used to print some debugging logs, as the core expects
 199          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 200          * just so it completes right away, without transferring anything and,
 201          * only then, we can go back to the SETUP phase.
 202          *
 203          * Because of this scenario, SNPS decided to change the programming
 204          * model of control transfers and support on-demand transfers only for
 205          * the STATUS phase. To fix the issue we have now, we will always wait
 206          * for gadget driver to queue the DATA phase's struct usb_request, then
 207          * start it right away.
 208          *
 209          * If we're actually in a 2-stage transfer, we will wait for
 210          * XferNotReady(STATUS).
 211          */
 212         if (dwc->three_stage_setup) {
 213                 unsigned        direction;
 214
 215                 direction = dwc->ep0_expect_in;
 216                 dwc->ep0state = EP0_DATA_PHASE;
 217
 218                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 219
 220                 dep->flags &= ~DWC3_EP0_DIR_IN;
 221         }
 222
 223         return 0;
 224 }
 225
 226 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 227                 gfp_t gfp_flags)
 228 {
 229         struct dwc3_request             *req = to_dwc3_request(request);
 230         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 231         struct dwc3                     *dwc = dep->dwc;
 232
 233         unsigned long                   flags;
 234
 235         int                             ret;
 236
 237         spin_lock_irqsave(&dwc->lock, flags);
 238         if (!dep->endpoint.desc) {
 239                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 240                                 request, dep->name);
 241                 ret = -ESHUTDOWN;
 242                 goto out;
 243         }
 244
 245         /* we share one TRB for ep0/1 */
 246         if (!list_empty(&dep->request_list)) {
 247                 ret = -EBUSY;
 248                 goto out;
 249         }
 250
 251         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 252                         request, dep->name, request->length,
 253                         dwc3_ep0_state_string(dwc->ep0state));
 254
 255         ret = __dwc3_gadget_ep0_queue(dep, req);
 256
 257 out:
 258         spin_unlock_irqrestore(&dwc->lock, flags);
 259
 260         return ret;
 261 }
 262
 263 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 264 {
 265         struct dwc3_ep          *dep;
 266
 267         /* reinitialize physical ep1 */
 268         dep = dwc->eps[1];
 269         dep->flags = DWC3_EP_ENABLED;
 270
 271         /* stall is always issued on EP0 */
 272         dep = dwc->eps[0];
 273         __dwc3_gadget_ep_set_halt(dep, 1);
 274         dep->flags = DWC3_EP_ENABLED;
 275         dwc->delayed_status = false;
 276
 277         if (!list_empty(&dep->request_list)) {
 278                 struct dwc3_request     *req;
 279
 280                 req = next_request(&dep->request_list);
 281                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 282         }
 283
 284         dwc->ep0state = EP0_SETUP_PHASE;
 285         dwc3_ep0_out_start(dwc);
 286 }
 287
 288 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 289 {
 290         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 291         struct dwc3                     *dwc = dep->dwc;
 292
 293         dwc3_ep0_stall_and_restart(dwc);
 294
 295         return 0;
 296 }
 297
 298 void dwc3_ep0_out_start(struct dwc3 *dwc)
 299 {
 300         int                             ret;
 301
 302         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 303                         DWC3_TRBCTL_CONTROL_SETUP);
 304         WARN_ON(ret < 0);
 305 }
 306
 307 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 308 {
 309         struct dwc3_ep          *dep;
 310         u32                     windex = le16_to_cpu(wIndex_le);
 311         u32                     epnum;
 312
 313         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 314         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 315                 epnum |= 1;
 316
 317         dep = dwc->eps[epnum];
 318         if (dep->flags & DWC3_EP_ENABLED)
 319                 return dep;
 320
 321         return NULL;
 322 }
 323
 324 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 325 {
 326 }
 327 /*
 328  * ch 9.4.5
 329  */
 330 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 331                 struct usb_ctrlrequest *ctrl)
 332 {
 333         struct dwc3_ep          *dep;
 334         u32                     recip;
 335         u32                     reg;
 336         u16                     usb_status = 0;
 337         __le16                  *response_pkt;
 338
 339         recip = ctrl->bRequestType & USB_RECIP_MASK;
 340         switch (recip) {
 341         case USB_RECIP_DEVICE:
 342                 /*
 343                  * LTM will be set once we know how to set this in HW.
 344                  */
 345                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 346
 347                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 348                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 349                         if (reg & DWC3_DCTL_INITU1ENA)
 350                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 351                         if (reg & DWC3_DCTL_INITU2ENA)
 352                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 353                 }
 354
 355                 break;
 356
 357         case USB_RECIP_INTERFACE:
 358                 /*
 359                  * Function Remote Wake Capable D0
 360                  * Function Remote Wakeup       D1
 361                  */
 362                 break;
 363
 364         case USB_RECIP_ENDPOINT:
 365                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 366                 if (!dep)
 367                         return -EINVAL;
 368
 369                 if (dep->flags & DWC3_EP_STALL)
 370                         usb_status = 1 << USB_ENDPOINT_HALT;
 371                 break;
 372         default:
 373                 return -EINVAL;
 374         };
 375
 376         response_pkt = (__le16 *) dwc->setup_buf;
 377         *response_pkt = cpu_to_le16(usb_status);
 378
 379         dep = dwc->eps[0];
 380         dwc->ep0_usb_req.dep = dep;
 381         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 382         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 383         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 384
 385         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 386 }
 387
 388 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 389                 struct usb_ctrlrequest *ctrl, int set)
 390 {
 391         struct dwc3_ep          *dep;
 392         u32                     recip;
 393         u32                     wValue;
 394         u32                     wIndex;
 395         u32                     reg;
 396         int                     ret;
 397         enum usb_device_state   state;
 398
 399         wValue = le16_to_cpu(ctrl->wValue);
 400         wIndex = le16_to_cpu(ctrl->wIndex);
 401         recip = ctrl->bRequestType & USB_RECIP_MASK;
 402         state = dwc->gadget.state;
 403
 404         switch (recip) {
 405         case USB_RECIP_DEVICE:
 406
 407                 switch (wValue) {
 408                 case USB_DEVICE_REMOTE_WAKEUP:
 409                         break;
 410                 /*
 411                  * 9.4.1 says only only for SS, in AddressState only for
 412                  * default control pipe
 413                  */
 414                 case USB_DEVICE_U1_ENABLE:
 415                         if (state != USB_STATE_CONFIGURED)
 416                                 return -EINVAL;
 417                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 418                                 return -EINVAL;
 419
 420                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 421                         if (set)
 422                                 reg |= DWC3_DCTL_INITU1ENA;
 423                         else
 424                                 reg &= ~DWC3_DCTL_INITU1ENA;
 425                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 426                         break;
 427
 428                 case USB_DEVICE_U2_ENABLE:
 429                         if (state != USB_STATE_CONFIGURED)
 430                                 return -EINVAL;
 431                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 432                                 return -EINVAL;
 433
 434                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 435                         if (set)
 436                                 reg |= DWC3_DCTL_INITU2ENA;
 437                         else
 438                                 reg &= ~DWC3_DCTL_INITU2ENA;
 439                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 440                         break;
 441
 442                 case USB_DEVICE_LTM_ENABLE:
 443                         return -EINVAL;
 444                         break;
 445
 446                 case USB_DEVICE_TEST_MODE:
 447                         if ((wIndex & 0xff) != 0)
 448                                 return -EINVAL;
 449                         if (!set)
 450                                 return -EINVAL;
 451
 452                         dwc->test_mode_nr = wIndex >> 8;
 453                         dwc->test_mode = true;
 454                         break;
 455                 default:
 456                         return -EINVAL;
 457                 }
 458                 break;
 459
 460         case USB_RECIP_INTERFACE:
 461                 switch (wValue) {
 462                 case USB_INTRF_FUNC_SUSPEND:
 463                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 464                                 /* XXX enable Low power suspend */
 465                                 ;
 466                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 467                                 /* XXX enable remote wakeup */
 468                                 ;
 469                         break;
 470                 default:
 471                         return -EINVAL;
 472                 }
 473                 break;
 474
 475         case USB_RECIP_ENDPOINT:
 476                 switch (wValue) {
 477                 case USB_ENDPOINT_HALT:
 478                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 479                         if (!dep)
 480                                 return -EINVAL;
 481                         ret = __dwc3_gadget_ep_set_halt(dep, set);
 482                         if (ret)
 483                                 return -EINVAL;
 484                         break;
 485                 default:
 486                         return -EINVAL;
 487                 }
 488                 break;
 489
 490         default:
 491                 return -EINVAL;
 492         };
 493
 494         return 0;
 495 }
 496
 497 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 498 {
 499         enum usb_device_state state = dwc->gadget.state;
 500         u32 addr;
 501         u32 reg;
 502
 503         addr = le16_to_cpu(ctrl->wValue);
 504         if (addr > 127) {
 505                 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
 506                 return -EINVAL;
 507         }
 508
 509         if (state == USB_STATE_CONFIGURED) {
 510                 dev_dbg(dwc->dev, "trying to set address when configured\n");
 511                 return -EINVAL;
 512         }
 513
 514         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 515         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 516         reg |= DWC3_DCFG_DEVADDR(addr);
 517         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 518
 519         if (addr)
 520                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 521         else
 522                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 523
 524         return 0;
 525 }
 526
 527 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 528 {
 529         int ret;
 530
 531         spin_unlock(&dwc->lock);
 532         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 533         spin_lock(&dwc->lock);
 534         return ret;
 535 }
 536
 537 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 538 {
 539         enum usb_device_state state = dwc->gadget.state;
 540         u32 cfg;
 541         int ret;
 542         u32 reg;
 543
 544         dwc->start_config_issued = false;
 545         cfg = le16_to_cpu(ctrl->wValue);
 546
 547         switch (state) {
 548         case USB_STATE_DEFAULT:
 549                 return -EINVAL;
 550                 break;
 551
 552         case USB_STATE_ADDRESS:
 553                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 554                 /* if the cfg matches and the cfg is non zero */
 555                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 556                         usb_gadget_set_state(&dwc->gadget,
 557                                         USB_STATE_CONFIGURED);
 558
 559                         /*
 560                          * Enable transition to U1/U2 state when
 561                          * nothing is pending from application.
 562                          */
 563                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 564                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 565                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 566
 567                         dwc->resize_fifos = true;
 568                         dev_dbg(dwc->dev, "resize fifos flag SET\n");
 569                 }
 570                 break;
 571
 572         case USB_STATE_CONFIGURED:
 573                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 574                 if (!cfg)
 575                         usb_gadget_set_state(&dwc->gadget,
 576                                         USB_STATE_ADDRESS);
 577                 break;
 578         default:
 579                 ret = -EINVAL;
 580         }
 581         return ret;
 582 }
 583
 584 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 585 {
 586         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 587         struct dwc3     *dwc = dep->dwc;
 588
 589         u32             param = 0;
 590         u32             reg;
 591
 592         struct timing {
 593                 u8      u1sel;
 594                 u8      u1pel;
 595                 u16     u2sel;
 596                 u16     u2pel;
 597         } __packed timing;
 598
 599         int             ret;
 600
 601         memcpy(&timing, req->buf, sizeof(timing));
 602
 603         dwc->u1sel = timing.u1sel;
 604         dwc->u1pel = timing.u1pel;
 605         dwc->u2sel = le16_to_cpu(timing.u2sel);
 606         dwc->u2pel = le16_to_cpu(timing.u2pel);
 607
 608         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 609         if (reg & DWC3_DCTL_INITU2ENA)
 610                 param = dwc->u2pel;
 611         if (reg & DWC3_DCTL_INITU1ENA)
 612                 param = dwc->u1pel;
 613
 614         /*
 615          * According to Synopsys Databook, if parameter is
 616          * greater than 125, a value of zero should be
 617          * programmed in the register.
 618          */
 619         if (param > 125)
 620                 param = 0;
 621
 622         /* now that we have the time, issue DGCMD Set Sel */
 623         ret = dwc3_send_gadget_generic_command(dwc,
 624                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 625         WARN_ON(ret < 0);
 626 }
 627
 628 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 629 {
 630         struct dwc3_ep  *dep;
 631         enum usb_device_state state = dwc->gadget.state;
 632         u16             wLength;
 633         u16             wValue;
 634
 635         if (state == USB_STATE_DEFAULT)
 636                 return -EINVAL;
 637
 638         wValue = le16_to_cpu(ctrl->wValue);
 639         wLength = le16_to_cpu(ctrl->wLength);
 640
 641         if (wLength != 6) {
 642                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 643                                 wLength);
 644                 return -EINVAL;
 645         }
 646
 647         /*
 648          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 649          * queue a usb_request for 6 bytes.
 650          *
 651          * Remember, though, this controller can't handle non-wMaxPacketSize
 652          * aligned transfers on the OUT direction, so we queue a request for
 653          * wMaxPacketSize instead.
 654          */
 655         dep = dwc->eps[0];
 656         dwc->ep0_usb_req.dep = dep;
 657         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 658         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 659         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 660
 661         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 662 }
 663
 664 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 665 {
 666         u16             wLength;
 667         u16             wValue;
 668         u16             wIndex;
 669
 670         wValue = le16_to_cpu(ctrl->wValue);
 671         wLength = le16_to_cpu(ctrl->wLength);
 672         wIndex = le16_to_cpu(ctrl->wIndex);
 673
 674         if (wIndex || wLength)
 675                 return -EINVAL;
 676
 677         /*
 678          * REVISIT It's unclear from Databook what to do with this
 679          * value. For now, just cache it.
 680          */
 681         dwc->isoch_delay = wValue;
 682
 683         return 0;
 684 }
 685
 686 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 687 {
 688         int ret;
 689
 690         switch (ctrl->bRequest) {
 691         case USB_REQ_GET_STATUS:
 692                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 693                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 694                 break;
 695         case USB_REQ_CLEAR_FEATURE:
 696                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 697                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 698                 break;
 699         case USB_REQ_SET_FEATURE:
 700                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 701                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 702                 break;
 703         case USB_REQ_SET_ADDRESS:
 704                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 705                 ret = dwc3_ep0_set_address(dwc, ctrl);
 706                 break;
 707         case USB_REQ_SET_CONFIGURATION:
 708                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 709                 ret = dwc3_ep0_set_config(dwc, ctrl);
 710                 break;
 711         case USB_REQ_SET_SEL:
 712                 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
 713                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 714                 break;
 715         case USB_REQ_SET_ISOCH_DELAY:
 716                 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
 717                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 718                 break;
 719         default:
 720                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 721                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 722                 break;
 723         };
 724
 725         return ret;
 726 }
 727
 728 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 729                 const struct dwc3_event_depevt *event)
 730 {
 731         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 732         int ret = -EINVAL;
 733         u32 len;
 734
 735         if (!dwc->gadget_driver)
 736                 goto out;
 737
 738         len = le16_to_cpu(ctrl->wLength);
 739         if (!len) {
 740                 dwc->three_stage_setup = false;
 741                 dwc->ep0_expect_in = false;
 742                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 743         } else {
 744                 dwc->three_stage_setup = true;
 745                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 746                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 747         }
 748
 749         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 750                 ret = dwc3_ep0_std_request(dwc, ctrl);
 751         else
 752                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 753
 754         if (ret == USB_GADGET_DELAYED_STATUS)
 755                 dwc->delayed_status = true;
 756
 757 out:
 758         if (ret < 0)
 759                 dwc3_ep0_stall_and_restart(dwc);
 760 }
 761
 762 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 763                 const struct dwc3_event_depevt *event)
 764 {
 765         struct dwc3_request     *r = NULL;
 766         struct usb_request      *ur;
 767         struct dwc3_trb         *trb;
 768         struct dwc3_ep          *ep0;
 769         u32                     transferred;
 770         u32                     status;
 771         u32                     length;
 772         u8                      epnum;
 773
 774         epnum = event->endpoint_number;
 775         ep0 = dwc->eps[0];
 776
 777         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 778
 779         r = next_request(&ep0->request_list);
 780         ur = &r->request;
 781
 782         trb = dwc->ep0_trb;
 783
 784         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 785         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 786                 dev_dbg(dwc->dev, "Setup Pending received\n");
 787
 788                 if (r)
 789                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 790
 791                 return;
 792         }
 793
 794         length = trb->size & DWC3_TRB_SIZE_MASK;
 795
 796         if (dwc->ep0_bounced) {
 797                 unsigned transfer_size = ur->length;
 798                 unsigned maxp = ep0->endpoint.maxpacket;
 799
 800                 transfer_size += (maxp - (transfer_size % maxp));
 801                 transferred = min_t(u32, ur->length,
 802                                 transfer_size - length);
 803                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 804         } else {
 805                 transferred = ur->length - length;
 806         }
 807
 808         ur->actual += transferred;
 809
 810         if ((epnum & 1) && ur->actual < ur->length) {
 811                 /* for some reason we did not get everything out */
 812
 813                 dwc3_ep0_stall_and_restart(dwc);
 814         } else {
 815                 /*
 816                  * handle the case where we have to send a zero packet. This
 817                  * seems to be case when req.length > maxpacket. Could it be?
 818                  */
 819                 if (r)
 820                         dwc3_gadget_giveback(ep0, r, 0);
 821         }
 822 }
 823
 824 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 825                 const struct dwc3_event_depevt *event)
 826 {
 827         struct dwc3_request     *r;
 828         struct dwc3_ep          *dep;
 829         struct dwc3_trb         *trb;
 830         u32                     status;
 831
 832         dep = dwc->eps[0];
 833         trb = dwc->ep0_trb;
 834
 835         if (!list_empty(&dep->request_list)) {
 836                 r = next_request(&dep->request_list);
 837
 838                 dwc3_gadget_giveback(dep, r, 0);
 839         }
 840
 841         if (dwc->test_mode) {
 842                 int ret;
 843
 844                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 845                 if (ret < 0) {
 846                         dev_dbg(dwc->dev, "Invalid Test #%d\n",
 847                                         dwc->test_mode_nr);
 848                         dwc3_ep0_stall_and_restart(dwc);
 849                         return;
 850                 }
 851         }
 852
 853         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 854         if (status == DWC3_TRBSTS_SETUP_PENDING)
 855                 dev_dbg(dwc->dev, "Setup Pending received\n");
 856
 857         dwc->ep0state = EP0_SETUP_PHASE;
 858         dwc3_ep0_out_start(dwc);
 859 }
 860
 861 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 862                         const struct dwc3_event_depevt *event)
 863 {
 864         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 865
 866         dep->flags &= ~DWC3_EP_BUSY;
 867         dep->resource_index = 0;
 868         dwc->setup_packet_pending = false;
 869
 870         switch (dwc->ep0state) {
 871         case EP0_SETUP_PHASE:
 872                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 873                 dwc3_ep0_inspect_setup(dwc, event);
 874                 break;
 875
 876         case EP0_DATA_PHASE:
 877                 dev_vdbg(dwc->dev, "Data Phase\n");
 878                 dwc3_ep0_complete_data(dwc, event);
 879                 break;
 880
 881         case EP0_STATUS_PHASE:
 882                 dev_vdbg(dwc->dev, "Status Phase\n");
 883                 dwc3_ep0_complete_status(dwc, event);
 884                 break;
 885         default:
 886                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 887         }
 888 }
 889
 890 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 891                 struct dwc3_ep *dep, struct dwc3_request *req)
 892 {
 893         int                     ret;
 894
 895         req->direction = !!dep->number;
 896
 897         if (req->request.length == 0) {
 898                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 899                                 dwc->ctrl_req_addr, 0,
 900                                 DWC3_TRBCTL_CONTROL_DATA);
 901         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 902                         && (dep->number == 0)) {
 903                 u32     transfer_size;
 904                 u32     maxpacket;
 905
 906                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 907                                 dep->number);
 908                 if (ret) {
 909                         dev_dbg(dwc->dev, "failed to map request\n");
 910                         return;
 911                 }
 912
 913                 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
 914
 915                 maxpacket = dep->endpoint.maxpacket;
 916                 transfer_size = roundup(req->request.length, maxpacket);
 917
 918                 dwc->ep0_bounced = true;
 919
 920                 /*
 921                  * REVISIT in case request length is bigger than
 922                  * DWC3_EP0_BOUNCE_SIZE we will need two chained
 923                  * TRBs to handle the transfer.
 924                  */
 925                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 926                                 dwc->ep0_bounce_addr, transfer_size,
 927                                 DWC3_TRBCTL_CONTROL_DATA);
 928         } else {
 929                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 930                                 dep->number);
 931                 if (ret) {
 932                         dev_dbg(dwc->dev, "failed to map request\n");
 933                         return;
 934                 }
 935
 936                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
 937                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
 938         }
 939
 940         WARN_ON(ret < 0);
 941 }
 942
 943 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
 944 {
 945         struct dwc3             *dwc = dep->dwc;
 946         u32                     type;
 947
 948         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 949                 : DWC3_TRBCTL_CONTROL_STATUS2;
 950
 951         return dwc3_ep0_start_trans(dwc, dep->number,
 952                         dwc->ctrl_req_addr, 0, type);
 953 }
 954
 955 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
 956 {
 957         if (dwc->resize_fifos) {
 958                 dev_dbg(dwc->dev, "starting to resize fifos\n");
 959                 dwc3_gadget_resize_tx_fifos(dwc);
 960                 dwc->resize_fifos = 0;
 961         }
 962
 963         WARN_ON(dwc3_ep0_start_control_status(dep));
 964 }
 965
 966 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 967                 const struct dwc3_event_depevt *event)
 968 {
 969         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 970
 971         __dwc3_ep0_do_control_status(dwc, dep);
 972 }
 973
 974 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
 975 {
 976         struct dwc3_gadget_ep_cmd_params params;
 977         u32                     cmd;
 978         int                     ret;
 979
 980         if (!dep->resource_index)
 981                 return;
 982
 983         cmd = DWC3_DEPCMD_ENDTRANSFER;
 984         cmd |= DWC3_DEPCMD_CMDIOC;
 985         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
 986         memset(&params, 0, sizeof(params));
 987         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 988         WARN_ON_ONCE(ret);
 989         dep->resource_index = 0;
 990 }
 991
 992 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 993                 const struct dwc3_event_depevt *event)
 994 {
 995         dwc->setup_packet_pending = true;
 996
 997         switch (event->status) {
 998         case DEPEVT_STATUS_CONTROL_DATA:
 999                 dev_vdbg(dwc->dev, "Control Data\n");
1000
1001                 /*
1002                  * We already have a DATA transfer in the controller's cache,
1003                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1004                  * it's for the wrong direction.
1005                  *
1006                  * In that case, we must issue END_TRANSFER command to the Data
1007                  * Phase we already have started and issue SetStall on the
1008                  * control endpoint.
1009                  */
1010                 if (dwc->ep0_expect_in != event->endpoint_number) {
1011                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1012
1013                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
1014                         dwc3_ep0_end_control_data(dwc, dep);
1015                         dwc3_ep0_stall_and_restart(dwc);
1016                         return;
1017                 }
1018
1019                 break;
1020
1021         case DEPEVT_STATUS_CONTROL_STATUS:
1022                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1023                         return;
1024
1025                 dev_vdbg(dwc->dev, "Control Status\n");
1026
1027                 dwc->ep0state = EP0_STATUS_PHASE;
1028
1029                 if (dwc->delayed_status) {
1030                         WARN_ON_ONCE(event->endpoint_number != 1);
1031                         dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
1032                         return;
1033                 }
1034
1035                 dwc3_ep0_do_control_status(dwc, event);
1036         }
1037 }
1038
1039 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1040                 const struct dwc3_event_depevt *event)
1041 {
1042         u8                      epnum = event->endpoint_number;
1043
1044         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
1045                         dwc3_ep_event_string(event->endpoint_event),
1046                         epnum >> 1, (epnum & 1) ? "in" : "out",
1047                         dwc3_ep0_state_string(dwc->ep0state));
1048
1049         switch (event->endpoint_event) {
1050         case DWC3_DEPEVT_XFERCOMPLETE:
1051                 dwc3_ep0_xfer_complete(dwc, event);
1052                 break;
1053
1054         case DWC3_DEPEVT_XFERNOTREADY:
1055                 dwc3_ep0_xfernotready(dwc, event);
1056                 break;
1057
1058         case DWC3_DEPEVT_XFERINPROGRESS:
1059         case DWC3_DEPEVT_RXTXFIFOEVT:
1060         case DWC3_DEPEVT_STREAMEVT:
1061         case DWC3_DEPEVT_EPCMDCMPLT:
1062                 break;
1063         }
1064 }