drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum,
  59                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  60 {
  61         struct dwc3_trb                 *trb;
  62         struct dwc3_ep                  *dep;
  63
  64         dep = dwc->eps[epnum];
  65
  66         trb = &dwc->ep0_trb[dep->trb_enqueue];
  67
  68         if (chain)
  69                 dep->trb_enqueue++;
  70
  71         trb->bpl = lower_32_bits(buf_dma);
  72         trb->bph = upper_32_bits(buf_dma);
  73         trb->size = len;
  74         trb->ctrl = type;
  75
  76         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  77                         | DWC3_TRB_CTRL_ISP_IMI);
  78
  79         if (chain)
  80                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  81         else
  82                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  83                                 | DWC3_TRB_CTRL_LST);
  84
  85         trace_dwc3_prepare_trb(dep, trb);
  86 }
  87
  88 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum)
  89 {
  90         struct dwc3_gadget_ep_cmd_params params;
  91         struct dwc3_ep                  *dep;
  92         int                             ret;
  93
  94         dep = dwc->eps[epnum];
  95         if (dep->flags & DWC3_EP_BUSY) {
  96                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  97                 return 0;
  98         }
  99
 100         memset(&params, 0, sizeof(params));
 101         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 102         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 103
 104         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
 105         if (ret < 0) {
 106                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
 107                                 dep->name);
 108                 return ret;
 109         }
 110
 111         dep->flags |= DWC3_EP_BUSY;
 112         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
 113         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 114
 115         return 0;
 116 }
 117
 118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 119                 struct dwc3_request *req)
 120 {
 121         struct dwc3             *dwc = dep->dwc;
 122
 123         req->request.actual     = 0;
 124         req->request.status     = -EINPROGRESS;
 125         req->epnum              = dep->number;
 126
 127         list_add_tail(&req->list, &dep->pending_list);
 128
 129         /*
 130          * Gadget driver might not be quick enough to queue a request
 131          * before we get a Transfer Not Ready event on this endpoint.
 132          *
 133          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 134          * flag is set, it's telling us that as soon as Gadget queues the
 135          * required request, we should kick the transfer here because the
 136          * IRQ we were waiting for is long gone.
 137          */
 138         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 139                 unsigned        direction;
 140
 141                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 142
 143                 if (dwc->ep0state != EP0_DATA_PHASE) {
 144                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 145                         return 0;
 146                 }
 147
 148                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 149
 150                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 151                                 DWC3_EP0_DIR_IN);
 152
 153                 return 0;
 154         }
 155
 156         /*
 157          * In case gadget driver asked us to delay the STATUS phase,
 158          * handle it here.
 159          */
 160         if (dwc->delayed_status) {
 161                 unsigned        direction;
 162
 163                 direction = !dwc->ep0_expect_in;
 164                 dwc->delayed_status = false;
 165                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 166
 167                 if (dwc->ep0state == EP0_STATUS_PHASE)
 168                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 169                 else
 170                         dwc3_trace(trace_dwc3_ep0,
 171                                         "too early for delayed status");
 172
 173                 return 0;
 174         }
 175
 176         /*
 177          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 178          *
 179          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 180          * come before issueing Start Transfer command, but if we do, we will
 181          * miss situations where the host starts another SETUP phase instead of
 182          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 183          * Layer Compliance Suite.
 184          *
 185          * The problem surfaces due to the fact that in case of back-to-back
 186          * SETUP packets there will be no XferNotReady(DATA) generated and we
 187          * will be stuck waiting for XferNotReady(DATA) forever.
 188          *
 189          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 190          * it tells us to start Data Phase right away. It also mentions that if
 191          * we receive a SETUP phase instead of the DATA phase, core will issue
 192          * XferComplete for the DATA phase, before actually initiating it in
 193          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 194          * can only be used to print some debugging logs, as the core expects
 195          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 196          * just so it completes right away, without transferring anything and,
 197          * only then, we can go back to the SETUP phase.
 198          *
 199          * Because of this scenario, SNPS decided to change the programming
 200          * model of control transfers and support on-demand transfers only for
 201          * the STATUS phase. To fix the issue we have now, we will always wait
 202          * for gadget driver to queue the DATA phase's struct usb_request, then
 203          * start it right away.
 204          *
 205          * If we're actually in a 2-stage transfer, we will wait for
 206          * XferNotReady(STATUS).
 207          */
 208         if (dwc->three_stage_setup) {
 209                 unsigned        direction;
 210
 211                 direction = dwc->ep0_expect_in;
 212                 dwc->ep0state = EP0_DATA_PHASE;
 213
 214                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 215
 216                 dep->flags &= ~DWC3_EP0_DIR_IN;
 217         }
 218
 219         return 0;
 220 }
 221
 222 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 223                 gfp_t gfp_flags)
 224 {
 225         struct dwc3_request             *req = to_dwc3_request(request);
 226         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 227         struct dwc3                     *dwc = dep->dwc;
 228
 229         unsigned long                   flags;
 230
 231         int                             ret;
 232
 233         spin_lock_irqsave(&dwc->lock, flags);
 234         if (!dep->endpoint.desc) {
 235                 dwc3_trace(trace_dwc3_ep0,
 236                                 "trying to queue request %p to disabled %s",
 237                                 request, dep->name);
 238                 ret = -ESHUTDOWN;
 239                 goto out;
 240         }
 241
 242         /* we share one TRB for ep0/1 */
 243         if (!list_empty(&dep->pending_list)) {
 244                 ret = -EBUSY;
 245                 goto out;
 246         }
 247
 248         dwc3_trace(trace_dwc3_ep0,
 249                         "queueing request %p to %s length %d state '%s'",
 250                         request, dep->name, request->length,
 251                         dwc3_ep0_state_string(dwc->ep0state));
 252
 253         ret = __dwc3_gadget_ep0_queue(dep, req);
 254
 255 out:
 256         spin_unlock_irqrestore(&dwc->lock, flags);
 257
 258         return ret;
 259 }
 260
 261 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 262 {
 263         struct dwc3_ep          *dep;
 264
 265         /* reinitialize physical ep1 */
 266         dep = dwc->eps[1];
 267         dep->flags = DWC3_EP_ENABLED;
 268
 269         /* stall is always issued on EP0 */
 270         dep = dwc->eps[0];
 271         __dwc3_gadget_ep_set_halt(dep, 1, false);
 272         dep->flags = DWC3_EP_ENABLED;
 273         dwc->delayed_status = false;
 274
 275         if (!list_empty(&dep->pending_list)) {
 276                 struct dwc3_request     *req;
 277
 278                 req = next_request(&dep->pending_list);
 279                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 280         }
 281
 282         dwc->ep0state = EP0_SETUP_PHASE;
 283         dwc3_ep0_out_start(dwc);
 284 }
 285
 286 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 287 {
 288         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 289         struct dwc3                     *dwc = dep->dwc;
 290
 291         dwc3_ep0_stall_and_restart(dwc);
 292
 293         return 0;
 294 }
 295
 296 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 297 {
 298         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 299         struct dwc3                     *dwc = dep->dwc;
 300         unsigned long                   flags;
 301         int                             ret;
 302
 303         spin_lock_irqsave(&dwc->lock, flags);
 304         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 305         spin_unlock_irqrestore(&dwc->lock, flags);
 306
 307         return ret;
 308 }
 309
 310 void dwc3_ep0_out_start(struct dwc3 *dwc)
 311 {
 312         int                             ret;
 313
 314         dwc3_ep0_prepare_one_trb(dwc, 0, dwc->ctrl_req_addr, 8,
 315                         DWC3_TRBCTL_CONTROL_SETUP, false);
 316         ret = dwc3_ep0_start_trans(dwc, 0);
 317         WARN_ON(ret < 0);
 318 }
 319
 320 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 321 {
 322         struct dwc3_ep          *dep;
 323         u32                     windex = le16_to_cpu(wIndex_le);
 324         u32                     epnum;
 325
 326         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 327         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 328                 epnum |= 1;
 329
 330         dep = dwc->eps[epnum];
 331         if (dep->flags & DWC3_EP_ENABLED)
 332                 return dep;
 333
 334         return NULL;
 335 }
 336
 337 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 338 {
 339 }
 340 /*
 341  * ch 9.4.5
 342  */
 343 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 344                 struct usb_ctrlrequest *ctrl)
 345 {
 346         struct dwc3_ep          *dep;
 347         u32                     recip;
 348         u32                     reg;
 349         u16                     usb_status = 0;
 350         __le16                  *response_pkt;
 351
 352         recip = ctrl->bRequestType & USB_RECIP_MASK;
 353         switch (recip) {
 354         case USB_RECIP_DEVICE:
 355                 /*
 356                  * LTM will be set once we know how to set this in HW.
 357                  */
 358                 usb_status |= dwc->gadget.is_selfpowered;
 359
 360                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 361                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 362                         if (reg & DWC3_DCTL_INITU1ENA)
 363                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 364                         if (reg & DWC3_DCTL_INITU2ENA)
 365                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 366                 }
 367
 368                 break;
 369
 370         case USB_RECIP_INTERFACE:
 371                 /*
 372                  * Function Remote Wake Capable D0
 373                  * Function Remote Wakeup       D1
 374                  */
 375                 break;
 376
 377         case USB_RECIP_ENDPOINT:
 378                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 379                 if (!dep)
 380                         return -EINVAL;
 381
 382                 if (dep->flags & DWC3_EP_STALL)
 383                         usb_status = 1 << USB_ENDPOINT_HALT;
 384                 break;
 385         default:
 386                 return -EINVAL;
 387         }
 388
 389         response_pkt = (__le16 *) dwc->setup_buf;
 390         *response_pkt = cpu_to_le16(usb_status);
 391
 392         dep = dwc->eps[0];
 393         dwc->ep0_usb_req.dep = dep;
 394         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 395         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 396         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 397
 398         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 399 }
 400
 401 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 402                 struct usb_ctrlrequest *ctrl, int set)
 403 {
 404         struct dwc3_ep          *dep;
 405         u32                     recip;
 406         u32                     wValue;
 407         u32                     wIndex;
 408         u32                     reg;
 409         int                     ret;
 410         enum usb_device_state   state;
 411
 412         wValue = le16_to_cpu(ctrl->wValue);
 413         wIndex = le16_to_cpu(ctrl->wIndex);
 414         recip = ctrl->bRequestType & USB_RECIP_MASK;
 415         state = dwc->gadget.state;
 416
 417         switch (recip) {
 418         case USB_RECIP_DEVICE:
 419
 420                 switch (wValue) {
 421                 case USB_DEVICE_REMOTE_WAKEUP:
 422                         break;
 423                 /*
 424                  * 9.4.1 says only only for SS, in AddressState only for
 425                  * default control pipe
 426                  */
 427                 case USB_DEVICE_U1_ENABLE:
 428                         if (state != USB_STATE_CONFIGURED)
 429                                 return -EINVAL;
 430                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 431                                 return -EINVAL;
 432
 433                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 434                         if (set)
 435                                 reg |= DWC3_DCTL_INITU1ENA;
 436                         else
 437                                 reg &= ~DWC3_DCTL_INITU1ENA;
 438                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 439                         break;
 440
 441                 case USB_DEVICE_U2_ENABLE:
 442                         if (state != USB_STATE_CONFIGURED)
 443                                 return -EINVAL;
 444                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 445                                 return -EINVAL;
 446
 447                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 448                         if (set)
 449                                 reg |= DWC3_DCTL_INITU2ENA;
 450                         else
 451                                 reg &= ~DWC3_DCTL_INITU2ENA;
 452                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 453                         break;
 454
 455                 case USB_DEVICE_LTM_ENABLE:
 456                         return -EINVAL;
 457
 458                 case USB_DEVICE_TEST_MODE:
 459                         if ((wIndex & 0xff) != 0)
 460                                 return -EINVAL;
 461                         if (!set)
 462                                 return -EINVAL;
 463
 464                         switch (wIndex >> 8) {
 465                         case TEST_J:
 466                         case TEST_K:
 467                         case TEST_SE0_NAK:
 468                         case TEST_PACKET:
 469                         case TEST_FORCE_EN:
 470                                 dwc->test_mode_nr = wIndex >> 8;
 471                                 dwc->test_mode = true;
 472                                 break;
 473                         default:
 474                                 return -EINVAL;
 475                         }
 476                         break;
 477                 default:
 478                         return -EINVAL;
 479                 }
 480                 break;
 481
 482         case USB_RECIP_INTERFACE:
 483                 switch (wValue) {
 484                 case USB_INTRF_FUNC_SUSPEND:
 485                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 486                                 /* XXX enable Low power suspend */
 487                                 ;
 488                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 489                                 /* XXX enable remote wakeup */
 490                                 ;
 491                         break;
 492                 default:
 493                         return -EINVAL;
 494                 }
 495                 break;
 496
 497         case USB_RECIP_ENDPOINT:
 498                 switch (wValue) {
 499                 case USB_ENDPOINT_HALT:
 500                         dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 501                         if (!dep)
 502                                 return -EINVAL;
 503                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 504                                 break;
 505                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 506                         if (ret)
 507                                 return -EINVAL;
 508                         break;
 509                 default:
 510                         return -EINVAL;
 511                 }
 512                 break;
 513
 514         default:
 515                 return -EINVAL;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 522 {
 523         enum usb_device_state state = dwc->gadget.state;
 524         u32 addr;
 525         u32 reg;
 526
 527         addr = le16_to_cpu(ctrl->wValue);
 528         if (addr > 127) {
 529                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 530                 return -EINVAL;
 531         }
 532
 533         if (state == USB_STATE_CONFIGURED) {
 534                 dwc3_trace(trace_dwc3_ep0,
 535                                 "trying to set address when configured");
 536                 return -EINVAL;
 537         }
 538
 539         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 540         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 541         reg |= DWC3_DCFG_DEVADDR(addr);
 542         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 543
 544         if (addr)
 545                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 546         else
 547                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 548
 549         return 0;
 550 }
 551
 552 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 553 {
 554         int ret;
 555
 556         spin_unlock(&dwc->lock);
 557         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 558         spin_lock(&dwc->lock);
 559         return ret;
 560 }
 561
 562 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 563 {
 564         enum usb_device_state state = dwc->gadget.state;
 565         u32 cfg;
 566         int ret;
 567         u32 reg;
 568
 569         cfg = le16_to_cpu(ctrl->wValue);
 570
 571         switch (state) {
 572         case USB_STATE_DEFAULT:
 573                 return -EINVAL;
 574
 575         case USB_STATE_ADDRESS:
 576                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 577                 /* if the cfg matches and the cfg is non zero */
 578                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 579
 580                         /*
 581                          * only change state if set_config has already
 582                          * been processed. If gadget driver returns
 583                          * USB_GADGET_DELAYED_STATUS, we will wait
 584                          * to change the state on the next usb_ep_queue()
 585                          */
 586                         if (ret == 0)
 587                                 usb_gadget_set_state(&dwc->gadget,
 588                                                 USB_STATE_CONFIGURED);
 589
 590                         /*
 591                          * Enable transition to U1/U2 state when
 592                          * nothing is pending from application.
 593                          */
 594                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 595                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 596                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 597                 }
 598                 break;
 599
 600         case USB_STATE_CONFIGURED:
 601                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 602                 if (!cfg && !ret)
 603                         usb_gadget_set_state(&dwc->gadget,
 604                                         USB_STATE_ADDRESS);
 605                 break;
 606         default:
 607                 ret = -EINVAL;
 608         }
 609         return ret;
 610 }
 611
 612 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 613 {
 614         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 615         struct dwc3     *dwc = dep->dwc;
 616
 617         u32             param = 0;
 618         u32             reg;
 619
 620         struct timing {
 621                 u8      u1sel;
 622                 u8      u1pel;
 623                 __le16  u2sel;
 624                 __le16  u2pel;
 625         } __packed timing;
 626
 627         int             ret;
 628
 629         memcpy(&timing, req->buf, sizeof(timing));
 630
 631         dwc->u1sel = timing.u1sel;
 632         dwc->u1pel = timing.u1pel;
 633         dwc->u2sel = le16_to_cpu(timing.u2sel);
 634         dwc->u2pel = le16_to_cpu(timing.u2pel);
 635
 636         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 637         if (reg & DWC3_DCTL_INITU2ENA)
 638                 param = dwc->u2pel;
 639         if (reg & DWC3_DCTL_INITU1ENA)
 640                 param = dwc->u1pel;
 641
 642         /*
 643          * According to Synopsys Databook, if parameter is
 644          * greater than 125, a value of zero should be
 645          * programmed in the register.
 646          */
 647         if (param > 125)
 648                 param = 0;
 649
 650         /* now that we have the time, issue DGCMD Set Sel */
 651         ret = dwc3_send_gadget_generic_command(dwc,
 652                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 653         WARN_ON(ret < 0);
 654 }
 655
 656 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 657 {
 658         struct dwc3_ep  *dep;
 659         enum usb_device_state state = dwc->gadget.state;
 660         u16             wLength;
 661         u16             wValue;
 662
 663         if (state == USB_STATE_DEFAULT)
 664                 return -EINVAL;
 665
 666         wValue = le16_to_cpu(ctrl->wValue);
 667         wLength = le16_to_cpu(ctrl->wLength);
 668
 669         if (wLength != 6) {
 670                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 671                                 wLength);
 672                 return -EINVAL;
 673         }
 674
 675         /*
 676          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 677          * queue a usb_request for 6 bytes.
 678          *
 679          * Remember, though, this controller can't handle non-wMaxPacketSize
 680          * aligned transfers on the OUT direction, so we queue a request for
 681          * wMaxPacketSize instead.
 682          */
 683         dep = dwc->eps[0];
 684         dwc->ep0_usb_req.dep = dep;
 685         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 686         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 687         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 688
 689         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 690 }
 691
 692 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 693 {
 694         u16             wLength;
 695         u16             wValue;
 696         u16             wIndex;
 697
 698         wValue = le16_to_cpu(ctrl->wValue);
 699         wLength = le16_to_cpu(ctrl->wLength);
 700         wIndex = le16_to_cpu(ctrl->wIndex);
 701
 702         if (wIndex || wLength)
 703                 return -EINVAL;
 704
 705         /*
 706          * REVISIT It's unclear from Databook what to do with this
 707          * value. For now, just cache it.
 708          */
 709         dwc->isoch_delay = wValue;
 710
 711         return 0;
 712 }
 713
 714 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 715 {
 716         int ret;
 717
 718         switch (ctrl->bRequest) {
 719         case USB_REQ_GET_STATUS:
 720                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 721                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 722                 break;
 723         case USB_REQ_CLEAR_FEATURE:
 724                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 725                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 726                 break;
 727         case USB_REQ_SET_FEATURE:
 728                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 729                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 730                 break;
 731         case USB_REQ_SET_ADDRESS:
 732                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 733                 ret = dwc3_ep0_set_address(dwc, ctrl);
 734                 break;
 735         case USB_REQ_SET_CONFIGURATION:
 736                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 737                 ret = dwc3_ep0_set_config(dwc, ctrl);
 738                 break;
 739         case USB_REQ_SET_SEL:
 740                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 741                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 742                 break;
 743         case USB_REQ_SET_ISOCH_DELAY:
 744                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 745                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 746                 break;
 747         default:
 748                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 749                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 750                 break;
 751         }
 752
 753         return ret;
 754 }
 755
 756 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 757                 const struct dwc3_event_depevt *event)
 758 {
 759         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 760         int ret = -EINVAL;
 761         u32 len;
 762
 763         if (!dwc->gadget_driver)
 764                 goto out;
 765
 766         trace_dwc3_ctrl_req(ctrl);
 767
 768         len = le16_to_cpu(ctrl->wLength);
 769         if (!len) {
 770                 dwc->three_stage_setup = false;
 771                 dwc->ep0_expect_in = false;
 772                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 773         } else {
 774                 dwc->three_stage_setup = true;
 775                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 776                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 777         }
 778
 779         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 780                 ret = dwc3_ep0_std_request(dwc, ctrl);
 781         else
 782                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 783
 784         if (ret == USB_GADGET_DELAYED_STATUS)
 785                 dwc->delayed_status = true;
 786
 787 out:
 788         if (ret < 0)
 789                 dwc3_ep0_stall_and_restart(dwc);
 790 }
 791
 792 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 793                 const struct dwc3_event_depevt *event)
 794 {
 795         struct dwc3_request     *r = NULL;
 796         struct usb_request      *ur;
 797         struct dwc3_trb         *trb;
 798         struct dwc3_ep          *ep0;
 799         unsigned                transfer_size = 0;
 800         unsigned                maxp;
 801         unsigned                remaining_ur_length;
 802         void                    *buf;
 803         u32                     transferred = 0;
 804         u32                     status;
 805         u32                     length;
 806         u8                      epnum;
 807
 808         epnum = event->endpoint_number;
 809         ep0 = dwc->eps[0];
 810
 811         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 812
 813         trb = dwc->ep0_trb;
 814
 815         trace_dwc3_complete_trb(ep0, trb);
 816
 817         r = next_request(&ep0->pending_list);
 818         if (!r)
 819                 return;
 820
 821         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 822         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 823                 dwc->setup_packet_pending = true;
 824
 825                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 826
 827                 if (r)
 828                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 829
 830                 return;
 831         }
 832
 833         ur = &r->request;
 834         buf = ur->buf;
 835         remaining_ur_length = ur->length;
 836
 837         length = trb->size & DWC3_TRB_SIZE_MASK;
 838
 839         maxp = ep0->endpoint.maxpacket;
 840
 841         if (dwc->ep0_bounced) {
 842                 /*
 843                  * Handle the first TRB before handling the bounce buffer if
 844                  * the request length is greater than the bounce buffer size
 845                  */
 846                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 847                         transfer_size = ALIGN(ur->length - maxp, maxp);
 848                         transferred = transfer_size - length;
 849                         buf = (u8 *)buf + transferred;
 850                         ur->actual += transferred;
 851                         remaining_ur_length -= transferred;
 852
 853                         trb++;
 854                         length = trb->size & DWC3_TRB_SIZE_MASK;
 855
 856                         ep0->trb_enqueue = 0;
 857                 }
 858
 859                 transfer_size = roundup((ur->length - transfer_size),
 860                                         maxp);
 861
 862                 transferred = min_t(u32, remaining_ur_length,
 863                                     transfer_size - length);
 864                 memcpy(buf, dwc->ep0_bounce, transferred);
 865         } else {
 866                 transferred = ur->length - length;
 867         }
 868
 869         ur->actual += transferred;
 870
 871         if ((epnum & 1) && ur->actual < ur->length) {
 872                 /* for some reason we did not get everything out */
 873
 874                 dwc3_ep0_stall_and_restart(dwc);
 875         } else {
 876                 dwc3_gadget_giveback(ep0, r, 0);
 877
 878                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 879                                 ur->length && ur->zero) {
 880                         int ret;
 881
 882                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 883
 884                         dwc3_ep0_prepare_one_trb(dwc, epnum, dwc->ctrl_req_addr,
 885                                         0, DWC3_TRBCTL_CONTROL_DATA, false);
 886                         ret = dwc3_ep0_start_trans(dwc, epnum);
 887                         WARN_ON(ret < 0);
 888                 }
 889         }
 890 }
 891
 892 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 893                 const struct dwc3_event_depevt *event)
 894 {
 895         struct dwc3_request     *r;
 896         struct dwc3_ep          *dep;
 897         struct dwc3_trb         *trb;
 898         u32                     status;
 899
 900         dep = dwc->eps[0];
 901         trb = dwc->ep0_trb;
 902
 903         trace_dwc3_complete_trb(dep, trb);
 904
 905         if (!list_empty(&dep->pending_list)) {
 906                 r = next_request(&dep->pending_list);
 907
 908                 dwc3_gadget_giveback(dep, r, 0);
 909         }
 910
 911         if (dwc->test_mode) {
 912                 int ret;
 913
 914                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 915                 if (ret < 0) {
 916                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 917                                         dwc->test_mode_nr);
 918                         dwc3_ep0_stall_and_restart(dwc);
 919                         return;
 920                 }
 921         }
 922
 923         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 924         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 925                 dwc->setup_packet_pending = true;
 926                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 927         }
 928
 929         dwc->ep0state = EP0_SETUP_PHASE;
 930         dwc3_ep0_out_start(dwc);
 931 }
 932
 933 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 934                         const struct dwc3_event_depevt *event)
 935 {
 936         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 937
 938         dep->flags &= ~DWC3_EP_BUSY;
 939         dep->resource_index = 0;
 940         dwc->setup_packet_pending = false;
 941
 942         switch (dwc->ep0state) {
 943         case EP0_SETUP_PHASE:
 944                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 945                 dwc3_ep0_inspect_setup(dwc, event);
 946                 break;
 947
 948         case EP0_DATA_PHASE:
 949                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 950                 dwc3_ep0_complete_data(dwc, event);
 951                 break;
 952
 953         case EP0_STATUS_PHASE:
 954                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 955                 dwc3_ep0_complete_status(dwc, event);
 956                 break;
 957         default:
 958                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 959         }
 960 }
 961
 962 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 963                 struct dwc3_ep *dep, struct dwc3_request *req)
 964 {
 965         int                     ret;
 966
 967         req->direction = !!dep->number;
 968
 969         if (req->request.length == 0) {
 970                 dwc3_ep0_prepare_one_trb(dwc, dep->number,
 971                                 dwc->ctrl_req_addr, 0,
 972                                 DWC3_TRBCTL_CONTROL_DATA, false);
 973                 ret = dwc3_ep0_start_trans(dwc, dep->number);
 974         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 975                         && (dep->number == 0)) {
 976                 u32     transfer_size = 0;
 977                 u32     maxpacket;
 978
 979                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 980                                 dep->number);
 981                 if (ret) {
 982                         dwc3_trace(trace_dwc3_ep0, "failed to map request");
 983                         return;
 984                 }
 985
 986                 maxpacket = dep->endpoint.maxpacket;
 987
 988                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
 989                         transfer_size = ALIGN(req->request.length - maxpacket,
 990                                               maxpacket);
 991                         dwc3_ep0_prepare_one_trb(dwc, dep->number,
 992                                                    req->request.dma,
 993                                                    transfer_size,
 994                                                    DWC3_TRBCTL_CONTROL_DATA,
 995                                                    true);
 996                 }
 997
 998                 transfer_size = roundup((req->request.length - transfer_size),
 999                                         maxpacket);
1000
1001                 dwc->ep0_bounced = true;
1002
1003                 dwc3_ep0_prepare_one_trb(dwc, dep->number,
1004                                 dwc->ep0_bounce_addr, transfer_size,
1005                                 DWC3_TRBCTL_CONTROL_DATA, false);
1006                 ret = dwc3_ep0_start_trans(dwc, dep->number);
1007         } else {
1008                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1009                                 dep->number);
1010                 if (ret) {
1011                         dwc3_trace(trace_dwc3_ep0, "failed to map request");
1012                         return;
1013                 }
1014
1015                 dwc3_ep0_prepare_one_trb(dwc, dep->number, req->request.dma,
1016                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1017                                 false);
1018                 ret = dwc3_ep0_start_trans(dwc, dep->number);
1019         }
1020
1021         WARN_ON(ret < 0);
1022 }
1023
1024 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1025 {
1026         struct dwc3             *dwc = dep->dwc;
1027         u32                     type;
1028
1029         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1030                 : DWC3_TRBCTL_CONTROL_STATUS2;
1031
1032         dwc3_ep0_prepare_one_trb(dwc, dep->number,
1033                         dwc->ctrl_req_addr, 0, type, false);
1034         return dwc3_ep0_start_trans(dwc, dep->number);
1035 }
1036
1037 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1038 {
1039         WARN_ON(dwc3_ep0_start_control_status(dep));
1040 }
1041
1042 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1043                 const struct dwc3_event_depevt *event)
1044 {
1045         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1046
1047         __dwc3_ep0_do_control_status(dwc, dep);
1048 }
1049
1050 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1051 {
1052         struct dwc3_gadget_ep_cmd_params params;
1053         u32                     cmd;
1054         int                     ret;
1055
1056         if (!dep->resource_index)
1057                 return;
1058
1059         cmd = DWC3_DEPCMD_ENDTRANSFER;
1060         cmd |= DWC3_DEPCMD_CMDIOC;
1061         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1062         memset(&params, 0, sizeof(params));
1063         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1064         WARN_ON_ONCE(ret);
1065         dep->resource_index = 0;
1066 }
1067
1068 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1069                 const struct dwc3_event_depevt *event)
1070 {
1071         switch (event->status) {
1072         case DEPEVT_STATUS_CONTROL_DATA:
1073                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1074
1075                 /*
1076                  * We already have a DATA transfer in the controller's cache,
1077                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1078                  * it's for the wrong direction.
1079                  *
1080                  * In that case, we must issue END_TRANSFER command to the Data
1081                  * Phase we already have started and issue SetStall on the
1082                  * control endpoint.
1083                  */
1084                 if (dwc->ep0_expect_in != event->endpoint_number) {
1085                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1086
1087                         dwc3_trace(trace_dwc3_ep0,
1088                                         "Wrong direction for Data phase");
1089                         dwc3_ep0_end_control_data(dwc, dep);
1090                         dwc3_ep0_stall_and_restart(dwc);
1091                         return;
1092                 }
1093
1094                 break;
1095
1096         case DEPEVT_STATUS_CONTROL_STATUS:
1097                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1098                         return;
1099
1100                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1101
1102                 dwc->ep0state = EP0_STATUS_PHASE;
1103
1104                 if (dwc->delayed_status) {
1105                         WARN_ON_ONCE(event->endpoint_number != 1);
1106                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1107                         return;
1108                 }
1109
1110                 dwc3_ep0_do_control_status(dwc, event);
1111         }
1112 }
1113
1114 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1115                 const struct dwc3_event_depevt *event)
1116 {
1117         dwc3_trace(trace_dwc3_ep0, "%s: state '%s'",
1118                         dwc3_ep_event_string(event),
1119                         dwc3_ep0_state_string(dwc->ep0state));
1120
1121         switch (event->endpoint_event) {
1122         case DWC3_DEPEVT_XFERCOMPLETE:
1123                 dwc3_ep0_xfer_complete(dwc, event);
1124                 break;
1125
1126         case DWC3_DEPEVT_XFERNOTREADY:
1127                 dwc3_ep0_xfernotready(dwc, event);
1128                 break;
1129
1130         case DWC3_DEPEVT_XFERINPROGRESS:
1131         case DWC3_DEPEVT_RXTXFIFOEVT:
1132         case DWC3_DEPEVT_STREAMEVT:
1133         case DWC3_DEPEVT_EPCMDCMPLT:
1134                 break;
1135         }
1136 }