drivers/usb/dwc3/dwc3-rockchip.c

   1 /**
   2  * dwc3-rockchip.c - Rockchip Specific Glue layer
   3  *
   4  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   5  *
   6  * Authors: William Wu <william.wu@rock-chips.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2  of
  10  * the License as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/debugfs.h>
  27 #include <linux/of.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/extcon.h>
  31 #include <linux/freezer.h>
  32 #include <linux/iopoll.h>
  33 #include <linux/reset.h>
  34 #include <linux/uaccess.h>
  35 #include <linux/usb.h>
  36 #include <linux/usb/hcd.h>
  37 #include <linux/usb/ch9.h>
  38
  39 #include "core.h"
  40 #include "io.h"
  41 #include "../host/xhci.h"
  42
  43 #define DWC3_ROCKCHIP_AUTOSUSPEND_DELAY 500 /* ms */
  44 #define PERIPHERAL_DISCONNECT_TIMEOUT   1000000 /* us */
  45 #define WAIT_FOR_HCD_READY_TIMEOUT      5000000 /* us */
  46 #define XHCI_TSTCTRL_MASK               (0xf << 28)
  47
  48 struct dwc3_rockchip {
  49         int                     num_clocks;
  50         bool                    connected;
  51         bool                    skip_suspend;
  52         bool                    suspended;
  53         struct device           *dev;
  54         struct clk              **clks;
  55         struct dwc3             *dwc;
  56         struct dentry           *root;
  57         struct reset_control    *otg_rst;
  58         struct extcon_dev       *edev;
  59         struct notifier_block   device_nb;
  60         struct notifier_block   host_nb;
  61         struct work_struct      otg_work;
  62         struct mutex            lock;
  63 };
  64
  65 static int dwc3_rockchip_host_testmode_show(struct seq_file *s, void *unused)
  66 {
  67         struct dwc3_rockchip    *rockchip = s->private;
  68         struct dwc3             *dwc = rockchip->dwc;
  69         struct usb_hcd          *hcd  = dev_get_drvdata(&dwc->xhci->dev);
  70         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
  71         __le32 __iomem          **port_array;
  72         u32                     reg;
  73
  74         if (rockchip->dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
  75                 dev_warn(rockchip->dev, "USB HOST not support!\n");
  76                 return 0;
  77         }
  78
  79         if (hcd->state == HC_STATE_HALT) {
  80                 dev_warn(rockchip->dev, "HOST is halted, set test mode first!\n");
  81                 return 0;
  82         }
  83
  84         port_array = xhci->usb2_ports;
  85         reg = readl(port_array[0] + PORTPMSC);
  86         reg &= XHCI_TSTCTRL_MASK;
  87         reg >>= 28;
  88
  89         switch (reg) {
  90         case 0:
  91                 seq_puts(s, "U2: no test\n");
  92                 break;
  93         case TEST_J:
  94                 seq_puts(s, "U2: test_j\n");
  95                 break;
  96         case TEST_K:
  97                 seq_puts(s, "U2: test_k\n");
  98                 break;
  99         case TEST_SE0_NAK:
 100                 seq_puts(s, "U2: test_se0_nak\n");
 101                 break;
 102         case TEST_PACKET:
 103                 seq_puts(s, "U2: test_packet\n");
 104                 break;
 105         case TEST_FORCE_EN:
 106                 seq_puts(s, "U2: test_force_enable\n");
 107                 break;
 108         default:
 109                 seq_printf(s, "U2: UNKNOWN %d\n", reg);
 110         }
 111
 112         port_array = xhci->usb3_ports;
 113         reg = readl(port_array[0]);
 114         reg &= PORT_PLS_MASK;
 115         if (reg == USB_SS_PORT_LS_COMP_MOD)
 116                 seq_puts(s, "U3: compliance mode\n");
 117         else
 118                 seq_printf(s, "U3: UNKNOWN %d\n", reg >> 5);
 119
 120         return 0;
 121 }
 122
 123 static int dwc3_rockchip_host_testmode_open(struct inode *inode,
 124                                             struct file *file)
 125 {
 126         return single_open(file, dwc3_rockchip_host_testmode_show,
 127                            inode->i_private);
 128 }
 129
 130 /**
 131  * dwc3_rockchip_set_test_mode - Enables USB2/USB3 HOST Test Modes
 132  * @rockchip: pointer to our context structure
 133  * @mode: the mode to set (U2: J, K SE0 NAK, Test_packet,
 134  * Force Enable; U3: Compliance mode)
 135  *
 136  * This function will return 0 on success or -EINVAL if wrong Test
 137  * Selector is passed.
 138  */
 139 static int dwc3_rockchip_set_test_mode(struct dwc3_rockchip *rockchip,
 140                                        u32 mode)
 141 {
 142         struct dwc3     *dwc = rockchip->dwc;
 143         struct usb_hcd  *hcd  = dev_get_drvdata(&dwc->xhci->dev);
 144         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 145         __le32 __iomem  **port_array;
 146         int             ret, val;
 147         u32             reg;
 148
 149         ret = readx_poll_timeout(readl, &hcd->state, val,
 150                                  val != HC_STATE_HALT, 1000,
 151                                  WAIT_FOR_HCD_READY_TIMEOUT);
 152         if (ret < 0) {
 153                 dev_err(rockchip->dev, "Wait for HCD ready timeout\n");
 154                 return -EINVAL;
 155         }
 156
 157         switch (mode) {
 158         case TEST_J:
 159         case TEST_K:
 160         case TEST_SE0_NAK:
 161         case TEST_PACKET:
 162         case TEST_FORCE_EN:
 163                 port_array = xhci->usb2_ports;
 164                 reg = readl(port_array[0] + PORTPMSC);
 165                 reg &= ~XHCI_TSTCTRL_MASK;
 166                 reg |= mode << 28;
 167                 writel(reg, port_array[0] + PORTPMSC);
 168                 break;
 169         case USB_SS_PORT_LS_COMP_MOD:
 170                 port_array = xhci->usb3_ports;
 171                 xhci_set_link_state(xhci, port_array, 0, mode);
 172                 break;
 173         default:
 174                 return -EINVAL;
 175         }
 176
 177         dev_info(rockchip->dev, "set USB HOST test mode successfully!\n");
 178
 179         return 0;
 180 }
 181
 182 static ssize_t dwc3_rockchip_host_testmode_write(struct file *file,
 183                                                  const char __user *ubuf,
 184                                                  size_t count, loff_t *ppos)
 185 {
 186         struct seq_file                 *s = file->private_data;
 187         struct dwc3_rockchip            *rockchip = s->private;
 188         struct extcon_dev               *edev = rockchip->edev;
 189         u32                             testmode = 0;
 190         bool                            flip = 0;
 191         char                            buf[32];
 192         union extcon_property_value     property;
 193
 194         if (rockchip->dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
 195                 dev_warn(rockchip->dev, "USB HOST not support!\n");
 196                 return -EINVAL;
 197         }
 198
 199         if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
 200                 return -EFAULT;
 201
 202         if (!strncmp(buf, "test_j", 6)) {
 203                 testmode = TEST_J;
 204         } else if (!strncmp(buf, "test_k", 6)) {
 205                 testmode = TEST_K;
 206         } else if (!strncmp(buf, "test_se0_nak", 12)) {
 207                 testmode = TEST_SE0_NAK;
 208         } else if (!strncmp(buf, "test_packet", 11)) {
 209                 testmode = TEST_PACKET;
 210         } else if (!strncmp(buf, "test_force_enable", 17)) {
 211                 testmode = TEST_FORCE_EN;
 212         } else if (!strncmp(buf, "test_u3", 7)) {
 213                 testmode = USB_SS_PORT_LS_COMP_MOD;
 214         } else if (!strncmp(buf, "test_flip_u3", 12)) {
 215                 testmode = USB_SS_PORT_LS_COMP_MOD;
 216                 flip = 1;
 217         } else {
 218                 dev_warn(rockchip->dev, "Test cmd not support!\n");
 219                 return -EINVAL;
 220         }
 221
 222         if (edev && !extcon_get_cable_state_(edev, EXTCON_USB_HOST)) {
 223                 if (extcon_get_cable_state_(edev, EXTCON_USB) > 0)
 224                         extcon_set_cable_state_(edev, EXTCON_USB, false);
 225
 226                 property.intval = flip;
 227                 extcon_set_property(edev, EXTCON_USB_HOST,
 228                                     EXTCON_PROP_USB_TYPEC_POLARITY, property);
 229                 extcon_set_cable_state_(edev, EXTCON_USB_HOST, true);
 230
 231                 /* Add a delay 1~1.5s to wait for XHCI HCD init */
 232                 usleep_range(1000000, 1500000);
 233         }
 234
 235         dwc3_rockchip_set_test_mode(rockchip, testmode);
 236
 237         return count;
 238 }
 239
 240 static const struct file_operations dwc3_host_testmode_fops = {
 241         .open                   = dwc3_rockchip_host_testmode_open,
 242         .write                  = dwc3_rockchip_host_testmode_write,
 243         .read                   = seq_read,
 244         .llseek                 = seq_lseek,
 245         .release                = single_release,
 246 };
 247
 248 static void dwc3_rockchip_debugfs_init(struct dwc3_rockchip *rockchip)
 249 {
 250         struct dentry   *root;
 251         struct dentry   *file;
 252
 253         root = debugfs_create_dir(dev_name(rockchip->dev), NULL);
 254         if (IS_ERR_OR_NULL(root)) {
 255                 if (!root)
 256                         dev_err(rockchip->dev, "Can't create debugfs root\n");
 257                 return;
 258         }
 259         rockchip->root = root;
 260
 261         if (IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) ||
 262             IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
 263                 file = debugfs_create_file("host_testmode", S_IRUSR | S_IWUSR,
 264                                            root, rockchip,
 265                                            &dwc3_host_testmode_fops);
 266                 if (!file)
 267                         dev_dbg(rockchip->dev, "Can't create debugfs host_testmode\n");
 268         }
 269 }
 270
 271 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
 272                                          unsigned long event, void *ptr)
 273 {
 274         struct dwc3_rockchip *rockchip =
 275                 container_of(nb, struct dwc3_rockchip, device_nb);
 276
 277         if (!rockchip->suspended)
 278                 schedule_work(&rockchip->otg_work);
 279
 280         return NOTIFY_DONE;
 281 }
 282
 283 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
 284                                        unsigned long event, void *ptr)
 285 {
 286         struct dwc3_rockchip *rockchip =
 287                 container_of(nb, struct dwc3_rockchip, host_nb);
 288
 289         if (!rockchip->suspended)
 290                 schedule_work(&rockchip->otg_work);
 291
 292         return NOTIFY_DONE;
 293 }
 294
 295 static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
 296 {
 297         struct dwc3_rockchip    *rockchip =
 298                 container_of(work, struct dwc3_rockchip, otg_work);
 299         struct dwc3             *dwc = rockchip->dwc;
 300         struct extcon_dev       *edev = rockchip->edev;
 301         struct usb_hcd          *hcd;
 302         struct xhci_hcd         *xhci;
 303         unsigned long           flags;
 304         int                     ret;
 305         int                     val;
 306         u32                     reg, count;
 307
 308         mutex_lock(&rockchip->lock);
 309
 310         if (extcon_get_cable_state_(edev, EXTCON_USB) > 0) {
 311                 if (rockchip->connected)
 312                         goto out;
 313
 314                 /*
 315                  * If dr_mode is host only, never to set
 316                  * the mode to the peripheral mode.
 317                  */
 318                 if (dwc->dr_mode == USB_DR_MODE_HOST) {
 319                         dev_warn(rockchip->dev, "USB peripheral not support!\n");
 320                         goto out;
 321                 }
 322
 323                 /*
 324                  * Assert otg reset can put the dwc in P2 state, it's
 325                  * necessary operation prior to phy power on. However,
 326                  * asserting the otg reset may affect dwc chip operation.
 327                  * The reset will clear all of the dwc controller registers.
 328                  * So we need to reinit the dwc controller after deassert
 329                  * the reset. We use pm runtime to initialize dwc controller.
 330                  * Also, there are no synchronization primitives, meaning
 331                  * the dwc3 core code could at least in theory access chip
 332                  * registers while the reset is asserted, with unknown impact.
 333                  */
 334                 if (!rockchip->skip_suspend) {
 335                         reset_control_assert(rockchip->otg_rst);
 336                         usleep_range(1000, 1200);
 337                         reset_control_deassert(rockchip->otg_rst);
 338
 339                         pm_runtime_get_sync(rockchip->dev);
 340                         pm_runtime_get_sync(dwc->dev);
 341                 } else {
 342                         rockchip->skip_suspend = false;
 343                 }
 344
 345                 spin_lock_irqsave(&dwc->lock, flags);
 346                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 347                 spin_unlock_irqrestore(&dwc->lock, flags);
 348
 349                 rockchip->connected = true;
 350                 dev_info(rockchip->dev, "USB peripheral connected\n");
 351         } else if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) > 0) {
 352                 if (rockchip->connected)
 353                         goto out;
 354
 355                 if (rockchip->skip_suspend) {
 356                         pm_runtime_put(dwc->dev);
 357                         pm_runtime_put(rockchip->dev);
 358                         rockchip->skip_suspend = false;
 359                 }
 360
 361                 /*
 362                  * If dr_mode is device only, never to
 363                  * set the mode to the host mode.
 364                  */
 365                 if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
 366                         dev_warn(rockchip->dev, "USB HOST not support!\n");
 367                         goto out;
 368                 }
 369
 370                 /*
 371                  * Assert otg reset can put the dwc in P2 state, it's
 372                  * necessary operation prior to phy power on. However,
 373                  * asserting the otg reset may affect dwc chip operation.
 374                  * The reset will clear all of the dwc controller registers.
 375                  * So we need to reinit the dwc controller after deassert
 376                  * the reset. We use pm runtime to initialize dwc controller.
 377                  * Also, there are no synchronization primitives, meaning
 378                  * the dwc3 core code could at least in theory access chip
 379                  * registers while the reset is asserted, with unknown impact.
 380                  */
 381                 reset_control_assert(rockchip->otg_rst);
 382                 usleep_range(1000, 1200);
 383                 reset_control_deassert(rockchip->otg_rst);
 384
 385                 /*
 386                  * In usb3 phy init, it will access usb3 module, so we need
 387                  * to resume rockchip dev before phy init to make sure usb3
 388                  * pd is enabled.
 389                  */
 390                 pm_runtime_get_sync(rockchip->dev);
 391
 392                 /*
 393                  * Don't abort on errors. If powering on a phy fails,
 394                  * we still need to init dwc controller and add the
 395                  * HCDs to avoid a crash when unloading the driver.
 396                  */
 397                 ret = phy_power_on(dwc->usb2_generic_phy);
 398                 if (ret < 0)
 399                         dev_err(dwc->dev, "Failed to power on usb2 phy\n");
 400
 401                 ret = phy_power_on(dwc->usb3_generic_phy);
 402                 if (ret < 0) {
 403                         phy_power_off(dwc->usb2_generic_phy);
 404                         dev_err(dwc->dev, "Failed to power on usb3 phy\n");
 405                 }
 406
 407                 pm_runtime_get_sync(dwc->dev);
 408
 409                 spin_lock_irqsave(&dwc->lock, flags);
 410                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 411                 spin_unlock_irqrestore(&dwc->lock, flags);
 412
 413                 /*
 414                  * The following sleep helps to ensure that inserted USB3
 415                  * Ethernet devices are discovered if already inserted
 416                  * when booting.
 417                  */
 418                 usleep_range(10000, 11000);
 419
 420                 hcd = dev_get_drvdata(&dwc->xhci->dev);
 421
 422                 if (hcd->state == HC_STATE_HALT) {
 423                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 424                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 425                 }
 426
 427                 rockchip->connected = true;
 428                 dev_info(rockchip->dev, "USB HOST connected\n");
 429         } else {
 430                 if (!rockchip->connected)
 431                         goto out;
 432
 433                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 434
 435                 /*
 436                  * xhci does not support runtime pm. If HCDs are not removed
 437                  * here and and re-added after a cable is inserted, USB3
 438                  * connections will not work.
 439                  * A clean(er) solution would be to implement runtime pm
 440                  * support in xhci. After that is available, this code should
 441                  * be removed.
 442                  * HCDs have to be removed here to prevent attempts by the
 443                  * xhci code to access xhci registers after the call to
 444                  * pm_runtime_put_sync_suspend(). On rk3399, this can result
 445                  * in a crash under certain circumstances (this was observed
 446                  * on 3399 chromebook if the system is running on battery).
 447                  */
 448                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
 449                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 450                         hcd = dev_get_drvdata(&dwc->xhci->dev);
 451                         xhci = hcd_to_xhci(hcd);
 452
 453                         if (hcd->state != HC_STATE_HALT) {
 454                                 xhci->xhc_state |= XHCI_STATE_REMOVING;
 455                                 count = 0;
 456
 457                                 /*
 458                                  * Wait until XHCI controller resume from
 459                                  * PM suspend, them we can remove hcd safely.
 460                                  */
 461                                 while (dwc->xhci->dev.power.is_suspended) {
 462                                         if (++count > 100) {
 463                                                 dev_err(rockchip->dev,
 464                                                         "wait for XHCI resume 10s timeout!\n");
 465                                                 goto out;
 466                                         }
 467                                         msleep(100);
 468                                 }
 469
 470 #ifdef CONFIG_FREEZER
 471                                 /*
 472                                  * usb_remove_hcd() may call usb_disconnect() to
 473                                  * remove a block device pluged in before.
 474                                  * Unfortunately, the block layer suspend/resume
 475                                  * path is fundamentally broken due to freezable
 476                                  * kthreads and workqueue and may deadlock if a
 477                                  * block device gets removed while resume is in
 478                                  * progress.
 479                                  *
 480                                  * We need to add a ugly hack to avoid removing
 481                                  * hcd and kicking off device removal while
 482                                  * freezer is active. This is a joke but does
 483                                  * avoid this particular deadlock when test with
 484                                  * USB-C HUB and USB2/3 flash drive.
 485                                  */
 486                                 while (pm_freezing)
 487                                         usleep_range(10000, 11000);
 488 #endif
 489
 490                                 usb_remove_hcd(hcd->shared_hcd);
 491                                 usb_remove_hcd(hcd);
 492                         }
 493
 494                         phy_power_off(dwc->usb2_generic_phy);
 495                         phy_power_off(dwc->usb3_generic_phy);
 496                 }
 497
 498                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_DEVICE) {
 499                         ret = readx_poll_timeout(atomic_read,
 500                                                  &dwc->dev->power.usage_count,
 501                                                  val,
 502                                                  val < 2 && !dwc->connected,
 503                                                  1000,
 504                                                  PERIPHERAL_DISCONNECT_TIMEOUT);
 505                         if (ret < 0) {
 506                                 rockchip->skip_suspend = true;
 507                                 dev_warn(rockchip->dev, "Peripheral disconnect timeout\n");
 508                         }
 509                 }
 510
 511                 if (!rockchip->skip_suspend) {
 512                         pm_runtime_put_sync_suspend(dwc->dev);
 513                         pm_runtime_put_sync_suspend(rockchip->dev);
 514                 }
 515
 516                 rockchip->connected = false;
 517                 dev_info(rockchip->dev, "USB unconnected\n");
 518         }
 519
 520 out:
 521         mutex_unlock(&rockchip->lock);
 522 }
 523
 524 static int dwc3_rockchip_extcon_register(struct dwc3_rockchip *rockchip)
 525 {
 526         int                     ret;
 527         struct device           *dev = rockchip->dev;
 528         struct extcon_dev       *edev;
 529
 530         if (device_property_read_bool(dev, "extcon")) {
 531                 edev = extcon_get_edev_by_phandle(dev, 0);
 532                 if (IS_ERR(edev)) {
 533                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 534                                 dev_err(dev, "couldn't get extcon device\n");
 535                         return PTR_ERR(edev);
 536                 }
 537
 538                 INIT_WORK(&rockchip->otg_work,
 539                           dwc3_rockchip_otg_extcon_evt_work);
 540
 541                 rockchip->device_nb.notifier_call =
 542                                 dwc3_rockchip_device_notifier;
 543                 ret = extcon_register_notifier(edev, EXTCON_USB,
 544                                                &rockchip->device_nb);
 545                 if (ret < 0) {
 546                         dev_err(dev, "failed to register notifier for USB\n");
 547                         return ret;
 548                 }
 549
 550                 rockchip->host_nb.notifier_call =
 551                                 dwc3_rockchip_host_notifier;
 552                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 553                                                &rockchip->host_nb);
 554                 if (ret < 0) {
 555                         dev_err(dev, "failed to register notifier for USB HOST\n");
 556                         extcon_unregister_notifier(edev, EXTCON_USB,
 557                                                    &rockchip->device_nb);
 558                         return ret;
 559                 }
 560
 561                 rockchip->edev = edev;
 562         }
 563
 564         return 0;
 565 }
 566
 567 static void dwc3_rockchip_extcon_unregister(struct dwc3_rockchip *rockchip)
 568 {
 569         if (!rockchip->edev)
 570                 return;
 571
 572         extcon_unregister_notifier(rockchip->edev, EXTCON_USB,
 573                                    &rockchip->device_nb);
 574         extcon_unregister_notifier(rockchip->edev, EXTCON_USB_HOST,
 575                                    &rockchip->host_nb);
 576         cancel_work_sync(&rockchip->otg_work);
 577 }
 578
 579 static int dwc3_rockchip_probe(struct platform_device *pdev)
 580 {
 581         struct dwc3_rockchip    *rockchip;
 582         struct device           *dev = &pdev->dev;
 583         struct device_node      *np = dev->of_node, *child;
 584         struct platform_device  *child_pdev;
 585
 586         unsigned int            count;
 587         int                     ret;
 588         int                     i;
 589
 590         rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
 591
 592         if (!rockchip)
 593                 return -ENOMEM;
 594
 595         count = of_clk_get_parent_count(np);
 596         if (!count)
 597                 return -ENOENT;
 598
 599         rockchip->num_clocks = count;
 600
 601         rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
 602                                       sizeof(struct clk *), GFP_KERNEL);
 603         if (!rockchip->clks)
 604                 return -ENOMEM;
 605
 606         platform_set_drvdata(pdev, rockchip);
 607
 608         mutex_init(&rockchip->lock);
 609
 610         rockchip->dev = dev;
 611
 612         mutex_lock(&rockchip->lock);
 613
 614         for (i = 0; i < rockchip->num_clocks; i++) {
 615                 struct clk      *clk;
 616
 617                 clk = of_clk_get(np, i);
 618                 if (IS_ERR(clk)) {
 619                         ret = PTR_ERR(clk);
 620                         goto err0;
 621                 }
 622
 623                 ret = clk_prepare_enable(clk);
 624                 if (ret < 0) {
 625                         clk_put(clk);
 626                         goto err0;
 627                 }
 628
 629                 rockchip->clks[i] = clk;
 630         }
 631
 632         pm_runtime_set_active(dev);
 633         pm_runtime_enable(dev);
 634         ret = pm_runtime_get_sync(dev);
 635         if (ret < 0) {
 636                 dev_err(dev, "get_sync failed with err %d\n", ret);
 637                 goto err1;
 638         }
 639
 640         rockchip->otg_rst = devm_reset_control_get(dev, "usb3-otg");
 641         if (IS_ERR(rockchip->otg_rst)) {
 642                 dev_err(dev, "could not get reset controller\n");
 643                 ret = PTR_ERR(rockchip->otg_rst);
 644                 goto err1;
 645         }
 646
 647         child = of_get_child_by_name(np, "dwc3");
 648         if (!child) {
 649                 dev_err(dev, "failed to find dwc3 core node\n");
 650                 ret = -ENODEV;
 651                 goto err1;
 652         }
 653
 654         /* Allocate and initialize the core */
 655         ret = of_platform_populate(np, NULL, NULL, dev);
 656         if (ret) {
 657                 dev_err(dev, "failed to create dwc3 core\n");
 658                 goto err1;
 659         }
 660
 661         child_pdev = of_find_device_by_node(child);
 662         if (!child_pdev) {
 663                 dev_err(dev, "failed to find dwc3 core device\n");
 664                 ret = -ENODEV;
 665                 goto err2;
 666         }
 667
 668         rockchip->dwc = platform_get_drvdata(child_pdev);
 669         if (!rockchip->dwc) {
 670                 dev_err(dev, "failed to get drvdata dwc3\n");
 671                 ret = -EPROBE_DEFER;
 672                 goto err2;
 673         }
 674
 675         ret = dwc3_rockchip_extcon_register(rockchip);
 676         if (ret < 0)
 677                 goto err2;
 678
 679         if (rockchip->edev) {
 680                 if (rockchip->dwc->dr_mode == USB_DR_MODE_HOST ||
 681                     rockchip->dwc->dr_mode == USB_DR_MODE_OTG) {
 682                         struct usb_hcd *hcd =
 683                                 dev_get_drvdata(&rockchip->dwc->xhci->dev);
 684                         if (!hcd) {
 685                                 dev_err(dev, "fail to get drvdata hcd\n");
 686                                 ret = -EPROBE_DEFER;
 687                                 goto err3;
 688                         }
 689                         if (hcd->state != HC_STATE_HALT) {
 690                                 usb_remove_hcd(hcd->shared_hcd);
 691                                 usb_remove_hcd(hcd);
 692                         }
 693                 }
 694
 695                 pm_runtime_set_autosuspend_delay(&child_pdev->dev,
 696                                                  DWC3_ROCKCHIP_AUTOSUSPEND_DELAY);
 697                 pm_runtime_allow(&child_pdev->dev);
 698                 pm_runtime_suspend(&child_pdev->dev);
 699                 pm_runtime_put_sync(dev);
 700
 701                 if ((extcon_get_cable_state_(rockchip->edev,
 702                                              EXTCON_USB) > 0) ||
 703                     (extcon_get_cable_state_(rockchip->edev,
 704                                              EXTCON_USB_HOST) > 0))
 705                         schedule_work(&rockchip->otg_work);
 706         }
 707
 708         dwc3_rockchip_debugfs_init(rockchip);
 709
 710         mutex_unlock(&rockchip->lock);
 711
 712         return ret;
 713
 714 err3:
 715         dwc3_rockchip_extcon_unregister(rockchip);
 716
 717 err2:
 718         of_platform_depopulate(dev);
 719
 720 err1:
 721         pm_runtime_put_sync(dev);
 722         pm_runtime_disable(dev);
 723
 724 err0:
 725         for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
 726                 if (!pm_runtime_status_suspended(dev))
 727                         clk_disable(rockchip->clks[i]);
 728                 clk_unprepare(rockchip->clks[i]);
 729                 clk_put(rockchip->clks[i]);
 730         }
 731
 732         mutex_unlock(&rockchip->lock);
 733
 734         return ret;
 735 }
 736
 737 static int dwc3_rockchip_remove(struct platform_device *pdev)
 738 {
 739         struct dwc3_rockchip    *rockchip = platform_get_drvdata(pdev);
 740         struct device           *dev = &pdev->dev;
 741         int                     i;
 742
 743         dwc3_rockchip_extcon_unregister(rockchip);
 744
 745         /* Restore hcd state before unregistering xhci */
 746         if (rockchip->edev && !rockchip->connected) {
 747                 struct usb_hcd *hcd =
 748                         dev_get_drvdata(&rockchip->dwc->xhci->dev);
 749
 750                 pm_runtime_get_sync(dev);
 751
 752                 /*
 753                  * The xhci code does not expect that HCDs have been removed.
 754                  * It will unconditionally call usb_remove_hcd() when the xhci
 755                  * driver is unloaded in of_platform_depopulate(). This results
 756                  * in a crash if the HCDs were already removed. To avoid this
 757                  * crash, add the HCDs here as dummy operation.
 758                  * This code should be removed after pm runtime support
 759                  * has been added to xhci.
 760                  */
 761                 if (hcd->state == HC_STATE_HALT) {
 762                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 763                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 764                 }
 765         }
 766
 767         of_platform_depopulate(dev);
 768
 769         pm_runtime_put_sync(dev);
 770         pm_runtime_disable(dev);
 771
 772         for (i = 0; i < rockchip->num_clocks; i++) {
 773                 if (!pm_runtime_status_suspended(dev))
 774                         clk_disable(rockchip->clks[i]);
 775                 clk_unprepare(rockchip->clks[i]);
 776                 clk_put(rockchip->clks[i]);
 777         }
 778
 779         return 0;
 780 }
 781
 782 #ifdef CONFIG_PM
 783 static int dwc3_rockchip_runtime_suspend(struct device *dev)
 784 {
 785         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 786         int                     i;
 787
 788         for (i = 0; i < rockchip->num_clocks; i++)
 789                 clk_disable(rockchip->clks[i]);
 790
 791         device_init_wakeup(dev, false);
 792
 793         return 0;
 794 }
 795
 796 static int dwc3_rockchip_runtime_resume(struct device *dev)
 797 {
 798         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 799         int                     i;
 800
 801         for (i = 0; i < rockchip->num_clocks; i++)
 802                 clk_enable(rockchip->clks[i]);
 803
 804         device_init_wakeup(dev, true);
 805
 806         return 0;
 807 }
 808
 809 static int dwc3_rockchip_suspend(struct device *dev)
 810 {
 811         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 812         struct dwc3 *dwc = rockchip->dwc;
 813
 814         rockchip->suspended = true;
 815         cancel_work_sync(&rockchip->otg_work);
 816
 817         if (rockchip->edev && dwc->dr_mode != USB_DR_MODE_PERIPHERAL) {
 818                 /*
 819                  * If USB HOST connected, we will do phy power
 820                  * on in extcon evt work, so need to do phy
 821                  * power off in suspend. And we just power off
 822                  * USB2 PHY here because USB3 PHY power on operation
 823                  * need to be done while DWC3 controller is in P2
 824                  * state, but after resume DWC3 controller is in
 825                  * P0 state. So we put USB3 PHY in power on state.
 826                  */
 827                 if (extcon_get_cable_state_(rockchip->edev,
 828                                             EXTCON_USB_HOST) > 0)
 829                         phy_power_off(dwc->usb2_generic_phy);
 830         }
 831
 832         return 0;
 833 }
 834
 835 static int dwc3_rockchip_resume(struct device *dev)
 836 {
 837         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 838         struct dwc3 *dwc = rockchip->dwc;
 839
 840         rockchip->suspended = false;
 841
 842         if (rockchip->edev)
 843                 schedule_work(&rockchip->otg_work);
 844
 845         if (rockchip->edev && dwc->dr_mode != USB_DR_MODE_PERIPHERAL) {
 846                 if (extcon_get_cable_state_(rockchip->edev,
 847                                             EXTCON_USB_HOST) > 0)
 848                         phy_power_on(dwc->usb2_generic_phy);
 849         }
 850
 851         return 0;
 852 }
 853
 854 static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
 855         SET_SYSTEM_SLEEP_PM_OPS(dwc3_rockchip_suspend, dwc3_rockchip_resume)
 856         SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
 857                            dwc3_rockchip_runtime_resume, NULL)
 858 };
 859
 860 #define DEV_PM_OPS      (&dwc3_rockchip_dev_pm_ops)
 861 #else
 862 #define DEV_PM_OPS      NULL
 863 #endif /* CONFIG_PM */
 864
 865 static const struct of_device_id rockchip_dwc3_match[] = {
 866         { .compatible = "rockchip,rk3399-dwc3" },
 867         { /* Sentinel */ }
 868 };
 869
 870 MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
 871
 872 static struct platform_driver dwc3_rockchip_driver = {
 873         .probe          = dwc3_rockchip_probe,
 874         .remove         = dwc3_rockchip_remove,
 875         .driver         = {
 876                 .name   = "rockchip-dwc3",
 877                 .of_match_table = rockchip_dwc3_match,
 878                 .pm     = DEV_PM_OPS,
 879         },
 880 };
 881
 882 module_platform_driver(dwc3_rockchip_driver);
 883
 884 MODULE_ALIAS("platform:rockchip-dwc3");
 885 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
 886 MODULE_LICENSE("GPL v2");
 887 MODULE_DESCRIPTION("DesignWare USB3 ROCKCHIP Glue Layer");