drivers/usb/dwc3/dwc3-rockchip.c

   1 /**
   2  * dwc3-rockchip.c - Rockchip Specific Glue layer
   3  *
   4  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   5  *
   6  * Authors: William Wu <william.wu@rock-chips.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2  of
  10  * the License as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/of.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/extcon.h>
  30 #include <linux/reset.h>
  31 #include <linux/usb.h>
  32 #include <linux/usb/hcd.h>
  33
  34 #include "core.h"
  35 #include "io.h"
  36
  37 #define DWC3_ROCKCHIP_AUTOSUSPEND_DELAY  500 /* ms */
  38
  39 struct dwc3_rockchip {
  40         int                     num_clocks;
  41         bool                    connected;
  42         bool                    suspended;
  43         struct device           *dev;
  44         struct clk              **clks;
  45         struct dwc3             *dwc;
  46         struct reset_control    *otg_rst;
  47         struct extcon_dev       *edev;
  48         struct notifier_block   device_nb;
  49         struct notifier_block   host_nb;
  50         struct work_struct      otg_work;
  51         struct mutex            lock;
  52 };
  53
  54 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
  55                                          unsigned long event, void *ptr)
  56 {
  57         struct dwc3_rockchip *rockchip =
  58                 container_of(nb, struct dwc3_rockchip, device_nb);
  59
  60         if (!rockchip->suspended)
  61                 schedule_work(&rockchip->otg_work);
  62
  63         return NOTIFY_DONE;
  64 }
  65
  66 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
  67                                        unsigned long event, void *ptr)
  68 {
  69         struct dwc3_rockchip *rockchip =
  70                 container_of(nb, struct dwc3_rockchip, host_nb);
  71
  72         if (!rockchip->suspended)
  73                 schedule_work(&rockchip->otg_work);
  74
  75         return NOTIFY_DONE;
  76 }
  77
  78 static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
  79 {
  80         struct dwc3_rockchip    *rockchip =
  81                 container_of(work, struct dwc3_rockchip, otg_work);
  82         struct dwc3             *dwc = rockchip->dwc;
  83         struct extcon_dev       *edev = rockchip->edev;
  84         struct usb_hcd          *hcd;
  85         unsigned long           flags;
  86         int                     ret;
  87         u32                     reg;
  88
  89         mutex_lock(&rockchip->lock);
  90
  91         if (extcon_get_cable_state_(edev, EXTCON_USB) > 0) {
  92                 if (rockchip->connected)
  93                         goto out;
  94
  95                 /*
  96                  * If dr_mode is host only, never to set
  97                  * the mode to the peripheral mode.
  98                  */
  99                 if (dwc->dr_mode == USB_DR_MODE_HOST) {
 100                         dev_warn(rockchip->dev, "USB peripheral not support!\n");
 101                         goto out;
 102                 }
 103
 104                 /*
 105                  * Assert otg reset can put the dwc in P2 state, it's
 106                  * necessary operation prior to phy power on. However,
 107                  * asserting the otg reset may affect dwc chip operation.
 108                  * The reset will clear all of the dwc controller registers.
 109                  * So we need to reinit the dwc controller after deassert
 110                  * the reset. We use pm runtime to initialize dwc controller.
 111                  * Also, there are no synchronization primitives, meaning
 112                  * the dwc3 core code could at least in theory access chip
 113                  * registers while the reset is asserted, with unknown impact.
 114                  */
 115                 reset_control_assert(rockchip->otg_rst);
 116                 usleep_range(1000, 1200);
 117                 reset_control_deassert(rockchip->otg_rst);
 118
 119                 pm_runtime_get_sync(dwc->dev);
 120
 121                 spin_lock_irqsave(&dwc->lock, flags);
 122                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 123                 spin_unlock_irqrestore(&dwc->lock, flags);
 124
 125                 rockchip->connected = true;
 126                 dev_info(rockchip->dev, "USB peripheral connected\n");
 127         } else if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) > 0) {
 128                 if (rockchip->connected)
 129                         goto out;
 130
 131                 /*
 132                  * If dr_mode is device only, never to
 133                  * set the mode to the host mode.
 134                  */
 135                 if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
 136                         dev_warn(rockchip->dev, "USB HOST not support!\n");
 137                         goto out;
 138                 }
 139
 140                 /*
 141                  * Assert otg reset can put the dwc in P2 state, it's
 142                  * necessary operation prior to phy power on. However,
 143                  * asserting the otg reset may affect dwc chip operation.
 144                  * The reset will clear all of the dwc controller registers.
 145                  * So we need to reinit the dwc controller after deassert
 146                  * the reset. We use pm runtime to initialize dwc controller.
 147                  * Also, there are no synchronization primitives, meaning
 148                  * the dwc3 core code could at least in theory access chip
 149                  * registers while the reset is asserted, with unknown impact.
 150                  */
 151                 reset_control_assert(rockchip->otg_rst);
 152                 usleep_range(1000, 1200);
 153                 reset_control_deassert(rockchip->otg_rst);
 154
 155                 /*
 156                  * Don't abort on errors. If powering on a phy fails,
 157                  * we still need to init dwc controller and add the
 158                  * HCDs to avoid a crash when unloading the driver.
 159                  */
 160                 ret = phy_power_on(dwc->usb2_generic_phy);
 161                 if (ret < 0)
 162                         dev_err(dwc->dev, "Failed to power on usb2 phy\n");
 163
 164                 ret = phy_power_on(dwc->usb3_generic_phy);
 165                 if (ret < 0) {
 166                         phy_power_off(dwc->usb2_generic_phy);
 167                         dev_err(dwc->dev, "Failed to power on usb3 phy\n");
 168                 }
 169
 170                 pm_runtime_get_sync(dwc->dev);
 171
 172                 spin_lock_irqsave(&dwc->lock, flags);
 173                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 174                 spin_unlock_irqrestore(&dwc->lock, flags);
 175
 176                 /*
 177                  * The following sleep helps to ensure that inserted USB3
 178                  * Ethernet devices are discovered if already inserted
 179                  * when booting.
 180                  */
 181                 usleep_range(10000, 11000);
 182
 183                 hcd = dev_get_drvdata(&dwc->xhci->dev);
 184
 185                 if (hcd->state == HC_STATE_HALT) {
 186                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 187                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 188                 }
 189
 190                 rockchip->connected = true;
 191                 dev_info(rockchip->dev, "USB HOST connected\n");
 192         } else {
 193                 if (!rockchip->connected)
 194                         goto out;
 195
 196                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 197
 198                 /*
 199                  * xhci does not support runtime pm. If HCDs are not removed
 200                  * here and and re-added after a cable is inserted, USB3
 201                  * connections will not work.
 202                  * A clean(er) solution would be to implement runtime pm
 203                  * support in xhci. After that is available, this code should
 204                  * be removed.
 205                  * HCDs have to be removed here to prevent attempts by the
 206                  * xhci code to access xhci registers after the call to
 207                  * pm_runtime_put_sync_suspend(). On rk3399, this can result
 208                  * in a crash under certain circumstances (this was observed
 209                  * on 3399 chromebook if the system is running on battery).
 210                  */
 211                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
 212                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 213                         hcd = dev_get_drvdata(&dwc->xhci->dev);
 214
 215                         if (hcd->state == HC_STATE_SUSPENDED) {
 216                                 dev_dbg(rockchip->dev, "USB suspended\n");
 217                                 goto out;
 218                         }
 219
 220                         if (hcd->state != HC_STATE_HALT) {
 221                                 usb_remove_hcd(hcd->shared_hcd);
 222                                 usb_remove_hcd(hcd);
 223                         }
 224
 225                         phy_power_off(dwc->usb2_generic_phy);
 226                         phy_power_off(dwc->usb3_generic_phy);
 227                 }
 228
 229                 pm_runtime_put_sync(dwc->dev);
 230
 231                 rockchip->connected = false;
 232                 dev_info(rockchip->dev, "USB unconnected\n");
 233         }
 234
 235 out:
 236         mutex_unlock(&rockchip->lock);
 237 }
 238
 239 static int dwc3_rockchip_extcon_register(struct dwc3_rockchip *rockchip)
 240 {
 241         int                     ret;
 242         struct device           *dev = rockchip->dev;
 243         struct extcon_dev       *edev;
 244
 245         if (device_property_read_bool(dev, "extcon")) {
 246                 edev = extcon_get_edev_by_phandle(dev, 0);
 247                 if (IS_ERR(edev)) {
 248                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 249                                 dev_err(dev, "couldn't get extcon device\n");
 250                         return PTR_ERR(edev);
 251                 }
 252
 253                 INIT_WORK(&rockchip->otg_work,
 254                           dwc3_rockchip_otg_extcon_evt_work);
 255
 256                 rockchip->device_nb.notifier_call =
 257                                 dwc3_rockchip_device_notifier;
 258                 ret = extcon_register_notifier(edev, EXTCON_USB,
 259                                                &rockchip->device_nb);
 260                 if (ret < 0) {
 261                         dev_err(dev, "failed to register notifier for USB\n");
 262                         return ret;
 263                 }
 264
 265                 rockchip->host_nb.notifier_call =
 266                                 dwc3_rockchip_host_notifier;
 267                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 268                                                &rockchip->host_nb);
 269                 if (ret < 0) {
 270                         dev_err(dev, "failed to register notifier for USB HOST\n");
 271                         extcon_unregister_notifier(edev, EXTCON_USB,
 272                                                    &rockchip->device_nb);
 273                         return ret;
 274                 }
 275
 276                 rockchip->edev = edev;
 277         }
 278
 279         return 0;
 280 }
 281
 282 static void dwc3_rockchip_extcon_unregister(struct dwc3_rockchip *rockchip)
 283 {
 284         if (!rockchip->edev)
 285                 return;
 286
 287         extcon_unregister_notifier(rockchip->edev, EXTCON_USB,
 288                                    &rockchip->device_nb);
 289         extcon_unregister_notifier(rockchip->edev, EXTCON_USB_HOST,
 290                                    &rockchip->host_nb);
 291         cancel_work_sync(&rockchip->otg_work);
 292 }
 293
 294 static int dwc3_rockchip_probe(struct platform_device *pdev)
 295 {
 296         struct dwc3_rockchip    *rockchip;
 297         struct device           *dev = &pdev->dev;
 298         struct device_node      *np = dev->of_node, *child;
 299         struct platform_device  *child_pdev;
 300
 301         unsigned int            count;
 302         int                     ret;
 303         int                     i;
 304
 305         rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
 306
 307         if (!rockchip)
 308                 return -ENOMEM;
 309
 310         count = of_clk_get_parent_count(np);
 311         if (!count)
 312                 return -ENOENT;
 313
 314         rockchip->num_clocks = count;
 315
 316         rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
 317                                       sizeof(struct clk *), GFP_KERNEL);
 318         if (!rockchip->clks)
 319                 return -ENOMEM;
 320
 321         platform_set_drvdata(pdev, rockchip);
 322
 323         mutex_init(&rockchip->lock);
 324
 325         rockchip->dev = dev;
 326
 327         mutex_lock(&rockchip->lock);
 328
 329         for (i = 0; i < rockchip->num_clocks; i++) {
 330                 struct clk      *clk;
 331
 332                 clk = of_clk_get(np, i);
 333                 if (IS_ERR(clk)) {
 334                         ret = PTR_ERR(clk);
 335                         goto err0;
 336                 }
 337
 338                 ret = clk_prepare_enable(clk);
 339                 if (ret < 0) {
 340                         clk_put(clk);
 341                         goto err0;
 342                 }
 343
 344                 rockchip->clks[i] = clk;
 345         }
 346
 347         pm_runtime_set_active(dev);
 348         pm_runtime_enable(dev);
 349         ret = pm_runtime_get_sync(dev);
 350         if (ret < 0) {
 351                 dev_err(dev, "get_sync failed with err %d\n", ret);
 352                 goto err1;
 353         }
 354
 355         rockchip->otg_rst = devm_reset_control_get(dev, "usb3-otg");
 356         if (IS_ERR(rockchip->otg_rst)) {
 357                 dev_err(dev, "could not get reset controller\n");
 358                 ret = PTR_ERR(rockchip->otg_rst);
 359                 goto err1;
 360         }
 361
 362         child = of_get_child_by_name(np, "dwc3");
 363         if (!child) {
 364                 dev_err(dev, "failed to find dwc3 core node\n");
 365                 ret = -ENODEV;
 366                 goto err1;
 367         }
 368
 369         /* Allocate and initialize the core */
 370         ret = of_platform_populate(np, NULL, NULL, dev);
 371         if (ret) {
 372                 dev_err(dev, "failed to create dwc3 core\n");
 373                 goto err1;
 374         }
 375
 376         child_pdev = of_find_device_by_node(child);
 377         if (!child_pdev) {
 378                 dev_err(dev, "failed to find dwc3 core device\n");
 379                 ret = -ENODEV;
 380                 goto err2;
 381         }
 382
 383         rockchip->dwc = platform_get_drvdata(child_pdev);
 384         if (!rockchip->dwc) {
 385                 dev_err(dev, "failed to get drvdata dwc3\n");
 386                 ret = -EPROBE_DEFER;
 387                 goto err2;
 388         }
 389
 390         ret = dwc3_rockchip_extcon_register(rockchip);
 391         if (ret < 0)
 392                 goto err2;
 393
 394         if (rockchip->edev) {
 395                 if (rockchip->dwc->dr_mode == USB_DR_MODE_HOST ||
 396                     rockchip->dwc->dr_mode == USB_DR_MODE_OTG) {
 397                         struct usb_hcd *hcd =
 398                                 dev_get_drvdata(&rockchip->dwc->xhci->dev);
 399                         if (!hcd) {
 400                                 dev_err(dev, "fail to get drvdata hcd\n");
 401                                 ret = -EPROBE_DEFER;
 402                                 goto err3;
 403                         }
 404                         if (hcd->state != HC_STATE_HALT) {
 405                                 usb_remove_hcd(hcd->shared_hcd);
 406                                 usb_remove_hcd(hcd);
 407                         }
 408                 }
 409
 410                 pm_runtime_set_autosuspend_delay(&child_pdev->dev,
 411                                                  DWC3_ROCKCHIP_AUTOSUSPEND_DELAY);
 412                 pm_runtime_allow(&child_pdev->dev);
 413                 pm_runtime_suspend(&child_pdev->dev);
 414                 pm_runtime_put_sync(dev);
 415
 416                 if ((extcon_get_cable_state_(rockchip->edev,
 417                                              EXTCON_USB) > 0) ||
 418                     (extcon_get_cable_state_(rockchip->edev,
 419                                              EXTCON_USB_HOST) > 0))
 420                         schedule_work(&rockchip->otg_work);
 421         }
 422
 423         mutex_unlock(&rockchip->lock);
 424
 425         return ret;
 426
 427 err3:
 428         dwc3_rockchip_extcon_unregister(rockchip);
 429
 430 err2:
 431         of_platform_depopulate(dev);
 432
 433 err1:
 434         pm_runtime_put_sync(dev);
 435         pm_runtime_disable(dev);
 436
 437 err0:
 438         for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
 439                 if (!pm_runtime_status_suspended(dev))
 440                         clk_disable(rockchip->clks[i]);
 441                 clk_unprepare(rockchip->clks[i]);
 442                 clk_put(rockchip->clks[i]);
 443         }
 444
 445         mutex_unlock(&rockchip->lock);
 446
 447         return ret;
 448 }
 449
 450 static int dwc3_rockchip_remove(struct platform_device *pdev)
 451 {
 452         struct dwc3_rockchip    *rockchip = platform_get_drvdata(pdev);
 453         struct device           *dev = &pdev->dev;
 454         int                     i;
 455
 456         dwc3_rockchip_extcon_unregister(rockchip);
 457
 458         /* Restore hcd state before unregistering xhci */
 459         if (rockchip->edev && !rockchip->connected) {
 460                 struct usb_hcd *hcd =
 461                         dev_get_drvdata(&rockchip->dwc->xhci->dev);
 462
 463                 pm_runtime_get_sync(dev);
 464
 465                 /*
 466                  * The xhci code does not expect that HCDs have been removed.
 467                  * It will unconditionally call usb_remove_hcd() when the xhci
 468                  * driver is unloaded in of_platform_depopulate(). This results
 469                  * in a crash if the HCDs were already removed. To avoid this
 470                  * crash, add the HCDs here as dummy operation.
 471                  * This code should be removed after pm runtime support
 472                  * has been added to xhci.
 473                  */
 474                 if (hcd->state == HC_STATE_HALT) {
 475                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 476                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 477                 }
 478         }
 479
 480         of_platform_depopulate(dev);
 481
 482         pm_runtime_put_sync(dev);
 483         pm_runtime_disable(dev);
 484
 485         for (i = 0; i < rockchip->num_clocks; i++) {
 486                 if (!pm_runtime_status_suspended(dev))
 487                         clk_disable(rockchip->clks[i]);
 488                 clk_unprepare(rockchip->clks[i]);
 489                 clk_put(rockchip->clks[i]);
 490         }
 491
 492         return 0;
 493 }
 494
 495 #ifdef CONFIG_PM
 496 static int dwc3_rockchip_runtime_suspend(struct device *dev)
 497 {
 498         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 499         int                     i;
 500
 501         for (i = 0; i < rockchip->num_clocks; i++)
 502                 clk_disable(rockchip->clks[i]);
 503
 504         device_init_wakeup(dev, false);
 505
 506         return 0;
 507 }
 508
 509 static int dwc3_rockchip_runtime_resume(struct device *dev)
 510 {
 511         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 512         int                     i;
 513
 514         for (i = 0; i < rockchip->num_clocks; i++)
 515                 clk_enable(rockchip->clks[i]);
 516
 517         device_init_wakeup(dev, true);
 518
 519         return 0;
 520 }
 521
 522 static int dwc3_rockchip_suspend(struct device *dev)
 523 {
 524         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 525
 526         rockchip->suspended = true;
 527         cancel_work_sync(&rockchip->otg_work);
 528
 529         return 0;
 530 }
 531
 532 static int dwc3_rockchip_resume(struct device *dev)
 533 {
 534         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 535
 536         rockchip->suspended = false;
 537
 538         return 0;
 539 }
 540
 541 static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
 542         SET_SYSTEM_SLEEP_PM_OPS(dwc3_rockchip_suspend, dwc3_rockchip_resume)
 543         SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
 544                            dwc3_rockchip_runtime_resume, NULL)
 545 };
 546
 547 #define DEV_PM_OPS      (&dwc3_rockchip_dev_pm_ops)
 548 #else
 549 #define DEV_PM_OPS      NULL
 550 #endif /* CONFIG_PM */
 551
 552 static const struct of_device_id rockchip_dwc3_match[] = {
 553         { .compatible = "rockchip,rk3399-dwc3" },
 554         { /* Sentinel */ }
 555 };
 556
 557 MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
 558
 559 static struct platform_driver dwc3_rockchip_driver = {
 560         .probe          = dwc3_rockchip_probe,
 561         .remove         = dwc3_rockchip_remove,
 562         .driver         = {
 563                 .name   = "rockchip-dwc3",
 564                 .of_match_table = rockchip_dwc3_match,
 565                 .pm     = DEV_PM_OPS,
 566         },
 567 };
 568
 569 module_platform_driver(dwc3_rockchip_driver);
 570
 571 MODULE_ALIAS("platform:rockchip-dwc3");
 572 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
 573 MODULE_LICENSE("GPL v2");
 574 MODULE_DESCRIPTION("DesignWare USB3 ROCKCHIP Glue Layer");