drivers/usb/dwc3/dwc3-rockchip.c

   1 /**
   2  * dwc3-rockchip.c - Rockchip Specific Glue layer
   3  *
   4  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   5  *
   6  * Authors: William Wu <william.wu@rock-chips.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2  of
  10  * the License as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/of.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/extcon.h>
  30 #include <linux/reset.h>
  31 #include <linux/usb.h>
  32 #include <linux/usb/hcd.h>
  33
  34 #include "core.h"
  35 #include "io.h"
  36 #include "../host/xhci.h"
  37
  38 #define DWC3_ROCKCHIP_AUTOSUSPEND_DELAY  500 /* ms */
  39
  40 struct dwc3_rockchip {
  41         int                     num_clocks;
  42         bool                    connected;
  43         bool                    suspended;
  44         struct device           *dev;
  45         struct clk              **clks;
  46         struct dwc3             *dwc;
  47         struct reset_control    *otg_rst;
  48         struct extcon_dev       *edev;
  49         struct notifier_block   device_nb;
  50         struct notifier_block   host_nb;
  51         struct work_struct      otg_work;
  52         struct mutex            lock;
  53 };
  54
  55 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
  56                                          unsigned long event, void *ptr)
  57 {
  58         struct dwc3_rockchip *rockchip =
  59                 container_of(nb, struct dwc3_rockchip, device_nb);
  60
  61         if (!rockchip->suspended)
  62                 schedule_work(&rockchip->otg_work);
  63
  64         return NOTIFY_DONE;
  65 }
  66
  67 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
  68                                        unsigned long event, void *ptr)
  69 {
  70         struct dwc3_rockchip *rockchip =
  71                 container_of(nb, struct dwc3_rockchip, host_nb);
  72
  73         if (!rockchip->suspended)
  74                 schedule_work(&rockchip->otg_work);
  75
  76         return NOTIFY_DONE;
  77 }
  78
  79 static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
  80 {
  81         struct dwc3_rockchip    *rockchip =
  82                 container_of(work, struct dwc3_rockchip, otg_work);
  83         struct dwc3             *dwc = rockchip->dwc;
  84         struct extcon_dev       *edev = rockchip->edev;
  85         struct usb_hcd          *hcd;
  86         struct xhci_hcd         *xhci;
  87         unsigned long           flags;
  88         int                     ret;
  89         u32                     reg, count;
  90
  91         mutex_lock(&rockchip->lock);
  92
  93         if (extcon_get_cable_state_(edev, EXTCON_USB) > 0) {
  94                 if (rockchip->connected)
  95                         goto out;
  96
  97                 /*
  98                  * If dr_mode is host only, never to set
  99                  * the mode to the peripheral mode.
 100                  */
 101                 if (dwc->dr_mode == USB_DR_MODE_HOST) {
 102                         dev_warn(rockchip->dev, "USB peripheral not support!\n");
 103                         goto out;
 104                 }
 105
 106                 /*
 107                  * Assert otg reset can put the dwc in P2 state, it's
 108                  * necessary operation prior to phy power on. However,
 109                  * asserting the otg reset may affect dwc chip operation.
 110                  * The reset will clear all of the dwc controller registers.
 111                  * So we need to reinit the dwc controller after deassert
 112                  * the reset. We use pm runtime to initialize dwc controller.
 113                  * Also, there are no synchronization primitives, meaning
 114                  * the dwc3 core code could at least in theory access chip
 115                  * registers while the reset is asserted, with unknown impact.
 116                  */
 117                 reset_control_assert(rockchip->otg_rst);
 118                 usleep_range(1000, 1200);
 119                 reset_control_deassert(rockchip->otg_rst);
 120
 121                 pm_runtime_get_sync(rockchip->dev);
 122                 pm_runtime_get_sync(dwc->dev);
 123
 124                 spin_lock_irqsave(&dwc->lock, flags);
 125                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 126                 spin_unlock_irqrestore(&dwc->lock, flags);
 127
 128                 rockchip->connected = true;
 129                 dev_info(rockchip->dev, "USB peripheral connected\n");
 130         } else if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) > 0) {
 131                 if (rockchip->connected)
 132                         goto out;
 133
 134                 /*
 135                  * If dr_mode is device only, never to
 136                  * set the mode to the host mode.
 137                  */
 138                 if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
 139                         dev_warn(rockchip->dev, "USB HOST not support!\n");
 140                         goto out;
 141                 }
 142
 143                 /*
 144                  * Assert otg reset can put the dwc in P2 state, it's
 145                  * necessary operation prior to phy power on. However,
 146                  * asserting the otg reset may affect dwc chip operation.
 147                  * The reset will clear all of the dwc controller registers.
 148                  * So we need to reinit the dwc controller after deassert
 149                  * the reset. We use pm runtime to initialize dwc controller.
 150                  * Also, there are no synchronization primitives, meaning
 151                  * the dwc3 core code could at least in theory access chip
 152                  * registers while the reset is asserted, with unknown impact.
 153                  */
 154                 reset_control_assert(rockchip->otg_rst);
 155                 usleep_range(1000, 1200);
 156                 reset_control_deassert(rockchip->otg_rst);
 157
 158                 /*
 159                  * In usb3 phy init, it will access usb3 module, so we need
 160                  * to resume rockchip dev before phy init to make sure usb3
 161                  * pd is enabled.
 162                  */
 163                 pm_runtime_get_sync(rockchip->dev);
 164
 165                 /*
 166                  * Don't abort on errors. If powering on a phy fails,
 167                  * we still need to init dwc controller and add the
 168                  * HCDs to avoid a crash when unloading the driver.
 169                  */
 170                 ret = phy_power_on(dwc->usb2_generic_phy);
 171                 if (ret < 0)
 172                         dev_err(dwc->dev, "Failed to power on usb2 phy\n");
 173
 174                 ret = phy_power_on(dwc->usb3_generic_phy);
 175                 if (ret < 0) {
 176                         phy_power_off(dwc->usb2_generic_phy);
 177                         dev_err(dwc->dev, "Failed to power on usb3 phy\n");
 178                 }
 179
 180                 pm_runtime_get_sync(dwc->dev);
 181
 182                 spin_lock_irqsave(&dwc->lock, flags);
 183                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 184                 spin_unlock_irqrestore(&dwc->lock, flags);
 185
 186                 /*
 187                  * The following sleep helps to ensure that inserted USB3
 188                  * Ethernet devices are discovered if already inserted
 189                  * when booting.
 190                  */
 191                 usleep_range(10000, 11000);
 192
 193                 hcd = dev_get_drvdata(&dwc->xhci->dev);
 194
 195                 if (hcd->state == HC_STATE_HALT) {
 196                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 197                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 198                 }
 199
 200                 rockchip->connected = true;
 201                 dev_info(rockchip->dev, "USB HOST connected\n");
 202         } else {
 203                 if (!rockchip->connected)
 204                         goto out;
 205
 206                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 207
 208                 /*
 209                  * xhci does not support runtime pm. If HCDs are not removed
 210                  * here and and re-added after a cable is inserted, USB3
 211                  * connections will not work.
 212                  * A clean(er) solution would be to implement runtime pm
 213                  * support in xhci. After that is available, this code should
 214                  * be removed.
 215                  * HCDs have to be removed here to prevent attempts by the
 216                  * xhci code to access xhci registers after the call to
 217                  * pm_runtime_put_sync_suspend(). On rk3399, this can result
 218                  * in a crash under certain circumstances (this was observed
 219                  * on 3399 chromebook if the system is running on battery).
 220                  */
 221                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
 222                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 223                         hcd = dev_get_drvdata(&dwc->xhci->dev);
 224                         xhci = hcd_to_xhci(hcd);
 225
 226                         if (hcd->state != HC_STATE_HALT) {
 227                                 xhci->xhc_state |= XHCI_STATE_REMOVING;
 228                                 count = 0;
 229
 230                                 /*
 231                                  * Wait until XHCI controller resume from
 232                                  * PM suspend, them we can remove hcd safely.
 233                                  */
 234                                 while (dwc->xhci->dev.power.is_suspended) {
 235                                         if (++count > 100) {
 236                                                 dev_err(rockchip->dev,
 237                                                         "wait for XHCI resume 10s timeout!\n");
 238                                                 goto out;
 239                                         }
 240                                         msleep(100);
 241                                 }
 242
 243                                 usb_remove_hcd(hcd->shared_hcd);
 244                                 usb_remove_hcd(hcd);
 245                         }
 246
 247                         phy_power_off(dwc->usb2_generic_phy);
 248                         phy_power_off(dwc->usb3_generic_phy);
 249                 }
 250
 251                 pm_runtime_put_sync(rockchip->dev);
 252                 pm_runtime_put_sync_suspend(dwc->dev);
 253
 254                 rockchip->connected = false;
 255                 dev_info(rockchip->dev, "USB unconnected\n");
 256         }
 257
 258 out:
 259         mutex_unlock(&rockchip->lock);
 260 }
 261
 262 static int dwc3_rockchip_extcon_register(struct dwc3_rockchip *rockchip)
 263 {
 264         int                     ret;
 265         struct device           *dev = rockchip->dev;
 266         struct extcon_dev       *edev;
 267
 268         if (device_property_read_bool(dev, "extcon")) {
 269                 edev = extcon_get_edev_by_phandle(dev, 0);
 270                 if (IS_ERR(edev)) {
 271                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 272                                 dev_err(dev, "couldn't get extcon device\n");
 273                         return PTR_ERR(edev);
 274                 }
 275
 276                 INIT_WORK(&rockchip->otg_work,
 277                           dwc3_rockchip_otg_extcon_evt_work);
 278
 279                 rockchip->device_nb.notifier_call =
 280                                 dwc3_rockchip_device_notifier;
 281                 ret = extcon_register_notifier(edev, EXTCON_USB,
 282                                                &rockchip->device_nb);
 283                 if (ret < 0) {
 284                         dev_err(dev, "failed to register notifier for USB\n");
 285                         return ret;
 286                 }
 287
 288                 rockchip->host_nb.notifier_call =
 289                                 dwc3_rockchip_host_notifier;
 290                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 291                                                &rockchip->host_nb);
 292                 if (ret < 0) {
 293                         dev_err(dev, "failed to register notifier for USB HOST\n");
 294                         extcon_unregister_notifier(edev, EXTCON_USB,
 295                                                    &rockchip->device_nb);
 296                         return ret;
 297                 }
 298
 299                 rockchip->edev = edev;
 300         }
 301
 302         return 0;
 303 }
 304
 305 static void dwc3_rockchip_extcon_unregister(struct dwc3_rockchip *rockchip)
 306 {
 307         if (!rockchip->edev)
 308                 return;
 309
 310         extcon_unregister_notifier(rockchip->edev, EXTCON_USB,
 311                                    &rockchip->device_nb);
 312         extcon_unregister_notifier(rockchip->edev, EXTCON_USB_HOST,
 313                                    &rockchip->host_nb);
 314         cancel_work_sync(&rockchip->otg_work);
 315 }
 316
 317 static int dwc3_rockchip_probe(struct platform_device *pdev)
 318 {
 319         struct dwc3_rockchip    *rockchip;
 320         struct device           *dev = &pdev->dev;
 321         struct device_node      *np = dev->of_node, *child;
 322         struct platform_device  *child_pdev;
 323
 324         unsigned int            count;
 325         int                     ret;
 326         int                     i;
 327
 328         rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
 329
 330         if (!rockchip)
 331                 return -ENOMEM;
 332
 333         count = of_clk_get_parent_count(np);
 334         if (!count)
 335                 return -ENOENT;
 336
 337         rockchip->num_clocks = count;
 338
 339         rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
 340                                       sizeof(struct clk *), GFP_KERNEL);
 341         if (!rockchip->clks)
 342                 return -ENOMEM;
 343
 344         platform_set_drvdata(pdev, rockchip);
 345
 346         mutex_init(&rockchip->lock);
 347
 348         rockchip->dev = dev;
 349
 350         mutex_lock(&rockchip->lock);
 351
 352         for (i = 0; i < rockchip->num_clocks; i++) {
 353                 struct clk      *clk;
 354
 355                 clk = of_clk_get(np, i);
 356                 if (IS_ERR(clk)) {
 357                         ret = PTR_ERR(clk);
 358                         goto err0;
 359                 }
 360
 361                 ret = clk_prepare_enable(clk);
 362                 if (ret < 0) {
 363                         clk_put(clk);
 364                         goto err0;
 365                 }
 366
 367                 rockchip->clks[i] = clk;
 368         }
 369
 370         pm_runtime_set_active(dev);
 371         pm_runtime_enable(dev);
 372         ret = pm_runtime_get_sync(dev);
 373         if (ret < 0) {
 374                 dev_err(dev, "get_sync failed with err %d\n", ret);
 375                 goto err1;
 376         }
 377
 378         rockchip->otg_rst = devm_reset_control_get(dev, "usb3-otg");
 379         if (IS_ERR(rockchip->otg_rst)) {
 380                 dev_err(dev, "could not get reset controller\n");
 381                 ret = PTR_ERR(rockchip->otg_rst);
 382                 goto err1;
 383         }
 384
 385         child = of_get_child_by_name(np, "dwc3");
 386         if (!child) {
 387                 dev_err(dev, "failed to find dwc3 core node\n");
 388                 ret = -ENODEV;
 389                 goto err1;
 390         }
 391
 392         /* Allocate and initialize the core */
 393         ret = of_platform_populate(np, NULL, NULL, dev);
 394         if (ret) {
 395                 dev_err(dev, "failed to create dwc3 core\n");
 396                 goto err1;
 397         }
 398
 399         child_pdev = of_find_device_by_node(child);
 400         if (!child_pdev) {
 401                 dev_err(dev, "failed to find dwc3 core device\n");
 402                 ret = -ENODEV;
 403                 goto err2;
 404         }
 405
 406         rockchip->dwc = platform_get_drvdata(child_pdev);
 407         if (!rockchip->dwc) {
 408                 dev_err(dev, "failed to get drvdata dwc3\n");
 409                 ret = -EPROBE_DEFER;
 410                 goto err2;
 411         }
 412
 413         ret = dwc3_rockchip_extcon_register(rockchip);
 414         if (ret < 0)
 415                 goto err2;
 416
 417         if (rockchip->edev) {
 418                 if (rockchip->dwc->dr_mode == USB_DR_MODE_HOST ||
 419                     rockchip->dwc->dr_mode == USB_DR_MODE_OTG) {
 420                         struct usb_hcd *hcd =
 421                                 dev_get_drvdata(&rockchip->dwc->xhci->dev);
 422                         if (!hcd) {
 423                                 dev_err(dev, "fail to get drvdata hcd\n");
 424                                 ret = -EPROBE_DEFER;
 425                                 goto err3;
 426                         }
 427                         if (hcd->state != HC_STATE_HALT) {
 428                                 usb_remove_hcd(hcd->shared_hcd);
 429                                 usb_remove_hcd(hcd);
 430                         }
 431                 }
 432
 433                 pm_runtime_set_autosuspend_delay(&child_pdev->dev,
 434                                                  DWC3_ROCKCHIP_AUTOSUSPEND_DELAY);
 435                 pm_runtime_allow(&child_pdev->dev);
 436                 pm_runtime_suspend(&child_pdev->dev);
 437                 pm_runtime_put_sync(dev);
 438
 439                 if ((extcon_get_cable_state_(rockchip->edev,
 440                                              EXTCON_USB) > 0) ||
 441                     (extcon_get_cable_state_(rockchip->edev,
 442                                              EXTCON_USB_HOST) > 0))
 443                         schedule_work(&rockchip->otg_work);
 444         }
 445
 446         mutex_unlock(&rockchip->lock);
 447
 448         return ret;
 449
 450 err3:
 451         dwc3_rockchip_extcon_unregister(rockchip);
 452
 453 err2:
 454         of_platform_depopulate(dev);
 455
 456 err1:
 457         pm_runtime_put_sync(dev);
 458         pm_runtime_disable(dev);
 459
 460 err0:
 461         for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
 462                 if (!pm_runtime_status_suspended(dev))
 463                         clk_disable(rockchip->clks[i]);
 464                 clk_unprepare(rockchip->clks[i]);
 465                 clk_put(rockchip->clks[i]);
 466         }
 467
 468         mutex_unlock(&rockchip->lock);
 469
 470         return ret;
 471 }
 472
 473 static int dwc3_rockchip_remove(struct platform_device *pdev)
 474 {
 475         struct dwc3_rockchip    *rockchip = platform_get_drvdata(pdev);
 476         struct device           *dev = &pdev->dev;
 477         int                     i;
 478
 479         dwc3_rockchip_extcon_unregister(rockchip);
 480
 481         /* Restore hcd state before unregistering xhci */
 482         if (rockchip->edev && !rockchip->connected) {
 483                 struct usb_hcd *hcd =
 484                         dev_get_drvdata(&rockchip->dwc->xhci->dev);
 485
 486                 pm_runtime_get_sync(dev);
 487
 488                 /*
 489                  * The xhci code does not expect that HCDs have been removed.
 490                  * It will unconditionally call usb_remove_hcd() when the xhci
 491                  * driver is unloaded in of_platform_depopulate(). This results
 492                  * in a crash if the HCDs were already removed. To avoid this
 493                  * crash, add the HCDs here as dummy operation.
 494                  * This code should be removed after pm runtime support
 495                  * has been added to xhci.
 496                  */
 497                 if (hcd->state == HC_STATE_HALT) {
 498                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 499                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 500                 }
 501         }
 502
 503         of_platform_depopulate(dev);
 504
 505         pm_runtime_put_sync(dev);
 506         pm_runtime_disable(dev);
 507
 508         for (i = 0; i < rockchip->num_clocks; i++) {
 509                 if (!pm_runtime_status_suspended(dev))
 510                         clk_disable(rockchip->clks[i]);
 511                 clk_unprepare(rockchip->clks[i]);
 512                 clk_put(rockchip->clks[i]);
 513         }
 514
 515         return 0;
 516 }
 517
 518 #ifdef CONFIG_PM
 519 static int dwc3_rockchip_runtime_suspend(struct device *dev)
 520 {
 521         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 522         int                     i;
 523
 524         for (i = 0; i < rockchip->num_clocks; i++)
 525                 clk_disable(rockchip->clks[i]);
 526
 527         device_init_wakeup(dev, false);
 528
 529         return 0;
 530 }
 531
 532 static int dwc3_rockchip_runtime_resume(struct device *dev)
 533 {
 534         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 535         int                     i;
 536
 537         for (i = 0; i < rockchip->num_clocks; i++)
 538                 clk_enable(rockchip->clks[i]);
 539
 540         device_init_wakeup(dev, true);
 541
 542         return 0;
 543 }
 544
 545 static int dwc3_rockchip_suspend(struct device *dev)
 546 {
 547         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 548
 549         rockchip->suspended = true;
 550         cancel_work_sync(&rockchip->otg_work);
 551
 552         return 0;
 553 }
 554
 555 static int dwc3_rockchip_resume(struct device *dev)
 556 {
 557         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 558
 559         rockchip->suspended = false;
 560
 561         if (rockchip->edev)
 562                 schedule_work(&rockchip->otg_work);
 563
 564         return 0;
 565 }
 566
 567 static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
 568         SET_SYSTEM_SLEEP_PM_OPS(dwc3_rockchip_suspend, dwc3_rockchip_resume)
 569         SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
 570                            dwc3_rockchip_runtime_resume, NULL)
 571 };
 572
 573 #define DEV_PM_OPS      (&dwc3_rockchip_dev_pm_ops)
 574 #else
 575 #define DEV_PM_OPS      NULL
 576 #endif /* CONFIG_PM */
 577
 578 static const struct of_device_id rockchip_dwc3_match[] = {
 579         { .compatible = "rockchip,rk3399-dwc3" },
 580         { /* Sentinel */ }
 581 };
 582
 583 MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
 584
 585 static struct platform_driver dwc3_rockchip_driver = {
 586         .probe          = dwc3_rockchip_probe,
 587         .remove         = dwc3_rockchip_remove,
 588         .driver         = {
 589                 .name   = "rockchip-dwc3",
 590                 .of_match_table = rockchip_dwc3_match,
 591                 .pm     = DEV_PM_OPS,
 592         },
 593 };
 594
 595 module_platform_driver(dwc3_rockchip_driver);
 596
 597 MODULE_ALIAS("platform:rockchip-dwc3");
 598 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
 599 MODULE_LICENSE("GPL v2");
 600 MODULE_DESCRIPTION("DesignWare USB3 ROCKCHIP Glue Layer");