drivers/usb/dwc3/dwc3-rockchip.c

   1 /**
   2  * dwc3-rockchip.c - Rockchip Specific Glue layer
   3  *
   4  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   5  *
   6  * Authors: William Wu <william.wu@rock-chips.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2  of
  10  * the License as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/kernel.h>
  21 #include <linux/slab.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/of.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/extcon.h>
  30 #include <linux/freezer.h>
  31 #include <linux/reset.h>
  32 #include <linux/usb.h>
  33 #include <linux/usb/hcd.h>
  34
  35 #include "core.h"
  36 #include "io.h"
  37 #include "../host/xhci.h"
  38
  39 #define DWC3_ROCKCHIP_AUTOSUSPEND_DELAY  500 /* ms */
  40
  41 struct dwc3_rockchip {
  42         int                     num_clocks;
  43         bool                    connected;
  44         bool                    suspended;
  45         struct device           *dev;
  46         struct clk              **clks;
  47         struct dwc3             *dwc;
  48         struct reset_control    *otg_rst;
  49         struct extcon_dev       *edev;
  50         struct notifier_block   device_nb;
  51         struct notifier_block   host_nb;
  52         struct work_struct      otg_work;
  53         struct mutex            lock;
  54 };
  55
  56 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
  57                                          unsigned long event, void *ptr)
  58 {
  59         struct dwc3_rockchip *rockchip =
  60                 container_of(nb, struct dwc3_rockchip, device_nb);
  61
  62         if (!rockchip->suspended)
  63                 schedule_work(&rockchip->otg_work);
  64
  65         return NOTIFY_DONE;
  66 }
  67
  68 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
  69                                        unsigned long event, void *ptr)
  70 {
  71         struct dwc3_rockchip *rockchip =
  72                 container_of(nb, struct dwc3_rockchip, host_nb);
  73
  74         if (!rockchip->suspended)
  75                 schedule_work(&rockchip->otg_work);
  76
  77         return NOTIFY_DONE;
  78 }
  79
  80 static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
  81 {
  82         struct dwc3_rockchip    *rockchip =
  83                 container_of(work, struct dwc3_rockchip, otg_work);
  84         struct dwc3             *dwc = rockchip->dwc;
  85         struct extcon_dev       *edev = rockchip->edev;
  86         struct usb_hcd          *hcd;
  87         struct xhci_hcd         *xhci;
  88         unsigned long           flags;
  89         int                     ret;
  90         u32                     reg, count;
  91
  92         mutex_lock(&rockchip->lock);
  93
  94         if (extcon_get_cable_state_(edev, EXTCON_USB) > 0) {
  95                 if (rockchip->connected)
  96                         goto out;
  97
  98                 /*
  99                  * If dr_mode is host only, never to set
 100                  * the mode to the peripheral mode.
 101                  */
 102                 if (dwc->dr_mode == USB_DR_MODE_HOST) {
 103                         dev_warn(rockchip->dev, "USB peripheral not support!\n");
 104                         goto out;
 105                 }
 106
 107                 /*
 108                  * Assert otg reset can put the dwc in P2 state, it's
 109                  * necessary operation prior to phy power on. However,
 110                  * asserting the otg reset may affect dwc chip operation.
 111                  * The reset will clear all of the dwc controller registers.
 112                  * So we need to reinit the dwc controller after deassert
 113                  * the reset. We use pm runtime to initialize dwc controller.
 114                  * Also, there are no synchronization primitives, meaning
 115                  * the dwc3 core code could at least in theory access chip
 116                  * registers while the reset is asserted, with unknown impact.
 117                  */
 118                 reset_control_assert(rockchip->otg_rst);
 119                 usleep_range(1000, 1200);
 120                 reset_control_deassert(rockchip->otg_rst);
 121
 122                 pm_runtime_get_sync(rockchip->dev);
 123                 pm_runtime_get_sync(dwc->dev);
 124
 125                 spin_lock_irqsave(&dwc->lock, flags);
 126                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 127                 spin_unlock_irqrestore(&dwc->lock, flags);
 128
 129                 rockchip->connected = true;
 130                 dev_info(rockchip->dev, "USB peripheral connected\n");
 131         } else if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) > 0) {
 132                 if (rockchip->connected)
 133                         goto out;
 134
 135                 /*
 136                  * If dr_mode is device only, never to
 137                  * set the mode to the host mode.
 138                  */
 139                 if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
 140                         dev_warn(rockchip->dev, "USB HOST not support!\n");
 141                         goto out;
 142                 }
 143
 144                 /*
 145                  * Assert otg reset can put the dwc in P2 state, it's
 146                  * necessary operation prior to phy power on. However,
 147                  * asserting the otg reset may affect dwc chip operation.
 148                  * The reset will clear all of the dwc controller registers.
 149                  * So we need to reinit the dwc controller after deassert
 150                  * the reset. We use pm runtime to initialize dwc controller.
 151                  * Also, there are no synchronization primitives, meaning
 152                  * the dwc3 core code could at least in theory access chip
 153                  * registers while the reset is asserted, with unknown impact.
 154                  */
 155                 reset_control_assert(rockchip->otg_rst);
 156                 usleep_range(1000, 1200);
 157                 reset_control_deassert(rockchip->otg_rst);
 158
 159                 /*
 160                  * In usb3 phy init, it will access usb3 module, so we need
 161                  * to resume rockchip dev before phy init to make sure usb3
 162                  * pd is enabled.
 163                  */
 164                 pm_runtime_get_sync(rockchip->dev);
 165
 166                 /*
 167                  * Don't abort on errors. If powering on a phy fails,
 168                  * we still need to init dwc controller and add the
 169                  * HCDs to avoid a crash when unloading the driver.
 170                  */
 171                 ret = phy_power_on(dwc->usb2_generic_phy);
 172                 if (ret < 0)
 173                         dev_err(dwc->dev, "Failed to power on usb2 phy\n");
 174
 175                 ret = phy_power_on(dwc->usb3_generic_phy);
 176                 if (ret < 0) {
 177                         phy_power_off(dwc->usb2_generic_phy);
 178                         dev_err(dwc->dev, "Failed to power on usb3 phy\n");
 179                 }
 180
 181                 pm_runtime_get_sync(dwc->dev);
 182
 183                 spin_lock_irqsave(&dwc->lock, flags);
 184                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 185                 spin_unlock_irqrestore(&dwc->lock, flags);
 186
 187                 /*
 188                  * The following sleep helps to ensure that inserted USB3
 189                  * Ethernet devices are discovered if already inserted
 190                  * when booting.
 191                  */
 192                 usleep_range(10000, 11000);
 193
 194                 hcd = dev_get_drvdata(&dwc->xhci->dev);
 195
 196                 if (hcd->state == HC_STATE_HALT) {
 197                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 198                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 199                 }
 200
 201                 rockchip->connected = true;
 202                 dev_info(rockchip->dev, "USB HOST connected\n");
 203         } else {
 204                 if (!rockchip->connected)
 205                         goto out;
 206
 207                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 208
 209                 /*
 210                  * xhci does not support runtime pm. If HCDs are not removed
 211                  * here and and re-added after a cable is inserted, USB3
 212                  * connections will not work.
 213                  * A clean(er) solution would be to implement runtime pm
 214                  * support in xhci. After that is available, this code should
 215                  * be removed.
 216                  * HCDs have to be removed here to prevent attempts by the
 217                  * xhci code to access xhci registers after the call to
 218                  * pm_runtime_put_sync_suspend(). On rk3399, this can result
 219                  * in a crash under certain circumstances (this was observed
 220                  * on 3399 chromebook if the system is running on battery).
 221                  */
 222                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
 223                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 224                         hcd = dev_get_drvdata(&dwc->xhci->dev);
 225                         xhci = hcd_to_xhci(hcd);
 226
 227                         if (hcd->state != HC_STATE_HALT) {
 228                                 xhci->xhc_state |= XHCI_STATE_REMOVING;
 229                                 count = 0;
 230
 231                                 /*
 232                                  * Wait until XHCI controller resume from
 233                                  * PM suspend, them we can remove hcd safely.
 234                                  */
 235                                 while (dwc->xhci->dev.power.is_suspended) {
 236                                         if (++count > 100) {
 237                                                 dev_err(rockchip->dev,
 238                                                         "wait for XHCI resume 10s timeout!\n");
 239                                                 goto out;
 240                                         }
 241                                         msleep(100);
 242                                 }
 243
 244 #ifdef CONFIG_FREEZER
 245                                 /*
 246                                  * usb_remove_hcd() may call usb_disconnect() to
 247                                  * remove a block device pluged in before.
 248                                  * Unfortunately, the block layer suspend/resume
 249                                  * path is fundamentally broken due to freezable
 250                                  * kthreads and workqueue and may deadlock if a
 251                                  * block device gets removed while resume is in
 252                                  * progress.
 253                                  *
 254                                  * We need to add a ugly hack to avoid removing
 255                                  * hcd and kicking off device removal while
 256                                  * freezer is active. This is a joke but does
 257                                  * avoid this particular deadlock when test with
 258                                  * USB-C HUB and USB2/3 flash drive.
 259                                  */
 260                                 while (pm_freezing)
 261                                         usleep_range(10000, 11000);
 262 #endif
 263
 264                                 usb_remove_hcd(hcd->shared_hcd);
 265                                 usb_remove_hcd(hcd);
 266                         }
 267
 268                         phy_power_off(dwc->usb2_generic_phy);
 269                         phy_power_off(dwc->usb3_generic_phy);
 270                 }
 271
 272                 pm_runtime_put_sync(rockchip->dev);
 273                 pm_runtime_put_sync_suspend(dwc->dev);
 274
 275                 rockchip->connected = false;
 276                 dev_info(rockchip->dev, "USB unconnected\n");
 277         }
 278
 279 out:
 280         mutex_unlock(&rockchip->lock);
 281 }
 282
 283 static int dwc3_rockchip_extcon_register(struct dwc3_rockchip *rockchip)
 284 {
 285         int                     ret;
 286         struct device           *dev = rockchip->dev;
 287         struct extcon_dev       *edev;
 288
 289         if (device_property_read_bool(dev, "extcon")) {
 290                 edev = extcon_get_edev_by_phandle(dev, 0);
 291                 if (IS_ERR(edev)) {
 292                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 293                                 dev_err(dev, "couldn't get extcon device\n");
 294                         return PTR_ERR(edev);
 295                 }
 296
 297                 INIT_WORK(&rockchip->otg_work,
 298                           dwc3_rockchip_otg_extcon_evt_work);
 299
 300                 rockchip->device_nb.notifier_call =
 301                                 dwc3_rockchip_device_notifier;
 302                 ret = extcon_register_notifier(edev, EXTCON_USB,
 303                                                &rockchip->device_nb);
 304                 if (ret < 0) {
 305                         dev_err(dev, "failed to register notifier for USB\n");
 306                         return ret;
 307                 }
 308
 309                 rockchip->host_nb.notifier_call =
 310                                 dwc3_rockchip_host_notifier;
 311                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
 312                                                &rockchip->host_nb);
 313                 if (ret < 0) {
 314                         dev_err(dev, "failed to register notifier for USB HOST\n");
 315                         extcon_unregister_notifier(edev, EXTCON_USB,
 316                                                    &rockchip->device_nb);
 317                         return ret;
 318                 }
 319
 320                 rockchip->edev = edev;
 321         }
 322
 323         return 0;
 324 }
 325
 326 static void dwc3_rockchip_extcon_unregister(struct dwc3_rockchip *rockchip)
 327 {
 328         if (!rockchip->edev)
 329                 return;
 330
 331         extcon_unregister_notifier(rockchip->edev, EXTCON_USB,
 332                                    &rockchip->device_nb);
 333         extcon_unregister_notifier(rockchip->edev, EXTCON_USB_HOST,
 334                                    &rockchip->host_nb);
 335         cancel_work_sync(&rockchip->otg_work);
 336 }
 337
 338 static int dwc3_rockchip_probe(struct platform_device *pdev)
 339 {
 340         struct dwc3_rockchip    *rockchip;
 341         struct device           *dev = &pdev->dev;
 342         struct device_node      *np = dev->of_node, *child;
 343         struct platform_device  *child_pdev;
 344
 345         unsigned int            count;
 346         int                     ret;
 347         int                     i;
 348
 349         rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
 350
 351         if (!rockchip)
 352                 return -ENOMEM;
 353
 354         count = of_clk_get_parent_count(np);
 355         if (!count)
 356                 return -ENOENT;
 357
 358         rockchip->num_clocks = count;
 359
 360         rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
 361                                       sizeof(struct clk *), GFP_KERNEL);
 362         if (!rockchip->clks)
 363                 return -ENOMEM;
 364
 365         platform_set_drvdata(pdev, rockchip);
 366
 367         mutex_init(&rockchip->lock);
 368
 369         rockchip->dev = dev;
 370
 371         mutex_lock(&rockchip->lock);
 372
 373         for (i = 0; i < rockchip->num_clocks; i++) {
 374                 struct clk      *clk;
 375
 376                 clk = of_clk_get(np, i);
 377                 if (IS_ERR(clk)) {
 378                         ret = PTR_ERR(clk);
 379                         goto err0;
 380                 }
 381
 382                 ret = clk_prepare_enable(clk);
 383                 if (ret < 0) {
 384                         clk_put(clk);
 385                         goto err0;
 386                 }
 387
 388                 rockchip->clks[i] = clk;
 389         }
 390
 391         pm_runtime_set_active(dev);
 392         pm_runtime_enable(dev);
 393         ret = pm_runtime_get_sync(dev);
 394         if (ret < 0) {
 395                 dev_err(dev, "get_sync failed with err %d\n", ret);
 396                 goto err1;
 397         }
 398
 399         rockchip->otg_rst = devm_reset_control_get(dev, "usb3-otg");
 400         if (IS_ERR(rockchip->otg_rst)) {
 401                 dev_err(dev, "could not get reset controller\n");
 402                 ret = PTR_ERR(rockchip->otg_rst);
 403                 goto err1;
 404         }
 405
 406         child = of_get_child_by_name(np, "dwc3");
 407         if (!child) {
 408                 dev_err(dev, "failed to find dwc3 core node\n");
 409                 ret = -ENODEV;
 410                 goto err1;
 411         }
 412
 413         /* Allocate and initialize the core */
 414         ret = of_platform_populate(np, NULL, NULL, dev);
 415         if (ret) {
 416                 dev_err(dev, "failed to create dwc3 core\n");
 417                 goto err1;
 418         }
 419
 420         child_pdev = of_find_device_by_node(child);
 421         if (!child_pdev) {
 422                 dev_err(dev, "failed to find dwc3 core device\n");
 423                 ret = -ENODEV;
 424                 goto err2;
 425         }
 426
 427         rockchip->dwc = platform_get_drvdata(child_pdev);
 428         if (!rockchip->dwc) {
 429                 dev_err(dev, "failed to get drvdata dwc3\n");
 430                 ret = -EPROBE_DEFER;
 431                 goto err2;
 432         }
 433
 434         ret = dwc3_rockchip_extcon_register(rockchip);
 435         if (ret < 0)
 436                 goto err2;
 437
 438         if (rockchip->edev) {
 439                 if (rockchip->dwc->dr_mode == USB_DR_MODE_HOST ||
 440                     rockchip->dwc->dr_mode == USB_DR_MODE_OTG) {
 441                         struct usb_hcd *hcd =
 442                                 dev_get_drvdata(&rockchip->dwc->xhci->dev);
 443                         if (!hcd) {
 444                                 dev_err(dev, "fail to get drvdata hcd\n");
 445                                 ret = -EPROBE_DEFER;
 446                                 goto err3;
 447                         }
 448                         if (hcd->state != HC_STATE_HALT) {
 449                                 usb_remove_hcd(hcd->shared_hcd);
 450                                 usb_remove_hcd(hcd);
 451                         }
 452                 }
 453
 454                 pm_runtime_set_autosuspend_delay(&child_pdev->dev,
 455                                                  DWC3_ROCKCHIP_AUTOSUSPEND_DELAY);
 456                 pm_runtime_allow(&child_pdev->dev);
 457                 pm_runtime_suspend(&child_pdev->dev);
 458                 pm_runtime_put_sync(dev);
 459
 460                 if ((extcon_get_cable_state_(rockchip->edev,
 461                                              EXTCON_USB) > 0) ||
 462                     (extcon_get_cable_state_(rockchip->edev,
 463                                              EXTCON_USB_HOST) > 0))
 464                         schedule_work(&rockchip->otg_work);
 465         }
 466
 467         mutex_unlock(&rockchip->lock);
 468
 469         return ret;
 470
 471 err3:
 472         dwc3_rockchip_extcon_unregister(rockchip);
 473
 474 err2:
 475         of_platform_depopulate(dev);
 476
 477 err1:
 478         pm_runtime_put_sync(dev);
 479         pm_runtime_disable(dev);
 480
 481 err0:
 482         for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
 483                 if (!pm_runtime_status_suspended(dev))
 484                         clk_disable(rockchip->clks[i]);
 485                 clk_unprepare(rockchip->clks[i]);
 486                 clk_put(rockchip->clks[i]);
 487         }
 488
 489         mutex_unlock(&rockchip->lock);
 490
 491         return ret;
 492 }
 493
 494 static int dwc3_rockchip_remove(struct platform_device *pdev)
 495 {
 496         struct dwc3_rockchip    *rockchip = platform_get_drvdata(pdev);
 497         struct device           *dev = &pdev->dev;
 498         int                     i;
 499
 500         dwc3_rockchip_extcon_unregister(rockchip);
 501
 502         /* Restore hcd state before unregistering xhci */
 503         if (rockchip->edev && !rockchip->connected) {
 504                 struct usb_hcd *hcd =
 505                         dev_get_drvdata(&rockchip->dwc->xhci->dev);
 506
 507                 pm_runtime_get_sync(dev);
 508
 509                 /*
 510                  * The xhci code does not expect that HCDs have been removed.
 511                  * It will unconditionally call usb_remove_hcd() when the xhci
 512                  * driver is unloaded in of_platform_depopulate(). This results
 513                  * in a crash if the HCDs were already removed. To avoid this
 514                  * crash, add the HCDs here as dummy operation.
 515                  * This code should be removed after pm runtime support
 516                  * has been added to xhci.
 517                  */
 518                 if (hcd->state == HC_STATE_HALT) {
 519                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 520                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 521                 }
 522         }
 523
 524         of_platform_depopulate(dev);
 525
 526         pm_runtime_put_sync(dev);
 527         pm_runtime_disable(dev);
 528
 529         for (i = 0; i < rockchip->num_clocks; i++) {
 530                 if (!pm_runtime_status_suspended(dev))
 531                         clk_disable(rockchip->clks[i]);
 532                 clk_unprepare(rockchip->clks[i]);
 533                 clk_put(rockchip->clks[i]);
 534         }
 535
 536         return 0;
 537 }
 538
 539 #ifdef CONFIG_PM
 540 static int dwc3_rockchip_runtime_suspend(struct device *dev)
 541 {
 542         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 543         int                     i;
 544
 545         for (i = 0; i < rockchip->num_clocks; i++)
 546                 clk_disable(rockchip->clks[i]);
 547
 548         device_init_wakeup(dev, false);
 549
 550         return 0;
 551 }
 552
 553 static int dwc3_rockchip_runtime_resume(struct device *dev)
 554 {
 555         struct dwc3_rockchip    *rockchip = dev_get_drvdata(dev);
 556         int                     i;
 557
 558         for (i = 0; i < rockchip->num_clocks; i++)
 559                 clk_enable(rockchip->clks[i]);
 560
 561         device_init_wakeup(dev, true);
 562
 563         return 0;
 564 }
 565
 566 static int dwc3_rockchip_suspend(struct device *dev)
 567 {
 568         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 569
 570         rockchip->suspended = true;
 571         cancel_work_sync(&rockchip->otg_work);
 572
 573         return 0;
 574 }
 575
 576 static int dwc3_rockchip_resume(struct device *dev)
 577 {
 578         struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
 579
 580         rockchip->suspended = false;
 581
 582         if (rockchip->edev)
 583                 schedule_work(&rockchip->otg_work);
 584
 585         return 0;
 586 }
 587
 588 static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
 589         SET_SYSTEM_SLEEP_PM_OPS(dwc3_rockchip_suspend, dwc3_rockchip_resume)
 590         SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
 591                            dwc3_rockchip_runtime_resume, NULL)
 592 };
 593
 594 #define DEV_PM_OPS      (&dwc3_rockchip_dev_pm_ops)
 595 #else
 596 #define DEV_PM_OPS      NULL
 597 #endif /* CONFIG_PM */
 598
 599 static const struct of_device_id rockchip_dwc3_match[] = {
 600         { .compatible = "rockchip,rk3399-dwc3" },
 601         { /* Sentinel */ }
 602 };
 603
 604 MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
 605
 606 static struct platform_driver dwc3_rockchip_driver = {
 607         .probe          = dwc3_rockchip_probe,
 608         .remove         = dwc3_rockchip_remove,
 609         .driver         = {
 610                 .name   = "rockchip-dwc3",
 611                 .of_match_table = rockchip_dwc3_match,
 612                 .pm     = DEV_PM_OPS,
 613         },
 614 };
 615
 616 module_platform_driver(dwc3_rockchip_driver);
 617
 618 MODULE_ALIAS("platform:rockchip-dwc3");
 619 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
 620 MODULE_LICENSE("GPL v2");
 621 MODULE_DESCRIPTION("DesignWare USB3 ROCKCHIP Glue Layer");